System Direct Memory Access Engine Unload

Abstract

Systems, apparatus, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message to a data structure device, the message including the physical addresses of a source buffer and a destination buffer, and the size of a data transfer. The data structure device sends an instruction to a first proxy device, the instruction including the physical addresses of the source buffer and the destination buffer, and the size of the data transfer. Each of the first proxy devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first proxy devices sends the portion of the source buffer to one of the second proxy devices. Each of the second proxy devices writes the portion of the source buffer to the destination buffer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. nonprovisional patent application No. 16 / 723,709, filed December 20, 2019, the entire contents of which are hereby incorporated herein by reference. Background Technology

[0003] A System Direct Memory Access (SDMA) engine is a device used to coordinate direct memory access (DMA) transfers of data between devices and memory or between different locations within memory within a computer system. The SDMA engine typically resides on a processor, such as a graphics processing unit (GPU), and receives commands from applications running on that processor. Based on the commands, the SDMA engine reads data from an SDMA source (e.g., a first memory buffer defined in main memory) and writes the data to an SDMA destination (e.g., a second buffer defined in main memory).

[0004] In some cases, the SDMA source and SDMA destination are physically located on different devices. In multiprocessor systems, the SDMA source and SDMA destination may reside on different devices associated with different processors. In such cases, the SDMA engine resolves the virtual address to obtain the physical address and issues remote read and / or write commands to achieve the DMA transfer. Attached Figure Description

[0005] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings, in which:

[0006] Figure 1 It is a block diagram of an exemplary apparatus in which one or more features of this disclosure may be implemented;

[0007] Figure 2 This is a block diagram illustrating a portion of an exemplary computing system;

[0008] Figure 3 This is a block diagram illustrating a portion of an exemplary multiprocessor computing system;

[0009] Figure 4 This is a message sequence diagram illustrating an exemplary direct memory access message passing mechanism; and

[0010] Figure 5 This is a flowchart illustrating an exemplary method for direct memory access. Detailed Implementation

[0011] Some implementations provide a computing system configured for direct memory access. The system includes an SDMA device on a processor die. The SDMA device sends a message to a data structure device. The message includes the physical address of a source buffer, the physical address of a destination buffer, and the size of a data transfer from the source buffer to the destination buffer. The data structure device sends one or more instructions to a first proxy device. The instructions include the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer. Each of the first proxy devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first proxy devices also sends the portion of the source buffer to one of the second proxy devices. Each of the second proxy devices operates a memory controller to write the portion of the source buffer to the destination buffer.

[0012] In some embodiments, the SDMA device receives one or more instructions from a processor on a processor die. The one or more instructions indicate a virtual address for a source buffer and a virtual address for a destination buffer. The SDMA device translates the virtual address of the source buffer into a physical address for the source buffer. The SDMA device translates the virtual address of the destination buffer into a physical address for the destination buffer. In some embodiments, the data structure device includes a miscellaneous (MISC) function block of the data structure. In some embodiments, the proxy device includes a consistent slave device of the data structure. In some embodiments, the first proxy device is on a processor die, while the second proxy device is on a remote processor die. In some embodiments, the second proxy device is on a processor die, while the first proxy device is on a remote processor die. In some embodiments, each of the first proxy devices stores said portion of the source buffer in a local buffer before sending said portion of the source buffer to one of the second proxy devices. Some embodiments include a consistent link between the processor die and the remote processor die, and the first proxy device communicates with the second proxy device through the consistent link. In some embodiments, each of the first agent devices operates a memory controller to read the portion of the source buffer from a memory device at a physical address of the source buffer. In some embodiments, the data structure device broadcasts one or more instructions to the first agent device.

[0013] Some implementations provide a method for direct memory access. The method includes sending a message from a System Direct Memory Access (SDMA) device disposed on a processor die to a data structure device. The message includes a physical address of a source buffer, a physical address of a destination buffer, and the size of a data transfer from the source buffer to the destination buffer. The method also includes sending one or more instructions from the data structure device to a first proxy device. The one or more instructions include the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer. The method further includes each of the first proxy devices reading a portion of the source buffer from a memory device at the physical address of the source buffer. The method also includes each of the first proxy devices sending the portion of the source buffer to one of the second proxy devices. The method further includes each of the second proxy devices writing the portion of the source buffer to the destination buffer.

[0014] Some implementations include an SDMA device receiving one or more instructions from a processor on a processor die. The instructions indicate a virtual address for a source buffer and a virtual address for a destination buffer. Some implementations include the SDMA device translating the virtual address of the source buffer into a physical address of the source buffer. Some implementations include the SDMA device translating the virtual address of the destination buffer into a physical address of the destination buffer. In some implementations, a data structure device includes a MISC function block of a data structure. In some implementations, a proxy device includes a consistent slave device of the data structure. In some implementations, a first proxy device is on a processor die, while a second proxy device is on a remote processor die. In some implementations, a second proxy device is on a processor die, while a first proxy device is on a remote processor die. Some implementations include each of the first proxy devices storing said portion of the source buffer in a local buffer before sending said portion of the source buffer to one of the second proxy devices. Some implementations include the first proxy device communicating with the second proxy device via a consistent link between the processor die and the remote processor die. Some implementations include each of the first agent devices operating a memory controller to read said portion of the source buffer from a memory device at a physical address of the source buffer. Some implementations include a data structure device broadcasting one or more instructions to the first agent device.

[0015] Figure 1This is a block diagram of an exemplary device 100 in which one or more features of this disclosure may be implemented. Device 100 may include, for example, a computer, gaming device, handheld device, set-top box, television, mobile phone, or tablet computer. Device 100 includes a processor 102, memory 104, storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include components not in... Figure 1 Additional components are shown in the image.

[0016] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0017] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid-state drives, optical disks, or flash drives. Input device 108 includes, but is not limited to, keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to, displays, speakers, printers, haptic feedback devices, one or more lights, antennas, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals).

[0018] Input driver 112 communicates with processor 102 and input device 108, and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, and allows processor 102 to send output to output device 110. Note that input driver 112 and output driver 114 are optional components, and device 100 will operate in the same manner in the absence of input driver 112 and output driver 114. Output driver 116 includes an accelerated processing unit (“APD”) 116 coupled to display device 118. APD receives computation commands and graphics rendering commands from processor 102, processes those commands, and provides pixel output to display device 118 for display. As described in further detail below, APD 116 includes one or more parallel processing units that perform computations according to the Single Instruction Multiple Data (“SIMD”) paradigm. Therefore, although various functions are described herein as being performed by or in combination with APD 116, in various alternatives, the functions described as being performed by APD 116 may additionally or alternatively be performed by other computing devices with similar capabilities, which are not driven by a host processor (e.g., processor 102) and provide graphics output to display device 118. For example, it is conceivable that any processing system performing processing tasks according to the SIMD paradigm can perform the functionality described herein. Alternatively, it is conceivable that a computing system not performing processing tasks according to the SIMD paradigm can perform the functionality described herein.

[0019] Figure 2 This is a block diagram illustrating a portion of an exemplary computing system 200. In some examples, the computing system 200 uses, as shown in the diagram... Figure 1 Some or all of the apparatus 100 shown and described are implemented. The computing system 200 includes a first semiconductor die 205. The semiconductor die 205 includes one or more processors 210A-N, input / output (I / O) interfaces 220, interconnects 230, a memory controller 240, and a network interface 250. In other examples, the computing system 200 includes additional components, different components, and / or is arranged in a different manner.

[0020] In some embodiments, each of the processors 210A-N includes one or more processing devices. In this example, at least one of the processors 210A-N includes one or more general-purpose processing devices, such as a CPU. In some embodiments, the use of... Figure 1The processor 102 shown and described implements such a processing device. In this example, at least one of the processors 210A-N includes one or more data-parallel processors. Examples of data-parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc. In some embodiments, such a processing device uses, as described above... Figure 1 The APD 116 is shown and described for implementation.

[0021] In some implementations, each processor includes a cache subsystem with one or more tiers of cache. In one implementation, each core complex 210A-N includes a cache (e.g., a Level 3 (L3) cache) shared among multiple processor cores.

[0022] Memory controller 240 includes at least one memory controller accessible by the core complex 210A-N, for example, via interconnect 230. Memory controller 240 includes one or more of any suitable type of memory controller. Each of the memory controllers is coupled to (or otherwise communicates with) any number and type of memory device (not shown) and controls access to it. In some embodiments, such memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and / or any other suitable memory device. Interconnect 230 includes components suitable for… Figure 2 Any computer communication medium, such as a bus, data structure, etc., for communication between the devices shown.

[0023] I / O interface 220 includes one or more I / O interfaces (e.g., Peripheral Component Interconnect (PCI) bus, PCI Expansion (PCI-X), PCIe (PCI Express) bus, Gigabit Ethernet (GBE) bus, Universal Serial Bus (USB), etc.). In some embodiments, I / O interface 220 uses, as described above... Figure 1 The input driver 112 and / or output driver 114 shown and described are used in this implementation. Various types of peripheral devices can be coupled to the I / O interface 220. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so on. In some embodiments, such peripheral devices are implemented using methods such as those described above. Figure 1 The input device 108 and / or output device 118 shown and described are used to implement this.

[0024] Figure 3This is a block diagram illustrating a portion of an exemplary multiprocessor computing system 300. System 300 or a portion thereof may utilize a semiconductor die 205 (as per [reference to...]). Figure 2 (shown and described) and / or device 100 (as per...) Figure 1 and Figure 2 (Shown and described) some or all of them to be implemented.

[0025] System 300 includes one or more processors 310A-N and one or more memory controllers 340A-N communicating with the processors 310A-N via interconnects 330 (e.g., via other components). In some examples, the processors 310A-N are coupled to the interconnects 330 via coherent master devices 315A-N, and the memory controllers 340A-N are coupled to the interconnects 330 via coherent slave devices 345A-N. The interconnects 330, the coherent master devices 315A-N, and the coherent slave devices 345A-N form part of a data structure that facilitates communication between the components of system 300.

[0026] In this example, system 300 includes semiconductor die 0 and semiconductor die 1, and a consistent link 350 extends the data structure on both dies via interconnect 330 and I / O interfaces 360A-B (which also form part of the data structure). Interconnect 330 includes components suitable for… Figure 3 The communication between the devices shown may be any computer communication medium, such as a bus, data structure, etc. Each of the processors 310A-N includes one or more processor cores (e.g., CPU and / or GPU, as per [reference]). Figure 2 (As discussed). Each of the processors 310A-N also includes a corresponding SDMA engine 370A-N.

[0027] Each processor 310A-N communicates with a corresponding consistency master 315A-N. In some embodiments, the consistency master is an agent that processes traffic flowing on the interconnect (e.g., interconnect 330) and manages the consistency of connected CPUs or core complexes. In some embodiments, to manage consistency, the consistency master receives and processes consistency-related messages and probes, and generates consistency-related requests and probes.

[0028] Each processor 310A-N communicates with one or more consistent slave devices 345A-N via its corresponding consistent master device 315A-N and interconnect 330. A consistent slave device is a proxy device that manages the consistency of a memory controller (e.g., a memory controller connected to a consistent slave device). In some embodiments, for the purpose of managing consistency, the consistent slave device receives and processes requests and probes targeting its corresponding memory controller.

[0029] existFigure 3 In one example, processor 310A communicates with consistent slave device 345A via a consistent master device 315A and interconnect 330. The consistent slave device (CS) 345A communicates with a memory controller (MC) 340A that controls the memory device (e.g., a main memory DRAM device). In some embodiments, each processor 310A-N communicates with any suitable number of memory controllers 340A-N via a corresponding consistent master device 315A-N and a corresponding consistent slave device 340A-N.

[0030] Probes include messages passed from a consistency point (e.g., a consistency slave device) to one or more caches in a computer system, requesting a response indicating whether the cache has a copy of a data block, and in some implementations, indicating a cache state in which the data block should be placed. In some implementations, if a consistency slave device receives a memory request for its corresponding memory controller (e.g., a memory request for data stored at an address or address region in memory controlled by a memory controller that manages the consistency of the consistency slave device), the consistency slave device performs a lookup (e.g., a tag-based lookup) in its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of either of the cache subsystems.

[0031] The SDMA engines 370A-N coordinate DMA transfers of data between devices and memory or between different locations within memory within the system 300. The SDMA engines 370A-N are capable of receiving instructions from their corresponding processors 310A-N. Based on the received instructions, in some cases, the SDMA engines 370A-N read and buffer data from any memory via data structures, and write buffered data to any memory via data structures. In some embodiments, based on the received instructions, the SDMA engines 370A-N send messages to data structure devices (such as miscellaneous (MISC) blocks of data structures) containing instructions for implementing DMA.

[0032] MISC blocks 380A-B are data structure devices that handle miscellaneous functions. In some cases, MISC blocks 380A-B manage power management and interrupt functions. In some examples, MISC blocks 380A-B manage SDMA functions as discussed herein. For example, MISC block 380A receives messages from SDMA engine 370A (e.g., via a proxy device, such as a coherent master 315A) with instructions for implementing a DMA transfer of a specified size from a source buffer at a physical address to a destination buffer at a physical address. In this example, MISC block 380A also broadcasts corresponding commands to proxy devices on the same die (e.g., coherent slave devices 345A-D) to implement the DMA transfer, for example, as discussed further herein.

[0033] In some embodiments, the interconnect 330 is connected to and / or communicates with other components, which, for ease of description, are... Figure 3 Not shown. For example, in some embodiments, interconnect 330 includes a connection to one or more network interfaces 250, as per [reference to...]. Figure 2 Shown and described.

[0034] Figure 4 This is a message sequence diagram illustrating an exemplary direct memory access messaging 400, which can be, for example, in the context of... Figure 3 The system 300 shown and described is implemented between devices.

[0035] The SDMA 370A coordinates DMA from a source memory buffer physically located on the processor 310A (i.e., accessible via on-die memory controllers 340A-440B) to a destination buffer physically located on the processor 310N (i.e., accessible via on-die memory controllers 340E-N). This is referred to herein as "local read, remote write" DMA. The corresponding "remote read, local write" operation is implemented by rearranging message passing accordingly. Similarly, the corresponding "local read, local write" or "read remote, remote write" operation is also implemented by rearranging message passing accordingly.

[0036] In instruction 405, processor 310A sends an SDMA command to SDMA 370A, the SDMA command including the virtual address of the source buffer, the virtual address of the destination buffer, and the size of the data transfer. It should be noted that in some embodiments, instruction 405 includes more than one instruction and / or message.

[0037] At step 410, the SDMA 370A performs virtual-to-physical address translation on the virtual address of the source buffer and the virtual address of the destination buffer to obtain the physical address of the source buffer and the physical address of the destination buffer, respectively.

[0038] In SDMA message 415, SDMA 370A sends the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer to MISC block 380A.

[0039] MISC block 380A sends an SDMA command broadcast 420 to all coherent slave devices on die 0. This SDMA command broadcast includes the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer. In this example, CS 345A-D is on die 0.

[0040] Each CS 345A-D sends a read command 425 to its associated local MC 340A-D. Each MC 340A-D reads the corresponding portion of its source buffer in step 430 and returns the source buffer data to the CS 340A-D in step 435. Each CS 340A-D buffers the source buffer data in its local buffer 440 (if and / or as needed) for transmission.

[0041] Each CS 345-AD sends a remote write command 445 to a remote CS 345E-N, which in turn sends a write command 450 to its associated MC 340E-N. Each MC 340E-N writes the corresponding portion of its destination buffer in step 455 and returns an acknowledgment 460 to its corresponding CS 345E-N. In some implementations, acknowledgment is requested only for the last delivery (i.e., for the last write command 450), thus only one acknowledgment 460 is returned for all write commands 450.

[0042] After the destination buffer has been fully written; that is, after the final MC 340E-N has returned an acknowledgment to its corresponding CS345E-N, the CS445E-N that received the final acknowledgment (or the sole acknowledgment in the case of a request for acknowledgment only for the last write command 450) returns a cumulative acknowledgment 465 to the CS445A-D. Upon receiving the cumulative acknowledgment 465, each CS345A-D issues a command 470 to the MISC block 380A to indicate that the transfer is complete. In some implementations, the command 470 includes the transfer identity (e.g., a transfer ID). Based on the command 470, the MISC block 380A sends an indication 475 to the SDMA 370A indicating that the transfer is complete.

[0043] Figure 5This is a flowchart illustrating an exemplary method for direct memory access. For example, method 500 can be used in system 300 (as per...). Figure 3 Signaling 400 (as shown and described) is used on and / or in some examples in some cases (such as regarding Figure 4 (Show and describe) Implementation.

[0044] In block 505, SDMA 370A receives instructions from processor 310A. These instructions may be SDMA commands that include the virtual address of the source buffer, the virtual address of the destination buffer, and the size of the data transfer, for example, as in instruction 405 (as per [reference]). Figure 4 (Shown and described).

[0045] In box 510, the SDMA 370A performs virtual-to-physical address translation on the virtual address of the source buffer and the virtual address of the destination buffer to obtain the physical address of the source buffer and the physical address of the destination buffer, respectively (e.g., as relative to the virtual address of the source buffer). Figure 4 410 (shown and described).

[0046] In block 515, the SDMA 370A sends the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer to the MISC block 380A (e.g., as per the context of...). Figure 4 Message 415 shown and described.

[0047] In block 520, MISC block 380A receives the message, and in block 525, it broadcasts an SDMA command to all coherent slave devices on die 0 (e.g., as...). Figure 4 The broadcast 420 shown and described includes the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer. In this example, the CS 345A-D is on die 0. In some embodiments, the broadcast 420 includes a transfer identifier (e.g., a transfer ID) to identify the transfer task.

[0048] Under condition 530, where the source buffer is local and the destination buffer is remote, in box 535, each local CS345A-D sends a read command to its associated MC 340A-D (e.g., as per the context of...). Figure 4 Command 425, shown and described, causes each MC 340A-D to read the corresponding portion of its source buffer (if any) and return the source buffer data to the CS 340A-D. Each CS 340A-D buffers the source buffer data in a local buffer (if and / or as needed) for transmission.

[0049] In box 540, local CSs 345A-D each send a remote write command to a remote CS 345E-N to write the buffer to remote memory. In box 545, each remote CS 345E-N sends a write command to its associated MC 340E-N, causing each MC 340E-N to write the corresponding portion of its source buffer data to the destination buffer in its associated memory. After writing the corresponding portion to its destination buffer, each MC 340E-N returns an acknowledgment to its corresponding CS 345E-N.

[0050] In block 550, after the destination buffer has been fully written; that is, after the final MC 340E-N has returned an acknowledgment to its corresponding CS 345E-N, the CS 345E-N receiving the final acknowledgment returns a cumulative acknowledgment 465 to its local CS 345A-D. Upon receiving the cumulative acknowledgment 465, each CS 345A-D issues a command to the MISC block 380A to indicate that the transfer is complete. In some embodiments, the command includes the transfer identity (e.g., a transfer ID). Based on the command, the MISC block 380A sends an indication to the SDMA 370A indicating that the transfer is complete.

[0051] Under condition 530, where the source buffer is remote and the destination buffer is local, local CS 345A-Ds each send a remote read command to the remote CS 345E-N in box 555. Based on the remote read command, each remote CS 345E-N sends a read command to its associated MC 340E-N in box 560, causing the MC 340E-N to return the source buffer data to the CS 345E-N. The CS 345E-N buffers the source buffer data in its local buffer (if and / or as needed) for transmission.

[0052] In block 565, the remote CS 345E-N transmits the buffered data to the local CS 345A-D via a consistent link. The local CS 345A-D writes the data to the destination buffer at the physical memory address via the associated MC 340A-D in block 570. After the destination buffer has been fully written; that is, after the final MC 340A-D has returned an acknowledgment to its corresponding CS 345A-D, the CS 345A-D receiving the final acknowledgment issues a command to the MISC block 380A in block 575 to indicate that the transfer is complete. In some embodiments, the command includes the transfer identity (e.g., a transfer ID). Based on the command, the MISC block 380A sends an indication to the SDMA 370A indicating that the transfer is complete.

[0053] It should be understood that many variations are possible based on the disclosed content of this document. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0054] The various functional units shown in the figures and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, and accelerated processing device 116) can be implemented as a general-purpose computer, processor, or processor core, or as a program, software, or firmware stored in a non-transitory computer-readable medium or another medium and executable by a general-purpose computer, processor, or processor core. The provided methods can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data (including netlists) (such instructions can be stored on a computer-readable medium). The result of such processing can be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor implementing the features of this disclosure.

[0055] The methods or flowcharts provided herein can be implemented in computer programs, software, or firmware incorporated into non-transitory computer-readable storage media for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media such as CD-ROMs and digital versatile optical discs (DVDs).

[0056] ***

Claims

1. A computing system configured for direct memory access, the system comprising: a system direct memory access device disposed on a processor die and configured to send a message to a data fabric device, the message comprising a physical address of a source buffer, a physical address of a destination buffer, and a size of a data transfer from the source buffer to the destination buffer; the data fabric device configured to send at least one instruction to a first plurality of agent devices, the at least one instruction comprising the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer; the first plurality of agent devices each configured to: read a portion of the source buffer from a memory device at the physical address of the source buffer; and send the portion of the source buffer to one of a second plurality of agent devices; and the second plurality of agent devices each configured to operate a memory controller to write the portion of the source buffer to the destination buffer.

2. The system of claim 1, wherein the system direct memory access device is further configured to: receive at least one instruction from a processor of the processor die, the at least one instruction indicating a virtual address of the source buffer and a virtual address of the destination buffer; translate the virtual address of the source buffer to the physical address of the source buffer; and translate the virtual address of the destination buffer to the physical address of the destination buffer.

3. The system of claim 1, wherein the data fabric device comprises a miscellaneous function block of a data fabric.

4. The system of claim 1, wherein the first plurality of agent devices and the second plurality of agent devices comprise coherent slaves of a data fabric.

5. The system of claim 1, wherein: the first plurality of agent devices are disposed on the processor die; and the second plurality of agent devices are disposed on a remote processor die.

6. The system of claim 1, wherein: the second plurality of agent devices are disposed on the processor die; and the first plurality of agent devices are disposed on a remote processor die.

7. The system of claim 1, wherein each of the first plurality of agent devices is further configured to store the portion of the source buffer in a local buffer prior to sending the portion of the source buffer to the one of the second plurality of agent devices.

8. The system of claim 1, further comprising a coherent link between the processor die and a remote processor die, wherein the first plurality of agent devices are further configured to communicate with the second plurality of agent devices over the coherent link.

9. The system of claim 1, wherein the first plurality of agent devices are each further configured to operate a memory controller to read the portion of the source buffer from the memory device at the physical address of the source buffer. ​ ​ 10. The system of claim 1, wherein the data fabric device is further configured to broadcast the at least one instruction to the first plurality of agent devices.

11. A method for direct memory access, the method comprising: sending, from a system direct memory access device disposed on a processor die, a message to a data fabric device, the message comprising a physical address of a source buffer, a physical address of a destination buffer, and a size of a data transfer from the source buffer to the destination buffer; sending, by the data fabric device, at least one instruction to a first plurality of agent devices, the at least one instruction comprising the physical address of the source buffer, the physical address of the destination buffer, and the size of the data transfer; reading, by each of the first plurality of agent devices, a portion of the source buffer from a memory device at the physical address of the source buffer; sending, by each of the first plurality of agent devices, the portion of the source buffer to one of a second plurality of agent devices; and writing, by each of the second plurality of agent devices, the portion of the source buffer to the destination buffer.

12. The method of claim 11, further comprising: receiving, by the system direct memory access device, at least one instruction from a processor of the processor die, the at least one instruction indicating a virtual address of the source buffer and a virtual address of the destination buffer; translating, by the system direct memory access device, the virtual address of the source buffer to the physical address of the source buffer; and translating, by the system direct memory access device, the virtual address of the destination buffer to the physical address of the destination buffer.

13. The method of claim 11, wherein the data fabric device comprises a miscellaneous function block of a data fabric.

14. The method of claim 11, wherein the first plurality of agent devices and the second plurality of agent devices comprise consistent slaves of a data fabric.

15. The method of claim 11, wherein: the first plurality of agent devices are disposed on the processor die; and the second plurality of agent devices are disposed on a remote processor die.

16. The method of claim 11, wherein: the second plurality of agent devices are disposed on the processor die; and the first plurality of agent devices are disposed on a remote processor die.

17. The method of claim 11, further comprising storing, by each of the first plurality of agent devices, the portion of the source buffer in a local buffer prior to sending the portion of the source buffer to the one of the second plurality of agent devices.

18. The method of claim 11, further comprising communicating, by the first plurality of agent devices and the second plurality of agent devices, over a consistent link between the processor die and a remote processor die.

19. The method of claim 11, further comprising operating, by each of the first plurality of agent devices, a memory controller to read the portion of the source buffer from a memory device at the physical address of the source buffer.

20. The method of claim 11, further comprising broadcasting, by the data structure device, the at least one instruction to the first plurality of agent devices.

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