Display device

Abstract

The display device comprises: a first connecting wiring (21b), which is electrically connected to the first electrode (31) via a first through hole (Hi) formed in the second planarizing film (22); and a second connecting wiring (18i), which is electrically connected to the first connecting wiring (21b) via a second through hole (Hj) formed in the first planarizing film (19), passes through the second interlayer insulating film (20a), overlaps with the first connecting wiring (21b), and is provided with a contact opening portion (M) in a manner that surrounds the first through hole (Hi) and the second through hole (Hj) when viewed from above.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In recent years, as a display device that replaces liquid crystal display devices, self-luminous organic EL display devices using organic electroluminescence (hereinafter referred to as "EL") elements have attracted much attention. This organic EL display device includes, for example: a base substrate; a thin film transistor (hereinafter also referred to as "TFT") layer provided on the base substrate; an organic EL element layer provided on the TFT layer; and a sealing film provided in a manner covering the organic EL element layer. Here, the TFT layer includes, for example, a plurality of TFTs provided on the base substrate and a planarization film provided in a manner covering each TFT. In addition, the organic EL element layer includes, for example: a plurality of first electrodes provided on the planarization film and electrically connected to corresponding TFTs of the TFT layer; an organic EL layer provided on each first electrode; and a second electrode provided to cover each organic EL layer.

[0003] For example, Patent Document 1 discloses a display device including a resin layer provided as a base substrate, a TFT layer provided on the resin layer, and a self-luminous element layer provided as an organic EL element layer on the TFT layer.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-44921 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] In addition, the following structure is proposed: a planarizing film of the TFT layer is formed by a first planarizing film on the lower side and a second planarizing film on the upper side, and a connecting wiring is provided between the first planarizing film and the second planarizing film, and the TFT and the first electrode are electrically connected via the connecting wiring. In this case, in order to form the connecting wiring on the first planarizing film, when the metal film formed on the first planarizing film is patterned by dry etching, the surface of the first planarizing film is also etched, and thus there is a possibility of contaminating the chamber of the dry etching device. Therefore, it is proposed to provide an interlayer insulating film composed of an inorganic insulating film on the first planarizing film, and to provide connecting wiring on the interlayer insulating film to suppress the surface exposure of the first planarizing film. Here, a through hole is provided on the first planarizing film in a manner that reaches the connected wiring of the TFT. In addition, a contact hole is provided in the interlayer insulating film so that the connected wiring exposed from the through hole is exposed. However, when the contact hole is arranged on the outside of the through hole in a planar view, the through hole is side-etched due to the dry etching when the contact hole is formed, so that the side surface of the through hole is formed in an inverted cone shape. This can easily cause disconnection of the connecting wiring within the through-hole due to the step, resulting in poor electrical continuity. Furthermore, when the contact hole is positioned inside the through-hole when viewed from above, the relatively thick first planarizing film made of resin prevents the resist pattern from being formed into the desired shape when the contact hole is formed. Consequently, the contact hole may not reach the connected wiring, resulting in poor electrical continuity in the connecting wiring.

[0009] The present invention has been made in view of this point, and an object thereof is to suppress the occurrence of poor conduction between a connected wiring and a connecting wiring in a stacked structure in which a connected wiring, a planarizing film, an interlayer insulating film, and a connecting wiring are provided in this order.

[0010] Solutions to the Problem

[0011] In order to achieve the above-mentioned object, the display device according to the present invention comprises: a base substrate; a thin film transistor layer having a semiconductor layer, a first wiring layer, and a gate insulating film arranged between the semiconductor layer and the first wiring layer, the thin film transistor layer being arranged on the base substrate and sequentially stacked with the first wiring layer, a first interlayer insulating film, a second wiring layer, a first planarizing film, a second interlayer insulating film, a third wiring layer, and a second planarizing film; a light-emitting element layer being arranged on the thin film transistor layer and sequentially stacked with a plurality of first electrodes, a plurality of light-emitting layers, and a common second electrode corresponding to a plurality of sub-pixels arranged in a matrix to constitute a display area; and a plurality of gate lines being arranged in the display area in a manner extending parallel to each other in a row direction. A wiring layer; a plurality of source lines, which are arranged as the second wiring layer in the above-mentioned display area in a manner extending parallel to each other in the column direction; a first connecting wiring, which is arranged as the third wiring layer in the display area and is electrically connected to the first electrode of each sub-pixel through a first through hole formed in the second planarization film; and a second connecting wiring, which is arranged as the second wiring layer in the display area and is electrically connected to the first connecting wiring through a second through hole formed in the first planarization film in each sub-pixel, and a contact opening portion is provided in the second interlayer insulating film, the contact opening portion passes through the second interlayer insulating film and overlaps with the first connecting wiring, and the periphery surrounds the first through hole and the second through hole when viewed from above.

[0012] Effects of the Invention

[0013] According to the present invention, since a contact opening portion is provided in the second interlayer insulating film, the contact opening portion overlaps with the first connecting wiring and surrounds the first through hole and the second through hole at the periphery when viewed from above, in a stacked structure in which a connected wiring, a planarization film, an interlayer insulating film and a connecting wiring are provided in sequence, the occurrence of poor conduction between the connected wiring and the connecting wiring can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a plan view schematically showing the configuration of an organic EL display device according to the first embodiment of the present invention.

[0015] Figure 2 It is a plan view of a display area of the organic EL display device according to the first embodiment of the present invention.

[0016] Figure 3 It is a plan view of a first wiring layer arranged in the display area of the organic EL display device according to the first embodiment of the present invention.

[0017] Figure 4 It is a plan view of a fourth wiring layer arranged in the display area of the organic EL display device according to the first embodiment of the present invention.

[0018] Figure 5 It is a plan view of a second wiring layer arranged in the display area of the organic EL display device according to the first embodiment of the present invention.

[0019] Figure 6 It is a plan view of a third wiring layer arranged in the display area of the organic EL display device according to the first embodiment of the present invention.

[0020] Figure 7 It is a plan view of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention.

[0021] Figure 8 This is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention.

[0022] Figure 9 It is along Figure 7 A cross-sectional view of an organic EL display device taken along line IX-IX in FIG.

[0023] Figure 10 It means magnification Figure 7 A top view of a first electrode of an organic EL element layer constituting the region Rd in the organic EL display device.

[0024] Figure 11 It is along Figure 10 A cross-sectional view of the TFT layer taken along line XI-XI in FIG.

[0025] Figure 12 It is along Figure 10 A cross-sectional view of the TFT layer along line XII-XII in FIG.

[0026] Figure 13 This is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.

[0027] Figure 14 It will Figure 1 A magnified top view of the region Rx.

[0028] Figure 15 It will Figure 1 The enlarged top view of the area Ry in FIG.

[0029] Figure 16 It is along Figure 15 A cross-sectional view of the TFT layer 30a taken along line XVI-XVI in FIG.

[0030] Figure 17 This is a diagram showing a modified example of the organic EL display device according to the first embodiment of the present invention. Figure 14 Picture. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. However, the present invention is not limited to the following embodiments.

[0032] First Implementation Method

[0033] Figures 1 to 17 The first embodiment of the display device according to the present invention is shown. In the following embodiments, an organic EL display device including an organic EL element is exemplified as a display device including a light-emitting element. Figure 1 : is a plan view showing an organic EL display device 50a of this embodiment. Figure 2 : is a top view of the display area D of the organic EL display device 50a. Figure 3 、 Figure 4 、 Figure 5 and Figure 6 : is a top view of the first wiring layer 14, the fourth wiring layer 16, the second wiring layer 18, and the third wiring layer 21 arranged in the display area D of the organic EL display device 50a. Figure 7 3 is a top view of the TFT layer 30a constituting the organic EL display device 50. Figure 8 : is an equivalent circuit diagram of the TFT layer 30a. Figure 9 It is along Figure 7 1 is a cross-sectional view of the organic EL display device 50a taken along line IX-IX in FIG. Figure 10 It means magnification Figure 7 The region Rd in the organic EL display device 50a is a plan view of the first electrode 31 constituting the organic EL element layer 40. Figure 11 and Figure 12 It is along Figure 10 1 and 2 are cross-sectional views of the TFT layer 30 a taken along lines XI-XI and XII-XII in FIG. Figure 13 3 is a cross-sectional view of the organic EL layer 33 constituting the organic EL display device 50a. Figure 14 as well as Figure 15 It will Figure 1 The top view of the area Rx and the area Ry in FIG. Figure 16 It is along Figure 15 A cross-sectional view of the TFT layer 30a along the XVI-XVI line in FIG. Figure 17 It is a modified example of an organic EL display device equivalent to Figure 14 Picture.

[0034] like Figure 1As shown, the organic EL display device 50a includes, for example, a display area D that is provided in a rectangular shape and displays an image, and a frame area F that is provided around the display area D and is provided in a rectangular frame shape. In this embodiment, the display area D is shown as a rectangular shape, but the rectangle also includes a generally rectangular shape such as a shape with arc-shaped sides, a shape with arc-shaped corners, or a shape with a notch on a portion of the side.

[0035] like Figure 2 As shown in FIG. 1 , in the display area D, a plurality of sub-pixels P are arranged in a matrix. Figure 2 As shown, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are arranged adjacent to each other. Furthermore, in the display area D, for example, three adjacent sub-pixels P having the red light-emitting region Er, the green light-emitting region Eg, and the blue light-emitting region Eb constitute one pixel.

[0036] In the border area F Figure 1 At the middle and lower end, the terminal portion T is arranged to extend in one direction (the X direction in the figure). Figure 1 As shown, in the frame region F, between the display region D and the terminal portion T, a bent portion B is provided extending in one direction (the X direction in the figure) and capable of being bent 180° (U-shaped) with the X direction in the figure as the bending axis. Figure 1 As shown, in the first planarizing film 19 and the second planarizing film 22 described later, a groove G having a substantially C-shape in a planar view is provided to penetrate the first planarizing film 19 and the second planarizing film 22. Figure 1 As shown, the groove G is formed in a substantially C-shape so as to be open on the terminal portion T side in a plan view.

[0037] like Figure 9 As shown, the organic EL display device 50a includes: a resin substrate layer 10, which serves as a base substrate; a TFT layer 30a, which is arranged on the resin substrate layer 10; an organic EL element layer 40, which serves as a light-emitting element layer and is arranged on the TFT layer 30a; and a sealing film 45, which is arranged to cover the organic EL element layer 40.

[0038] The resin substrate layer 10 is made of, for example, polyimide resin.

[0039] like Figure 9As shown, the TFT layer 30a includes an undercoat film 11, a semiconductor layer 12a, a gate insulating film 13, a first wiring layer 14, a lower first interlayer insulating film 15, a fourth wiring layer 16, an upper first interlayer insulating film 17, a second wiring layer 18, a first planarizing film 19, a second interlayer insulating film 20a, a third wiring layer 21, and a second planarizing film 22, which are sequentially stacked on the resin substrate layer 10. Figure 7 and Figure 8 As shown, the TFT layer 30a includes a first initialization TFT 9a, a threshold voltage compensation TFT 9b, a write control TFT 9c, a drive TFT 9d, a power supply TFT 9e, a light emission control TFT 9f, a second initialization TFT 9g, and a capacitor 9h, which are provided for each sub-pixel P on the base coat film 11. Figure 2 and Figure 3 As shown, the TFT layer 30a includes a plurality of gate lines 14g provided on the gate insulating film 13 as the first wiring layer 14 extending parallel to each other in the row direction (X direction in the figure) in the display region D. Figure 2 and Figure 3 As shown, the TFT layer 30a includes a plurality of light emission control lines 14e provided on the gate insulating film 13 as the first wiring layer 14 extending parallel to each other in the row direction (X direction in the figure) in the display area D. Figure 2 and Figure 3 As shown, each light emitting control line 14e is arranged adjacent to each gate line 14g. Figure 2 and Figure 4 As shown, the TFT layer 30a includes a plurality of initialization power supply lines 16i provided as a fourth wiring layer 16 on the lower first interlayer insulating film 15 so as to extend parallel to each other in the row direction (X direction in the figure) in the display region D. Figure 2 and Figure 4 As shown, the TFT layer 30a includes a plurality of third power supply lines 16c provided as a fourth wiring layer 16 on the lower first interlayer insulating film 15 so as to extend in parallel to each other in the row direction (X direction in the figure) in the display region D. Figure 4 As shown, each third power line 16c is arranged adjacent to each initialization power line 16i. Figure 2 and Figure 5 As shown, the TFT layer 30a includes a plurality of source lines 18f provided as the second wiring layer 18 on the upper first interlayer insulating film 17 in the display region D so as to extend in parallel to each other in the column direction (Y direction in the figure). Figure 2 and Figure 5As shown, the TFT layer 30a includes a plurality of second power supply lines 18g provided as a second wiring layer 18 on the upper first interlayer insulating film 17 in a manner extending parallel to each other along the column direction (Y direction in the figure) in the display area D. Figure 2 as well as Figure 5 As shown, each second power supply line 18g is arranged adjacent to the source line 18f. Figure 16 As shown, the plurality of second power supply lines 18g and the plurality of third power supply lines 16c are electrically connected in each sub-pixel P via the eighth contact hole Hh formed in the upper first interlayer insulating film 17. Figure 6 As shown, the TFT layer 30a includes a plurality of first power supply lines 21aa provided on the upper second interlayer insulating film 20a as the third wiring layer 21 extending in parallel to each other along the column direction (Y direction in the figure). Figure 10 as well as Figure 12 As shown, the plurality of first power supply lines 21aa and the plurality of second power supply lines 18g are electrically connected in each sub-pixel P via the third through hole Hk formed in the first planarization film 19. Figure 6 As shown, the TFT layer 30a includes a plurality of other first power supply lines 21aa extending in parallel to each other in the row direction (X direction in the figure) and provided on the second interlayer insulating film 20a as the third wiring layer 21. Figure 6 As shown, multiple first power lines 21a and multiple other first power lines 21a are integrally arranged in a grid pattern. Here, the first wiring layer 14, the fourth wiring layer 16, the second wiring layer 18, and the third wiring layer 21 are formed, for example, from a single metal layer of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or tungsten (W), or a metal stacked film of Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, or Cu / Ti. Furthermore, the first wiring layer 14 and the fourth wiring layer 16 are preferably formed from the same material. Furthermore, the second wiring layer 18 and the third wiring layer 21 are preferably formed from the same material. Furthermore, the undercoat film 11, the gate insulating film 13, the lower first interlayer insulating film 15, the upper and lower second interlayer insulating films 17, and the second interlayer insulating film 20a are formed from a single layer or stacked film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride. The semiconductor layer 12a is composed of, for example, a low-temperature polysilicon film or an In-Ga-Zn-O-based oxide semiconductor film. Furthermore, the first planarizing film 19, the second planarizing film 22, and the edge mask described later are composed of, for example, an organic resin material such as a polyimide resin. Furthermore, in this embodiment, a configuration in which the fourth wiring layer 16 is provided between the lower first interlayer insulating film 15 and the upper first interlayer insulating film 17 is illustrated, but the fourth wiring layer 16 (and the upper first interlayer insulating film 17) may also be omitted.

[0040] The first initialization TFT 9a, the threshold voltage compensation TFT 9b, the write control TFT 9c, the drive TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, and the second initialization TFT 9g each have a first terminal disposed separately from each other (see Figure 8 Na in) and the second terminal (refer to Figure 8 The first terminal and the second terminal of each TFT 9a to 9g are the conductive regions of the semiconductor layer 12a.

[0041] like Figure 8 As shown, in each sub-pixel P, the control terminal of the first initialization TFT 9a is electrically connected to the corresponding gate line 14g, the first terminal electrode thereof is electrically connected to the gate 14a of the capacitor 9h described later, and the second terminal electrode thereof is electrically connected to the corresponding initialization power supply line 16i. Figure 7 As shown, the control terminal of the first initialization TFT 9a is two portions overlapping with the semiconductor layer 12a of the gate line 14g. Figure 7 and Figure 9 As shown, the first terminal of the first initialization TFT 9a is electrically connected to the gate 14a of the capacitor 9h via the third contact hole Hc formed in the gate insulating film 13, the lower first interlayer insulating film 15, and the upper first interlayer insulating film 17, the third connection wiring 18e, and the first contact hole Ha formed in the lower first interlayer insulating film 15 and the upper first interlayer insulating film 17. Figure 7 As shown, the second terminal of the first initialization TFT 9a is electrically connected to the initialization power supply line 16i via a fourth contact hole Hd formed in the gate insulating film 13, the lower first interlayer insulating film 15, and the upper first interlayer insulating film 17, a fourth connecting wiring 18k, and a fifth contact hole He formed in the upper first interlayer insulating film 17. Here, the first initialization TFT 9a is configured so that the voltage applied to the control terminal of the drive TFT 9d is initialized by applying the voltage of the initialization power supply line 16i to the capacitor 9h. Furthermore, the first initialization TFT 9a is electrically connected to the gate line 14g(n-1), which is scanned before the gate line 14g(n) electrically connected to the control terminals of the threshold voltage compensation TFT 9b and the write control TFT 9c.

[0042] like Figure 8 As shown, in each sub-pixel P, the threshold voltage compensation TFT 9b has its control terminal electrically connected to the corresponding gate line 14g, its first terminal electrically connected to the second terminal of the driving TFT 9d, and its second terminal electrically connected to the control terminal of the driving TFT 9d. Figure 7As shown in FIG. 1 , the control terminal of the threshold voltage compensation TFT 9b is two portions overlapping with the semiconductor layer 12a of the gate line 14g. Figure 7 As shown in FIG. 1 , the first terminal of the threshold voltage compensation TFT 9b is integrally formed with the second terminal of the driving TFT 9d and is electrically connected to the second terminal of the driving TFT 9d. Figure 7 As shown, the second terminal of the threshold voltage compensating TFT 9b is electrically connected to the gate 14a of the driving TFT 9d via the third contact hole Hc, the third connecting wiring 18e, and the first contact hole Ha. Here, the threshold voltage compensating TFT 9b is configured to place the driving TFT 9d in a diode connection state in response to selection of the gate line 14g, thereby compensating the threshold voltage of the driving TFT 9d.

[0043] like Figure 8 As shown, in each sub-pixel P, the control terminal of the write control TFT 9c is electrically connected to the corresponding gate line 14g, the first terminal thereof is electrically connected to the corresponding source line 18f, and the second terminal thereof is electrically connected to the first terminal of the drive TFT 9d. Figure 7 As shown in FIG. 1 , the control terminal of the write control TFT 9c is a portion overlapping with the semiconductor layer 12a of the gate line 14g. Figure 7 As shown, the first terminal of the write control TFT 9c is electrically connected to the source line 18f via a sixth contact hole Hf formed in the gate insulating film 13, the lower first interlayer insulating film 15, and the upper first interlayer insulating film 17. Figure 7 As shown, the second terminal of the write control TFT 9c is integrally formed with the first terminal of the drive TFT 9d and is electrically connected to the first terminal of the drive TFT 9d. Here, the write control TFT 9c is configured to apply the voltage of the source line 18f to the first terminal of the drive TFT 9d according to the selection of the gate line 14g.

[0044] like Figure 8 As shown, in each subpixel P, the drive TFT 9d has a control terminal electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b, a first terminal electrically connected to the second terminals of the write control TFT 9c and the power supply TFT 9e, and a second terminal electrically connected to the first terminals of the threshold voltage compensation TFT 9b and the emission control TFT 9f. The drive TFT 9d is configured to apply a drive current corresponding to the voltage applied between its control terminal and its first terminal to the first terminal of the emission control TFT 9f, thereby controlling the current flowing through the organic EL element 35.

[0045] More specifically, if Figure 7 and Figure 9As shown, the driving TFT 9d includes a semiconductor layer 12a, a gate insulating film 13, a gate (control terminal) 14a, a lower first interlayer insulating film 15, and an upper first interlayer insulating film 17, which are sequentially provided on the base coat film 11. Figure 7 and Figure 9 As shown, the semiconductor layer 12a is provided in a curved shape on the base coat film 11. In addition, the semiconductor layer 12a includes an intrinsic region provided so as to overlap with the gate electrode 14a in a plan view and a pair of conductor regions provided so as to sandwich the intrinsic region. Figure 7 As shown in FIG, the middle portion of the intrinsic region is set to be roughly V-shaped when viewed from above. Figure 7 As shown, a conductive region of the semiconductor layer 12a is provided as a first terminal integrally formed with each second terminal of the write control TFT 9c and the power supply TFT 9e, and is electrically connected to each second terminal of the write control TFT 9c and the power supply TFT 9e. Figure 7 As shown, another conductive region of the semiconductor layer 12a is provided as a second terminal integrally formed with each first terminal of the threshold voltage compensation TFT 9b and the emission control TFT 9f, and is electrically connected to each first terminal of the threshold voltage compensation TFT 9b and the emission control TFT 9f. Figure 9 As shown in FIG. 1 , the gate insulating film 13 is provided so as to cover the semiconductor layer 12a. Figure 7 and Figure 9 As shown in FIG. 1 , the gate electrode 14a is provided as the first wiring layer 14 on the gate insulating film 13 in a rectangular island shape when viewed from above so as to overlap with the intrinsic region of the semiconductor layer 12a. Figure 9 As shown in FIG. 1 , the lower first interlayer insulating film 15 is provided so as to cover the gate electrode 14a. Figure 9 As shown, the upper first interlayer insulating film 17 is provided on the lower first interlayer insulating film 15 via the third power supply line 16 c.

[0046] like Figure 8 As shown, in each sub-pixel P, the power supply TFT 9e has a control terminal electrically connected to the corresponding light emission control line 14e, a first terminal electrically connected to the corresponding second power supply line 18g, and a second terminal electrically connected to the first terminal of the driving TFT 9d. Figure 7 As shown in FIG. 1 , the control terminal of the power supply TFT 9e is a portion overlapping with the semiconductor layer 12a of the light emitting control line 14e. Figure 7 As shown, the first terminal of the power supply TFT 9e is electrically connected to the second power supply line 18g via a second contact hole Hb formed in the gate insulating film 13, the lower first interlayer insulating film, and the upper first interlayer insulating film 17. Figure 7As shown, the second terminal of the power supply TFT 9e is integrally formed with the first terminal of the driving TFT 9d and is electrically connected to the first terminal of the driving TFT 9d. Here, the power supply TFT 9e is configured to apply the voltage of the power supply line 18g to the first terminal of the driving TFT 9d in response to the selection of the light emission control line 14e.

[0047] like Figure 8 As shown, in each sub-pixel P, the control terminal of the light-emitting control TFT 9f is electrically connected to the corresponding light-emitting control line 14e, the first terminal thereof is electrically connected to the second terminal of the driving TFT 9d, and the second terminal thereof is electrically connected to the first electrode 31 of the organic EL element 35 described later. Figure 7 As shown, the control terminal of the light emission control TFT 9f is the portion overlapping with the semiconductor layer 12a of the light emission control line 14e. Figure 7 As shown in FIG. 1 , the first terminal of the light emission control TFT 9f is integrally formed with the second terminal of the driving TFT 9d and is electrically connected to the second terminal of the driving TFT 9d. Figure 7 As shown, the second terminal of the light emission control TFT 9f is electrically connected to the first electrode 31 of the organic EL element 35 via a seventh contact hole Hg formed in the gate insulating film 13, the lower first interlayer insulating film 15, and the upper first interlayer insulating film 17, and a second connecting wiring 18j provided as the second wiring layer 18. Here, the light emission control TFT 9f is configured to apply the driving current to the organic EL element 35 in accordance with the selection of the light emission control line 14e.

[0048] like Figure 8 As shown, the second initialization TFT 9g in each sub-pixel P has its control terminal electrically connected to the corresponding gate line 14g, its first terminal electrically connected to the first electrode 31 of the organic EL element 35, and its second terminal electrically connected to the corresponding initialization power supply line 16i. Figure 7 As shown, the control terminal of the second initialization TFT 9g is two portions overlapping with the semiconductor layer 12a of the gate line 14g. Figure 7 As shown, the first terminal of the second initialization TFT 9g is integrally formed with the second terminal of the light emission control TFT 9f and is electrically connected to the first electrode 31 of the organic EL element 35. Figure 7 As shown, the second terminal of the second initialization TFT 9g is electrically connected to the initialization power supply line 16i via the fourth contact hole Hd, the fourth connection wiring 18k, and the fifth contact hole He. Here, the second initialization TFT 9g is configured to reset the charge accumulated in the first electrode 31 of the organic EL element 35 according to the selection of the gate line 14g.

[0049] In addition, in this embodiment, although the top-gate type TFTs 9 a to 9 g are exemplified, the TFTs 9 a to 9 g may be bottom-gate type TFTs.

[0050] Here, if Figure 7 as well as Figure 9 As shown, the capacitor 9h includes: a gate 14a; a lower first interlayer insulating film 15 provided on the gate 14a; and a third power supply line 16c provided on the lower first interlayer insulating film 15 so as to overlap with the gate 14a in a plan view. Figure 7 and Figure 8 As shown, in each sub-pixel P, the capacitor 9h has a gate 14a integrally formed with the gate 14a of the driving TFT 9d, and is electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b. The third power supply line 16c is electrically connected to the corresponding second power supply line 18g via the eighth contact hole Hh formed in the upper first interlayer insulating film 17. Here, the capacitor 9h is configured to store electricity at the voltage of the corresponding source line 18f when the corresponding gate line 14g is in the selected state, and by maintaining the stored voltage, the voltage applied to the gate 14a of the driving TFT 9d is maintained when the corresponding gate line 14g is in the unselected state. In addition, as shown in FIG. Figure 7 As shown in FIG. 1 , the third power supply line 16c is provided over the entire periphery of the gate 14a to the outside of the periphery of the gate 14a. Figure 7 as well as Figure 9 As shown, a through hole A is provided on the third power line 16c so as to overlap with the gate 14a in a plan view and penetrate the third power line 16c. Figure 9 As shown in FIG. 1 , an upper first interlayer insulating film 17 is provided so as to cover the third power supply line 16c. Figure 7 as well as Figure 9 As shown, the gate electrode 14a is electrically connected to a third connection wiring 18e provided as the second wiring layer 18 via a first contact hole Ha.

[0051] The organic EL element layer 40 is composed of a plurality of organic EL elements 35 arranged in a matrix. Figure 9 As shown, a plurality of first electrodes 31 , a plurality of organic EL layers 33 , and a second electrode 34 are sequentially stacked on a TFT layer 30 a .

[0052] like Figure 9 and Figure 10 As shown in FIG. 1 , a plurality of first electrodes 31 are arranged in a matrix on the second planarization film 22 in a manner corresponding to a plurality of sub-pixels. Figure 11As shown, in each sub-pixel P, the first electrode 31 is electrically connected to the second connection wiring 18j via the first through hole Hi formed in the second planarizing film 22, the first connection wiring 21b provided as the third wiring layer 21, and the second through hole Hj formed in the first planarizing film 19. Figure 10 and Figure 11 As shown, in the second interlayer insulating film 20a, a contact opening M is provided which penetrates the second interlayer insulating film 20a, overlaps with the first connection wiring 21b, and surrounds the first through hole H1 and the second through hole Hj in a plan view. Figure 10 as well as Figure 12 As shown, in the second interlayer insulating film 20a, column slits Sy are provided through the second interlayer insulating film 20a from one end to the other end of the display region D in such a manner as to overlap with each first power supply line 21a. Figure 10 as well as Figure 11 As shown, a row slit Sx is provided in the second interlayer insulating film 20a, extending from one end of the display area D to the other, overlapping with each other first power supply line 21a. Furthermore, the first electrode 31 has the function of injecting holes into the organic EL layer 33. Furthermore, to improve the efficiency of hole injection into the organic EL layer 33, the first electrode 31 is preferably formed of a material with a high work function. Examples of materials for the first electrode 31 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), Yb, lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Alternatively, the material for the first electrode 31 may be an alloy such as astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 31 may be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Furthermore, the first electrode 31 may be formed by stacking multiple layers of the above-mentioned materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO). Furthermore, the peripheral end portion of the first electrode 31 is covered by a lattice-shaped edge cover 22 that is common to multiple sub-pixels P.

[0053] like Figure 9 As shown in FIG. 1 , a plurality of organic EL layers 33 are arranged on each first electrode 31 and are arranged in a matrix as light-emitting layers in a manner corresponding to a plurality of sub-pixels P. Figure 13As shown, each organic EL layer 33 includes a hole injection layer 1 , a hole transport layer 2 , a light emitting layer 3 , an electron transport layer 4 and an electron injection layer 5 which are sequentially provided on the first electrode 31 .

[0054] The hole injection layer 1, also called an anode buffer layer, brings the energy levels of the first electrode 31 and the organic EL layer 33 closer together, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0055] The hole transport layer 2 has a function of improving the efficiency of hole transport from the first electrode 31 to the organic EL layer 33. Examples of the material for the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, phenylethylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, aromatic amine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0056] The organic light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, when a voltage is applied to the first electrode 31 and the second electrode 34, and the holes and electrons recombine. The organic light-emitting layer 3 is formed of a material with high luminous efficiency. Examples of materials constituting the organic light-emitting layer 3 include metal hydroxyquinolinone compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, stilbene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, phenylethylamine derivatives, bisstyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazine, quinacridone derivatives, rubrene, poly(p-phenylene vinylene), and polysilane.

[0057] The electron transport layer 4 has the function of efficiently transferring electrons to the organic light-emitting layer 3. Here, examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, dibenzoquinone derivatives, fluorenone derivatives, silole derivatives, and metallohydroxyquinolinone compounds.

[0058] The electron injection layer 5 is close to the energy level of the second electrode 34 and the organic EL layer 33, and has the function of improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. This function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Examples of materials constituting the electron injection layer 5 include inorganic base compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), aluminum oxide (Al2O3), and strontium oxide (SrO).

[0059] like Figure 9 As shown, the second electrode 34 is common to multiple sub-pixels P and is provided to cover each organic EL layer 33 and the edge mask. Furthermore, the second electrode 34 has the function of injecting electrons into each organic EL layer 33. Furthermore, to improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is preferably formed of a material with a low work function. Examples of materials for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Alternatively, the second electrode 34 may be formed of, for example, an alloy of magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Alternatively, the second electrode 34 may be formed of, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Alternatively, the second electrode 34 may be formed by stacking multiple layers of the above materials. In addition, as materials with a small work function, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0060] like Figure 9As shown, the sealing film 45 includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43, which are provided in sequence to cover the second electrode 34 and protect the organic EL layer 33 of the organic EL element 35 from moisture and oxygen. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 are composed of, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. The organic sealing film 42 is composed of, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

[0061] In addition, if Figure 1 As shown, the organic EL display device 50a includes, in the frame region F, a first barrier wall Wa provided in a frame shape outside the groove G and a second barrier wall Wb provided in a frame shape around the first barrier wall Wa.

[0062] The first barrier wall Wa and the second barrier wall Wb are formed by laminating a plurality of resin layers, for example, a resin layer formed on the same layer with the same material as the first planarizing film 19 and a resin layer formed on the same layer with the same material as the second planarizing film 22. Furthermore, the first barrier wall Wa is provided so as to overlap with the peripheral end portion of the organic sealing film 42 of the sealing film 45, thereby suppressing the diffusion of the ink forming the organic sealing film 42.

[0063] In addition, if Figure 1 As shown, in the organic EL display device 50a, a second wiring layer 18 is provided in a frame shape inside the groove G in the frame region F, and both ends of the opening of the groove G are provided with first frame wiring 18m extending toward the terminal portion T. Here, the first frame wiring 18m is configured to input a high voltage (ELVDD) to the terminal portion T. In addition, as shown in FIG. Figure 1 As shown, the first frame wiring 18m includes: a second trunk wiring 18mx, which is provided in a manner overlapping with the first trunk wiring 21mx described later; and other second trunk wiring 18my, which is provided in a manner overlapping with other first trunk wiring 21my described later. Figure 14 As shown, the second trunk wiring 18mx branches into a plurality of second power supply lines 18g on the display area D side. In addition, the first trunk wiring 21mx is provided as the third wiring layer 21 in the frame area F so as to extend in the row direction (X direction in the figure). Figure 14 As shown in FIG. 1 , the first trunk wiring 12mx branches into a plurality of first power supply lines 21aa on the display region D side. Figure 14 As shown in FIG. 1 , a trunk slit Smx is provided on the second interlayer insulating film 20a in such a manner as to overlap with the first trunk wiring 12mx. Figure 14 As shown in FIG. 1 , the first trunk wiring 21mx and the second trunk wiring 18mx are electrically connected to each other via the fourth through hole Hn formed in the first planarizing film 19. Figure 15 As shown in FIG. 1 , the other first trunk wiring 21my is provided as the third wiring layer 21 in the frame region F so as to extend in the column direction (X direction in the figure). Figure 15 As shown in FIG. 1 , the other first trunk wiring 12my branches into a plurality of other first power supply lines 21ab on the display area D side. Figure 15 and Figure 16 As shown in FIG. 1 , a trunk slit Smy is provided on the second interlayer insulating film 20a in such a manner as to overlap with other first trunk wirings 12my. Figure 5 and Figure 16 As shown, the other first trunk wiring 21my and the other second trunk wiring 18my are electrically connected to each other via the fifth through hole Ho formed in the first planarization film 19. Figure 15 as well as Figure 16 As shown, the other second trunk wiring 18my is electrically connected to the third power supply line 16c via the tenth contact hole Hp formed in the upper first interlayer insulating film 17. In addition, in this embodiment, the structure of the trunk wiring not composed of the fourth wiring layer 16 is exemplified, but the initialization power supply line 16i may not be arranged in the frame area F, and the third trunk wiring 16m may be provided as the fourth wiring layer 16 in the frame area F so as to overlap with the other first trunk wiring 21my (see Figure 15 The third trunk wiring 16m is branched into a plurality of third power supply lines 16c on the display area D side. In addition, in this embodiment, a wiring structure including a first trunk wiring 21mx, a second trunk wiring 18mx, another first trunk wiring 21my, and another second trunk wiring 18my is exemplified, but if Figure 17 As shown, the first trunk wiring 21mx and the second trunk wiring 18mx (other first trunk wiring 21my and other second trunk wiring 18my) may be omitted.

[0064] In addition, if Figure 1 As shown, the organic EL display device 50a includes a second frame wiring 18i in the frame region F. The second frame wiring 18i is provided in a substantially C-shape as a second wiring layer 18 outside the groove G, with both ends extending to the terminal portion T. Here, the second frame wiring 18i is electrically connected to the second electrode 34 via, for example, a conductive layer provided in the groove G as a third wiring layer 21, and a low power supply voltage (ELVSS) is input to the terminal portion T.

[0065] In the organic EL display device 50a having the above structure, in each sub-pixel P, first, when the corresponding light emission control line 14e is selected and becomes the non-active state, the organic EL element 35 becomes the non-light emission state. In this non-light emission state, the gate line 14g corresponding to (electrically connected to the first initialization TFT 9a and the second initialization TFT 9g) is selected, and the gate signal is input to the first initialization TFT 9a via the gate line 14g, so that the first initialization TFT 9a and the second initialization TFT 9g become the conducting state, the voltage of the corresponding initialization power supply line 16i is applied to the capacitor 9h, and the driving TFT 9d becomes the conducting state. Thereby, the charge of the capacitor 9h is discharged, and the voltage applied to the control terminal (first gate) 14a of the driving TFT 9d is initialized. Next, by selecting the gate line 14g corresponding to (electrically connected to the threshold voltage compensation TFT 9b and the write control TFT 9c) to become the active state, the threshold voltage compensation TFT 9b and the write control TFT 9c become the conducting state, and the prescribed voltage corresponding to the source signal conveyed via the corresponding source line 18f is written into the capacitor 9h via the driving TFT 9d in the diode-connected state, and the initialization signal is applied to the first electrode 具有上述结构的有机EL显示装置50a中,在各子像素P中,首先,当选择对应的发光控制线并且成为非激活状态时,有机EL元件35成为非发光状态。在该非发光状态下,选择与(电连接于第一初始化TFT9a与第二初始化TFT9g)对应的栅极线,栅极信号经由该栅极线被输入到第一初始化TFT9a,从而第一初始化TFT9a与第二初始化TFT9g成为导通状态,对应的初始化电源线的电压被施加于电容器9h,并且驱动TFT9d成为导通状态。由此,电容器9h的电荷被放电,施加于驱动TFT9d的控制端子(第一栅极)的电压被初始化。接着,通过选择(电连接于阈值电压补偿TFT9b与写入控制TFT9c)对应的栅极线成为激活状态,阈值电压补偿TFT9b及写入控制TFT9c成为导通状态,与经由对应的源极线传达的源极信号对应的规定电压经由二极管连接状态下的驱动TFT9d写入电容器9h,经由对应的初始化电源线向有机EL元件35的第一电极施加初始化信号,在第一电极蓄积的电荷被复位。然后,所对应的发光控制线被选择,电源供给TFT9e和发光控制TFT9f成为导通状态,与施加于驱动TFT9d的控制端子(栅极)的电压相应的驱动电流从对应的电源线供给有机EL元件35。这样,在有机EL显示装置50a中,在各子像素P中,有机EL元件35以对应于驱动电流的亮度发光,进行图像显示。

[0066] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. In addition, the method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer forming step, an organic EL element forming step, and a sealing film forming step.

[0067] <TFT layer forming step>

[0068] First, for example, by a plasma CVD (Chemical Vapor Deposition) method, an inorganic insulating film such as a silicon oxide film (with a thickness of about 1000 nm) is formed on the resin substrate layer 10 formed on the glass substrate, thereby forming the undercoat film 11.

[0069] Next, using the plasma CVD method, an amorphous silicon film (thickness of about 50 nm) is formed on the entire substrate on which the base coating film 11 is formed. The amorphous silicon film is crystallized by laser annealing, etc. to form a semiconductor film of a polycrystalline silicon film. The semiconductor film is then patterned to form a semiconductor layer 12a.

[0070] Thereafter, an inorganic insulating film (about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the semiconductor layer 12 a and the like are formed by, for example, plasma CVD, to form the gate insulating film 13 covering the semiconductor layer 12 a.

[0071] In addition, for example, after an aluminum film (thickness of about 350 nm) and a molybdenum nitride film (thickness of about 50 nm) are formed in sequence on the entire substrate forming the gate insulating film 13 by a sputtering method, these metal stacked films are patterned to form a first wiring layer 14 such as a gate line 14g.

[0072] Next, impurity ions are doped using the first wiring layer 14 as a mask, thereby forming an intrinsic region and a conductor region on the semiconductor layer 12 a .

[0073] Then, an inorganic insulating film (about 100 nm thick) such as a silicon oxide film is formed on the entire substrate including the semiconductor layer 12 a having the intrinsic region and the conductor region by plasma CVD, thereby forming the lower first interlayer insulating film 15 .

[0074] Next, on the entire substrate with the first interlayer insulating film 15 on the lower side, an aluminum film (thickness of about 350nm) and a molybdenum nitride film (thickness of about 50nm) are formed in sequence, for example by sputtering, and then the metal stack film is patterned to form a fourth wiring layer 16 such as a third power line 16c.

[0075] Furthermore, an inorganic insulating film (about 500 nm thick) such as a silicon oxide film is formed on the entire substrate on which the fourth wiring layer 16 is formed by, for example, plasma CVD, thereby forming the upper first interlayer insulating film 17 .

[0076] Then, the upper first interlayer insulating film 17 , the lower first interlayer insulating film 15 , and the gate insulating film 13 are patterned to form contact holes Ha and the like.

[0077] Next, for example, a titanium film (thickness of about 30 nm), an aluminum film (thickness of about 300 nm) and a titanium film (thickness of about 50 nm) are formed in sequence on the entire substrate with the contact hole Ha formed thereon using a sputtering method, and then these metal stacked films are patterned to form a second wiring layer 18 such as the source line 18f.

[0078] Finally, a polyimide-based photosensitive resin film (about 2 μm thick) is coated on the entire substrate on which the second wiring layer 18 is formed, for example, by spin coating or slit coating, and then the coated film is pre-baked, exposed, developed and post-baked to form a first planarizing film 19 having through holes Hj, etc.

[0079] Thereafter, an inorganic insulating film (about 500 nm thick) such as a silicon oxide film is formed on the entire substrate having the first planarizing film 19 formed thereon by plasma CVD, for example, and then patterned to form the second interlayer insulating film 20 a .

[0080] Next, for example, a titanium film (thickness of about 30 nm), an aluminum film (thickness of about 300 nm) and a titanium film (thickness of about 50 nm) are formed in sequence on the entire substrate on which the second interlayer insulating film 20a is formed using a sputtering method. Then, these metal stacked films are patterned to form a third wiring layer 21 such as the first power line 21a.

[0081] Finally, a polyimide-based photosensitive resin film (about 2 μm thick) is coated on the entire substrate on which the third wiring layer 21 is formed, for example, by spin coating or slit coating, and then the coated film is pre-baked, exposed, developed and post-baked to form a second planarizing film 22 having through holes Hi, etc.

[0082] As described above, the TFT layer 30 a can be manufactured.

[0083] <Organic EL element formation process>

[0084] By using a known method, a first electrode 31, an edge cover, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, organic light-emitting layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 34 are formed on the second planarization film 22 of the TFT layer 30a formed in the above-mentioned TFT layer formation process to form an organic EL element layer 40.

[0085] <Sealing Film Forming Step>

[0086] A sealing film 45 (a first sealing inorganic insulating film 41, a sealing organic film 42, and a second sealing inorganic insulating film 43) is formed on the organic EL element layer 40 formed in the above-described organic EL element layer forming step using a known method. Finally, a protective sheet (not shown) is attached to the substrate surface on which the sealing film 45 is formed. Laser irradiation is then performed from the glass substrate side of the resin substrate layer 10 to peel the glass substrate from the lower surface of the resin substrate layer 10. Furthermore, a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled.

[0087] As described above, the organic EL display device 50 a of this embodiment can be manufactured.

[0088] As described above, according to the organic EL display device 50a of this embodiment, a contact opening M is provided in the second interlayer insulating film 20a, penetrating the second interlayer insulating film 20a, overlapping the first connecting wiring 21b, and surrounding the first through-hole Hi and the second through-hole Hj in a plan view. Consequently, even if the first connecting wiring 21b breaks due to a step around the contact opening M, the first connecting wiring 21b will not break between the first through-hole Hi and the second through-hole Hj, thereby ensuring electrical continuity between the first through-hole Hi and the second through-hole Hj. Furthermore, because the contact opening M is larger than the first through-hole Hi and the second through-hole Hj in a plan view, the first connecting wiring 21b can reliably contact the second connecting wiring 18j. Consequently, in a stacked structure comprising the second connecting wiring 18j (connected wiring), the first planarizing film 19, the second interlayer insulating film 20a, and the first connecting wiring 21b (connecting wiring), electrical continuity failure between the second connecting wiring 18j and the first connecting wiring 21b can be suppressed.

[0089] In addition, according to the organic EL display device 50a of this embodiment, since the periphery of the contact opening portion M provided in the second interlayer insulating film 20a surrounds the first through hole Hi and the second through hole Hj, during the manufacturing process, moisture and the like contained in the first planarizing film 19 can be easily discharged to the outside, thereby improving the reliability of the organic EL element 35.

[0090] Other Implementation Methods

[0091] In the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified, but the organic EL layer may also be a three-layer stacked structure of, for example, a hole injection layer serving as a hole transport layer, a light-emitting layer, and an electron transport layer serving as an electron injection layer.

[0092] In addition, in the above embodiment, an organic EL display device is illustrated in which the first electrode is set as an anode and the second electrode is set as a cathode, but the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is set as a cathode and the second electrode is set as an anode.

[0093] Furthermore, in the above embodiments, an organic EL display device is used as an example of a display device. However, the present invention can also be applied to a display device including multiple light-emitting elements driven by current. For example, it can be applied to a display device including a QLED (quantum-dot light emitting diode) light-emitting element using a quantum dot layer.

[0094] As described above, the present invention can be used in a flexible organic EL display device.

[0095] Description of Reference Numerals

[0096] D Display area

[0097] Hh eighth contact hole

[0098] Hi First Via

[0099] Hj Second through hole

[0100] Hk Third through hole

[0101] M contact opening

[0102] P sub-pixel

[0103] Smx trunk slit

[0104] Smy other trunk slits

[0105] Sx row slit

[0106] Sy column slits

[0107] 10 Resin substrate layer (base substrate)

[0108] 12a Semiconductor layer

[0109] 13 Gate insulating film

[0110] 14 First wiring layer

[0111] 14g gate line

[0112] 15 Lower side first interlayer insulation layer

[0113] 16 Fourth wiring layer

[0114] 16c Third power cord

[0115] 16m third backbone cabling

[0116] 17 Upper side first interlayer insulation layer

[0117] 18 Second wiring layer

[0118] 18f source line

[0119] 18g second power cable

[0120] 18j Second connection wiring

[0121] 18mx Secondary Backbone Cabling

[0122] 18my Other second backbone cabling

[0123] 19. First planarization film

[0124] 20a, 20ba, 20bb, 20ca, 20cb Second interlayer insulating film

[0125] 21 Third wiring layer

[0126] 21aa First power cord

[0127] 21ab Other first power cord

[0128] 21b First connecting wiring

[0129] 21mx first backbone cabling

[0130] 21my Other first backbone cabling

[0131] 22 Second planarization film

[0132] 30a, 30b, 30c TFT layer

[0133] 31 first electrode

[0134] 33 organic light-emitting layer (light-emitting layer)

[0135] 34 Second electrode

[0136] 40 Organic EL element layer (light-emitting element layer)

[0137] 50a Organic EL display device

Claims

1. A display device comprising: a base substrate; a thin film transistor layer comprising a semiconductor layer, a first wiring layer, and a gate insulating film disposed between the semiconductor layer and the first wiring layer, the thin film transistor layer being disposed on the base substrate and sequentially stacked with the first wiring layer, a first interlayer insulating film, a second wiring layer, a first planarizing film, a second interlayer insulating film, a third wiring layer, and a second planarizing film; a light-emitting element layer provided on the thin film transistor layer, wherein a plurality of first electrodes, a plurality of light-emitting layers, and a common second electrode are sequentially stacked corresponding to a plurality of sub-pixels arranged in a matrix to form a display area; a plurality of gate lines arranged in the first wiring layer in the display area so as to extend parallel to each other along a row direction; a plurality of source lines provided in the second wiring layer in the display area so as to extend parallel to each other in a column direction; a plurality of first power supply lines provided in the third wiring layer in the display area so as to extend parallel to each other in a column direction; The display device is characterized in that a column of slits is provided in the second interlayer insulating film, the column of slits penetrates the second interlayer insulating film, spans from one end of the display area to the other end and overlaps with the plurality of first power lines. In the display area, a plurality of second power supply lines are provided in the second wiring layer so as to extend parallel to each other in a column direction. The plurality of first power lines and the plurality of second power lines are electrically connected via third through holes formed in the first planarization film.

2. The display device according to claim 1, wherein In the display area, a plurality of other first power supply lines are provided in the third wiring layer so as to extend parallel to each other in the row direction. The plurality of first power lines and the plurality of other first power lines are integrally arranged in a lattice shape, A row of slits is provided in the second interlayer insulating film. The row of slits penetrates the second interlayer insulating film and spans from one end to the other end of the display area to overlap with the other first power lines.

3. The display device according to claim 1, wherein The first interlayer insulating film includes a lower first interlayer insulating film and an upper first interlayer insulating film provided on the lower first interlayer insulating film with a fourth wiring layer interposed therebetween. In the display area, a plurality of third power supply lines are provided in the fourth wiring layer so as to extend parallel to each other in a row direction. The plurality of second power supply lines and the plurality of third power supply lines are electrically connected via contact holes formed in the upper first interlayer insulating film.

4. The display device according to claim 1, wherein In a frame region surrounding the display region, a first trunk wiring provided as the third wiring layer is provided so as to extend in a row direction. The first trunk wiring is branched into a plurality of first power supply lines on the display area side. A trunk slit is provided on the second interlayer insulating film so as to overlap with the first trunk wiring.

5. The display device according to claim 4, wherein: In the frame region, a second trunk wiring is provided as the second wiring layer so as to overlap with the first trunk wiring. The second trunk wiring is branched into a plurality of second power supply lines on the display area side.

6. The display device according to claim 1, wherein Each of the light-emitting layers is an organic electroluminescent layer.

7. A display device comprising: a base substrate; a thin film transistor layer comprising a semiconductor layer, a first wiring layer, and a gate insulating film disposed between the semiconductor layer and the first wiring layer, the thin film transistor layer being disposed on the base substrate and sequentially stacked with the first wiring layer, a first interlayer insulating film, a second wiring layer, a first planarizing film, a second interlayer insulating film, a third wiring layer, and a second planarizing film; a light-emitting element layer provided on the thin film transistor layer, wherein a plurality of first electrodes, a plurality of light-emitting layers, and a common second electrode are sequentially stacked corresponding to a plurality of sub-pixels arranged in a matrix to form a display area; a plurality of gate lines arranged in the first wiring layer in the display area so as to extend parallel to each other along a row direction; a plurality of source lines provided in the second wiring layer in the display area so as to extend parallel to each other in a column direction; a plurality of first power supply lines provided in the third wiring layer in the display area so as to extend parallel to each other in a column direction; The second interlayer insulating film is provided with a column of slits, the column of slits penetrating the second interlayer insulating film, spanning from one end to the other end of the display area and overlapping the plurality of first power lines. In the display area, a plurality of other first power supply lines are provided in the third wiring layer so as to extend parallel to each other in the row direction. The plurality of first power lines and the plurality of other first power lines are integrally arranged in a lattice shape, The second interlayer insulating film is provided with a row of slits, the row of slits passing through the second interlayer insulating film, spanning from one end of the display area to the other end and overlapping with the other first power lines. In a frame region surrounding the display region, there is provided another first trunk wiring provided as the third wiring layer so as to extend in a column direction. The other first trunk wiring is branched into a plurality of branches on the display area side to form the plurality of other first power supply lines. The second interlayer insulating film is provided with a slit so as to overlap with the other first trunk wiring and the plurality of other first power supply lines.

8. The display device according to claim 7, wherein: In the frame region, another second trunk wiring is provided as the second wiring layer so as to overlap with the first trunk wiring.

9. The display device according to claim 8, wherein The first interlayer insulating film includes a lower first interlayer insulating film and an upper first interlayer insulating film provided on the lower first interlayer insulating film with a fourth wiring layer interposed therebetween. The display area includes: a plurality of third power supply lines provided in the fourth wiring layer so as to extend parallel to each other in a row direction; and In the frame region, the third trunk wiring of the fourth wiring layer is provided so as to overlap with the other first trunk wirings. The third trunk wiring is branched into a plurality of branches on the display area side to form the plurality of third power supply lines.

10. The display device according to claim 7, wherein: Each of the light-emitting layers is an organic electroluminescent layer.

Images