A Time Division Multiplexing Non-Coherent Accumulation System and Method for GNSS Interferometric Altimetry

Abstract

The present invention relates to the field of GNSS interferometric altimetry technology, and particularly to a time-division multiplexing non-coherent accumulation system and method for GNSS interferometric altimetry, which is implemented based on FPGA. The system includes a time-division multiplexing control module and a non-coherent accumulation module. The time-division multiplexing control module is used for timing control within a coherent integration time period to enable the non-coherent accumulation module to work in a time-division manner, and is also used to sequentially read a path of coherent integration results to the non-coherent accumulation module. The non-coherent accumulation module is used for performing time-division multiplexing non-coherent accumulation of each path of coherent integration results in a time-division manner under timing control. The present invention ingeniously utilizes the timing characteristics of coherent integration and non-coherent accumulation, and uses the idea of time-division multiplexing to achieve large-scale non-coherent accumulation operations with the smallest FPGA resources, greatly improving the utilization rate of FPGA resources and the timing margin of FPGA operation.

Description

Technical Field

[0001] The present invention relates to the field of GNSS interferometric altimetry technology, and particularly to a time-division multiplexing non-coherent accumulation system and method for GNSS interferometric altimetry. Background Art

[0002] The GNSS-R interferometric altimetry technology uses the GNSS direct signal and the reflected signal to directly perform correlation to obtain the interference correlation waveform, and then inversely calculates the pseudorange difference between the reflected signal and the direct signal, and finally inversely calculates the sea surface height of the GNSS new remote sensing detection technology. Currently, domestic and foreign GNSS navigation systems such as the Beidou navigation system, the GPS navigation system, the Galileo navigation system, and the GLONASS navigation system can all be applied to the interferometric altimetry technology.

[0003] The GNSS interference correlation technology is that after the direct GNSS signal undergoes down-conversion, signal delay, Doppler compensation and other measures, it is directly correlated with the reflected GNSS signal to obtain the interference signal correlation waveform. If the phases of the processed direct signal and the reflected signal are completely synchronized, the correlation waveform appears as the maximum value. Figure 1 This is the principle of the GNSS interference correlation technology. In order to improve the signal-to-noise ratio of the interference correlation waveform and thus obtain higher altitude measurement accuracy, not only a high-gain antenna is required in the hardware design to receive weak GNSS signals, but also sufficient non-coherent accumulation time is required in the software design to improve the signal-to-noise ratio of the interference waveform. Formula 1 describes the relationship between the accuracy of GNSS interferometric altimetry, the interference signal-to-noise ratio SNR, and the non-coherent accumulation times M.

[0004]

[0005] The formula shows that improving both SNR and non-coherent accumulation times can effectively improve the interferometric altimetry accuracy.

[0006] In order to obtain an effective interference correlation waveform, the direct signal needs to be delayed by N levels. Usually, at least a delay quantity in the range of ±2 GPS L1C / A code chips and a delay interval of 1 sampling clock cycle are required to achieve ideal altitude measurement accuracy. The value of the delay number N is determined by the following formula:

[0007]

[0008] Where: λ is the GPS L1C / A code length, c is the speed of light, f s is the sampling frequency, and Ceil is the ceiling function. Taking a typical design, if f s = 100 MHz, then N = 391. The higher the sampling rate, the larger the value of N.

[0009] Conventional GNSS receivers also use the method of increasing the number of non-coherent accumulations M to improve the signal-to-noise ratio. Currently, the more common navigation receiver design is in the form of CPU + FPGA. The FPGA is responsible for simple and fast correlation and accumulation operations, and the CPU is responsible for non-coherent accumulation operations. For example, Figure 2 , the advantage of this method is to make full use of the advantages of parallel and fast calculation of the FPGA. However, this method is not suitable for GNSS interferometric altimetry applications. The GNSS interferometric altimetry method requires the CPU to read the coherent integration results N times per millisecond and then perform non-coherent accumulation operations. The already task-heavy CPU cannot undertake to read N times and perform coherent accumulation operations within 1 ms.

[0010] Another common design method is to directly use the FPGA for coherent integration and non-coherent accumulation operations. For example, Figure 3 . The design advantage of this method is that the CPU does not need to calculate the final non-coherent accumulation result, which greatly reduces the burden on the CPU. Especially for applications with a large number of correlation points (large N value), this method has obvious advantages. For example, in GNSS interferometric altimetry applications, each clock sampling point requires delay and calculation of interference correlation values. However, it can be seen from the figure design that the disadvantages of this method are relatively obvious. As the N value increases, the resources of the FPGA multipliers and accumulators occupied will increase exponentially. This increase in resources not only occupies more FPGA resources, but also causes difficulties in the layout and routing of the FPGA due to the increase in resources, making it difficult to meet the timing requirements of the entire FPGA.

[0011] Aiming at the disadvantages of the second method and combining the characteristics of non-coherent accumulation in terms of timing, a time-division multiplexing non-coherent accumulation method is proposed. The greatest advantage of the present invention is to use the least amount of FPGA resources (2 multipliers, one accumulator, buffer, register, and timing control logic unit) to finally realize the non-coherent accumulation operation of N-way interference correlation results by cleverly arranging the calculation timing of N-way interference correlation results. See Figure 4 . Summary of the Invention

[0012] The purpose of the present invention is to overcome the defects of the prior art and propose a time-division multiplexing non-coherent accumulation system and method in GNSS interferometric altimetry.

[0013] To achieve the above purpose, the present invention proposes a time-division multiplexing non-coherent accumulation system in GNSS interferometric altimetry, which is implemented based on the FPGA. The system includes: a time-division multiplexing control module and a non-coherent accumulation module; wherein,

[0014] The time-division multiplexing control module is used for timing control within a coherent integration time period to realize the time-sharing operation of the non-coherent accumulation module, and is also used to sequentially read a path of coherent integration results to the non-coherent accumulation module;

[0015] The incoherent accumulation module is used to perform time-division multiplexing incoherent accumulation of the coherent integration results of each path under timing control.

[0016] As an improvement to the above system, the time-division multiplexing control module includes a multiplexer and a timing controller.

[0017] As an improvement to the above system, the incoherent accumulation module includes an accumulation calculation unit and a cache output unit; wherein,

[0018] The accumulation calculation unit includes a first multiplier, a second multiplier, an adder, and an accumulator;

[0019] The cache output unit includes a buffer and a register.

[0020] As an improvement to the above system, the processing process of the incoherent accumulation module under timing control includes:

[0021] The first multiplier receives the I interference correlation result of the nth path output by the multiplexer, performs multiplication processing, and outputs I2 n to the adder; wherein, the range of n is 1 to N, and N is the maximum delay number of interference correlation;

[0022] The second multiplier receives the Q interference correlation result of the nth path output by the multiplexer, performs multiplication processing, and outputs Q2 n to the adder;

[0023] The adder outputs the power value I2Q2 of the interference correlation result of the nth path n to the accumulator;

[0024] The accumulator reads the previous incoherent accumulation value PL from the buffer n and accumulates it with the power value I2Q2 n to obtain the current incoherent accumulation value PC of the nth path n , and outputs it to the buffer.

[0025] As an improvement to the above system, the processing process of the cache output unit under timing control includes:

[0026] Under the control of the timing controller, the buffer caches the current incoherent accumulation value PC of the nth path n ;

[0027] When the number of incoherent accumulations reaches the set value, under the control of the timing controller, the N-path incoherent accumulation results in the buffer are stored in the register.

[0028] A time-division multiplexing incoherent accumulation method for GNSS interferometric altimetry, implemented according to the above system, specifically includes:

[0029] When the coherent integration time arrives and N-channel interference correlation results are obtained, the following steps are performed:

[0030] Step 0) Set the non-coherent accumulation times m = 1 and the maximum delay number of interference correlation to N;

[0031] Step 1) Set the number of channels n for reading the interference correlation results to 1;

[0032] Step 2) The timing controller controls the multiplexer to enable the I and Q results of the nth channel to enter the multiplier, and at the same time sets the buffer address to n - 1;

[0033] Step 3) After 2 clock cycles, the power value I2Q2 of the nth channel is obtained at the output end of the adder n , and at the same time, the previous non-coherent accumulation value PL of the nth channel in the buffer is read n , and sent to the input end of the accumulator;

[0034] Step 4) After 1 clock cycle, the current non-coherent accumulation value PC of the nth channel is obtained at the output end of the accumulator n ;

[0035] Step 5) After 1 clock cycle, PC n is stored in the buffer, replacing PL n ;

[0036] Step 6) Determine whether n ≤ N. If the determination is yes, assign n + 1 to n and go to Step 2); otherwise, go to Step 7);

[0037] Step 7) Determine whether m ≤ M. If the determination is yes, assign m + 1 to m and go to Step 1); otherwise, go to Step 8);

[0038] Step 8) Store the N-channel non-coherent accumulation results in the register and clear the N-channel coherent accumulation results in the buffer.

[0039] Compared with the prior art, the advantages of the present invention are as follows:

[0040] 1. The present invention cleverly utilizes the timing characteristics of coherent integration and non-coherent accumulation, uses the time-division multiplexing idea, and realizes large-scale non-coherent accumulation operations with the least FPGA resources, greatly improving the utilization rate of FPGA resources;

[0041] 2. The present invention effectively reduces the precious FPGA resources for GNSS altimetry applications. Smaller resources are beneficial to improving the FPGA placement and routing capabilities, thereby greatly improving the timing margin of FPGA operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is the schematic diagram of GNSS interference correlation technology;

[0043] Figure 2 It is the control logic block diagram for performing incoherent accumulation operations in the existing technology CPU;

[0044] Figure 3 It is the control logic block diagram for performing incoherent accumulation operations in the existing technology FPGA;

[0045] Figure 4 It is the time-division multiplexing incoherent accumulation operation control logic block diagram in the FPGA of the present invention. Detailed implementation manners

[0046] The purpose of the present invention is to use limited FPGA resources to implement large-scale incoherent accumulation operations necessary for GNSS height measurement, and a time-division multiplexing incoherent accumulation method for GNSS interferometric height measurement is proposed. That is, the FPGA completes the time-division calculation of N-channel (for GNSS height measurement applications, N≥391) interference-related results through timing control logic, and cleverly completes the incoherent accumulation operation of N-channel interference-related results before the update of the next interference-related result, reducing the FPGA resources to 1 / N of the original. Greatly reducing the resource occupancy rate of the FPGA.

[0047] The characteristics of this invention are: according to the technical principle of incoherent accumulation in the FPGA, by cleverly using the time-division multiplexing idea to exchange time for precious FPGA resources, the incoherent accumulation operation of N-channel interference-related results is realized by sharing the same multiplier and accumulator, reducing the FPGA resources to 1 / N of the original. Greatly reducing the resource occupancy rate of the FPGA.

[0048] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0049] Embodiment 1

[0050] As Figure 4 shown, Embodiment 1 of the present invention proposes a time-division multiplexing incoherent accumulation system for GNSS interferometric height measurement, implemented based on FPGA. The system includes: an incoherent accumulation module and a time-division multiplexing control logic; wherein,

[0051] The incoherent accumulation module includes an accumulation calculation unit and a cache output unit; wherein,

[0052] The accumulation calculation unit includes 2 multipliers, 1 adder, and 1 accumulator;

[0053] The cache output unit includes 1 buffer and 1 register.

[0054] The N-channel interference-related results first pass through the multipliers and an adder one by one to obtain the power value I2Q2 of the interference-related results n :

[0055] I2Q2 n = I n * I n + Q n * Q n (3)

[0056] Where: I n , Q n are respectively the 1ms interference correlation results of I and Q of the nth path, and the subscript n ranges from 1 to N, where N is the maximum delay number of interference correlation.

[0057] The accumulator starts to accumulate the N power results one by one to obtain the N-channel non-coherent accumulation results.

[0058] PC n = PL n + I2Q2 n (4)

[0059] Where: PL n , PC n are respectively the previous non-coherent accumulation value and the current non-coherent accumulation value.

[0060] The buffer is used to buffer the non-coherent accumulation results each time.

[0061] The register is used to store the final non-coherent accumulation result when the non-coherent accumulation times M reaches.

[0062] The time-division multiplexing control logic is composed of a multiplexer and a timing controller, which completes the precise timing control of the input and output of each path signal to ensure the correctness of the non-coherent accumulation results each time.

[0063] The present invention makes full use of the parallel characteristics of FPGA. Utilizing the characteristic that the coherent integration results of the previous period remain unchanged within the coherent integration time of this period (usually set to 1ms in GNSS interferometric altimetry applications), it calculates the N-channel non-coherent accumulation values of the previous period one by one in time division and caches them in this period. The number of clocks consumed is 4N. The multiplier, adder and accumulator are shared in time division, trading time for the precious logic resources of FPGA. If the clock frequency is 100MHz and N = 391, the time consumption is 15.64 microseconds, which is much less than 1ms. Therefore, FPGA has enough time to calculate the non-coherent accumulation values of N channels.

[0064] Comparing this scheme with the non-coherent accumulation scheme implemented in ordinary FPGA, the results are the same. However, the FPGA resources are 1 / N of the ordinary scheme. Especially when the N value is large, the superiority of this scheme is more prominent. Smaller FPGA resources are more conducive to improving the layout and routing ability of FPGA, effectively improving the timing margin of FPGA.

[0065] Embodiment 2

[0066] Embodiment 2 of the present invention proposes a time-division multiplexing non-coherent accumulation method for GNSS interferometric altimetry.

[0067] The technical principle of time-division multiplexing non-coherent accumulation is introduced in detail below:

[0068] 1) When the coherent integration time arrives, the FPGA stores the N-channel interference correlation results of the previous time period, starts the coherent integration operation of this time period, and simultaneously starts the non-coherent accumulation operation of the previous coherent integration result.

[0069] 2) When the N GNSS interference-related coherent integration results I and Q are stored, the timing controller starts to work. First, it controls the multiplexer to make the first-channel I and Q results enter the multiplier, and simultaneously sets the buffer address to 0;

[0070] 3) After 2 clock cycles, the adder output gets the power value I2Q21 of the first channel, and simultaneously reads the previous correlation accumulation result PL1 of the first channel in the buffer and sends it to the input end of the accumulator;

[0071] 4) After 1 clock cycle, the output end of the accumulator gets the current non-coherent accumulation value PC1 of the first channel;

[0072] 5) After 1 clock cycle, PC1 is stored in the buffer to replace PL1;

[0073] 6) Control the multiplexer to make the second-channel I and Q results enter the multiplier, and simultaneously set the buffer address to 1, and repeat steps 3)-5) until all the non-coherent accumulation values of the N channels are calculated and stored in the buffer, and the timing controller stops working. Thus, 1 time of time-division multiplexing non-coherent accumulation calculation is completed, and a total of 4N clock cycles are consumed.

[0074] If the number of non-coherent accumulation times reaches the set value M, after completing steps 2)-6), the non-coherent accumulation results of the N channels are stored in the register, and then the N-channel coherent accumulation results in the buffer are cleared to prepare for subsequent non-coherent accumulation operations.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A time-division multiplexing non-coherent accumulation system for GNSS interferometric altimetry, implemented based on FPGA, characterized in that, The system includes: a time-division multiplexing control module and a non-coherent accumulation module; wherein, The time-division multiplexing control module is used for timing control within a coherent integration time period to enable the non-coherent accumulation module to work in a time-division manner, and is also used to sequentially read a path of coherent integration results to the non-coherent accumulation module; The non-coherent accumulation module is used for performing time-division multiplexing non-coherent accumulation of each path of coherent integration results under timing control; The time-division multiplexing control module includes a multiplexer and a timing controller; The non-coherent accumulation module includes an accumulation calculation unit and a buffer output unit; wherein, The accumulation calculation unit includes a first multiplier, a second multiplier, an adder, and an accumulator; The buffer output unit includes a buffer and a register; The processing process of the non-coherent accumulation module under timing control includes: The first multiplier receives the I interference correlation result of the nth path output by the multiplexer, performs multiplication processing and outputs to the adder; where, the range of n is 1 to N, and N is the maximum delay number of interference correlation; The second multiplier receives the Q interference correlation result of the nth path output by the multiplexer, performs multiplication processing and outputs to the adder; The power value I2Q2 of the n-th interference-related result output by the adder n to the accumulator; The accumulator reads the last incoherent accumulation value PL from the buffer n and the power value I2Q2 n are accumulated to obtain the nth-path current incoherent accumulation value PC n , and output to the buffer 2. The GNSS interferometric altimetry time-division multiplexing non-coherent accumulation system according to claim 1, wherein The processing process of the buffer output unit under timing control includes: Under the control of the timing controller, the buffer caches the non-coherent accumulation value PC of the nth path this time n ; When the number of non-coherent accumulations reaches the set value, under the control of the timing controller, the N-way non-coherent accumulation results in the buffer are stored in the register.

3. A time-division multiplexing non-coherent accumulation method in GNSS interferometric altimetry, implemented according to the system described in claim 1 or 2, specifically including: When the coherent integration time arrives and N-way interference correlation results are obtained, the following steps are performed: Step 0) Set the number of non-coherent accumulations m = 1, and the maximum delay number of interference correlation is N; Step 1) Set the number of paths n for reading the interference correlation results to 1; Step 2) The timing controller controls the multiplexer to enable the I and Q results of the nth path to enter the multiplier, and at the same time set the buffer address to n - 1; Step 3) The power value I2Q2 of the nth path is obtained at the output end of the adder after 2 clock cycles n , and at the same time, the previous non-coherent accumulation value PL of the nth path in the buffer is read n , and sent to the input end of the accumulator; Step 4) Obtain the current non-coherent accumulation value PC of the nth path at the output end of the accumulator after experiencing 1 clock cycle n ; Step 5) Store the PC into the cache after 1 clock cycle, replacing PL n ; n ; Step 6) Judge whether n ≤ N, if the judgment is yes, assign n + 1 to n, and go to step 2); Otherwise, go to step 7); Step 7) Judge whether m ≤ M, if the judgment is yes, assign m + 1 to m, and go to step 1); Otherwise, go to step 8); Step 8) Store the N-way non-coherent accumulation results in the register, and clear the N-way coherent accumulation results in the buffer.

Images