Method of managing nop instructions executed by a microcontroller and corresponding microcontroller

Abstract

The present disclosure relates to a method of managing NOP instructions in a microcontroller, the method comprising replicating all jump instructions that generate NOP instructions to form a new instruction set; inserting an internal NOP instruction into each of the jump instructions; running the subsequent instructions of the new instruction set when the jump instructions are run; and running the internal NOP instruction when the running of the subsequent instructions is skipped.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Italian patent application No. 102021000002642, filed on February 5, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a method for managing no-operation (NOP) instructions executed by a microcontroller and a corresponding microcontroller. Background Technology

[0004] Among various types of flash memory devices, NAND flash memory is increasingly used as a high-capacity data storage medium. Each cell of a flash memory needs to be programmed to store information by trapping electrons in a floating gate. Programming is performed by forcing current from the channel through the floating gate to the control gate by driving a strong positive voltage onto the control gate; this is known as the "Fowler Nordheim Tunneling" effect. The control gate terminals are connected to the word line of the flash memory, and a voltage is supplied to the control gate terminals through this word line. Similarly, a read operation is performed by applying an appropriate voltage to the control gate of the cell to be read.

[0005] The microcontroller executes appropriate read and program code to perform the required instructions corresponding to the read and program phases of the memory device. More specifically, the read and program code includes instructions to be executed to obtain the appropriate voltage to be applied to selected cells of the memory device. No-operation (NOP) instructions may appear within this code.

[0006] As is well known, the NOP instruction is a command that does not give any indication. Therefore, when an internal NOP instruction occurs, the NOP instruction is wasted during microcontroller operation.

[0007] Intel Corporation's U.S. patent application No. 9323535 relates to a processor that includes an instruction fetch unit and allows the execution of instructions and other subsequent instructions in the programming sequence to be pipelined or advanced, and is treated as a non-operation (NOP) instruction at a later stage after the input of the execution instruction.

[0008] Similarly, Intel's U.S. patent application No. 9703948 relates to a processor that includes a decoding unit that decodes return target restricted returns (or RTR returns) from program instructions that can be executed as NOP instructions. Summary of the Invention

[0009] Embodiments of this disclosure relate to a method and microcontroller for managing NOP instructions by copying all jump instructions that generate NOP instructions.

[0010] In embodiments of this disclosure, the method includes: copying all jump instructions that generate NOP instructions to form a new instruction set; inserting an internal NOP instruction into each of the jump instructions; executing subsequent instructions of the new instruction set when the jump instructions are executed; and executing the internal NOP instruction when the execution of subsequent instructions is skipped.

[0011] More specifically, the executable instructions of the new instruction set are subdivided into multiple subsets, including output modification instructions, Boolean algebra instructions, and stream instructions. The microcontroller is capable of executing two instructions from different subsets simultaneously. Furthermore, each line of code containing more than two instructions is subdivided into two lines of code containing two instructions from two different subsets.

[0012] In another embodiment of this disclosure, the method includes: removing non-critical instructions such as unused instructions in response to NOP instructions, copying the most frequently used instructions with jump instructions, and inserting the most frequently used instructions and jump instructions to replace the non-critical instructions (inserting these instructions at the locations of the non-critical instructions) to avoid wasting lines of code.

[0013] More specifically, the method includes: identifying a first group of non-critical instructions and a second group of jump instructions that generate NOP instructions; and copying the second group of instructions by inserting jump instructions to replace the non-critical instructions of the first group.

[0014] In this embodiment, inserting a second group of jump instructions to replace the non-critical instructions in the first group can form a new instruction set of code, and the unused code lines are used to encode the added jump instructions.

[0015] In addition, the method may include the step of removing the NOP instruction after a go-to, call, or return instruction by using an internal NOP code signal that can be provided internally by the microcontroller.

[0016] In embodiments of this disclosure, a NOP manager unit for a microcontroller that uses code requiring NOP instructions is provided. The NOP manager unit includes: an instruction decoder combiner block connected to the output terminal of the NOP manager unit and having an internal output terminal that provides an internal NOP code signal; and an instruction decoder sequence block having an input terminal for receiving memory instructions and an output terminal connected to the output terminal of the NOP manager unit. The instruction decoder sequence block also receives the internal NOP code signal from the instruction decoder combiner block.

[0017] In an embodiment, the instruction decoder sequence block may include at least a MUX having a first input terminal for receiving memory instructions and a second input terminal for receiving idle instruction (NOP) codes, as well as an output terminal connected to the output terminal of the NOP manager unit. The MUX is driven by an internal NOP code signal received through the internal output terminal of the instruction decoder combiner block.

[0018] The instruction decoder sequence block may further include a data latch that receives the microcontroller's clock signal and is connected to the output terminal of the NOP manager unit to provide internal memory instructions.

[0019] The NOP manager may further include an additional internal latch inserted between the instruction decoder combiner block and the instruction decoder sequence block. This additional internal latch receives the microcontroller's clock signal and reset signal and provides a further internal skip signal to the instruction decoder sequence block at a further internal output terminal. More specifically, the additional internal latch samples on the falling edge of the clock signal.

[0020] In another embodiment of this disclosure, a microcontroller using code requiring NOP instructions is provided. The microcontroller includes: a pipeline for managing multiple instructions of code to be used by the microcontroller, the multiple instructions including jump instructions that generate corresponding NOP instructions; and a NOP manager unit. The NOP manager unit includes: an instruction decoder combiner block connected to the output terminal of the NOP manager unit and having an internal output terminal providing an internal NOP code signal; and an instruction decoder sequence block having an input terminal for receiving memory instructions and an output terminal connected to the output terminal of the NOP manager unit, and configured to receive the internal NOP code signal from the instruction decoder combiner block.

[0021] In another embodiment of this disclosure, a microcontroller is provided that uses code requiring NOP instructions. The microcontroller includes: a pipeline configured to manage a plurality of instructions of code to be used by the microcontroller, the plurality of instructions including jump instructions that generate corresponding NOP instructions and each of the jump instructions being encoded to include an internal NOP instruction; and a NOP manager unit configured to, when one of the jump instructions is executed, execute a subsequent instruction in the instruction; or, when the subsequent instruction cannot be executed, execute the internal NOP instruction. Attached Figure Description

[0022] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings; however, embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0023] In the accompanying drawings, dimensions may be enlarged for clarity. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0024] The features and advantages of this disclosure will become apparent from the following description of embodiments of the disclosure given by way of indicative and non-limiting example with reference to the accompanying drawings, wherein:

[0025] Figure 1A A pipeline structure for processing multiple instructions for reading or programming code is shown according to an embodiment of the present disclosure;

[0026] Figure 1B The embodiments shown are derived from the present disclosure. Figure 1A Timing diagram of multiple instructions processed by the pipeline structure;

[0027] Figure 2 A timing diagram is shown for multiple instructions in the case where the jump instruction involves a NOP instruction, according to an embodiment of the present disclosure;

[0028] Figure 3A This illustrates a microcontroller that uses internal signals to manage NOP instructions, and Figure 3B A timing diagram is shown for a plurality of instructions according to embodiments of the present disclosure;

[0029] Figure 4A and Figure 4B Showing the corresponding use Figure 3A The internal signals or code sequence of a microcontroller that operates using an instruction set established according to embodiments of this disclosure.

[0030] Figure 5 A set of instructions is schematically shown that can be executed by a method according to an embodiment of the present disclosure;

[0031] Figure 6 and Figure 7 Block diagrams are schematically shown corresponding to the management of NOP instructions according to embodiments of this disclosure and prior art solutions, respectively;

[0032] Figure 8 A block diagram schematically illustrates a microcontroller portion for managing NOP instructions according to an embodiment of the present disclosure;

[0033] Figure 9 A block diagram schematically illustrates a microcontroller portion for managing NOP instructions according to an alternative embodiment of the present disclosure;

[0034] Figures 10A to 10C A flowchart illustrating a method for managing NOP instructions according to an embodiment of the present disclosure, and a corresponding timing diagram of multiple internal instructions of a controller using the method are shown. Detailed Implementation

[0035] Embodiments of this disclosure will be described below. In the accompanying drawings, thickness and distance are shown for ease of description and may be enlarged and shown in comparison to actual physical thickness and distance. Known configurations unrelated to this disclosure may be omitted in this specification. In this specification, when components in each drawing are labeled with reference numerals, it should be noted that even if reference numerals are depicted in several drawings, the same reference numerals denote the same elements.

[0036] Figure 1A It is a pipeline structure 100. Through the pipeline structure 100, more than 100 instructions are read, stored, decoded and executed in a series of blocks. The pipeline structure 100 is driven by the clock signal CK and can manage multiple instructions as shown in the figure.

[0037] In an embodiment, the pipeline structure 100 includes a storage block, such as a ROM memory 110, which receives an address signal ROM_ADD corresponding to a plurality of memory instructions I stored in the ROM memory 110 as ROM_DATA. The memory instructions I are read from the ROM memory 110 and stored in another block of the pipeline structure 100 (specifically, an instruction register 120), which is connected to the ROM memory 110 and receives memory instructions I from the ROM memory 110 and also stores a corresponding latched instruction ROMDATA_L, also represented as a register instruction E.

[0038] In an embodiment, the pipeline structure 100 may further include an instruction decoder 130, which is connected to the instruction register 120 and receives a register instruction E from the instruction register 120. The register instruction E is decoded and sent to a final destination register 140, which is connected to the instruction decoder 130 that stores a final instruction R to be executed.

[0039] Typically, a microcontroller can execute up to two subinstructions simultaneously per clock cycle. In particular, when the number of bits in an instruction is less than or equal to the number of resources that the microcontroller can process, the executable instructions are divided into three possible subsets: output modification instructions or PORT, such as SET / CLEAR for output ports; logical algebra instructions or ALU, such as TEST, SUM, AND, OR, etc.; and stream instructions or jumps (JMP), such as GOTO to a tag, CALL subroutine, RETURN from subroutine.

[0040] In this way, the microcontroller can execute two sub-instructions simultaneously according to the following groupings: PORT and JMP; or PORT and ALU; or ALU and JMP.

[0041] It should be clarified that the following jump instructions are intended to include all instructions that force the microcontroller to deviate from the continuous instruction stream and cause the microcontroller to read from another memory location, where the next statement to be executed in the continuous instruction stream is the instruction stored at the next memory address.

[0042] exist Figure 1B In the example shown, at a first time t1, which is the start of the read interval, a first address signal ROM_ADD with a value of, for example, 10, is read by the ROM memory 110, and the corresponding first memory instruction I10 is retrieved and stored in the instruction register 120. At a second time t2, which is the end of the read interval and the start of the decode interval, the first register instruction E10 is retrieved by the instruction register 120 and sent to the instruction decoder 130. At a third time t3, which is the end of the decode interval and the start of the run interval, the instruction decoder 130 provides the first final instruction R10. More specifically, the execution of the final instruction R10 can be changed in the destination register, either internally or externally to the microcontroller.

[0043] At the second time t2, the subsequent second address signal ROM_ADD with the value 11 is read and the subsequent second memory instruction I11 is received by the ROM memory 110. The pipeline structure 100 processes the second memory instruction I11 in the same way as the first memory instruction I10.

[0044] When the instruction includes a jump command, for example Figure 2As shown, for the GOTO instruction and the first register instruction E10 at the third time t3, the second memory instruction I11 is retrieved by the ROM memory 110, the corresponding read command at address 11 is executed at the second time t2, and the jump instruction is being decoded. In this case, while a new instruction at address xxx is being read from the ROM memory 110, the second memory instruction I11 is subsequently discarded, and the NOP instruction is stored in the appropriate location in the instruction register 120 at the third time t3. Therefore, the corresponding final instruction R10 should immediately follow the NOP instruction to provide an internal idle cycle to reload the pipeline structure 100.

[0045] However, it is clear that the NOP instruction inserted after each register / final instruction corresponding to the jump command is a wasted instruction, resulting in longer execution time for microcontrollers using pipeline architecture 100 and NOP instructions.

[0046] Additional specific signals can be used in this case to remove the internal NOP instruction following the jump instruction, such as in Figure 3A As schematically shown, the microcontroller skip circuit 200 is implemented by connecting the microcontroller 210 to an output port 220, which provides the microcontroller 210 with a skip signal MC_MICRO_INTNOP_SKIP and allows the execution of instructions following the skip instruction. Specifically, as... Figure 3B As shown, even if the first register instruction E10 is a GOTO instruction, the second register instruction E11 will be executed, and then the second final instruction R11 will be executed, thereby reducing the execution time of the jump instruction.

[0047] In this way, since skipping the signal MC_MICRO_INTNOP_SKIP would disable the internal NOP instruction, the microcontroller itself can set the skip signal MC_MICRO_INTNOP_SKIP during runtime.

[0048] However, it can be verified that using the skip signal MC_MICRO_INTNOP_SKIP alters the behavior of jump instructions. Specifically, two main problems arise.

[0049] First, not all jump instructions can be managed by the internal skip circuit 200 using the skip signal MC_MICRO_INTNOP_SKIP, and an explicit NOP instruction should be introduced after these instructions. In this case, wasted instruction lines still occur, and comparing the code line sequences with and without the skip signal MC_MICRO_INTNOP_SKIP separately, the benefit of reduced runtime is lost due to the increased number of code lines. For example... Figure 4AAs shown. Furthermore, the increase in the number of lines of code forces an increase in the ROM storage area.

[0050] Furthermore, since the behavior of a jump instruction depends on the setting of the skip signal MC_MICRO_INTNOP_SKIP, it cannot be understood simply by reading the code's behavior, which is related to code quality.

[0051] Because the code's execution depends on the state of the signal that disables the internal NOP instruction, this code cannot be univocally decodable, leading to an increase in the number of errors during the design phase.

[0052] The method according to an embodiment includes copying all jump instructions to allow subsequent instructions to be executed in a later clock cycle or to inherently execute internal NOP instructions when the jump instructions are executed. In this way, the method can be used to obtain a new instruction set including the copied jump instructions.

[0053] In this way, at each jump instruction, the code can be designed in a way that allows subsequent instructions to run, or even if this is not possible, the jump instruction itself can be written to include an internal NOP instruction, which does not need to be stored in the ROM memory 110, and therefore does not require an additional line of code.

[0054] For example, consider the case where, when condition C is true or false, the sequence of two instructions, I1 and I2t, or I1 and I2f, will be executed respectively, as in case 1 below.

[0055] Case 1: TEST(C); IF(C==1)THEN I2t ELSE I2f

[0056] In this scenario, the microcontroller uses code with a conditional GOTO instruction at the tag location, and the ROM memory 110 stores the file code line, such as... Figure 4A As shown.

[0057] The statement "cannot execute subsequent instructions" means that a conditional algorithm (IF...THEN... in the example below) may or may not be fully coded using jump instructions without internal NOPs. That is, the code should be written in such a way that, from the algorithm's perspective, the instructions written after the conditional jump will be executed regardless of whether the jump is performed. If the programmer cannot find a sequence of lines of code that allows the use of the "jump without internal NOPs" feature, then the instructions written after the jump instruction "cannot execute," and in this case, jumps with internal NOPs can be used without explicitly writing the NOPs in the code, such as... Figure 4B As shown.

[0058] In case 1, regardless of whether the jump instruction is executed, the instruction written to the line of code immediately following the jump instruction without an internal NOP instruction (INST2 in this example) is executed. INST2 is the subsequent instruction.

[0059] Conversely, in case 2, the subsequent instruction (INST2) written after the jump instruction with the internal NOP instruction is executed, depending on whether the jump instruction is executed. Additionally, the internal NOP instruction is executed when the skip instruction (INST2) is executed.

[0060] Specifically, according to an embodiment of the above method, in the part denoted as Micro 1 having Figure 3A In the case of a microcontroller with the signal MC_MICRO_INTNOP_SKIP, and in the case of a controller represented as Micro 2 with a copied jump instruction, it can be verified that the ROM memory 110 includes file code lines.

[0061] It should be noted that Micro 1 and Micro 2 have the same number of lines of code and require the same number of clock cycles.

[0062] Since a microcontroller can execute up to two subinstructions simultaneously per clock cycle, if there are more than two instructions to be executed, these instructions are subdivided according to two different groups that can be executed simultaneously, as in case 2. Figure 4A As shown, case 2 provides the execution of instructions I0, I1, and I2, where I2 is a conditional instruction. Figure 4A In the example, instructions I0 and TEST(C) and instructions I1 and GOTO can be executed simultaneously.

[0063] This verifies that file line Micro 2 still contains four lines of code. When condition C is true, the four lines of code will run within three clock cycles, and when condition C is false, the four lines of code will run within four clock cycles. Micro 1 contains five lines of code with NOP instructions inserted. These five lines of code will run within four clock cycles, regardless of condition C.

[0064] It should be noted that even if the line of code "I1; IF(C==1)THEN GOTO l_true;" is split into two lines "IF(C==1)THEN GOTO l_true;" after "I1" to remove the NOP operation, the number of lines of code and clock cycles required will be the same.

[0065] According to the embodiment, by copying all jump instructions, Micro 2 achieves an optimal working mode with the same running speed (case 1) and a lower number of lines of code (case 2).

[0066] It should be noted that, due to the presence of copied jump instructions, the method of this embodiment processes and decodes more instructions. Therefore, Micro 2, which implements this method, includes a decoder with a larger area than Micro 1, the decoder area being related to the number of instructions to be decoded. Furthermore, if the bit length of the instruction increases, the memory area storing the instruction increases accordingly; the memory is either ROM or RAM.

[0067] For example, for code that includes 16 jump instructions out of a total of 46 instructions, according to the method of this embodiment, a total of 62 instructions are processed, which significantly increases the total number of instructions.

[0068] Therefore, according to an embodiment, the method includes identifying: a first set of instructions GR1, including non-critical instructions, particularly unused instructions or instructions that are called a limited number of times and can be replaced without affecting the microcontroller's calibration operation; and a second set of instructions GR2, including the most frequently used jump instructions, such as those in... Figure 5 It is shown schematically.

[0069] The method according to this embodiment further includes a copy instruction of the second group of GR2 and an insert jump instruction of the second group of GR2 replacing the non-critical instructions of the first group of GR1, to obtain a new instruction set with a reduced number of copied jump instructions compared to the previous embodiment. In this way, the internal NOP instruction is removed after the jump instruction that generates the NOP instruction. The microcontroller with a reduced number of copied jump instructions according to the method of the above embodiment is also referred to as Micro 3.

[0070] It can be verified that the selection of jump instructions to be copied and non-critical instructions to be removed, such as unused instructions, depends on the specific situation being analyzed. The lines of code for non-critical instructions are always used to encode the added jump instructions.

[0071] The new instruction set with a reduced number of copied jump instructions allows for clearer code reading and simplifies the evaluation of code behavior.

[0072] The method according to the embodiment strikes a tradeoff between the number of lines of code, execution speed, and region footprint of the microcontroller by adjusting the number of jump instructions to be copied. Specifically, it can be verified that file code line Micro 3, with a new instruction set having a reduced number of copied jump instructions, applied only to read and program code, still shows a savings in lines of code, even compared to file code line Micro 2, while maintaining the same region footprint and execution time as file code line Micro 1.

[0073] According to embodiments of this disclosure, a new instruction set obtained by identifying the non-critical instructions of the first group GR1 and inserting a jump instruction from the most frequently used jump instructions of the second group GR2 to replace the instructions of the first group GR1 is used in conjunction with the internal NOP signal to manage NOP instructions.

[0074] More specifically, such as Figure 6 As shown, the internal NOP code signal INTERNAL_NOP is provided to both the programming counter block 310 and the instruction decoder sequence block 320 of the microcontroller executing the method.

[0075] In this way, the internal management unit 300 is located within a microcontroller including a programming counter block 310, an instruction decoder sequence block 320, and an instruction decoder combiner block 330, and is appropriately modified to provide the internal NOP code signal INTERNAL_NOP to the programming counter block 310 and the instruction decoder sequence block 320, and to provide jump calls to the programming counter block 310.

[0076] Figure 7 The diagram shows a previous configuration of an internal management unit 300' that uses an externally provided skip signal MC_MICRO_INTNOP_SKIP. This known internal management unit 300' includes a programming counter block 310 that receives the skip signal MC_MICRO_INTNOP_SKIP from the output port of the microcontroller skip circuit 200, as previously described, and provides the internal NOP code signal INTERNAL_NOP to the instruction decoder sequence block 320, while the instruction decoder combiner block 330 only provides the JMP or CALL flag to the programming counter block 310.

[0077] In this previous configuration of the internal management unit 300', the internal NOP code signal INTERNAL_NOP is driven high by the jump flag whenever a jump instruction is decoded in the instruction decoder combiner block 330. However, if the skip signal MC_MICRO_INTNOP_SKIP is set, this internal NOP code signal INTERNAL_NOP is masked to zero.

[0078] The skip signal MC_MICRO_INTNOP_SKIP is used to remove NOP instructions after a jump instruction that has already generated such a NOP instruction.

[0079] It can be verified that the association between the internal NOP code signal INTERNAL_NOP and the new instruction set allows for savings in lines of code, and that algorithms using the new instruction set have the same runtime as those not modified according to this method.

[0080] Figure 8A block diagram of a microcontroller’s NOP manager unit is shown, which uses a combination of instruction decoder combiner blocks that provide the internal NOP code signal INTERNAL_NOP to the instruction decoder sequence block.

[0081] Specifically, the NOP manager unit 400 includes an instruction decoder combiner block 410, which has an input section 410A. The input section 410A is connected to the output terminal OUT of the NOP manager unit 400 and provides the operation code OPCODE to the output section 410B of the instruction decoder combiner block 410, and in turn provides the internal NOP code signal INTERNAL_NOP at the internal output terminal OUT1.

[0082] The NOP manager unit 400 further includes an instruction decoder sequence block 420, which receives an internal NOP code signal INTERNAL_NOP from the instruction decoder combiner block 410 and a clock signal MC_CLK from the microcontroller including the NOP manager unit 400. More specifically, the instruction decoder sequence block 420 includes a MUX having a first input terminal for receiving memory instructions ROM_DATA and a second input terminal for receiving idle instructions NOP 000...0, and is driven by the internal NOP code signal INTERNAL_NOP received from the internal output terminal OUT1 of the instruction decoder combiner block 410. The instruction decoder sequence block 420 also includes a ROM DATA latch 420L, which receives the clock signal MC_CLK and the output signal of the MUX, and is connected to the output terminal OUT of the NOP manager unit 400 and provides the internal memory instruction int_ROM_DATA_L.

[0083] Specifically, if the instruction requires a JUMP, the internal NOP code signal INTERNAL_NOP is set to 1 and the MUX of instruction decoder sequence block 420 is set to idle.

[0084] Optionally, such as Figure 9As shown, the NOP manager unit 400 may further include an additional internal latch 430 inserted between the internal output terminal OUT1 of the instruction decoder combiner block 410 and the instruction decoder sequence block 420. The additional internal latch 430 receives the microcontroller's clock signal MC_CLK and provides another internal NOP code signal INTERNAL_NOP_L to the instruction decoder sequence block 420 at another internal output terminal OUT2. The instruction decoder sequence block 420, in turn, is connected to the output terminal OUT of the NOP manager unit 400 and provides the internal memory instruction int_ROM_DATA_L. More specifically, it should be noted that the additional internal latch 430 samples on the falling edge of the clock signal MC_CLK.

[0085] According to this optional embodiment, potential glitches in the internal NOP code signal INTERNAL_NOP are removed.

[0086] Referring to the latter embodiment, Figure 10A , Figure 10B and Figure 10C The flowcharts and corresponding timing diagrams for the operation of the NOP manager unit 400 are shown respectively.

[0087] Specifically, in the first operation S1, the operation code OPCODE is verified to check if an internal NOP instruction is needed. If the verification in the first operation S1 is positive (yes), the second operation S2 is executed, setting the internal NOP code signal INTERNAL_NOP to 1, and subsequently, in the third operation S3, the internal memory instruction int_ROM_DATA_L is set to the idle instruction NOP 0000...0, resulting in the corresponding change. Figure 10B The signals shown correspond to the rising and falling edges of the clock signal MC_CLK.

[0088] Doublely, in the event of a negative response (No) to the verification of the first operation S1, an optional second operation S2' is executed, setting the internal NOP code signal INTERNAL_NOP to 0, and a subsequent optional third operation S3' sets the internal memory instruction int_ROM_DATA_L to the memory instruction ROM_DATA, resulting in the corresponding change. Figure 10C The signals shown correspond to the rising and falling edges of the clock signal MC_CLK.

[0089] By using the aforementioned method and microcontroller, high-performance management of NOP instructions is achieved without wasting or even saving lines of code while maintaining constant runtime, thus overcoming the problems related to the generation of NOP instructions when the microcontroller is running.

[0090] Furthermore, according to the embodiments, by adjusting the number of jump instructions to be copied, a suitable trade-off is achieved between the number of lines of code, running speed, and space usage.

[0091] As will be apparent from the foregoing, while specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited except as provided in the appended claims.

Claims

1. A method for managing NOP instructions in a microcontroller, the method comprising: Copy all jump instructions that generate NOP instructions to form a new instruction set; Insert the internal NOP instruction into each of the jump instructions in the new instruction set; When a jump instruction of the new instruction set is executed, the subsequent instructions of the jump instruction of the new instruction set are executed; and When the subsequent instructions are skipped during runtime, the internal NOP instruction is executed.

2. The method according to claim 1, The executable instructions of the new instruction set are subdivided into multiple subsets, including output modification instructions, Boolean algebra instructions, and stream instructions. The microcontroller described therein executes two instructions from different subsets simultaneously.

3. The method of claim 2, wherein within the new instruction set, each line of code comprising more than two instructions is subdivided into two lines of code, the two lines of code comprising two instructions from two different subsets.

4. A method for managing NOP instructions in a microcontroller, the method comprising: Identify the non-critical instructions in the first group and the jump instructions in the second group, wherein the jump instructions generate NOP instructions; The instructions in the second group are copied to form a new instruction set of code by inserting jump instructions to replace the non-critical instructions in the first group; Insert the internal NOP instruction into each of the jump instructions in the new instruction set; When a jump instruction of the new instruction set is executed, the subsequent instructions of the jump instruction of the new instruction set are executed; and When the subsequent instructions are skipped during runtime, the internal NOP instruction is executed.

5. The method of claim 4, further comprising: The NOP instruction following the jump instruction in the new instruction set is removed by using an internal NOP code signal.

6. The method of claim 5, wherein the internal NOP code signal is provided internally by the microcontroller.

7. The method of claim 4, further comprising: After the code changes resulting from copying the instructions of the second group by inserting the jump instructions to replace the non-critical instructions of the first group, the code is verified.

8. The method of claim 4, wherein the number of jump instructions to be copied is adjusted to compromise between the number of lines of code, running speed, and area occupancy of the microcontroller implementing the method.

9. A microcontroller that uses code requiring NOP instructions, the microcontroller comprising: A pipeline for managing multiple instructions of code to be used by the microcontroller, the multiple instructions including jump instructions that generate corresponding NOP instructions; as well as The NOP manager unit executes the method according to any one of claims 1-8, the NOP manager unit comprising: The instruction decoder combiner block is connected to the output terminal of the NOP manager unit and has an internal output terminal that provides internal NOP code signals. as well as The instruction decoder sequence block has an input terminal for receiving memory instructions and an output terminal connected to the output terminal of the NOP manager unit, and receives the internal NOP code signal from the instruction decoder combiner block.

10. The microcontroller of claim 9, wherein the instruction decoder sequence block includes at least a MUX, the MUX having a first input terminal for receiving the memory instruction and a second input terminal for receiving an idle instruction (NOP), wherein the output terminal is connected to the output terminal of the NOP manager unit, and wherein the MUX is driven by the internal NOP code signal.

11. The microcontroller of claim 9, wherein the instruction decoder sequence block further receives at least the clock signal of the microcontroller.

12. The microcontroller according to claim 9, The instruction decoder combiner block includes: The input section is connected to the output terminal of the NOP manager unit; as well as The output section is connected to the internal output terminal of the instruction decoder combiner block. The input and output sections of the instruction decoder combiner block are interconnected, and The input section provides operation codes to the output section of the instruction decoder combiner block.

13. The microcontroller of claim 9, wherein the instruction decoder sequence block of the NOP manager unit further includes a data latch that receives a clock signal from the microcontroller and is connected to an output terminal of the NOP manager unit to provide internal memory instructions.

14. The microcontroller of claim 9, wherein the NOP manager unit further includes an additional internal latch inserted between an internal output terminal of the instruction decoder combiner block and the instruction decoder sequence block.

15. The microcontroller of claim 14, wherein an additional internal latch of the NOP manager unit receives a clock signal from the microcontroller and provides another internal NOP code signal to the instruction decoder sequence block at another internal output terminal.

16. The microcontroller of claim 15, wherein the pipeline comprises: A memory block stores multiple memory instructions at corresponding address signal values; An instruction register is connected to the memory block and receives the memory instructions from the memory block, and stores the corresponding register instructions; An instruction decoder is connected to the instruction register and decodes the register instructions received from the instruction register; as well as The final destination register is connected to the instruction decoder and stores the final instructions to be executed received from the instruction decoder.

17. The microcontroller of claim 16, wherein the execution of the final instruction is modified in the destination register.

18. The microcontroller of claim 17, further comprising the destination register.

19. A microcontroller that uses code requiring NOP instructions, the microcontroller comprising: A pipeline that manages multiple instructions of code to be used by the microcontroller, the multiple instructions including jump instructions that generate corresponding NOP instructions, and each of the jump instructions being encoded to include an internal NOP instruction; and The NOP manager unit executes the method according to any one of claims 1-8.

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