An interactive computing device and execution method for SIMD computing instructions

Abstract

The present invention provides an operation device for SIMD calculation instructions, comprising: a data packing pipeline register for receiving and storing a SIMD calculation instruction to be processed and a group of operands corresponding to the instruction; a fixed-point decoder for decoding and rearranging the operands corresponding to the fixed-point integer instruction and transmitting them to a fixed-point integer operator; a fixed-point integer operator for performing integer operations on the operands processed by the fixed-point decoder; a floating-point decoder for decoding and rearranging the operands corresponding to the floating-point instruction and transmitting the rearranged operands to a floating-point multiplier or a floating-point divider according to the instruction; a floating-point multiplier for performing floating-point multiplication and addition on the operands processed by the floating-point decoder; a floating-point divider for performing floating-point division on the operands processed by the floating-point decoder; and an operation result arbiter for selecting the operation results of the calculation components to output the final SIMD calculation result.

Description

Technical Field

[0001] The present invention relates to the field of computer system structure design, specifically, to the field of accelerator chip design, and more specifically, to an interactive computing device for SIMD computing instructions and a SIMD computing instruction execution method. Background Art

[0002] Computer instructions are instructions and commands that direct the work of the machine. In the computer system, the instruction processing process is further subdivided, such as Figure 1 As shown, it can be divided into the following six stages:

[0003] Instruction fetch stage (FI for short): fetches an instruction from the memory and places it into the instruction unit buffer;

[0004] Instruction decoding stage (abbreviated as DI): determines the nature of the operation and the method of forming the operand address;

[0005] Calculate operand address stage / address formation (abbreviated as CO): calculate the effective address of the operation;

[0006] Operand fetch stage (FO): fetch operands from memory;

[0007] Execute instruction stage (abbreviated as EI): execute the instruction and store the result in the destination location;

[0008] Write operand stage / write back result (abbreviated as WO): store the result into the register.

[0009] like Figure 1 As shown in the figure, the instruction execution process is divided into multiple stages. Each stage requires different resources and hardware. FI corresponds to the instruction fetch unit, DI corresponds to the instruction decoding unit, CO corresponds to the address formation unit, FO corresponds to the operand fetch unit, EI corresponds to the operation execution unit, and WO corresponds to the write-back result unit. Therefore, the pipeline multi-issue technology can be used to execute different stages of multiple instructions at the same time. Figure 2 As shown, a 6-stage pipeline operation of instructions can be realized. The vertical axis is the pipeline steps used simultaneously at each moment, and the horizontal axis is time. It can be seen that after dividing the instructions into stages, different stages of different instructions can be executed at the same time. For example, Figure 2 As shown in , in the second clock cycle, the DI stage of instruction 1 and the FI stage of instruction 2 can be executed simultaneously.

[0010] SIMD (Single Instruction Multiple Data) is a set of instructions that can copy multiple operands and pack them into large registers. Figure 3As shown, a SIMD calculation operand contains two data vectors, each vector contains multiple data components, one of which contains four data components A11, B11, C11, and D11, and the other vector contains four data components A12, B12, C12, and D12. In a SIMD-type CPU, after instruction decoding, several execution units access the memory at the same time and obtain all operands at one time for calculation. This feature makes SIMD particularly suitable for data-intensive operations such as multimedia applications. However, traditional SIMD technology and hardware modules have the following problems: 1. When it comes to multiple data precision types, such as single / double precision / fixed-point integer SIMD processing, multiple sets of pipelines need to be configured on the hardware, which results in high hardware overhead; 2. Traditional SIMD technology does not support conditional branches, such as Figure 4 As shown, different SIMD components need to execute different code paths according to branch conditions, and different results are difficult to merge under traditional SIMD technology.

[0011] The mainstream existing pipeline multi-issue technologies include superscalar technology and very long instruction word technology.

[0012] like Figure 5 As shown in the figure, superscalar technology is to issue multiple independent instructions simultaneously in each clock cycle. Multiple functional components and instruction decoding circuits, multiple register ports and buses are configured in the processor. The compiler determines which adjacent instructions can be executed in parallel. However, this technology has the following disadvantages: 1. It requires multiple sets of control logic for fetching, decoding, and writing back instructions, which consumes a lot of hardware resources; 2. The operation execution components (such as Figure 5 The EI part shown in ) can only be executed synchronously, which makes it difficult to support mixed computing precision with asynchronous clock cycles; 3. It cannot support SIMD computing mode.

[0013] The very long instruction word technology is to use the compiler to dig out the potential parallelism between instructions and combine multiple instructions that can be operated in parallel into a very long instruction with multiple opcode fields, such as Figure 6 The example shown combines the CO, FO, and DI stages into a single stage (EX). The EX stages of multiple instructions that can be executed in parallel are combined into a single, very long instruction with multiple opcode fields. However, this technique has the following drawbacks: 1. It requires compiler software to coordinate and schedule the program, making it difficult to separate the combined operands; 2. If the program mixes different computational precisions, compiler coordination becomes more difficult, resulting in poor parallel optimization results; and 3. It does not support SIMD computing.

[0014] In summary, the shortcomings of the existing technology can be summarized into the following two aspects:

[0015] 1. Traditional SIMD single instruction multiple data stream technology: When supporting multiple data precision formats, multiple sets of hardware pipelines are required, which is costly. In addition, traditional SIMD vector components do not support conditional branches, making it difficult to merge conditional results.

[0016] 2. Superscalar technology and very long instruction word technology: Requires multiple sets of control logic for instruction fetch, decoding, and write-back, resulting in high hardware resource overhead; the calculation execution part can only be executed synchronously, making it difficult to support mixed computing precision; the compiler needs to do a lot of instruction scheduling and coordination work; does not support SIMD computing mode, and the data computing throughput is insufficient. Summary of the Invention

[0017] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide a computing device for SIMD computing instructions and a SIMD computing instruction execution method.

[0018] According to a first aspect of the present invention, there is provided an operation device for SIMD calculation instructions, the operation device comprising: a data packing pipeline register for receiving and storing a SIMD calculation instruction to be processed and a set of operands corresponding to the instruction, and dispatching the operands to a fixed-point decoder or a floating-point decoder according to the type of instruction, wherein the instruction type includes a fixed-point integer instruction and a floating-point instruction; a fixed-point decoder for decoding and rearranging the operands corresponding to the fixed-point integer instruction and transmitting them to a fixed-point integer operator; a fixed-point integer operator ... The decoder performs integer operations on operands processed by the decoder; the floating-point decoder is used to decode and rearrange the operands corresponding to the floating-point instructions and transmit the rearranged operands to the floating-point multiplier or floating-point divider according to the instruction; the floating-point multiplier is used to perform floating-point multiplication and addition calculations on the operands processed by the floating-point decoder; the floating-point divider is used to perform floating-point division calculations on the operands processed by the floating-point decoder; the operation result arbiter is used to select the operation results of the fixed-point integer operator, floating-point multiplier and adder, and floating-point divider to output the final SIMD calculation result.

[0019] In some embodiments of the present invention, the number of operands in a group of operands received by the data packing pipeline register is 1 to 3. Preferably, each group of input operands is 1024-bit SIMD data.

[0020] In some embodiments of the present invention, the fixed-point decoder is configured to parse the input 1024-bit operand into 128 8-bit integers or 32 32-bit integers according to instruction precision requirements.

[0021] In some embodiments of the present invention, the floating-point decoder is configured to parse an input 1024-bit operand into 32 3-bit single-precision floating-point numbers or 16 64-bit double-precision floating-point numbers according to instruction precision requirements.

[0022] Preferably, the fixed-point integer arithmetic unit is configured to complete the calculation within one clock cycle; the floating-point multiplier-adder is configured to complete the calculation within two clock cycles; and the floating-point divider is configured to complete the calculation within nine clock cycles. Preferably, the calculation result arbiter is configured with a 3-bit result valid register for determining whether the calculation component has an output. The output ends of the fixed-point integer arithmetic unit, the floating-point multiplier-adder, and the floating-point divider respectively correspond to a bit of the result valid register. When the bit value is 1, it indicates that the calculation component corresponding to the bit has an output. When multiple components output calculation results simultaneously in the same clock cycle, the calculation result arbiter is configured to select the final result in the following priority order: floating-point divider > floating-point multiplier-adder > fixed-point integer arithmetic unit.

[0023] Preferably, the apparatus further comprises: a conditional mask flag register for storing a conditional mask and sending the conditional mask to the operation result arbiter to control it to merge calculation results of different branches of SIMD operands containing conditional branches.

[0024] According to a second aspect of the present invention, a method for executing SIMD computing instructions based on the device described in the first aspect of the present invention is provided, the method comprising the following steps: obtaining a SIMD computing instruction and a set of operands corresponding to the instruction; determining whether the instruction type is a fixed-point integer instruction or a floating-point instruction, so as to dispatch the operands corresponding to the fixed-point integer instruction to a fixed-point decoder, and dispatch the operands corresponding to the floating-point instruction to a floating-point decoder; performing decoding and rearrangement processing on the operands corresponding to the fixed-point integer instruction by the fixed-point decoder, and performing integer operations on the operands processed by the fixed-point decoder by the fixed-point integer operator; performing decoding and rearrangement processing on the operands corresponding to the floating-point instruction by the floating-point decoder, and selecting a floating-point multiplier-adder or a floating-point divider according to the instruction function to perform calculations on the operands processed by the floating-point decoder; and selecting the operation results of the fixed-point integer operator, the floating-point multiplier-adder, and the floating-point divider by an operation result arbiter to output a final SIMD calculation result.

[0025] According to a third aspect of the present invention, there is provided an acceleration chip, on which is configured an operation device for SIMD computing instructions as described in the second aspect of the present invention.

[0026] Compared with the prior art, the advantages of the present invention are: the present invention can achieve the following functions by adopting a single-issue + multi-unit selection arbitration method and a conditional mask marking method in the computing device: only one set of hardware resources for the instruction execution sequence is used, saving hardware resources and reducing component power consumption; the computing unit only uses a single control pipeline + arbiter selector, realizing the concurrent execution of three types of computing units with different precisions, covering the occasions of mixed operations with different precisions, and at the same time only occupying fewer hardware resources; each type of computing unit adopts the method of a vector unit, which can support the concurrent calculation of SIMD multiple data, has a relatively high data throughput, can realize asynchronous parallel execution during the instruction calculation process, supports calculation precision of different execution cycle numbers, and realizes asynchronous and efficient execution of computing units with different precisions and delays while retaining a single set of control pipelines; it is compatible with the SIMD single instruction multiple data mode, and realizes the branch control function of SIMD component results through conditional masks, thereby expanding the versatility of SIMD functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0028] Figure 1 A schematic diagram of a stage-by-stage instruction process in the prior art according to an embodiment of the present invention;

[0029] Figure 2 1 is a timing diagram of an instruction pipeline execution process according to the prior art of an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of an example of SIMD calculation according to an embodiment of the present invention;

[0031] Figure 4 Schematic diagram of an example of SIMD conditional branch calculation according to an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of a superscalar pipelining technique according to an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of a very long instruction word pipeline technology according to an embodiment of the present invention;

[0034] Figure 7 Schematic diagram of the structure of an interactive computing device for SIMD computing instructions according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] The purpose of the present invention is to solve the problems that the pipeline technology under the existing technology cannot support the SIMD computing mode and the traditional SIMD computing technology does not support mixed-precision computing. When the inventor was conducting research on the design of high-throughput computing components in general-purpose processors, he found that the design of computing components in the existing technology was relatively simple in terms of computing accuracy. For multi-precision computing scenarios, multiple sets of pipeline components are often required to implement them. There is redundancy in control logic and timing register resources, which brings large hardware overhead. In addition, the single-instruction, multiple-data type computing mode corresponding to SIMD does not have conditional judgment execution on data components, making it difficult to meet some simple conditional judgment operations in common program codes. In response to the above problems, the present invention specially designs a mixed-precision conditionally controllable SIMD vector component to solve the above problems.

[0037] According to one embodiment of the present invention, an interactive computing device for SIMD computing instructions is provided, the device comprising: a data packing pipeline register for receiving and storing a SIMD computing instruction to be processed and a set of operands corresponding to the instruction, and dispatching the operands to a fixed-point decoder or a floating-point decoder according to the type of instruction, wherein the instruction type includes a fixed-point integer instruction and a floating-point instruction; a fixed-point decoder for decoding and rearranging the operands corresponding to the fixed-point integer instruction and transmitting them to a fixed-point integer arithmetic unit; a fixed-point integer arithmetic unit for performing integer operations on the operands processed by the fixed-point decoder; and a floating-point decoder for decoding and rearranging the operands corresponding to the floating-point instruction. The invention further comprises a plurality of steps of: processing and selectively transmitting rearranged operands to a floating-point multiplier / adder or a floating-point divider according to the instruction function; a floating-point multiplier / adder for performing floating-point multiplication and addition calculations on operands processed by a floating-point decoder; a floating-point divider for performing floating-point division calculations on operands processed by a floating-point decoder; an operation result arbiter for selecting the operation results of the fixed-point integer operator, the floating-point multiplier / adder, and the floating-point divider to output a final SIMD calculation result; a conditional mask register for storing a conditional mask, sending the conditional mask to the operation result arbiter and controlling it to merge the calculation results of different branches of SIMD operands containing conditional branches to obtain a final SIMD calculation result. In order to better understand the present invention, the present invention will be described in detail below with reference to the accompanying drawings.

[0038] like Figure 7 The figure shows the interactive computing device for SIMD computing instructions and the component pipeline diagram during the operation of the computing device of the present invention. The computing device includes three types of component arrays with different computing precision types and scheduling control logic. Figure 7In the example shown, the three groups of computing components are: 1) 128 INT8-precision ALUs (fixed-point multiplication and addition units, also called fixed-point integer arithmetic units); 2) 32 single-precision float32 FALUS (single-precision multiplication and addition units); and 3) 16 single-precision float64 Fdivs (double-precision division units). The scheduling control logic is a condition mask register. The operation process of the computing device includes the following stages: input operands, instruction decoding and execution, and writeback of results.

[0039] 1. Input operands

[0040] The input operands are all SIMD data with a high bit width of 1024 bits, which are sent from pktDataReg (data packing pipeline register). Different instruction functions require different number of input operands, ranging from 1 to 3. Assuming that the operands are data0, data1, and data2, the following examples illustrate the different operands corresponding to different instruction functions:

[0041] (1) The FMADD floating-point multiply-add instruction implements the function result = data0 * data1 + data2 and requires three operands. The three required data operands are sequentially sent to the three input ports src_input0, src_input1, and src_input2 of the Falu single-precision multiply-add component. The Falu single-precision multiply-add component is a component that is easily seen in the field of chip design and will not be described in detail here.

[0042] (2) NOT fixed-point negation instruction, the function of which is result = ~data0, requires an operand, which is sent to src_input0 of the Alu fixed-point operation component. The fixed-point operation component is also a component that is easily seen in the field of chip design, and will not be described in detail here.

[0043] (3) FSUB floating-point subtraction instruction, the implementation function is result = data0-data1, which requires two operands. The required two data operands are sent to the two input ports src_input0 and src_input2 of Falu in sequence (src_input1 is left empty).

[0044] (4) The FDIV floating-point division instruction implements the function result = data0 / data1 and requires two operands. The two required data operands are sent to the two input ports src_input0 and src_input1 of the FDIV double-precision division component in sequence. The FDIV double-precision division component is a component that is easily seen in the field of chip design and will not be described in detail here.

[0045] 2. Instruction decoding and execution

[0046] If a fixed-point integer instruction is currently being executed, the operand is dispatched to the AluDecoder for decoding and rearrangement before being sent to the Alu (fixed-point integer arithmetic unit). A 1024-bit operand can be parsed into 128 int8 integers or 32 int32 integers, corresponding to the type of operation with different precision requirements. The fixed-point integer arithmetic unit can calculate the result in one clock cycle.

[0047] If a floating-point instruction is currently being executed, the operands will be dispatched to the fluDecoder (floating-point decoder) for decoding, and then selectively sent to the Falu (floating-point multiplier / accumulator) or Fdiv (floating-point divider) according to the instruction function. Each set of operands is also 1024 bits and can be parsed into 32 fp32 (single-precision floating-point numbers) or 16 fp64 (double-precision floating-point numbers). Falu calculates the result in 2 clock cycles, and Fdiv calculates the result in 9 clock cycles.

[0048] 3. Write back the results

[0049] The output ports of Alu, Falu, and Fdiv are all connected to the MUX (calculation result arbiter) for selection. Each calculation component corresponds to one bit, and the three calculation components correspond to three bits. When a calculation component outputs a result, the corresponding result valid register bit value of the calculation component is 1. If multiple calculation components output results simultaneously in the same clock cycle, the result valid register values ​​corresponding to the output ports of the three calculation components will be judged based on the priority (Fdiv>Falu>Alu) to select the result value that should be written back. To better understand the execution principle of writing back results, the following example is further explained.

[0050] Whether there is a result output is determined based on the 3-bit result valid register value sent to the output of the three calculation components:

[0051] 1) If only one of the three computing components outputs a result, that is, the register value is 001, 010, or 100, then select the current valid result to output.

[0052] 2) If the register value is 011, 110, or 101, it means that two components output results at the same time. At this time, the higher priority result is selected for output based on the priority (Fdiv>Falu>Alu).

[0053] 3) If the register value is 111, it means that the three components output results at the same time. At this time, the Fdiv division result with the highest priority is selected for output.

[0054] When a conditional branch occurs in a SIMD calculation, the MUX arbiter merges the component results obtained from different branches according to the conditional mask input by the 32-bit Condition Mask register, and combines them into the resulting SIMD data value as the final SIMD calculation result.

[0055] For example, assuming that a conditional branch occurs in a SIMD calculation: a set of operands includes integer addition operations and floating-point multiplication operations, the corresponding conditional mask will be stored in the Condition Mask register to instruct the MUX to merge the integer operation results and the floating-point multiplication results.

[0056] It can be seen that the present invention can achieve the following functions by adopting a single-issue + multi-unit selection arbitration method and a conditional mask marking method in the computing device: only one set of hardware resources for the instruction execution sequence is used, which saves hardware resources and reduces component power consumption. The computing component only uses a single control pipeline + arbiter selector to achieve concurrent execution of three types of computing components with different precisions, which can cover the occasions of mixed operations with different precisions and only occupy fewer hardware resources. Each type of computing component adopts the method of vector components, which can support the concurrent calculation of SIMD multiple data and has a relatively high data throughput. It can realize asynchronous parallel execution during the instruction calculation process and support calculation precision of different execution cycles. On the basis of retaining a single set of control pipelines, it realizes asynchronous and efficient execution of computing devices with different precisions and delays. It is compatible with the SIMD single instruction multiple data mode and realizes the branch control function of SIMD component results through conditional masks, which expands the versatility of SIMD functions.

[0057] It should be noted that although the above describes the various steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0058] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0059] Computer-readable storage media can be a tangible device that holds and stores the instructions used by an instruction execution device. Computer-readable storage media can, for example, include, but are not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, a punch card or a raised structure in a groove on which instructions are stored, for example, and any suitable combination thereof.

[0060] While various embodiments of the present invention have been described above, the above descriptions are intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computing device for SIMD computing instructions, characterized in that: The computing device includes: A data packing pipeline register is used to receive and store a SIMD computing instruction to be processed and a set of operands corresponding to the instruction, and dispatch the operands to a fixed-point decoder or a floating-point decoder according to the instruction type, wherein the instruction type includes fixed-point integer instructions and floating-point instructions; The fixed-point decoder is used to decode and reorder the operands corresponding to the fixed-point integer instructions and transmit them to the fixed-point integer arithmetic unit; Fixed-point integer arithmetic unit; used to perform integer operations on operands processed by the fixed-point decoder; A floating-point decoder is used to decode and rearrange the operands corresponding to the floating-point instructions and transmit the rearranged operands to the floating-point multiplier-accumulator or floating-point divider according to the instructions; A floating-point multiplier-adder, used for performing floating-point multiplication and addition calculations on operands processed by the floating-point decoder; A floating-point divider, used for performing floating-point division calculation on operands processed by the floating-point decoder; The calculation result arbiter is used to select the calculation results of the fixed-point integer operator, floating-point multiplier-accumulator, and floating-point divider to output the final SIMD calculation result; The conditional mask flag register is used to store the conditional mask and send the conditional mask to the operation result arbiter to control it to merge different branch calculation results of SIMD operands containing conditional branches.

2. The device according to claim 1, characterized in that The number of operands in a group of operands received by the data packing pipeline register is 1 to 3.

3. The device according to claim 2, characterized in that Each group of input operands is 1024-bit SIMD data.

4. The device according to claim 3, characterized in that The fixed-point decoder is configured to parse an input 1024-bit operand into 128 8-bit integers or 32 32-bit integers according to instruction precision requirements.

5. The device according to claim 3, characterized in that The floating-point decoder is configured to parse an input 1024-bit operand into 32 3-bit single-precision floating-point numbers or 16 64-bit double-precision floating-point numbers according to instruction precision requirements.

6. The device according to claim 1, characterized in that The fixed-point integer operator is configured to complete calculation within one clock cycle; the floating-point multiplier / accumulator is configured to complete calculation within two clock cycles; and the floating-point divider is configured to complete calculation within nine clock cycles.

7. The device according to claim 6, characterized in that The calculation result arbiter is configured with a 3-bit result valid register, which is used to determine whether the calculation component has output. The output ends of the fixed-point integer operator, floating-point multiplier and adder, and floating-point divider each correspond to a bit of the result valid register value. When the bit value is 1, it indicates that the calculation component corresponding to the bit has output.

8. The device according to claim 6, characterized in that When multiple components output calculation results simultaneously in the same clock cycle, the calculation result arbiter is configured to select the final result according to the following priority order: floating-point divider > floating-point multiplier-accumulator > fixed-point integer operator.

9. A method for executing SIMD computing instructions based on the device according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: Get SIMD calculation instructions and a set of operands corresponding to the instructions; Determine whether the instruction type is a fixed-point integer instruction or a floating-point instruction, so as to dispatch operands corresponding to the fixed-point integer instruction to a fixed-point decoder and dispatch operands corresponding to the floating-point instruction to a floating-point decoder; The fixed-point decoder decodes and rearranges the operands corresponding to the fixed-point integer instructions, and the fixed-point integer arithmetic unit performs integer operations on the operands processed by the fixed-point decoder; Decoding and rearranging the operands corresponding to the floating-point instructions through a floating-point decoder and selecting a floating-point multiplier-accumulator or a floating-point divider according to the instruction function to calculate the operands processed by the floating-point decoder; The calculation results of the fixed-point integer operator, floating-point multiplier-accumulator, and floating-point divider are selected by the calculation result arbiter to output the final SIMD calculation result.

10. An acceleration chip, characterized in that: The chip is equipped with a computing device for SIMD computing instructions as described in any one of claims 1-8.

11. A computer device, characterized in that: include: one or more processors; Each processor is configured with the chip as claimed in claim 10.

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