Methods, electronic devices, computer-readable storage media for mapping

Abstract

The present disclosure provides a mapping method, comprising: constructing a computation graph with a plurality of nodes according to a target algorithm to be mapped; mapping the nodes in the computation graph to processing units; wherein each node is connected with at least one other node and has an input and an output; the nodes comprise operation nodes, control nodes and switch nodes; each operation node is configured to perform a sub-operation on input data from its input to generate output data at its output; each control node is configured to perform a logical operation on input data from its input to generate a control instruction at its output; and each switch node is connected with at least one control node and configured to control the connection relationship between its input and output according to a control instruction from its connected control node. The present disclosure also provides an electronic device and a computer readable storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of computational graph mapping technology, and in particular to mapping methods, electronic devices, and computer-readable storage media. Background Technology

[0002] To improve operational efficiency, different parts of the overall computation (the computation used to achieve a specific function, such as speech recognition or image processing) can be mapped (or allocated) to different processing units for execution. For example, different neurons or layers in a neural network can be mapped to different processing cores in a many-core system for separate execution.

[0003] To achieve mapping, a "computation graph" must first be constructed. This graph uses multiple nodes and connections between them to represent the overall logical process of the operation. Each node represents a sub-operation within the overall operation, while connections represent the flow of data (tokens) between nodes. For example, the output of one node is connected to the input of another, meaning the output data of the preceding node serves as the input data for the following node (e.g., the result of one neuron's operation serves as the basis for the operation of another neuron). Once the computation graph is obtained, each node can be mapped to the corresponding processing unit.

[0004] With the development of technology, more and more computations involve "control flow," meaning that the actual computation process may differ depending on the input. For example, decision-making and looping processes all fall under control flow. In related technologies, even a simple control flow can greatly increase the complexity of the computation graph (control explosion). This poses significant challenges to the construction and understanding of the computation graph, leading to unreasonable mapping results based on such a graph, failure to fully utilize the computing power of each processing unit, and an increase in the amount of data that needs to be transferred between different processing units. Summary of the Invention

[0005] This disclosure provides a mapping method, an electronic device, and a computer-readable storage medium.

[0006] In a first aspect, embodiments of this disclosure provide a mapping method, which includes:

[0007] Construct a computation graph with multiple nodes based on the target algorithm to be mapped;

[0008] Map the nodes in the computation graph to the processing unit;

[0009] Each node is connected to at least one other node and has inputs and outputs; the nodes include arithmetic nodes, control nodes, and switching nodes; each arithmetic node is used to perform sub-operations on input data from its inputs to generate output data at its output; each control node is used to perform logical operations on input data from its inputs to generate control instructions at its output; each switching node is connected to at least one control node and is used to control the connection relationship between its inputs and outputs according to the control instructions from the control node to which it is connected.

[0010] In some embodiments, the node further includes a connection node;

[0011] Each of the connection nodes includes a varying number of connections and inputs, wherein each input is connected to at least one output, and each output is connected to at least one input.

[0012] In some embodiments, before mapping the nodes in the computation graph to the processing unit, the method further includes at least one of the following:

[0013] Merge two directly connected switching nodes into one switching node;

[0014] Split a switching node into two directly connected switching nodes.

[0015] In some embodiments, before mapping the nodes in the computation graph to the processing unit, the method further includes at least one of the following:

[0016] Merge two control nodes connected to the same switching node into one control node;

[0017] Split a control node into two control nodes connected to the same switching node.

[0018] In some embodiments, mapping nodes in the computation graph to the processing unit includes:

[0019] The nodes in the computation graph are mapped to the processing cores of the many-core system.

[0020] In some embodiments, mapping nodes in the computation graph to the processing unit includes:

[0021] The nodes in the computation graph are mapped to at least two different types of processing units; wherein nodes of the same type are mapped to the same type of processing unit.

[0022] In some embodiments, when mapping nodes in the computation graph to at least two different types of processing units, at least one of the following is satisfied:

[0023] The operation node is mapped to a processor;

[0024] The control node is mapped to a logic controller;

[0025] The switching node is mapped to a switching circuit.

[0026] In some embodiments, the operation node satisfies at least one of the following:

[0027] At least part of the operation node operates when all inputs thereof have input data;

[0028] At least part of the operation node operates when at least one input thereof has input data.

[0029] In a second aspect, the present disclosure provides an electronic device, which comprises:

[0030] At least one processor;

[0031] A memory in communication connection with the at least one processor;

[0032] The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to execute the mapping method described above.

[0033] In a third aspect, the present disclosure provides a computer readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the mapping method described above.

[0034] In the embodiments of the present disclosure, the control node plays a role of deciding "what control to perform", and the switching node "implements the corresponding control", so that each control (such as judgment) can be implemented through two nodes (the control node and the switching node); therefore, for the same operation with control flow, the computing graph obtained by the embodiments of the present disclosure is much simpler than the computing graph structure based on data flow, the computing graph is easy to construct and easy to understand, and the mapping result obtained according to such a computing graph is more reasonable, can fully utilize the computing power of each processing unit, and reduces the amount of data to be transmitted between different processing units. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the detailed embodiments serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed embodiments described below, with reference to the accompanying drawings, in which:

[0036] Figure 1A computation graph constructed according to certain operations in the related art;

[0037] Figure 2 A flowchart of a mapping method provided by an embodiment of the present disclosure;

[0038] Figure 3 A computation graph constructed according to certain operations in a mapping method of an embodiment of the present disclosure;

[0039] Figure 4 A schematic diagram of the role of a switching node in a mapping method of an embodiment of the present disclosure;

[0040] Figure 5 A schematic diagram of a node merging process in a mapping method of an embodiment of the present disclosure;

[0041] Figure 6 A component block diagram of an electronic device provided by an embodiment of the present disclosure;

[0042] Figure 7 A component block diagram of a computer readable storage medium provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To enable persons skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0044] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0045] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" and / or "consist of, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "connected" or "coupled" and / or similar terms are not limited to a physical or mechanical connection or linkage to either another part or device and can also include an electrical connection, whether direct or indirect.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0048] In some related technologies, a computation graph (also referred to as a data flow graph) is mainly constructed based on a "data flow", and mapping is performed according to the computation graph.

[0049] In the data flow-based computation graph, when there is a control flow process such as a judgment, a loop, etc., each different result branch is respectively regarded as a different connection (or a different data flow), which greatly increases the complexity of the computation graph.

[0050] For example, for the operation represented by the following program code including a control flow (a judgment process), according to the related technologies, the corresponding data flow-based computation graph can be referred to as Figure 1 (see related technology Dennis J B, Fosseen J B, Linderman J P. Data flow schemas [J]. Lecture Notes in Computer Science, 1974: 187-216):

[0051]

[0052] Figure 1 In the computation graph, x, y, w, v, z respectively represent corresponding data (tokens), h, f, p, q, g respectively represent corresponding functions (sub-operations), T, F respectively represent the case that the judgment result is true (True) or false (False), the connection line represents the connection, and the arrow represents the data flow direction in the connection.

[0053] As can be seen, the logic process represented by the above program code is actually very simple, but the corresponding computation graph is already very complex. Therefore, according to the mapping manner of the related technologies, the computation graph structure is complex, which causes great difficulty in the construction and understanding of the computation graph, and the mapping result according to the computation graph is unreasonable, the computing power of each processing unit cannot be fully utilized, and the amount of data to be transmitted between different processing units is increased.

[0054] In a first aspect, the embodiments of the present disclosure provide a mapping method.

[0055] The mapping method of the embodiments of the present disclosure is used to map (or assign) a target algorithm (such as a neural network) that needs to be run to processing units of a processing device.

[0056] The target algorithm (such as a neural network) that needs to be run is used to implement a certain function, such as speech recognition, image processing, etc.

[0057] The processing device includes a plurality of processing units, each of which has a certain data processing capability, and data transmission can be achieved between different processing units; thus, after mapping is completed, each processing unit can process part of the content of the target algorithm mapped thereto, and the above target algorithm is collectively implemented through cooperation of the processing units.

[0058] The mapping method of the embodiments of the present disclosure can be implemented by an independent mapping device, or by part of the devices (such as a separate controller or part of the processing units) in the processing device.

[0059] Referring to Figure 2 The mapping method of the embodiments of the present disclosure includes:

[0060] S101, constructing a computation graph having a plurality of nodes according to a target algorithm to be mapped.

[0061] S102, mapping the nodes in the computation graph to the processing units.

[0062] Each node is connected with at least one other node and has an input and an output; the nodes include operation nodes, control nodes, and switching nodes; each operation node is used to perform a sub-operation on input data from its input to generate output data at its output; each control node is used to perform a logical operation on input data from its input to generate a control instruction at its output; and each switching node is connected with at least one control node and is used to control a connection relationship between its input and output according to a control instruction from the control node connected thereto.

[0063] In the mapping method of the embodiments of the present disclosure, a computation graph is first constructed according to the target algorithm.

[0064] The computation graph includes a plurality of nodes, each of which has one or more inputs (input ends) and one or more outputs (output ends), so that each node can perform a certain processing on input data from its input to generate output data at its output. The computation graph also includes connections between different nodes, which are used to transmit data (tokens), such as output data generated by one node, to the input of another node.

[0065] After the above computation graph is obtained, the nodes therein are mapped to processing units in the processing device, specifically, each node must be mapped to a processing unit for processing, of course, one or more nodes can be mapped in each processing unit of the processing device, or no node can be mapped; thus each processing unit can process the computation of the node mapped therein, and if the nodes having a connection (i.e. data transmission is required) are located in different processing units, data transmission between the corresponding processing units is required.

[0066] From the perspective of fully utilizing the processing capability of the processing device, the computation graph is usually mapped to multiple processing units; but when the total size of the computation graph is small, if all nodes are mapped to one processing unit, it is also feasible.

[0067] In the computation graph of the embodiments of the present disclosure, in addition to the operation nodes directly used for performing certain actual operations (sub-operations), there are also control nodes and switch nodes.

[0068] Among them, the control node can generate a certain control instruction according to the input data, that is, perform a certain logical processing (such as judging whether the input data meets a certain condition) on the input data, and determine what operation should be performed in the current situation according to the result of the logical processing (such as the judgment result), that is, determine how the data should flow at present, and generate the corresponding control instruction.

[0069] And the switch node (Switch) can change the connection relationship between its input and output according to the control instruction from the control node, that is, determine which (or which) output the data from each input of it can be transmitted to, so that the switch node can change the connection relationship between other nodes according to the control instruction without performing substantial operation, that is, "control the flow of data".

[0070] In the embodiments of the present disclosure, the control node plays a role in determining "what control to perform", and the switch node "implements the corresponding control", so that each control (such as judgment) can be implemented through two nodes (control node and switch node); therefore, for the same operation with control flow, the computation graph obtained by the embodiments of the present disclosure is much simpler than the computation graph structure based on data flow, the computation graph is easy to construct and easy to understand, and the mapping result obtained according to such computation graph is more reasonable, which can fully utilize the computing power of each processing unit and reduce the amount of data to be transmitted between different processing units

[0071] For example, for the above computation graph based on data flow ( Figure 1 ), the corresponding computation graph according to the manner of the embodiments of the present disclosure can refer to Figure 3 It can be seen that Figure 3 the structure of the computation graph in Figure 1 is much simpler than the structure of the computation graph in

[0072] Figure 3 In the figures, the meaning of each figure is as the description above, x, y, w, v, z represent the corresponding data (Token) respectively, h, f, p, q, g represent the corresponding function (sub-operation) respectively, the line represents the connection, and the arrow represents the data flow direction in the connection.

[0073] The specific form of the control instruction is various. For example, the control instruction can be in the form of a "matrix".

[0074] Specifically, referring to Figure 4 On the left side, assuming that a switching node has four inputs a1, a2, a3, a4 and three outputs b1, b2, b3, the corresponding control instruction of the switching node can be a 4-row*3-column matrix.

[0075] If the control instruction is a matrix in Figure 4 , the connection represented thereby can refer to Figure 4 On the right side, that is, the input data from the input a2 can reach the output b1 (that is, the input a2 is connected to the output b1), the input data from the input a3 can reach the output b2, and the input data from the inputs a1, a3, a4 can all reach the output b3.

[0076] Of course, according to different control instructions, the connection relationship represented by the switching node is also different.

[0077] In some embodiments, the node further includes a connection node;

[0078] Each connection node includes a number of connections and inputs, wherein each input is connected to at least one output, and each output is connected to at least one input.

[0079] Referring to Figure 3 , the computing graph obtained by the embodiments of the present disclosure can further include a connection node, which also does not perform substantial operation, but is used to connect each input to one or more outputs, that is, to realize the shunting (duplication), convergence, cross, etc. of data, so as to change the flow direction of data.

[0080] Therefore, the connection node can be regarded as a special "switching node (static switching node)"; and the difference from the actual switching node is that the connection relationship between the input and the output in the connection node is determined, rather than changing the connection relationship according to the switching instruction.

[0081] It should be understood that the number of inputs and outputs of the connection node should be different, that is, each input cannot be connected to only one output, because if so, it is equivalent to one or more connections, rather than a node.

[0082] For example, referring toFigure 3 The graphic within the switching node has a three-pronged top and a single-pronged bottom, indicating that the switching node is used to connect all three inputs to the single output.

[0083] It should be understood that switching nodes can also achieve other functions, such as splitting (copying) an input to multiple outputs.

[0084] It should be understood that Figure 3 The specific graphics within the switching nodes shown are merely illustrative and not intended to limit the embodiments of this disclosure.

[0085] In some embodiments, before mapping nodes in the computation graph to the processing unit (S102), at least one of the following is further included:

[0086] S1011. Merge two directly connected switching nodes into one switching node.

[0087] S1012. Split a switching node into two directly connected switching nodes.

[0088] S1013. Merge two control nodes connected to the same switching node into one control node.

[0089] S1014. Split a control node into two control nodes connected to the same switching node.

[0090] As one embodiment of this disclosure, after obtaining the computation graph, the switching nodes and control nodes therein can be merged or split to further optimize the computation graph. Then, the nodes in the optimized computation graph are mapped to obtain better mapping results.

[0091] For example, refer to Figure 5 ,right Figure 3 The computational graph shown has two switching nodes that are directly connected and controlled by two control nodes respectively. Therefore, the two can be merged into a single switching node that is controlled by two control nodes and can perform more complex switching functions.

[0092] For example, refer to Figure 5 After the switching nodes are merged, two of the control nodes are essentially controlling the same switching node. Therefore, these two control nodes can also be merged into one control node, which can then generate more complex control commands based on more complex rules to control the switching node.

[0093] It should be understood that the process of splitting control nodes and switching nodes is the reverse process, and will not be described in detail here.

[0094] It should be understood that Figure 3The connection node also can be regarded as a state-invariant "static switching node", as before, and thus reference is made to Figure 5 The connection node can also be merged with the switching node, but part of the connection relationship in the merged switching node is fixed and invariable.

[0095] It should be understood that whether the above splitting and merging steps are performed and which nodes are specifically split and merged can be determined according to the situation of the computation graph and the situation of the processing unit each time the method of the embodiments of the present disclosure is executed.

[0096] It should be understood that the operation nodes can also be split, merged, and the like. For example, when the operation amount required by a single operation node is too large to be mapped into a processing unit, it can be split into multiple serial or parallel operation nodes; and multiple serial or parallel operation nodes can also be merged for processing by one operation node.

[0097] In some embodiments, mapping the nodes in the computation graph into the processing units (S102) includes:

[0098] S1021, mapping the nodes in the computation graph into the processing cores of the many-core system.

[0099] As a way of the embodiments of the present disclosure, each node in the computation graph can be mapped into a processing core of the many-core system, that is, the target operation is mapped into the many-core system.

[0100] The many-core system includes multiple processing cores with processing capabilities; and data transmission between the processing cores and between the processing cores and the outside of the many-core system can be achieved through an on-chip network; by mapping part of the nodes of the computation graph in each processing core, the many-core system can be used to process the target operation, for example, to run a neural network using the many-core system.

[0101] In some embodiments, mapping the nodes in the computation graph into the processing units (S102) includes:

[0102] S1022, mapping the nodes in the computation graph into at least two different types of processing units.

[0103] Among them, nodes of the same type are mapped into processing units of the same type.

[0104] As another way of the embodiments of the present disclosure, multiple different types of processing units can also be provided, each of which is particularly suitable for processing nodes of different types (of course, at this time, the nodes of the computation graph must be mapped into multiple processing units), so that each type of node can be mapped into a processing unit of the corresponding type to further make full use of the computing power of the processing units.

[0105] In some embodiments, when mapping the nodes in the computation graph to at least two different types of processing units (S1022), at least one of the following is satisfied:

[0106] The operation nodes are mapped to processors;

[0107] The control nodes are mapped to logic controllers;

[0108] The switching nodes are mapped to switch circuits.

[0109] As a specific way of the embodiments of the present disclosure, the operation nodes mainly perform actual operations (such as addition, subtraction, multiplication, division, matrix operation, etc.), so they can be mapped to processors (such as processing cores) for processing general operations; and the control nodes mainly perform logical operations (such as comparison, judgment, etc.), so they can be mapped to logic controllers for implementation; and the switching nodes actually act as "switches", so they can be mapped to switch circuits (such as gate circuits) for implementation, and of course, the switch circuits should be controlled by control instructions.

[0110] In some embodiments, at least one of the following is satisfied for the operation nodes:

[0111] At least part of the operation nodes performs operation only when all inputs have input data;

[0112] At least part of the operation nodes performs operation when at least one input has input data.

[0113] As mentioned before, the computation graph constructed according to the embodiments of the present disclosure includes control nodes and switching nodes, and since the switching nodes change the data flow direction, the input data of the operation nodes at different times may be different, such as there may be a case that "sometimes all inputs have input data, and sometimes part or all inputs have no input data".

[0114] And according to the different needs of the operation nodes, different "triggering rules (starting rules)" can be set for different operation nodes, that is, the operation nodes only perform operation when the triggering rules are met, for example, the triggering rules can be that all inputs must have input data to perform operation, or the triggering rules can be that as long as at least one input or part of specific inputs has input data, the operation is performed.

[0115] For example, if an operation node has three inputs, and its sub-operation is to sum the input data as output data, its triggering rule can be to perform summation calculation only when all three inputs have input data, or its triggering rule can be to perform summation calculation as long as at least one input (or part of specific inputs) has input data (the input without input data can be considered as 0).

[0116] It should be understood that the above trigger rules cannot contradict the requirements of the sub-operations of the operation node. For example, if a certain operation node must perform an operation based on multiple input data, it must not be triggered when it has only one input with input data.

[0117] It should be understood that the control node performs a certain logical operation on its input data and generates a control instruction, which can also be regarded as the control node working according to a certain trigger rule (i.e., generating a control instruction according to the input only when the trigger rule is met). For example, if a certain control node has two inputs and performs a "comparison operation" on the two inputs, and generates a control instruction when a certain comparison result (such as the two input data being the same) is obtained; the trigger rule of the control node can also be regarded as "both inputs have input data, and the two input data are the same, that is, triggering".

[0118] It should be understood that the switching node controls the connection relationship between its input and output according to the control instruction, which can also be regarded as the switching node working according to a certain trigger rule (i.e., at least one input and output are connected only when the trigger rule is met). For example, if a certain switching node has one input and one output, and is simultaneously connected to control node 1, control node 2, and control node 3, and the input and output are connected when there are control instructions in control node 1 and control node 2 at the same time, and / or there is a control instruction in control node 3; the trigger rule of the switching node can also be regarded as "triggering at least one of the following: (1) control node 1 and control node 2 have control instructions at the same time, (2) control node 3 has a control instruction".

[0119] It should be understood that the connection relationship between the input and output of the connection node is determined, so it can also be regarded as a special static switching node, and therefore whether the connection node has output data is only determined by the condition of its input data, which can also be regarded as the connection node working according to a certain trigger rule (i.e., generating output data on the output only when the trigger rule is met). For example, if the three inputs of a certain connection node are connected to the same output, the trigger rule of the connection node can be regarded as "triggering as long as at least one input has input data".

[0120] In a second aspect, the present disclosure provides an electronic device.

[0121] With reference to Figure 6 , the electronic device 500 of the embodiment of the present disclosure comprises:

[0122] at least one processor 501;

[0123] a memory 502 in communication connection with the at least one processor 501;

[0124] The memory 502 stores one or more computer programs executable by the at least one processor 501, and the at least one processor 501 executes the one or more computer programs to enable the at least one processor 501 to perform the mapping method described above.

[0125] In a third aspect, the present disclosure provides a computer-readable storage medium.

[0126] With reference to Figure 7 The computer-readable storage medium 600 of the embodiment of the present disclosure stores a computer program, and the computer program, when executed by a processor (including a processing core), implements the mapping method described above.

[0127] The computer-readable storage medium of the embodiment of the present disclosure can be a volatile or non-volatile computer-readable storage medium.

[0128] The embodiment of the present disclosure also provides a computer program product, including computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in the processor of the electronic device, the processor in the electronic device performs the mapping method described above.

[0129] Those skilled in the art can understand that all or some steps in the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0130] As those skilled in the art will appreciate, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as those skilled in the art will appreciate, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. As used herein, the term "exemplary" means serving as an example, instance, or illustration. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations.

[0131] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0132] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or any combination of one or more of the above in any combination, written in any combination of one or more programming languages, including object oriented programming languages such as Smalltalk, C++ or the like, and conventional procedural programming languages such as "C" or the like. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0133] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), and the like.

[0134] The various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer readable program instructions.

[0135] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0136] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0137] The flow and block diagrams in the drawings show architectural, functional, and operational aspects of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may

[0138] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the convenience of the reader and is not intended to be limiting. In some instances, specific details have been included for the purpose of providing a thorough understanding of the embodiments presented, but it will be apparent to those skilled in the art that embodiments of the application can be practiced without these specific details. In some instances, features, characteristics and / or elements described in connection with a particular embodiment can be used in conjunction with, or switched to, features, characteristics and / or elements described in connection with other embodiments, unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A mapping method, characterized in that, include: Construct a computation graph with multiple nodes based on the target algorithm to be mapped; Map the nodes in the computation graph to the processing unit; Each node is connected to at least one other node and has inputs and outputs; the nodes include computation nodes, control nodes, and switching nodes; each computation node performs sub-operations on input data from its inputs to generate output data at its output; each control node performs logical operations on input data from its inputs to generate control instructions at its output; wherein the control instructions characterize the connection mapping relationship between the inputs and outputs of the corresponding switching node; each switching node is connected to at least one control node and controls the connection relationship between its inputs and outputs according to the control instructions from the control node to which it is connected; The control commands are represented in matrix form. The number of rows and columns of the matrix is ​​determined according to the number of inputs and outputs of the corresponding switching node. Any element value in the matrix is ​​used to represent the connection relationship between the corresponding input and output.

2. The method according to claim 1, characterized in that, The node also includes connection nodes; Each of the connection nodes includes a varying number of connections and inputs, wherein each input is connected to at least one output, and each output is connected to at least one input.

3. The method according to claim 1, characterized in that, Before mapping the nodes in the computation graph to the processing unit, the method further includes at least one of the following: Merge two directly connected switching nodes into one switching node; Split a switching node into two directly connected switching nodes.

4. The method according to claim 1, characterized in that, Before mapping the nodes in the computation graph to the processing unit, the method further includes at least one of the following: Merge two control nodes connected to the same switching node into one control node; Split a control node into two control nodes connected to the same switching node.

5. The method according to claim 1, characterized in that, The step of mapping the nodes in the computation graph to the processing unit includes: The nodes in the computation graph are mapped to the processing cores of the many-core system.

6. The method according to claim 1, characterized in that, The step of mapping the nodes in the computation graph to the processing unit includes: The nodes in the computation graph are mapped to at least two different types of processing units; wherein nodes of the same type are mapped to the same type of processing unit.

7. The method according to claim 6, characterized in that, When mapping nodes in the computation graph to at least two different types of processing units, at least one of the following conditions must be met: The computing nodes are mapped into the processor; The control node is mapped to the logic controller; The switching node is mapped to a switching circuit.

8. The method according to claim 1, characterized in that, The computing node satisfies at least one of the following: At least some of the aforementioned computing nodes perform operations only when all of their inputs have input data; At least some of the computing nodes perform operations when at least one of their inputs has input data.

9. An electronic device, characterized in that, include: At least one processor; A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the mapping method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the mapping method as described in any one of claims 1 to 8.

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