Processing unit, its operation method, and computing chip

Abstract

A processing unit, its operation method, and a computing chip. The processing unit includes: a memristor array configured to be mapped as a weight matrix for a network layer of a neural network; an input module configured to receive input data and convert the input data into an input signal to input into the memristor array; an output module configured to receive an output signal obtained after the memristor array performs computational processing on the input signal and convert the output signal into output data; a sign logic module configured to respectively obtain the sign values of each element in a first input vector, a first output vector, and a first error vector, and determine the update direction of each weight parameter in the weight matrix according to these sign values; an update logic module configured to update the conductance values of each memristor corresponding to each weight parameter in the memristor array according to the update direction of each weight parameter in the weight matrix.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processing unit, an operation method thereof, and a computing chip. Background Art

[0002] Artificial neural networks have shown excellent performance in fields such as image recognition and classification, natural language processing, and decision-making and control, and have been widely applied to various intelligent devices such as mobile phones and autonomous driving vehicles. Currently, the training of artificial neural network models is usually completed in the cloud. Intelligent devices can only run pre-deployed models, cannot achieve online training, and cannot dynamically adjust model parameters according to actual scenarios. This is because traditional computing systems adopt a separated memory and computing architecture. The latency and energy consumption caused by off-chip memory access restrict the performance of the computing system, and further limit the realization of the online training function of intelligent devices.

[0003] The memory-computation integrated computing technology based on memristors can greatly reduce the memory access overhead, is expected to significantly improve the energy efficiency and computing power of the computing system, and further support intelligent devices to achieve the online training function. Implementing a complete chip based on memristors that supports online training is a prerequisite for its large-scale application. Currently, there have been some studies on memristor-based online training computing systems, including device optimization and array-level demonstrations, etc., but there is still a lack of reports on complete chips that support online training. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a processing unit, which includes: a memristor array configured to be mapped as a weight matrix for a network layer of a neural network; an input module configured to receive input data and convert the input data into an input signal to input into the memristor array; an output module configured to receive an output signal obtained after the memristor array performs computational processing on the input signal, and convert the output signal into output data; an error solving module configured to obtain a first error vector of the network layer according to the output data; a sign logic module configured to, based on a first input vector and a first output vector of the memristor array corresponding to the network layer obtained from the forward calculation process of the neural network, and the first error vector of the subsequent network layer adjacent to the network layer obtained from the error solving module, respectively obtain the sign values of each element in the first input vector, the first output vector, and the first error vector, so as to determine the update direction of each weight parameter in the weight matrix according to the sign values of each element in the first input vector, the first output vector, and the first error vector; and an update logic module configured to update the conductance values of each memristor corresponding to each weight parameter in the memristor array according to the update direction of each weight parameter in the weight matrix.

[0005] For example, a processing unit provided in some embodiments of the present disclosure further includes: an array driving module configured to apply a voltage signal as the input signal to the memristor array or receive a current signal as the output signal from the memristor array in response to a control signal; and a processing unit module configured to switch and schedule the working mode of the processing unit.

[0006] For example, in a processing unit provided in some embodiments of the present disclosure, the input module includes: a first input module configured to generate a first input signal according to first input data of a forward calculation task and input the first input signal into the memristor array, and a second input module configured to generate a second input signal according to second input data of a backward calculation task and input the second input signal into the memristor array, where the input data includes the first input data and the second input data, and the input signal includes the first input signal and the second input signal; the output module includes: a first output module configured to receive a first output signal obtained by the memristor array performing forward calculation processing on the first input signal and generate first output data according to the first output signal, and a second output module configured to receive a second output signal obtained by the memristor array performing backward calculation processing on the second input signal and generate second output data according to the second output signal, where the output data includes the first output data and the second output data, and the output signal includes the first output signal and the second output signal.

[0007] For example, in a processing unit provided in some embodiments of the present disclosure, the array driving module includes: a first array driving module configured to receive a first input voltage signal corresponding to the first input signal and apply the first input voltage signal to the memristor array in a forward calculation state, and a second array driving module configured to receive a second input voltage signal corresponding to the second input signal and apply the second input voltage signal to the memristor array in a backward calculation state.

[0008] For example, in a processing unit provided in some embodiments of the present disclosure, the symbol logic module is further configured to obtain the binary symbol value of each element in the first input vector according to a first threshold parameter; or obtain the ternary symbol value of each element in the first input vector according to two first threshold parameters; the symbol logic module is further configured to obtain the binary symbol value of each element in the first output vector according to a second threshold parameter; obtain the ternary symbol value of each element in the first output vector according to two second threshold parameters; and the symbol logic module is further configured to obtain the binary symbol value of each element in the first error vector according to a third threshold parameter; or obtain the ternary symbol value of each element in the first error vector according to two third threshold parameters.

[0009] For example, in a processing unit provided in some embodiments of the present disclosure, the symbol logic module is further configured to take the first n bits of the digital-form signal obtained after analog-to-digital conversion to be used for setting the first threshold parameter, the second threshold parameter, or the third threshold parameter, where n is a positive integer.

[0010] For example, in a processing unit provided in some embodiments of the present disclosure, when the first threshold parameter, the second threshold parameter, and the third threshold parameter are fixed values, the symbol logic module is further configured to amplify the value of each element in the first input vector, the first output vector, and the first error vector, and respectively obtain the symbol value of each element in the first input vector, the first output vector, and the first error vector according to the first threshold parameter, the second threshold parameter, and the third threshold parameter and the amplified first input vector, first output vector, and first error vector.

[0011] For example, in a processing unit provided in some embodiments of the present disclosure, the symbol logic module is further configured to take the nth period of the pulse-form signal obtained after analog-to-digital conversion to be used for setting the first threshold parameter, the second threshold parameter, or the third threshold parameter, where n is a positive integer.

[0012] For example, in a processing unit provided in some embodiments of the present disclosure, the symbol logic module is further configured to use a reference voltage as the third threshold parameter, and includes: an integration circuit configured to integrate the current signal corresponding to the value of each element in the first error vector; and a comparison circuit configured to compare the output voltage of the integration circuit with the third threshold parameter to obtain the symbol value of each element in the first error vector.

[0013] For example, in a processing unit provided in some embodiments of the present disclosure, the number of at least one of the first threshold parameter, the second threshold parameter, and the third threshold parameter is two, so that at least one of the obtained first input vector, first output vector, and first error vector is a ternary symbol value.

[0014] For example, in a processing unit provided in some embodiments of the present disclosure, for the case of updating the conductance values of the memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix, the update logic module is configured to: increase the conductance value of the memristor when the sign of the weight parameter is positive, or decrease the conductance value of the memristor when the sign of the weight parameter is negative.

[0015] Some embodiments of the present disclosure further provide a computing chip, which includes the processing unit in any of the above embodiments.

[0016] Some embodiments of the present disclosure further provide an operation method for the above-mentioned any processing unit. The operation method includes: mapping the weight matrix for the network layer of the neural network to the memristor array; receiving, through the input module, the input data and converting the input data into an input signal to input into the memristor array; receiving, through the output module, the output signal obtained after the memristor array performs calculation processing on the input signal, and converting the output signal into output data; obtaining, through the error solving module, the first error vector of the network layer according to the output data; based on the first input vector and the first output vector of the memristor array corresponding to the network layer obtained from the forward calculation process of the neural network, and the first error vector of the subsequent network layer adjacent to the network layer obtained from the error solving module, respectively obtaining the sign values of each element of each of the first input vector, the first output vector, and the first error vector, so as to determine the update directions of the respective weight parameters in the weight matrix according to the sign values of each element of each of the first input vector, the first output vector, and the first error vector; and updating the conductance values of the memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix through the update logic module. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0018] Figure 1ASchematic diagram of a neural network proposed by at least one embodiment of the present disclosure;

[0019] Figure 1B Schematic diagram of a processing unit proposed by at least one embodiment of the present disclosure;

[0020] Figure 2A Schematic diagram of a memristor device provided by at least one embodiment of the present disclosure;

[0021] Figure 2B Schematic diagram of another memristor device provided by at least one embodiment of the present disclosure

[0022] Figure 3 Schematic diagram of the calculation process of a processing unit proposed by at least one embodiment of the present disclosure;

[0023] Figure 4 Schematic diagram of a threshold parameter selection method proposed by at least one embodiment of the present disclosure;

[0024] Figure 5 Schematic diagram of an error solving module proposed by at least one embodiment of the present disclosure;

[0025] Figure 6 Schematic diagram of a symbolic logic module proposed by at least one embodiment of the present disclosure;

[0026] Figure 7 Schematic diagram of another symbolic logic module proposed by at least one embodiment of the present disclosure;

[0027] Figure 8 Schematic diagram of a computing chip proposed by at least one embodiment of the present disclosure; and

[0028] Figure 9 Schematic diagram of the calculation process of a computing chip proposed by at least one embodiment of the present disclosure. Detailed implementation manners

[0029] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the described embodiments of the present disclosure fall within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] The following illustrates this disclosure through several specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components (elements) may be omitted. When any component (element) of an embodiment of this disclosure appears in more than one drawing, the component (element) is denoted by the same or similar reference numerals in each drawing.

[0032] Currently, the memristor-based in-memory computing system relies on the Back Propagation (BP) algorithm to calculate the weight update amount, and relies on verify write to accurately program the memristors for mapping weights to update the weights. The backpropagation algorithm is similar to updating the weight matrix of each layer of the neural network algorithm layer by layer in the direction opposite to the forward propagation algorithm of the forward calculation. The update value of the weight matrix is calculated from the error value of each layer. The error value of each layer is obtained by multiplying the transpose of the weight matrix of the subsequent layer adjacent to this layer by the error value of the subsequent layer. Therefore, under the condition of obtaining the error value of the last layer of a neural network algorithm and the weight matrix of the last layer, the update value of the weight matrix of the last layer can be calculated, and at the same time, the error value of the penultimate layer can be calculated according to the backpropagation algorithm, so as to calculate the update value of the weight matrix of the penultimate layer, and so on, until all layers of the neural network algorithm are updated in reverse.

[0033] However, accurately calculating the weight update amount using the BP algorithm is relatively complex, with high system and circuit implementation complexity, and high energy consumption required during system operation. On the one hand, relying on verify write to accurately program the memristors incurs a large cost. Verify write requires the use of analog-to-digital conversion circuits, significantly increasing the area and energy consumption cost of the system. On the other hand, during the verify write process, multiple operations need to be performed on the memristors, which not only increases the system energy consumption cost but also raises the requirements for the erasable and writable characteristics of the memristors.

[0034] At least one embodiment of the present disclosure provides a processing unit based on an in-memory computing symbol update algorithm. The processing unit includes: a memristor array, an input module, an output module, an error solving module, a symbol logic module, and an update logic module. Among them, the memristor array is configured to be mapped to a weight matrix for a network layer of a neural network; the input module is configured to receive input data and convert the input data into an input signal to be input into the memristor array; the output module is configured to receive the output signal obtained after the memristor array performs computational processing on the input signal, and convert the output signal into output data; the error solving module is configured to obtain a first error vector of the network layer according to the output data; the symbol logic module is configured to respectively obtain the sign values of each element in the first input vector, the first output vector, and the first error vector based on the first input vector and the first output vector of the memristor array corresponding to the network layer obtained from the forward calculation process of the neural network, and the first error vector of the subsequent network layer adjacent to the network layer obtained from the error solving module, so as to determine the update direction of each weight parameter in the weight matrix according to the sign values of each element in the first input vector, the first output vector, and the first error vector; the update logic module is configured to update the conductance values of the respective memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix. This processing unit can greatly simplify the circuit design of a chip supporting online training, and effectively reduce the area of the analog-to-digital conversion circuit and the energy consumption overhead of the system.

[0035] At least one embodiment of the present disclosure further provides a computing chip including the above-mentioned processing unit.

[0036] At least one embodiment of the present disclosure further provides an operation method for the above-mentioned processing unit.

[0037] The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1A A neural network with three neuron layers (network layers) is shown. The neural network has an input layer L1, a hidden layer L2, and an output layer L3. The adjacent two neuron layers of the neural network are connected by a synaptic weight network W.

[0039] For example, the input layer L1 transmits the received input data to the hidden layer L2, the hidden layer L2 performs layer-by-layer computational conversion on the input data and sends it to the output layer L3, and the output layer L3 outputs the output result of the neural network. For example, as Figure 1A shown, the structure between the layers of the neural network is fully connected.

[0040] For example, as Figure 1AAs shown, the input layer L1, the hidden layer L2, and the output layer L3 each include multiple neurons, and the number of neurons in each layer can be set according to different application scenarios. For example, when there are M (M is an integer greater than 1) input data, the input layer L1 has M neurons. For example, Figure 1A The input layer L1 shown has 3 neurons corresponding to 3 input data X1, X2, and X3 respectively.

[0041] Such as Figure 1A As shown, z (l) represents the input vector of the L-th layer of neurons, and z j (l) represents the input value of the j-th neuron in the L-th layer. For example, the input vector of the L2 layer is z (2) , and the input value of the first neuron in the L2 layer is z1 (2) . a (l) represents the activation output vector of the L-th layer of neurons, and a (l) represents the activation value of the L-th layer of neurons. For example, the activation output vector of the L2 layer is a (2) , and the activation value of the first neuron in the L2 layer is a1 (2) . w (l) represents the weight matrix between the L-th layer of neurons and the (L + 1)-th layer of neurons, and w jk (l) represents the weight from the k-th neuron in the L-th layer to the j-th neuron in the (L + 1)-th layer. For example, w 21 (1) represents the weight from the first neuron in the L1 layer to the second neuron in the L2 layer, and w 12 (2) represents the weight from the second neuron in the L2 layer to the first neuron in the L3 layer.

[0042] In the backpropagation algorithm, the updated value of the weight matrix can be obtained according to the following formula:

[0043] Δw (l) = αa (l) ×δ (l)

[0044] where α is the learning rate.

[0045] In the above formula, Δw (l) represents the exact updated value of the weight in the weight matrix, a (l) represents the activation output vector of the L-th layer of neurons, and δ (l) represents the error vector of the L-th layer of neurons. Among them, δ (l) can be obtained according to the following formula:

[0046] δ (l)= ((w (l+1) ) T δ (l+1) )·σ'(z (l+1) )

[0047] In the above formula, w (l+1) represents the weight matrix between the (L + 1)-th neuron layer and the (L + 2)-th neuron layer, δ (l+1) represents the error vector of the (L + 1)-th neuron layer. z (l+1) represents the input vector of the (L + 1)-th neuron layer, and σ represents the activation function.

[0048] The above two formulas represent the calculation process of backpropagation. The error value of each layer is obtained by multiplying the transpose of the weight matrix of the subsequent layer adjacent to each layer of the network layer (neuron layer) by the error value of the subsequent layer, and then taking the inner product with the derivative of the activation function of the input vector of each layer in the forward calculation process. After obtaining the error value of each layer, the updated value of the weight matrix is obtained by taking the outer product of the error value of each layer and the activation output vector of each layer in the forward calculation process.

[0049] Since the memristor array is mapped to the weight matrix of the network layer for the neural network, in the forward calculation process, for the memristor array, the activation output vector of each layer of the neural network is the "input" of the memristor array, and the input vector of the subsequent layer adjacent to each layer of the network layer is the "output" of the memristor array.

[0050] Therefore, in the embodiments of the present disclosure, the "first input vector" represents the "input" of the memristor array corresponding to a certain network layer obtained from the forward calculation process of the neural network, that is, the activation output vector of a certain network layer obtained from the forward calculation process of the neural network. For example, the "first input vector" of the memristor array corresponding to the L2 layer is Figure 1A the a of the activation output vector of the L2 layer network layer in (2) . The "first output vector" represents the "output" of the memristor array corresponding to a certain network layer obtained from the forward calculation process of the neural network, that is, the input vector of the subsequent layer adjacent to the certain network layer obtained from the forward calculation process of the neural network. For example, the "first output vector" of the memristor array corresponding to the L2 layer is Figure 1A the input vector z of the L3 layer network layer in (3) . The "first error vector" represents the error value corresponding to the subsequent layer adjacent to the certain network layer.

[0051] The processing unit provided by at least one embodiment of the present disclosure obtains a first input vector and a first output vector respectively from the forward calculation process of the neural network by the symbolic logic module, obtains a first error vector in the reverse calculation process, and obtains the symbolic values of the elements in the first input vector, the first output vector, and the first error vector according to the exact numerical values of the obtained first input vector, first output vector, and first error vector and the corresponding first threshold parameter, second threshold parameter, and third threshold parameter, so as to determine the update direction of each weight parameter in the weight matrix.

[0052] It should be noted that in at least one embodiment of the present disclosure, the symbolic values of the elements in the first output vector obtained according to the second threshold parameter can replace the activation function σ in the foregoing formula in the BP algorithm. For example, the error vector of each layer in the neural network can be obtained by multiplying the transpose of the weight matrix of the subsequent layer adjacent to each layer by the symbolic value of the first error vector of the subsequent layer, and then taking the inner product with the symbolic value of the first output vector that has been binarized or ternarized for each layer (that is, multiplying one by one with the symbolic values of the elements in the first output vector).

[0053] If A represents the symbolic value of the first input vector, B represents the symbolic value of the first output vector, and C represents the symbolic value of the first error vector, then the update direction of each weight in the weight matrix can be obtained according to the following formula:

[0054] W = αA (l) ×[((w (l+1) ) T C (l+1) )·B (l+1)

[0055] Where W is the symbolic value of the update direction of each weight in the weight matrix, and the values of the elements in W are -1, 0, or 1.

[0056] In the above formula, the values of the elements in A (l) , B (l+1) , C (l+1) are -1, 0, or 1.

[0057] Therefore, at least one embodiment of the present disclosure simplifies the calculation process and improves the calculation speed by binarizing or ternarizing the elements in the first input vector, the first output vector, and the first error vector. Further, the processing unit and its operation method provided by at least one embodiment of the present disclosure only consider the symbolic value when calculating the update direction of the weight parameter, can avoid precise programming of the memristor conductance value, have low circuit implementation complexity, and small energy consumption overhead during system operation. For example, only a single operation on the memristor is required during update without verification, alleviating the requirement for the erasable and writable characteristics of the memristor.

[0058] Figure 1B ​FIG. 0 is a schematic diagram of a processing unit according to at least one embodiment of the present disclosure. As shown in FIG. 1, the processing unit includes a memristor array, a forward input module, a forward output module, a reverse input module, a reverse output module, two array driving modules, an error solving module, a sign logic module, an update logic module, and a processing unit control module.

[0059] For example, the memristor array is configured to be mapped as a weight matrix for a network layer of a neural network. The embodiments of the present disclosure do not limit the type of neural network. For example, it can be a recurrent neural network (RNN), a convolutional neural network (CNN), a long / short-term memory (LSTM), and so on.

[0060] The memristor array may include a plurality of memristor units arranged in an array. For example, the memristor units constituting the memristor array may include a switching element and a memristor (i.e., 1T1R) or two switching elements and two memristors (i.e., 2T2R). For example, the conductance value of a single memristor in each memristor unit in the memristor array can be used to represent a weight parameter of the weight matrix, or the difference between the conductance values of two memristors in each memristor unit in the memristor array can be used to represent a weight parameter of the weight matrix, that is, the output of a column of output current is realized through two columns of memristors in the memristor array.

[0061] In the memristor unit, the switching element includes a transistor. For example, the transistor can be a thin-film transistor or a field-effect transistor (such as a MOS field-effect transistor) or other switching devices with the same characteristics. For example, the transistor can be an N-type transistor or a P-type transistor. It should be noted that the present disclosure also does not limit the type, structure, etc. of the memristor device.

[0062] For example, the input module is configured to receive input data and convert the input data into an input signal for input into the memristor array.

[0063] As Figure 1BAs shown, the input module includes a forward input module and a reverse input module. For example, the forward input module is used to process the input data of the forward inference calculation task of the neural network algorithm and convert the input data into a forward input signal for the inference calculation task. The forward input signal can be an analog signal, such as a voltage signal. For example, the reverse input module is used to process the input data of the reverse training calculation task of the neural network algorithm and convert the input data into a reverse input signal for the training calculation task. The reverse input signal can be an analog signal, such as a voltage signal. For example, the forward input module corresponds to the first input module of the embodiment of the present disclosure, the reverse input module corresponds to the second input module of the embodiment of the present disclosure, the forward input data corresponds to the first input data of the embodiment of the present disclosure, the reverse input data corresponds to the second input data of the embodiment of the present disclosure, the forward input signal corresponds to the first input signal of the embodiment of the present disclosure, and the reverse input signal corresponds to the second input signal of the embodiment of the present disclosure.

[0064] For example, the output module is configured to receive the output signal obtained after the memristor array processes the input signal and convert the output signal into output data.

[0065] For example, as Figure 1B shown, the output module includes a forward output module and a reverse output module. For example, the forward output module receives the forward output signal obtained after the memristor array performs forward inference calculation processing on the forward input signal and generates forward output data according to the forward output signal. The forward output signal can be an analog signal, such as a current signal. For example, the reverse output module receives the reverse output signal obtained after the memristor array performs reverse training calculation processing on the reverse input signal and generates reverse output data according to the reverse output signal. The reverse output signal can be an analog signal, such as a current signal. For example, the forward output module corresponds to the first output module of the embodiment of the present disclosure, the reverse output module corresponds to the second output module of the embodiment of the present disclosure, the forward output data corresponds to the first output data of the embodiment of the present disclosure, the reverse output data corresponds to the second output data of the embodiment of the present disclosure, the forward output signal corresponds to the first output signal of the embodiment of the present disclosure, and the reverse output signal corresponds to the second output signal of the embodiment of the present disclosure.

[0066] For example, the array driving module is configured to respond to a control signal, apply a voltage signal as an input signal to the memristor array, or receive a current signal as an output signal from the memristor array.

[0067] For example, as Figure 1BAs shown, one array driving module is configured to receive a forward input voltage signal corresponding to a forward input signal and apply the forward input voltage signal to the memristor array in the forward calculation state, and the other array driving module is configured to receive a current signal corresponding to a forward output signal from the memristor array. In the reverse calculation state, the configurations and execution directions of the two array driving modules are opposite to those in the forward calculation state.

[0068] For example, the error solving module is configured to obtain a first error vector of the network layer according to the output data, where the "first error vector" represents the exact error value of a certain network layer in the embodiments of the present disclosure. For example, the error solving module receives the forward output data of the memristor array corresponding to the last network layer from the forward output module of the last layer, and compares the output values of each forward output data with the preset target values to obtain the differences between the output values of each forward output data and each target value, so as to obtain the first error vector of the last network layer and perform backpropagation of the first error vector. For example, the error solving module calculates the respective first error vectors of each network layer according to the weight matrix of the subsequent layer adjacent to each network layer and the first error vector of the subsequent layer.

[0069] For example, the symbolic logic module is configured to obtain the respective sign values of each element in the first input vector, the first output vector, and the first error vector, and determine the update direction of each weight parameter in the weight matrix according to the respective sign values of each element in the first input vector, the first output vector, and the first error vector. For example, the symbolic logic module obtains the respective sign values of each element in the first input vector of the memristor array corresponding to a certain network layer according to the first threshold parameter, obtains the respective sign values of each element in the first output vector of the memristor array corresponding to the subsequent network layer according to the second threshold parameter, obtains the first error vector of the subsequent network layer according to the third threshold parameter, and calculates the update direction of the weight parameter of a certain network layer according to the sign values of each element of the three, rather than the exact values of each element.

[0070] For example, the symbolic logic module is configured to obtain the respective binarized sign values of each element in the first input vector according to a first threshold parameter. For example, the first threshold parameter is S11. When the first input element in the first input vector is greater than or equal to the first threshold parameter S11, the sign value of the first input element is +1; when the first input element in the first input vector is less than the first threshold parameter S11, the sign value of the first input element is 0.

[0071] For example, the symbolic logic module is configured to obtain the respective ternary symbolic values of each element in the first input vector according to two first threshold parameters. For example, the two first threshold parameters are S11 and S12 respectively, where S11 is greater than S12. When the first input element in the first input vector is greater than or equal to the first threshold parameter S11, the symbolic value of the first input element is +1; when the first input element in the first input vector is less than or equal to the first threshold parameter S12, the symbolic value of the first input element is -1; when the first input element in the first input vector is less than the first threshold parameter S11 and greater than the first threshold parameter S12, the symbolic value of the first input element is 0.

[0072] For example, the symbolic logic module is configured to obtain the respective binary symbolic values of each element in the first output vector according to a second threshold parameter. For example, the second threshold parameter is S21. When the first output element in the first output vector is greater than the second threshold parameter S21, the symbolic value of the first output element is +1; when the first output element in the first output vector is less than or equal to the second threshold parameter S21, the symbolic value of the first output element is 0.

[0073] For example, the symbolic logic module is configured to obtain the respective ternary symbolic values of each element in the first output vector according to two second threshold parameters. For example, the two second threshold parameters are S21 and S22 respectively, where S21 is greater than S22. When the first output element in the first output vector is greater than the second threshold parameter S21, the symbolic value of the first output element is +1; when the first output element in the first output vector is less than the second threshold parameter S22, the symbolic value of the first output element is -1; when the first output element in the first output vector is less than or equal to the second threshold parameter S21 and greater than or equal to the second threshold parameter S22, the symbolic value of the first output element is 0.

[0074] For example, the symbolic logic module is configured to obtain the respective binary symbolic values of each element in the first error vector according to a third threshold parameter. For example, the third threshold parameter is S31. When the first error element in the first error vector is greater than the third threshold parameter S31, the symbolic value of the first error element is +1; when the first error element in the first error vector is less than or equal to the third threshold parameter S31, the symbolic value of the first error element is 0.

[0075] For example, the symbolic logic module is configured to obtain the ternary symbolic value of each element in the first error vector according to two third threshold parameters. For example, the two third threshold parameters are S31 and S32 respectively, where S31 is greater than S32. When the first error element in the first error vector is greater than the third threshold parameter S31, the symbolic value of the first error element is +1; when the first error element in the first error vector is less than the third threshold parameter S32, the symbolic value of the first error element is -1; when the first error element in the first error vector is less than or equal to the third threshold parameter S31 and greater than or equal to the third threshold parameter S32, the symbolic value of the first error element is 0.

[0076] It should be noted that the method in which the above-mentioned symbolic logic module obtains the binary or ternary symbolic value of each element in the first input vector of a certain network layer according to the first threshold parameter, obtains the binary or ternary symbol of each element in the first output vector according to the second threshold parameter, and obtains the binary or ternary symbol of each element in the first error vector according to the third threshold parameter are only some examples listed in the embodiments of the present disclosure, but are not limited thereto. The selection of the threshold parameter and the comparison relationship between the element and the threshold parameter can be set according to the actual situation.

[0077] For example, the update logic module is configured to update the conductance values of the memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix. For example, when the symbol of the weight parameter is positive (+1), increase the conductance value of the memristor in the memristor unit; when the symbol of the weight parameter is negative (-1), decrease the conductance value of the memristor in the memristor unit; when the symbol of the weight parameter is 0, keep the conductance value of the memristor in the memristor unit unchanged.

[0078] For example, when the symbolic logic module calculates that the weight update direction in the weight matrix of the network layer is positive, the update logic module increases the conductance values of the memristors corresponding to the respective weight parameters in the memristor array; when the symbolic logic module calculates that the weight update direction in the weight matrix of the network layer is negative, the update logic module decreases the conductance values of the memristors corresponding to the respective weight parameters in the memristor array; when the symbolic logic module calculates that the weight update direction in the weight matrix of the network layer remains unchanged, the update logic module keeps the conductance values of the memristors corresponding to the respective weight parameters in the memristor array.

[0079] For example, the processing unit control module is configured to be able to switch and schedule the working mode of the processing unit. For example, the processing unit control module can switch the working mode of the processing unit to the forward calculation mode to execute the inference calculation task. For example, the processing unit control module can switch the working mode of the processing unit to the backward calculation mode to execute the training calculation task. For example, the processing unit control module can switch the working mode of the processing unit to the mapping mode to perform a setting operation or a reset operation on the corresponding memristors in the memristor array according to the calculated weight update direction, so as to increase or decrease the conductance value of the memristors. For example, the processing unit control module can switch the working mode of the processing unit to the reading mode to read the current conductance value of each memristor from the memristor array, and the read conductance value can be used to verify whether the foregoing setting operation or reset operation meets the requirements. If not, the setting operation or reset operation needs to be performed again.

[0080] Figure 2A Schematic diagram of a memristor device provided by at least one embodiment of the present disclosure. The memristor device includes a memristor (sub) array and its peripheral driving circuit, and the peripheral driving circuit is used to implement the input / output module and the array driving module of the present disclosure. For example, as Figure 2A shown, the memristor device includes a signal acquisition device, a word line driving circuit, a bit line driving circuit, a source line driving circuit, a memristor array, and a data output circuit.

[0081] For example, the signal acquisition device is configured to convert a digital signal into a plurality of first analog signals through a digital-to-analog converter (Digital to Analog Converter, abbreviated as DAC) and input them to the plurality of column signal input ends of the memristor array during convolution processing.

[0082] For example, the memristor array includes M source lines, M word lines, and N bit lines, and a plurality of memristor units arranged in an array of M rows and N columns. For example, each memristor unit has a 1T1R structure, and the parameter matrix for Fourier transform can be mapped to a plurality of memristor units in the memristor array.

[0083] For example, the operations on the memristor array are realized through the word line driving circuit, the bit line driving circuit, and the source line driving circuit.

[0084] For example, the word line driving circuit includes multiple multiplexers (Mux) for switching the word line input voltage; the bit line driving circuit includes multiple multiplexers for switching the bit line input voltage; and the source line driving circuit also includes multiple multiplexers (Mux) for switching the source line input voltage. For example, the source line driving circuit further includes multiple analog-to-digital converters (ADC) for converting analog signals into digital signals. In addition, a trans-impedance amplifier (TIA) (not shown in the figure) can be further provided between the Mux and the ADC in the source line driving circuit to complete the current-to-voltage conversion for facilitating the processing by the ADC.

[0085] For example, the memristor array includes an operation mode and a computing mode. When the memristor array is in the operation mode, the memristor cells are in the initialization state, and the numerical values of the weight parameters in the weight matrix can be written into the memristor array. For example, the source line input voltage, the bit line input voltage, and the word line input voltage of the memristor are switched to corresponding preset voltage ranges through multiplexers.

[0086] For example, through Figure 2A the control signal WL_sw[1:M] of the multiplexer in the word line driving circuit in Figure 2A the word line input voltage is switched to the corresponding voltage range. For example, when performing a set operation on the memristor, the word line input voltage is set to 2V (volts). For example, when performing a reset operation on the memristor, the word line input voltage is set to 5V. For example, the word line input voltage can be obtained through

[0087] For example, through Figure 2A the control signal SL_sw[1:M] of the multiplexer in the source line driving circuit in Figure 2A the source line input voltage is switched to the corresponding voltage range. For example, when performing a set operation on the memristor, the source line input voltage is set to 0V. For example, when performing a reset operation on the memristor, the source line input voltage is set to 2V. For example, the source line input voltage can be obtained through

[0088] For example, through Figure 2A the control signal BL_sw[1:N] of the multiplexer in the bit line driving circuit in Figure 2A the bit line input voltage is switched to the corresponding voltage range. For example, when performing a set operation on the memristor, the bit line input voltage is set to 2V. For example, when performing a reset operation on the memristor, the bit line input voltage is set to 0V. For example, the bit line input voltage can be obtained through

[0089] For example, when the memristor array is in the computing mode (forward computing or backward computing), the memristors in the memristor array are in a conductive state available for computing, and the bitline input voltage input at the column signal input terminal does not change the conductance value of the memristors. For example, multiplication and addition operations can be performed through the memristor array to complete the computing. For example, through Figure 2A the control signal WL_sw[1:M] of the multiplexer in the wordline driving circuit in Figure 2A switches the wordline input voltage to the corresponding voltage range. For example, when an enabling signal is applied, the wordline input voltage of the corresponding row is set to 5V. For example, when the enabling signal is not applied, the wordline input voltage of the corresponding row is set to 0V, such as connecting to the GND signal; through Figure 2A the control signal SL_sw[1:M] of the multiplexer in the source line driving circuit in

[0090] switches the source line input voltage to the corresponding voltage range. For example, the source line input voltage is set to 0V, so that the current signals at multiple row signal output terminals can flow into the data output circuit. Through

[0091] Figure 2B Schematic diagram of another memristor device provided by at least one embodiment of the present disclosure. Figure 2B The shown memristor device and Figure 2A the structure of the shown memristor device are basically the same, and also include a memristor (sub)array and its peripheral driving circuit, and this peripheral driving circuit is used to implement the input / output module of the present disclosure. For example, as Figure 2B shown, this memristor device includes a signal acquisition device, a wordline driving circuit, a bitline driving circuit, a source line driving circuit, a memristor array, and a data output circuit.

[0092] For example, the memristor array includes M source lines, 2M word lines, and 2N bit lines, as well as a plurality of memristor cells arranged in an array of M rows and N columns. For example, each memristor cell has a 2T2R structure. The operation of mapping the parameter matrix for transformation processing to different memristor cells in the memristor array will not be elaborated here. It should be noted that the memristor array may also include M source lines, M word lines, and 2N bit lines, as well as a plurality of memristor cells arranged in an array of M rows and N columns. Since - in order to simultaneously apply the enable signal to multiple signal control terminals of the memristor array, two memristors in each row of memristor cells can be controlled simultaneously by each word line.

[0093] The descriptions of the signal acquisition device, the control driving circuit, and the data output circuit can be referred to the previous descriptions and will not be elaborated here.

[0094] Figure 3 It is a schematic diagram of the calculation process of a processing unit proposed in at least one embodiment of the present disclosure. The calculation data path of the processing unit may include (a) a forward data path and (b) a backward data path according to the calculation mode. The forward data path may be a path for performing the inference calculation task of the neural network algorithm, and the backward data path may be a path for performing the training calculation task of the neural network algorithm.

[0095] For example, as Figure 3 shown, (a) the forward data path includes a forward input module, a first array driving module, a memristor array, a second array driving module, a forward output module, and an error solving module. When the processing unit is controlled to be in the forward calculation state, the input data of the forward inference calculation task enters the forward input module from the input end of the forward input module and is converted into a forward input signal. For example, it is output from the output end of the forward input module in the form of a voltage signal. The first array driving module responds to the control signal, such as the control signal of the Mux, etc., and applies the forward input voltage signal to the corresponding bit lines of the memristor array. The memristor array completes the matrix multiplication operation of the input data and outputs a current signal through the corresponding source lines. The second array driving module receives the current signal as the output signal and transmits the forward output current signal to the forward output module. The forward output module converts the output signal into output data and transmits it to the error solving module.

[0096] For example, as Figure 3As shown, (b) the reverse data path includes a reverse input module, a second array driving module, a memristor array, a first array driving module, and a reverse output module. When the processing unit is controlled to be in the reverse calculation state, the input data of the reverse training calculation task enters the reverse input module from the input end of the reverse input module and is converted into a reverse input signal. For example, it is output from the output end of the reverse input module in the form of a voltage signal. The second array driving module applies a reverse input voltage signal to the source lines corresponding to the memristor array. The memristor array completes the matrix multiplication operation on the input data and outputs a current signal through the corresponding bit lines. The first array driving module receives the current signal as the output signal and transmits it to the reverse output module.

[0097] During the training calculation process of the neural network, only considering the update direction of the weight parameters can effectively reduce the operating energy consumption and verification write times of the system. And the calculation result of the update direction of the weight parameters depends to a large extent on the selection of the threshold parameter. Therefore, the selection of the threshold parameter has a direct impact on the training effect. Figure 4 A method for selecting a threshold parameter is shown, that is, the first n bits are taken from the digital-form signal obtained after analog-to-digital conversion, which is used to set the threshold parameter and compare it with the threshold parameter to obtain the sign value of the signal. For example, for an 8-bit unsigned binary number, if n = 3, the threshold parameter is actually set to 2 5 = 32, then the first n bits of the first element of the signal are taken and compared with 1...1 (n bits), that is, the first element is actually compared with the threshold parameter. The first element can be, for example, the first input element, the first output element, or the first error element.

[0098] For example, for the selection rule of the binarized sign value in an embodiment of the present disclosure, if the first 3 bits of the first element are 111, the first element is greater than or equal to the threshold parameter, and the sign value corresponding to the first element is +1. If the first 3 bits of the first element are less than 111, the first element is less than the threshold parameter, and the sign value corresponding to the first element is 0.

[0099] For example, for an 8-bit signed binary number where the highest bit is 1 indicating a negative number, if n = 4, the first threshold parameter is set to 2 4 = 16, and the second threshold parameter is set to -2 4 = -16, then the first 4 bits of the first element of the signal are taken to be used for comparison with the first threshold parameter and the second threshold parameter.

[0100] For example, for the selection rule of the ternary symbol value in an embodiment of the present disclosure, if the first 4 digits of the first element are 0111, the first element is greater than or equal to the first threshold parameter 16, then the symbol value of the first element is +1; if the first 4 digits of the first element are 1111, the first element is less than or equal to the second threshold parameter -16, then the symbol value of the first element is -1; if the first 4 digits of the first element are other values except 0111 and 1111, the first element is between the first threshold parameter 16 and the second threshold parameter -16, then the symbol value of the first element is 0.

[0101] In at least one embodiment provided by the present disclosure, the symbol logic module may set the threshold parameter by using the threshold parameter selection method as Figure 4 shown. For example, the symbol logic module may select different n values to adjust the size of the threshold parameter according to actual needs. For example, the symbol logic module may change the calculation result of the symbol value by reducing the set value of the threshold parameter, so as to improve the calculation accuracy of the update direction of the weight matrix in the process of layer-by-layer training of the neural network.

[0102] In another embodiment provided by the present disclosure, the symbol logic module may also change the symbol value of each calculated element by changing the element values in the first input vector, the first output vector, and the first error vector without changing the set value of the threshold parameter. For example, when the first threshold parameter, the second threshold parameter, or the third threshold parameter is of a specific bit width, the symbol logic module may proportionally amplify the value of each element in the first input vector, the first output vector, and the first error vector, and compare each element in the amplified first input vector, first output vector, and first error vector with the first threshold parameter and the second threshold parameter respectively, so as to obtain the symbol value of each element in the first input vector, first output vector, and first error vector respectively. In the case where the threshold parameter cannot be changed, proportionally amplifying the exact value of each element in the first input vector, the first output vector, and the first error vector is equivalent to reducing the set value of the threshold parameter, so that the calculation accuracy of the update direction of the weight matrix can be continuously improved as the training progresses in the process of layer-by-layer training of the neural network.

[0103] For example, amplifying the value of each element in the first error vector can also be achieved by proportionally amplifying the output value and the target value of the output data.

[0104] For example, Figure 5Shows a specific implementation solution of an error solving module based on pulse number encoding. For example, the error solving module includes at least one counting unit, and each counting unit includes at least one counter. For example, a preset target value is loaded into the counter, and this target value is used to calculate the error value of the last network layer. For example, the error solving module receives output data in the form of pulse number encoding from the forward output module, that is, the output value size of the output data is represented by the number of pulses. Multiple counters in the error solving module count the number of pulses of each column of output data to obtain the output value, and subtract this output value based on the preset target value of each column, so as to obtain multiple error values of the last network layer, that is, the values of each element in the first error vector in the embodiments of the present disclosure.

[0105] Figure 6 Schematic diagram of a symbol logic module proposed in at least one embodiment of the present disclosure. The symbol logic module is configured to take the nth cycle of the signal in pulse form obtained after analog-to-digital conversion for setting the first threshold parameter, the second threshold parameter, or the third threshold parameter. For example, as Figure 6 shown, the symbol logic module includes at least one flip-flop. For example, the input signal is input into the symbol logic module in the form of pulse number encoding, and the number of input pulses represents the input value size of the input signal. The threshold parameter is set as the trigger signal to calculate the symbol value of the input signal. For example, at the nth cycle, the threshold signal is ANDed with the input pulse signal in high level form to obtain the symbol value of each input pulse signal.

[0106] Figure 7 Schematic diagram of another symbol logic module proposed in at least one embodiment of the present disclosure. The symbol logic module is configured to use the reference voltage as the third threshold parameter. For example, as Figure 7 shown, the symbol logic module includes an integration circuit and a comparison circuit. For example, the integration circuit includes at least one integrator configured to integrate the current signal corresponding to the value of each element in the first error vector. For example, the comparison circuit includes at least one comparator configured to compare the output voltage of the integration circuit with the third threshold parameter to obtain the symbol value of each element in the first error vector. For example, as Figure 7 shown, the symbol logic circuit has two comparators, and the number of third threshold parameters is two, which are respectively compared with the output voltage of the integration circuit in the form of a positive reference voltage and a negative reference voltage to obtain the ternary symbol value of the output signal. For example, the symbol logic circuit has one comparator, and the number of third threshold parameters is one, which is compared with the output voltage of the integration circuit in the form of a reference voltage to obtain the binary symbol value of the output signal.

[0107] For example, the symbolic logic module can be used for the network layer of the last layer in the reverse training calculation task, that is, without calculating the exact value of the first error vector of the last layer network layer, directly obtaining the symbolic values of the elements in the first error vector, so as to effectively simplify the circuit and save system power consumption.

[0108] It is worth mentioning that Figure 7 The magnitude of the threshold parameter in the shown symbolic logic module can also be adjusted. For example, the first threshold parameter or the second threshold parameter can be changed by adjusting the magnitude of the reference voltage.

[0109] In at least one embodiment of the present disclosure, the symbolic values of the first input vector, the first output vector, and the first error vector calculated by the symbolic logic module, one of the element symbolic values of the three must be a ternary symbolic value, so as to ensure that the update direction of each weight parameter in the weight matrix calculated according to the element symbolic values of the three has positive and negative distinctions.

[0110] For example, the number of one of the first threshold parameter, the second threshold parameter, and the third threshold parameter set in the symbolic logic module is two, so that the element value of one of the obtained first input vector, first output vector, or first error vector is a ternary symbolic value. For example, in Figure 7 In the shown circuit, when calculating the symbolic values of the elements in the first error vector, only one comparator is selected, and a reference voltage is set as the first threshold parameter, so that the symbolic value of the obtained first error vector is a binary symbol. When calculating the symbolic values of the elements in the first input vector and the first output vector, two comparators are selected, and two reference voltages are set as the second threshold parameter and the third threshold parameter, so that the symbolic values of the elements of the obtained first input vector and first output vector are ternary symbols. The symbolic logic module calculates the symbolic values of each weight parameter in the weight matrix according to the binary symbolic values of the elements in the first error vector and the ternary symbolic values of the elements in the first input vector and the first output vector, and the conductance value of the memristor is updated accordingly by the symbol update logic module.

[0111] At least one embodiment of the present disclosure provides a computing chip, including the processing unit in any of the above embodiments. As Figure 8As shown, in at least one embodiment of the present disclosure, a computing chip includes one or more processing unit modules (abbreviated as PE modules), each PE module includes one or more memristor processing units, and each processing unit can interact and cooperate with each other under the control of the processing unit control unit. There are various ways to implement communication between different PE modules; one is based on an on-chip routing (including several routing nodes) mechanism, such as a switch array method or an on-chip network method, etc.; the other is to implement point-to-point communication between PE modules based on a bus (such as the AXI bus, etc.). Each PE module can be both a master unit and a slave unit, and different PE modules have different interface addresses.

[0112] In practice, one or more network layers of an artificial neural network can be deployed on one or more PE modules. For example, Figure 9 is a schematic diagram of the computing process of a computing chip proposed in at least one embodiment of the present disclosure.

[0113] As Figure 9 shown, in the forward process, the forward inference calculation process of each PE module is completed in sequence. In the reverse process, the reverse training calculation process of each PE module is completed in the reverse order of the forward process, and the weight update of the weight matrix is completed within each PE module.

[0114] For each processing unit among them, the operation method of at least one embodiment of the present disclosure includes: mapping the weight matrix of the network layer for the neural network into the memristor array; receiving input data through the input module and converting the input data into an input signal to input into the memristor array; receiving the output signal obtained after the memristor array calculates and processes the input signal through the output module, and converting the output signal into output data; obtaining the first error vector of the network layer according to the output data through the error solving module; obtaining the sign value of each element in the first input vector, the first output vector, and the first error vector through the symbolic logic module, and determining the update direction of each weight parameter in the weight matrix according to the sign value of each element in the first input vector, the first output vector, and the first error vector; updating the conductance value of each memristor corresponding to each weight parameter in the memristor array according to the update direction of each weight parameter in the weight matrix. For details, reference can be made to the above description, and it will not be elaborated here.

[0115] For the present disclosure, the following points need to be noted:

[0116] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0117] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0118] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A processing unit, comprising: A memristor array configured to be mapped as a weight matrix for a network layer of a neural network; An input module configured to receive input data and convert the input data into an input signal for input into the memristor array; An output module configured to receive an output signal obtained after the memristor array performs computational processing on the input signal, and convert the output signal into output data; An error solving module configured to obtain a first error vector of the network layer based on the output data; A symbolic logic module configured to, based on a first input vector and a first output vector of the memristor array corresponding to the network layer obtained from the forward calculation process of the neural network, and the first error vector of the subsequent network layer adjacent to the network layer obtained from the error solving module, respectively obtain the symbolic values of each element in the first input vector, the first output vector, and the first error vector, so as to determine the update direction of each weight parameter in the weight matrix according to the symbolic values of each element in the first input vector, the first output vector, and the first error vector; And An update logic module configured to update the conductance values of the respective memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix.

2. The processing unit according to claim 1, further comprising: An array driving module configured to, in response to a control signal, apply a voltage signal as the input signal to the memristor array, or receive a current signal as the output signal from the memristor array; And A processing unit module configured to switch and schedule the working mode of the processing unit.

3. The processing unit according to claim 2, wherein The input module comprises: A first input module configured to generate A first input signal according to first input data of a forward calculation task, and input the first input signal into the memristor array, and A second input module configured to generate a second input signal according to second input data of a backward calculation task, and input the second input signal into the memristor array, wherein the input data comprises the first input data and the second input data, The input signal comprises the first input signal and the second input signal; The output module comprises: A first output module configured to receive a first output signal obtained after the memristor array performs forward calculation processing on the first input signal, and generate first output data according to the first output signal, and A second output module configured to receive a second output signal obtained after the memristor array performs backward calculation processing on the second input signal, and generate second output data according to the second output signal, wherein the output data comprises the first output data and the second output data, and the output signal comprises the first output signal and the second output signal.

4. The processing unit according to claim 3, wherein The array driving module comprises: The first array driving module is configured to receive a first input voltage signal corresponding to the first input signal and apply the first input voltage signal to the memristor array in the forward calculation state, and the second array driving module is configured to receive a second input voltage signal corresponding to the second input signal and apply the second input voltage signal to the memristor array in the reverse calculation state.

5. The processing unit according to claim 1, wherein, The symbolic logic module is further configured to obtain the binary symbolic value of each element in the first input vector according to a first threshold parameter; or obtain the ternary symbolic value of each element in the first input vector according to two first threshold parameters; The symbolic logic module is further configured to obtain the binary symbolic value of each element in the first output vector according to a second threshold parameter; or obtain the ternary symbolic value of each element in the first output vector according to two second threshold parameters; and The symbolic logic module is further configured to obtain the binary symbolic value of each element in the first error vector according to a third threshold parameter; or obtain the ternary symbolic value of each element in the first error vector according to two third threshold parameters.

6. The processing unit according to claim 5, wherein, The symbolic logic module is further configured to take the first n bits of the signal in digital form obtained after analog-to-digital conversion for setting the first threshold parameter, the second threshold parameter, or the third threshold parameter, where n is a positive integer.

7. The processing unit according to claim 5, wherein, When the first threshold parameter, the second threshold parameter, and the third threshold parameter are fixed values, the symbolic logic module is further configured to amplify the value of each element in the first input vector, the first output vector, and the first error vector, and obtain the symbolic value of each element in the first input vector, the first output vector, and the first error vector respectively according to the first threshold parameter, the second threshold parameter, and the third threshold parameter and the amplified first input vector, first output vector, and first error vector.

8. The processing unit according to claim 5, wherein The symbolic logic module is further configured to take the nth cycle of the signal in pulse form obtained after analog-to-digital conversion for setting the first threshold parameter, the second threshold parameter, or the third threshold parameter, where n is a positive integer.

9. The processing unit according to claim 5, wherein, The symbolic logic module is further configured to use a reference voltage as the third threshold parameter and includes: an integration circuit configured to integrate the current signal corresponding to the value of each element in the first error vector; and a comparison circuit configured to compare the output voltage of the integration circuit with the third threshold parameter to obtain the symbolic value of each element in the first error vector.

10. The processing unit according to claim 5, wherein, The number of at least one of the first threshold parameter, the second threshold parameter, and the third threshold parameter is two, so that at least one of the obtained first input vector, first output vector, and first error vector is a ternary symbolic value.

11. The processing unit according to claim 1, wherein, For the case of updating the conductance values of the memristors corresponding to the respective weight parameters in the memristor array according to the update directions of the respective weight parameters in the weight matrix, the update logic module is configured to: increase the conductance value of the memristor when the sign of the weight parameter is positive, or decrease the conductance value of the memristor when the sign of the weight parameter is negative.

12. A computing chip, comprising at least one processing unit according to any one of claims 1-11.

13. An operation method for a processing unit according to any one of claims 1-11, comprising: mapping a weight matrix for a network layer of the neural network into the memristor array; receiving, through the input module, the input data and converting the input data into an input signal to input into the memristor array; receiving, through the output module, an output signal obtained after the memristor array performs computational processing on the input signal, and converting the output signal into output data; obtaining, through the error solving module, a first error vector of the network layer according to the output data; respectively obtaining the sign values of each element of the first input vector, the first output vector, and the first error vector based on the first input vector and the first output vector of the memristor array corresponding to the network layer obtained from the forward calculation process of the neural network and the first error vector of the subsequent network layer adjacent to the network layer obtained from the error solving module, so as to determine the update directions of the respective weight parameters in the weight matrix according to the sign values of each element of the first input vector, the first output vector, and the first error vector; updating the conductance values of the memristors corresponding to the respective weight parameters in the weight matrix according to the update directions of the respective weight parameters in the weight matrix through the update logic module.

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