Method of forming a semiconductor structure

Abstract

The present application provides a method for forming a semiconductor structure, the method comprising: providing a substrate, on the surface of which a first hard mask layer, a second hard mask layer and a patterned mandrel layer are sequentially formed, the patterned mandrel layer comprising a plurality of first trenches exposing the second hard mask layer; forming a plurality of first partition openings in the patterned mandrel layer exposing the second hard mask layer; forming a plurality of second partition openings in the second hard mask layer exposed by the first trenches exposing the first hard mask layer; forming sidewalls on both sides of the first trenches, the sidewalls not filling the first trenches, and the sidewalls also filling the first partition openings and the second partition openings; removing the patterned mandrel layer; etching the first hard mask layer and the second hard mask layer to form a plurality of second trenches; etching along the second trenches into the substrate; and removing the first hard mask layer and the second hard mask layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Currently, in the semiconductor back end of line (BEOL), the self-aligned double patterning (SADP) method is usually selected to form metal layers.

[0003] In some designs, a discontinuous metal layer needs to be formed, so a partition opening needs to be formed to partition the metal layer. Currently, the main methods for forming partition openings are merge cut and block cut, but in these two methods, an additional mask layer needs to be formed, making the mask stack more complex and requiring more materials, increasing the overall cost.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to simplify the process, save materials, and thus reduce costs. Summary of the Invention

[0005] This application provides a method for forming a semiconductor structure, which can simplify the process, save materials, and thus reduce costs.

[0006] This application provides a method for forming a semiconductor structure, including: providing a substrate, on the surface of which a first hard mask layer, a second hard mask layer, and a patterned mandrel layer are sequentially formed, the patterned mandrel layer including a plurality of first trenches exposing the second hard mask layer; forming a plurality of first partition openings exposing the second hard mask layer in the patterned mandrel layer; forming a plurality of second partition openings exposing the first hard mask layer in the second hard mask layer exposed by the first trenches; forming sidewalls on both sides of the first trenches, the sidewalls not filling the first trenches, and the sidewalls also filling the first partition openings and the second partition openings; removing the patterned mandrel layer; etching the first hard mask layer and the second hard mask layer to form a plurality of second trenches; etching along the second trenches into the substrate; removing the first hard mask layer and the second hard mask layer.

[0007] In some embodiments of this application, the method for forming the patterned mandrel layer includes: forming a mandrel layer on the surface of the second hard mask layer; forming a patterned first photoresist layer on the surface of the mandrel layer, the patterned first photoresist layer including a plurality of first openings; etching the mandrel layer along the plurality of first openings using the patterned first photoresist layer as a mask to form the first trenches; removing the patterned first photoresist layer.

[0008] In some embodiments of the present application, the method for forming sidewalls on both sides of the first trench includes: forming a sidewall material layer on the bottom and both sides of the first trench, in the first partition opening and the second partition opening, and on the surface of the mandrel layer; etching away the sidewall material layer on the surface of the mandrel layer and the bottom of the first trench to form the sidewalls on both sides of the first trench.

[0009] In some embodiments of the present application, the method for etching the first hard mask layer and the second hard mask layer to form a plurality of second trenches includes: etching the second hard mask layer using the sidewall as a mask until the first hard mask layer is exposed; etching away the sidewalls above the top surface of the second hard mask layer; etching the first hard mask layer using the sidewall and the second hard mask layer as a mask until the substrate is exposed.

[0010] In some embodiments of the present application, when etching along the second trench into the substrate, the sidewall, the first hard mask layer, and the second hard mask layer are used as masks, and the sidewall and the second hard mask layer are completely consumed.

[0011] In some embodiments of the present application, the material of the first hard mask layer includes metal nitride, silicon oxide, or silicon nitride, and the thickness of the first hard mask layer is 100 angstroms to 300 angstroms.

[0012] In some embodiments of the present application, the material of the second hard mask layer includes metal nitride, silicon oxide, or silicon nitride, and the thickness of the second hard mask layer is 100 angstroms to 300 angstroms.

[0013] In some embodiments of the present application, the substrate includes a substrate and a dielectric layer on the surface of the substrate.

[0014] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a metal layer in the second trench, wherein a part of the metal layer is blocked by the substrate.

[0015] In some embodiments of the present application, the method for forming the metal layer includes: forming a metal material layer on the substrate to completely cover the substrate and the first hard mask layer; using a chemical mechanical polishing process to polish the first hard mask layer and the metal material layer until the substrate is exposed to form the metal layer.

[0016] In the method for forming the semiconductor structure according to the present application, by utilizing the etching selectivity difference between the first hard mask layer and the second hard mask layer, and using the first hard mask layer and the second hard mask layer as etching stop layers respectively to form the first partition opening and the second partition opening, the process can be simplified, materials can be saved, and thus the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings detail the exemplary embodiments disclosed in the present application. The same reference numerals denote similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0018] Figure 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0019] Figures 2 to 21 are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to an embodiment of the present application. Detailed Description of the Specific Embodiment

[0020] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but to the broadest scope consistent with the claims.

[0021] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0022] Figure 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present application.

[0023] Referring to Figure 1 as shown, the method for forming a semiconductor structure according to the present application includes:

[0024] Step S110: Provide a substrate, on the surface of which a first hard mask layer, a second hard mask layer, and a patterned mandrel layer are sequentially formed. The patterned mandrel layer includes a plurality of first trenches exposing the second hard mask layer;

[0025] Step S120: Form a plurality of first partition openings in the patterned mandrel layer exposing the second hard mask layer;

[0026] Step S130: Form a plurality of second partition openings in the second hard mask layer exposed by the first trenches exposing the first hard mask layer;

[0027] Step S140: Form sidewalls on both sides of the first trenches. The sidewalls do not fill the first trenches, and the sidewalls also fill the first partition openings and the second partition openings;

[0028] Step S150: Remove the patterned mandrel layer;

[0029] Step S160: Etch the first hard mask layer and the second hard mask layer to form a plurality of second trenches;

[0030] Step S170: Etch along the second trenches into the substrate;

[0031] Step S180: Remove the first hard mask layer and the second hard mask layer.

[0032] Figures 2 to 21 are the schematic structural diagrams of the steps in the method for forming the semiconductor structure according to the embodiments of the present application. The following will be combined with Figure 1 and Figures 2 to 21 to describe in detail the method for forming the semiconductor structure according to the present application.

[0033] Refer to Figure 2 and Figure 3 As shown, in step S110, a substrate 100 is provided, and a first hard mask layer 111, a second hard mask layer 112, and a patterned mandrel layer 120 are sequentially formed on the surface of the substrate 100. The patterned mandrel layer 120 includes a plurality of first trenches 121 exposing the second hard mask layer 112. Among them, Figure 3 is a top view, Figure 2 is a cross-sectional view taken along the dashed line in Figure 3 . It should be noted that since each step in the method for forming the semiconductor structure according to the present application involves different positions on the substrate 100, a single cross-sectional view of a single position cannot be used to show all steps. Therefore, a top view is needed to illustrate the position corresponding to the cross-sectional view of each step. For example, Figure 2 is the cross-sectional view at the dashed line position in Figure 3 . It should be noted that the position in the top view corresponding to the cross-sectional view of each step may be different, and it is necessary to refer to the corresponding top view. In addition, it should be understood that since Figure 3 is a top view, the underlying substrate 100 and the first hard mask layer 111 are covered and cannot be observed, and only the topmost patterned mandrel layer 120 and the exposed second hard mask layer 112 can be observed.

[0034] In some embodiments of the present application, the substrate 100 includes a substrate 101 and a dielectric layer 102 on the surface of the substrate 101. In the embodiments of the present application, the backend process of the semiconductor process is used as an example for illustration. The substrate 101 includes, but is not limited to, a semiconductor substrate, a semiconductor substrate formed with active devices, etc. The dielectric layer 102 is located on the surface of the substrate 101 and is used to form a metal layer.

[0035] In some embodiments of the present application, the material of the dielectric layer 102 is a dielectric material such as silicon oxide.

[0036] In some embodiments of the present application, the material of the first hard mask layer 111 includes metal nitride, silicon oxide or silicon nitride, such as silicon nitride or silicon oxide, etc. The thickness of the first hard mask layer 111 is 100 angstroms to 300 angstroms, such as 150 angstroms, 200 angstroms, 250 angstroms, etc. In some embodiments of the present application, the material of the second hard mask layer 112 includes metal nitride, silicon oxide or silicon nitride, such as silicon nitride or silicon oxide, etc. The thickness of the second hard mask layer 112 is 100 angstroms to 300 angstroms, such as 150 angstroms, 200 angstroms, 250 angstroms, etc.

[0037] In the method for forming the semiconductor structure described in the present application, by utilizing the etching selectivity difference between the first hard mask layer 111 and the second hard mask layer 112, the first partition opening and the second partition opening are formed respectively with the first hard mask layer 111 and the second hard mask layer 112 as the etching stop layers. Therefore, the material selection and thickness setting of the first hard mask layer 111 and the second hard mask layer 112 are crucial. First, there should be a certain difference in the etching selectivity between the first hard mask layer 111 and the second hard mask layer 112 to avoid being unable to stop on the first hard mask layer 111 when etching the second hard mask layer; in addition, in the specific selection, the material and thickness can be combined for selection. For example, when the selected material has a faster etching rate, a relatively thick thickness can be set to extend the etching time.

[0038] In some embodiments of the present application, the methods for forming the first hard mask layer 111 and the second hard mask layer 112 include chemical vapor deposition process or physical vapor deposition process, etc.

[0039] In some embodiments of the present application, the method for forming the patterned mandrel layer 120 includes: forming a mandrel layer on the surface of the second hard mask layer 112; forming a patterned first photoresist layer on the surface of the mandrel layer, the patterned first photoresist layer includes a plurality of first openings; etching the mandrel layer along the plurality of first openings with the patterned first photoresist layer as a mask to form the first trench 121; removing the patterned first photoresist layer.

[0040] Reference Figure 4 and Figure 5 As shown, in step S120, a plurality of first partition openings 131 exposing the second hard mask layer 112 are formed in the patterned mandrel layer 120. Among them, Figure 5 is a top view, Figure 4 is a cross-sectional view taken along the Figure 5 dashed line in. It should be noted thatFigure 4 Only the position of the first partition opening 131 is shown by a dashed box, which is not an actual structure.

[0041] The first partition opening 131 cuts off part of the mandrel layer 120, and the position of the first partition opening 131 is also the position where the subsequently formed metal layer is partitioned. The size, position, and number of the first partition openings 131 are set according to the design of the metal layer in the subsequent process. The first partition opening 131 in this application is only an example.

[0042] In some embodiments of this application, the method of forming the first partition opening 131 includes wet etching, dry etching, etc.

[0043] Reference Figure 6 and Figure 7 As shown in Figure 7 which is a top view, Figure 6 and Figure 7 which is a cross-sectional view taken along the dashed line in

[0044] The second partition opening 132 cuts through part of the second hard mask layer. The size, position, and number of the second partition openings 132 are set according to the design of the metal layer in the subsequent process. The second partition opening 132 in this application is only an example.

[0045] In some embodiments of this application, the method of forming the second partition opening 132 includes wet etching, dry etching, etc. The etchant for etching the second hard mask layer 112 can be selected to have a relatively high etching selectivity for the first hard mask layer 111 and the second hard mask layer 112, so that the etching can stop on the first hard mask layer 111.

[0046] Reference Figure 8 and Figure 9 As shown in Figure 9 which is a top view, Figure 8 and Figure 9 which is a cross-sectional view taken along the dashed line in

[0047] In some embodiments of the present application, the method for forming sidewalls 140 on both sides of the first trench 121 includes: forming a sidewall material layer on the bottom and both sides of the first trench 121, in the first partition opening 131 and the second partition opening 132, and on the surface of the mandrel layer 120; etching and removing the sidewall material layer on the surface of the mandrel layer 120 and the bottom of the first trench 121 to form the sidewalls 140 on both sides of the first trench 121. When etching the sidewall material layer, the second hard mask layer 112 is used as the etching stop layer, so that the part of the sidewall material layer in the first partition opening 131 and the second partition opening 132 below the top surface of the second hard mask layer 112 will not be etched, thereby enabling the sidewalls 140 to fill the first partition opening 131 and the second partition opening 132.

[0048] In some embodiments of the present application, the sidewalls are silicides. Specifically, the silicides can be oxides of silicon, nitrides of silicon, oxynitrides of silicon, such as silicon carbide, silicon carbonitride, silicon nitride, or silicon oxide.

[0049] In some embodiments of the present application, the method for forming the sidewall material layer may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., such as low-pressure chemical vapor deposition, laser ablation deposition, and selective epitaxial growth process formed thereby.

[0050] In some embodiments of the present application, the method for etching the sidewall material layer includes wet etching or dry etching, etc. The etchant can be a C-F compound, and the C-F compound can be one or more of CF4, CHF3, C4F8, and C5F8.

[0051] Reference Figure 10 and Figure 11 As shown, in step S150, the patterned mandrel layer 120 is removed. Among them, Figure 11 is a top view, Figure 10 is a cross-sectional view taken along the Figure 11 dotted line in

[0052] In some embodiments of the present application, the method for removing the patterned mandrel layer 120 includes wet etching or dry etching, etc.

[0053] Reference Figures 12 to 17 As shown, in step S160, the first hard mask layer 111 and the second hard mask layer 112 are etched to form a plurality of second trenches 122. The specific etching process is described as follows.

[0054] Reference Figure 12 and Figure 13 As shown, using the sidewalls 140 as a mask, the second hard mask layer 112 is etched until the first hard mask layer 111 is exposed. Among them, Figure 13is a top view, Figure 12 is along Figure 13 the cross-sectional view taken along the dashed line in

[0055] In some embodiments of the present application, the method of etching the second hard mask layer 112 includes wet etching or dry etching, etc. An etchant with a relatively high etching selectivity for the first hard mask layer 111 and the second hard mask layer 112 is selected for etching the second hard mask layer 112, so that the etching can stop on the first hard mask layer 111.

[0056] Referring to Figure 14 and Figure 15 as shown, with the second hard mask layer 112 as the etching stop layer, the sidewall 140 above the top surface of the second hard mask layer 112 is etched away. Among them, Figure 15 is a top view, Figure 14 is along Figure 15 the cross-sectional view taken along the dashed line in

[0057] In some embodiments of the present application, the method of etching the sidewall 140 includes wet etching or dry etching, etc. Since the second hard mask layer 112 is used as the etching stop layer, that is, the part of the sidewall located in the second partition opening below the top surface of the second hard mask layer 112 will not be etched.

[0058] Referring to Figure 16 and Figure 17 as shown, the first hard mask layer 111 is etched using the sidewall 140 and the second hard mask layer 112 as masks until the substrate 100 is exposed, specifically, the dielectric layer 102 is exposed. Among them, Figure 17 is a top view, Figure 16 is along Figure 17 the cross-sectional view taken along the dashed line in

[0059] In some embodiments of the present application, the method of etching the first hard mask layer 111 includes wet etching or dry etching, etc.

[0060] Referring to Figure 18 and Figure 19 as shown, in step S170, etching is performed along the second trench 122 into the substrate 100, specifically, etching the dielectric layer 102 until the substrate 101 is exposed. Among them, Figure 19 is a top view, Figure 18 is along Figure 19 the cross-sectional view taken along the dashed line in

[0061] In some embodiments of the present application, the method of etching along the second trench 122 into the substrate 100 includes wet etching or dry etching, etc.

[0062] In some embodiments of the present application, when etching along the second trench 122 into the substrate 100, the sidewall 140, the first hard mask layer 111, and the second hard mask layer 112 are used as masks, and the sidewall 140 and the second hard mask layer 112 are completely consumed.

[0063] In some other embodiments of the present application, if the sidewall 140 and the second hard mask layer 112 are not completely consumed, a step of separately removing the sidewall 140 and the second hard mask layer 112 is added.

[0064] Reference Figure 20 and Figure 21 As shown, in step S180, the first hard mask layer 111 and the second hard mask layer 122 are removed, and a metal layer 150 is formed in the second trench, wherein a part of the metal layer 150 is blocked by the dielectric layer 102 in the substrate 100. Among them, Figure 21 is a top view, Figure 20 is along Figure 21 the cross-sectional view taken along the dotted line in

[0065] If the sidewall 140 and the second hard mask layer 112 are completely consumed, there is no need to remove the second hard mask layer 122 in this step; if the sidewall 140 and the second hard mask layer 112 are not completely consumed, the sidewall 140 and the second hard mask layer 112 can be removed in this step.

[0066] In some embodiments of the present application, the method for forming the metal layer 150 includes: forming a metal material layer on the substrate 100 that completely covers the substrate 100 and the first hard mask layer 111; using a chemical mechanical polishing process to polish the first hard mask layer 111 and the metal material layer until the substrate 100 is exposed to form the metal layer 150. Specifically, the dielectric layer 102 in the substrate 100 is exposed.

[0067] In the method for forming the semiconductor structure described in the present application, by utilizing the etching selectivity difference between the first hard mask layer and the second hard mask layer, the first partition opening and the second partition opening are formed with the first hard mask layer and the second hard mask layer as the etching stop layers respectively, which can simplify the process, save materials, and thus reduce costs.

[0068] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0069] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intervening elements.

[0070] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intervening elements. In contrast, the term "directly" means without intervening elements. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0071] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of this application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0072] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, on the surface of which a first hard mask layer, a second hard mask layer, and a patterned mandrel layer are sequentially formed. The patterned mandrel layer includes a plurality of first trenches exposing the second hard mask layer; Forming a plurality of first partition openings in the patterned mandrel layer to expose the second hard mask layer; Forming a plurality of second partition openings in the exposed second hard mask layer to expose the first hard mask layer; Forming sidewalls on both sides of the first trenches, the sidewalls not filling the first trenches, and the sidewalls also filling the first partition openings and the second partition openings; Removing the patterned mandrel layer; Etching the first hard mask layer and the second hard mask layer to form a plurality of second trenches; Etching along the second trenches into the substrate; Removing the first hard mask layer and the second hard mask layer.

2. The method for forming a semiconductor structure as described in claim 1, wherein, The method of forming the patterned mandrel layer includes: Forming a mandrel layer on the surface of the second hard mask layer; Forming a patterned first photoresist layer on the surface of the mandrel layer, the patterned first photoresist layer including a plurality of first openings; Using the patterned first photoresist layer as a mask to etch the mandrel layer along the plurality of first openings to form the first trenches; Removing the patterned first photoresist layer.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein The method of forming sidewalls on both sides of the first trenches includes: Forming a sidewall material layer at the bottom and on both sides of the first trenches, in the first partition openings and the second partition openings, and on the surface of the mandrel layer; Etching and removing the sidewall material layer on the surface of the mandrel layer and at the bottom of the first trenches to form the sidewalls on both sides of the first trenches.

4. The method for forming a semiconductor structure according to claim 1, wherein The method of etching the first hard mask layer and the second hard mask layer to form a plurality of second trenches includes: Using the sidewalls as a mask to etch the second hard mask layer until the first hard mask layer is exposed; Etching and removing the sidewalls higher than the top surface of the second hard mask layer; Using the sidewalls and the second hard mask layer as a mask to etch the first hard mask layer until the substrate is exposed.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein, When etching along the second trenches into the substrate, using the sidewalls, the first hard mask layer, and the second hard mask layer as a mask, and the sidewalls and the second hard mask layer are completely consumed.

6. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first hard mask layer includes metal nitride, silicon oxide, or silicon nitride, and the thickness of the first hard mask layer is 100 Å to 300 Å.

7. The method for forming a semiconductor structure according to claim 1, wherein, The material of the second hard mask layer includes metal nitride, silicon oxide, or silicon nitride, and the thickness of the second hard mask layer is 100 Å to 300 Å.

8. The method for forming a semiconductor structure according to claim 1, wherein, The substrate includes a substrate and a dielectric layer on the surface of the substrate.

9. The method for forming a semiconductor structure as claimed in claim 8, wherein, Also comprising: Forming a metal layer in the second trenches, wherein part of the metal layer is blocked by the substrate.

10. The method for forming a semiconductor structure according to claim 9, wherein, The method of forming the metal layer includes: Forming a metal material layer on the substrate to completely cover the substrate and the first hard mask layer; Using a chemical mechanical polishing process to polish the first hard mask layer and the metal material layer until the substrate is exposed to form the metal layer.

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