Ultra-thin multi-type chip integrated package structure and manufacturing method thereof

Abstract

The application discloses a kind of ultra-thin multi-type chip integrated packaging structure and manufacturing method thereof, the packaging structure includes bearing sheet, the lower surface of bearing sheet has metal redistribution layer, the lower surface of bearing sheet and the upper surface of metal redistribution layer have protective film layer, the upper surface of bearing sheet is horizontally provided with at least two recess structures, the photosensitive area of chip in one recess structure faces downward, the front of chip in adjacent recess structure faces upward, there is first insulating medium layer on chip, there is redistribution layer at the opening on first insulating medium layer, there is second insulating medium layer on first insulating medium layer and redistribution layer, expose the pad on redistribution layer, solder ball is connected with redistribution layer through corresponding pad, chip is electrically connected with solder ball through corresponding redistribution layer.The application effectively integrates at least two functionally different chips in horizontal direction, obtains ultra-thin packaging structure;The signal of chip with photosensitive function is led out from the front, avoids back hole, protects chip and reduces process difficulty.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor chip packaging, and particularly relates to an ultrathin multi-type chip integrated packaging structure and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of modern electronic technology, mobile consumer electronic products such as mobile phones and PDAs have increasingly strict requirements for portability and multifunctionality. Integrating more functions, improving product performance, thinning, and reducing manufacturing costs have gradually become the development direction of intelligent terminal products and industry manufacturers. With the increasing richness of the functions of current electronic products, single chip type integrated packaging cannot meet the actual use needs. How to effectively integrate and package different types of chips in the same integrated structure to meet the development direction of chip multifunctionality has become a hot topic in the packaging industry. SUMMARY

[0003] To solve the technical problems existing in the prior art, the purpose of the present application is to provide an ultrathin multi-type chip integrated packaging structure and a manufacturing method thereof.

[0004] To achieve the above-mentioned purposes and achieve the above-mentioned technical effects, the technical solution adopted by the present application is as follows:

[0005] An ultrathin multi-type chip integrated packaging structure comprises a carrier sheet, the lower surface of the carrier sheet forms a metal redistribution layer, and a protective film layer is covered on the lower surface of the carrier sheet and the metal redistribution layer. At least two recess structures are horizontally arranged on the upper surface of the carrier sheet, one chip is arranged in each recess structure, the chips in all recess structures are horizontally arranged at intervals, the chips in all recess structures belong to different functional chips, and a gap exists between the recess structure and the chip inside the recess structure. The photosensitive area of the chip in one of the recess structures is placed downward and bonded to the conductive copper pillars on both sides of the electrode, the chip in the adjacent recess structure is placed upward and bonded in the recess structure, a first insulating medium layer is covered on the upper surface of the chip, the first insulating medium layer has an opening and a redistribution layer is formed at the opening, a second insulating medium layer is further covered on the upper surface of the first insulating medium layer and the redistribution layer, the second insulating medium layer has a conductive via structure, and a pad on the redistribution layer is exposed. Each solder ball is connected to the redistribution layer through a matching pad, and the electrode of the chip is electrically connected to the corresponding solder ball through the corresponding redistribution layer.

[0006] Further, the upper surface of the carrier sheet is horizontally spaced apart by two groove structures, respectively denoted as a first groove structure and a second groove structure, the carrier sheet is provided with a first conductive copper column and a second conductive copper column on both sides of the first groove structure, the electrodes of the first chip are bonded together with the first conductive copper column in the first groove structure through conductive adhesive, the photosensitive region of the first chip is placed downward, there is a gap between the first chip and the inner wall of the first groove structure and a first gap is formed, the second chip is pasted on the inner bottom of the second groove structure through the adhesive film, the front surface of the second chip is placed upward, there is a gap between the second chip and the inner wall of the second groove structure and a second gap is formed, and the back surface of the first chip and the front surface of the second chip are provided with a first insulating medium layer.

[0007] Further, the first insulating medium layer has an opening, forming a first conductive via and a second conductive via, the first conductive via is matched with the position of the second conductive copper column on the upper surface of the carrier sheet, and the first conductive via and the second conductive via are provided with a redistribution layer.

[0008] Further, the electrodes of the first chip are sequentially electrically connected with the corresponding solder balls through the corresponding first conductive copper column, metal redistribution layer, second conductive copper column and redistribution layer, and the electrodes of the second chip are electrically connected with the corresponding solder balls through the corresponding redistribution layer.

[0009] A manufacturing method of an ultrathin multi-type chip integrated packaging structure, comprising the following steps:

[0010] Step one: take a carrier sheet, form a semi-finished product with groove structure, conductive copper column and metal redistribution layer on the carrier sheet, wherein the groove structure is provided with at least two and is horizontally arranged;

[0011] Step two: bond a chip in each groove structure, all the chips in the groove structures belong to different functional chips, and there is a gap between the groove structure and the chip inside the groove structure;

[0012] Step three: plastic encapsulation is performed on the surface of the chip to form a first insulating medium layer with an opening;

[0013] Step four: form a redistribution layer in the opening of the first insulating medium layer;

[0014] Step five: cover the first insulating medium layer and the redistribution layer with a second insulating medium layer, the second insulating medium layer has a conductive via structure, exposes the pads on the redistribution layer, and completes the ball mounting process.

[0015] Further, in step one, a carrier sheet with good light transmittance is taken, a metal redistribution layer is formed on the lower surface of the carrier sheet, the lower surface of the carrier sheet and the metal redistribution layer are covered with a protective film layer with high light transmittance, at least two groove structures are formed on the upper surface of the carrier sheet, and a plurality of conductive copper columns are formed on the carrier sheet and located on both sides of one of the groove structures.

[0016] Further, the upper surface of the carrier sheet forms a first groove structure and a second groove structure, and two conductive copper columns, a first conductive copper column and a second conductive copper column, are formed on the carrier sheet and located on both sides of the first groove structure; the material of the metal redistribution layer is one of aluminum, copper, gold, platinum, nickel, tin or a combination of two or more thereof, and the metal redistribution layer is formed by a photolithography or etching process and a deposition process, such as a coating process, a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless plating process or other suitable process.

[0017] Further, in step two, the electrodes of the first chip and the first conductive copper column are bonded together by conductive glue in the first groove structure, the photosensitive area of the first chip is placed downward, there is a gap between the first chip and the inner wall of the first groove structure and a first gap is formed, and the second chip is pasted on the bottom of the second groove structure by the adhesive film, the front surface of the second chip is placed upward, there is a gap between the second chip and the inner wall of the second groove structure and a second gap is formed.

[0018] Further, in step three, a first insulating dielectric layer is formed on the back surface of the first chip and the front surface of the second chip, there is an opening on the first insulating dielectric layer, a first conductive via and a second conductive via are formed, and the first conductive via is matched with the second conductive copper column in position.

[0019] Further, in step four, a redistribution layer is formed in the first conductive via and the second conductive via.

[0020] Compared with the prior art, the beneficial effects of the present application are:

[0021] 1. At least two functionally different chips are effectively integrated in the horizontal direction, realizing the integration of different types of chips while obtaining an ultra-thin packaging structure;

[0022] 2. The chip signal with photosensitive function is led out from the front surface, avoiding the opening on the back surface of the chip, which reduces the process difficulty and effectively protects the functional layer material of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The structure schematic diagram after step one of the manufacturing method of embodiment 1 of the present application is shown in the figure.

[0024] Figure 2Structure schematic diagram after step two of the manufacturing method of embodiment 1 of the present application;

[0025] Figure 3 Structure schematic diagram after step three of the manufacturing method of embodiment 1 of the present application;

[0026] Figure 4 Structure schematic diagram after step four of the manufacturing method of embodiment 1 of the present application;

[0027] Figure 5 Structure schematic diagram after step five of the manufacturing method of embodiment 1 of the present application. DETAILED DESCRIPTION

[0028] The present application will be described in detail below so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.

[0029] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0030] As shown in Figures 1-5 A super-thin multi-type chip integrated packaging structure includes a carrier sheet 10, the lower surface of the carrier sheet 10 forms a metal redistribution layer 12, the lower surface of the carrier sheet 10 and the metal redistribution layer 12 are covered with a protective film layer 11 with high light transmittance, the upper surface of the carrier sheet 10 is horizontally spaced apart to form at least two recess structures with the same depth or different depths, one chip is arranged in each recess structure, the chips in all recess structures are horizontally spaced apart, the chips in all recess structures belong to different functional chips, there is a gap between the recess structure and the chip inside it, the first conductive copper column 13 and the second conductive copper column 14 are formed on the carrier sheet 10 and located on both sides of one of the recess structures, and the photosensitive area of the chip in the recess structure is placed downward and bonded with the first conductive copper column 13, the chip in the adjacent recess structure is placed with the front face upward and bonded in the recess structure, the upper surface of the chip is covered with a first insulating medium layer 20, the first insulating medium layer 20 has an opening and a redistribution layer 21 is formed at the opening, and the upper surface of the first insulating medium layer 20 and the redistribution layer 21 needs to be further covered with a second insulating medium layer 22, the second insulating medium layer 22 has a conductive via structure, and exposes a pad 23 on the redistribution layer 21, each solder ball 24 is connected with the redistribution layer 21 through a corresponding pad 23, and the electrode of the chip forms an electrical connection with the corresponding solder ball 24 through the corresponding redistribution layer 21.

[0031] A manufacturing method of an ultrathin multi-type chip integrated packaging structure, comprising the following steps:

[0032] Step one: take a carrier sheet 10 with good light transmittance, form a metal redistribution layer 12 on the lower surface of the carrier sheet 10, the lower surface of the carrier sheet 10 and the metal redistribution layer 12 are covered with a protective film layer 11 with high light transmittance, form a plurality of groove structures on the upper surface of the carrier sheet 10, form a first conductive copper column 13 and a second conductive copper column 14 on the carrier sheet 10 and on both sides of one of the groove structures, wherein the lower surface of the protective film layer 11 is numbered 201, the upper surface of the carrier sheet 10 is numbered 202, the material of the metal redistribution layer 12 is one of aluminum, copper, gold, platinum, nickel, tin or a combination of two or more thereof, which is made by photolithography or etching process and deposition process, and the deposition process can be coating process, physical vapor deposition process, chemical vapor deposition process, electroplating process, electroless plating process or other suitable process.

[0033] Step two: bond the electrode 16 of the first chip 17 with the first conductive copper column 13 together through the conductive adhesive 15 in the groove structure with the first conductive copper column 13 and the second conductive copper column 14, place the photosensitive area of the first chip 17 downward, there is a gap between the first chip 17 and the inner wall of the groove structure and forms a first gap 207, paste the second chip 19 on the bottom of the adjacent groove structure through the adhesive film 18, place the front surface of the second chip 19 upward, there is a gap between the second chip 19 and the inner wall of the groove structure and forms a second gap 208.

[0034] Step three: form a first insulating medium layer 20 on the back surface 205 of the first chip 17 and the front surface 206 of the second chip 19, the first insulating medium layer 20 has an opening on the upper surface thereof, forming a conductive via, and the upper surface of the first insulating medium layer 20 is numbered 209.

[0035] Step four: form a redistribution layer 21 in the conductive via of the first insulating medium layer 20, wherein the upper surface of the redistribution layer 21 is numbered 212.

[0036] Step five: cover the upper surfaces of the first insulating medium layer 20 and the redistribution layer 21 with a second insulating medium layer 22, the second insulating medium layer 22 has a conductive via structure thereon, exposing the pads 23 on the redistribution layer 21, the solder balls 24 are connected with the redistribution layer 21 through the pads 23, the electrodes of the second chip 19 form electrical connection with the corresponding solder balls 24 through the corresponding redistribution layer 21, the electrodes 16 of the first chip 17 form electrical connection with the corresponding solder balls 24 in turn through the corresponding first conductive copper column 13, the metal redistribution layer 12, the second conductive copper column 14 and the redistribution layer 21, and the upper surface of the second insulating medium layer 22 is numbered 213.

[0037] Example 1

[0038] like Figures 1-5 As shown, an ultra-thin multi-chip integrated packaging structure includes a carrier sheet 10. A metal redistribution layer 12 is formed on the lower surface of the carrier sheet 10. A protective film layer 11 with high light transmittance is covered on the lower surface of the carrier sheet 10 and the metal redistribution layer 12. Two groove structures are horizontally spaced on the upper surface of the carrier sheet 10, and a chip is disposed in each groove structure. The chips in all groove structures are horizontally spaced and belong to different functions. There is a gap between the chip and the groove structure. In this embodiment, the upper surface of the carrier sheet 10 forms a first groove structure. The first conductive copper pillar 13 and the second conductive copper pillar 14 are formed on the carrier sheet 10 on both sides of the first groove structure 203, 203 and 204 respectively. The electrodes 16 of the first chip 17 are bonded to the first conductive copper pillars 13 within the first groove structure 203 using conductive adhesive 15. The photosensitive area of ​​the first chip 17 is placed downwards. A gap exists between the first chip 17 and the inner wall of the first groove structure 203, forming a first gap 207. The second chip 19 is adhered to the bottom of the second groove structure 204 using adhesive film 18, with the front of the second chip 19 facing upwards. A gap exists between the second chip 19 and the inner wall of the second groove structure 204, forming a second gap 208. A first insulating dielectric layer 20 is formed on the back side 205 of the first chip 17 and the front side 206 of the second chip 19. The first insulating dielectric layer 20 has openings, forming a first conductive via 210 and a second conductive via 211, exposing the electrodes of the second conductive copper pillar 14 and the second chip 19. The first conductive via 210 is matched with the position of the second conductive copper pillar 14. A redistribution layer 21 is formed within the first conductive via 210 and the second conductive via 211 of the first insulating dielectric layer 20. An insulating dielectric layer 20 and a redistribution layer 21 are covered with a second insulating dielectric layer 22. The second insulating dielectric layer 22 has a conductive via structure, exposing the pads 23 on the redistribution layer 21. Each solder ball 24 is connected to the redistribution layer 21 through a matching pad 23. The electrode 16 of the first chip 17 is electrically connected to the corresponding solder ball 24 through its corresponding first conductive copper pillar 13, the metal redistribution layer 12, the second conductive copper pillar 14, the redistribution layer 21, and the corresponding electrode 19. The electrode of the second chip 19 is electrically connected to the corresponding solder ball 24 through its corresponding redistribution layer 21.

[0039] A method for manufacturing an ultra-thin multi-chip integrated packaging structure includes the following steps:

[0040] Step one: take a carrier sheet 10 with good light transmittance, form a metal redistribution layer 12 on the lower surface of the carrier sheet 10, the lower surface of the carrier sheet 10 and the metal redistribution layer 12 are covered with a protective film layer 11 with high light transmittance, form a first recess structure 203 and a second recess structure 204 on the upper surface of the carrier sheet 10, form a first conductive copper column 13 and a second conductive copper column 14 on the carrier sheet 10 and on both sides of the first recess structure 203 respectively, and get the structure as shown in Figure 1 , wherein the lower surface of the protective film layer 11 is numbered 201, the upper surface of the carrier sheet 10 is numbered 202, the material of the metal redistribution layer 12 is copper, and the metal redistribution layer 12 is made by photolithography-deposition process.

[0041] Step two: bond the electrode 16 of the first chip 17 and the first conductive copper column 13 together by conductive glue 15 in the first recess structure 203, place the photosensitive area of the first chip 17 downward, there is a gap between the first chip 17 and the inner wall of the first recess structure 203 and form a first gap 207, paste the second chip 19 on the bottom of the second recess structure 204 by the adhesive film 18, place the front surface of the second chip 19 upward, there is a gap between the second chip 19 and the inner wall of the second recess structure 204 and form a second gap 208, and get the structure as shown in Figure 2 .

[0042] Step three: form a first insulating medium layer 20 on the back surface 205 of the first chip 17 and the front surface 206 of the second chip 19, there are openings on the first insulating medium layer 20, form a first conductive via 210 and a second conductive via 211, and get the structure as shown in Figure 3 , wherein the first conductive via 210 is matched with the position of the second conductive copper column 14, and the upper surface of the first insulating medium layer 20 is numbered 209.

[0043] Step four: form a redistribution layer 21 in the first conductive via 210 and the second conductive via 211 of the first insulating medium layer 20, and get the structure as shown in Figure 4 , wherein the upper surface of the redistribution layer 21 is numbered 212.

[0044] Step five: cover the second insulating medium layer 22 on the upper surface of the first insulating medium layer 20 and the redistribution layer 21, the second insulating medium layer 22 has a conductive via structure, which exposes the pad 23 on the redistribution layer 21, the solder ball 24 is connected with the redistribution layer 21 through the pad 23, the electrodes of the second chip 19 form electrical connection with the corresponding solder ball 24 through the corresponding redistribution layer 21, and the electrodes 16 of the first chip 17 form electrical connection with the corresponding solder ball 24 through the first conductive copper column 13, the metal redistribution layer 12, the second conductive copper column 14 and the redistribution layer 21 in turn, and get the structure as shown in Figure 5The structure shown, wherein the upper surface of the second insulating medium layer 22 is numbered 213.

[0045] The parts or structures not specifically described in the present application can be implemented by using the prior art or existing products, and will not be described here.

[0046] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An ultrathin multi-die chip integrated package structure, characterized in that, The application relates to a chip carrier, which comprises a carrier sheet, a lower surface of the carrier sheet forms a metal redistribution layer, a protective film layer covers the lower surface of the carrier sheet and the metal redistribution layer, two groove structures are horizontally arranged on the upper surface of the carrier sheet, the two groove structures are respectively a first groove structure and a second groove structure, a first conductive copper column and a second conductive copper column are respectively arranged on the carrier sheet and located on the two sides of the first groove structure, electrodes of a first chip are bonded together with the first conductive copper column through conductive glue in the first groove structure, a photosensitive area of the first chip is placed downward, a gap exists between the first chip and the inner wall of the first groove structure and forms a first gap, a second chip is pasted on the inner bottom of the second groove structure through a bonding film, the front surface of the second chip is placed upward, a gap exists between the second chip and the inner wall of the second groove structure and forms a second gap, a first insulating medium layer is formed on the back surface of the first chip and the front surface of the second chip, a second insulating medium layer needs to be further covered on the upper surface of the first insulating medium layer and the redistribution layer, the second insulating medium layer is provided with a conductive via structure, and a bonding pad on the redistribution layer is exposed, each solder ball is connected with the redistribution layer through a matched bonding pad, and the electrodes of the chips are electrically connected with the corresponding solder balls through the corresponding redistribution layer. The first insulating medium layer is provided with an opening, and a first conductive via and a second conductive via are formed, the first conductive via is matched with the position of the second conductive copper column on the upper surface of the carrier sheet, and the first conductive via and the second conductive via form the redistribution layer. The electrodes of the first chip are electrically connected with the corresponding solder balls through the first conductive copper column, the metal redistribution layer, the second conductive copper column and the redistribution layer in sequence, and the electrodes of the second chip are electrically connected with the corresponding solder balls through the corresponding redistribution layer.

2. The method of claim 1, wherein the method further comprises: forming a plurality of through-silicon vias (TSVs) in the plurality of chips; and forming a plurality of redistribution layers (RDLs) on the plurality of chips. The application further discloses a chip carrier manufacturing method, which comprises the following steps: Step one: taking a carrier sheet, forming a semi-finished product with groove structures, conductive copper columns and a metal redistribution layer on the carrier sheet, wherein two groove structures are horizontally arranged; Step two: bonding a chip in each groove structure, the chips in all the groove structures belong to different functional chips, and a gap exists between the groove structures and the chips in the groove structures; Step three: plastic packaging on the surface of the chip to form a first insulating medium layer with an opening; Step four: forming a redistribution layer in the opening of the first insulating medium layer; Step five: covering a second insulating medium layer on the upper surface of the first insulating medium layer and the redistribution layer, the second insulating medium layer is provided with a conductive via structure, a bonding pad on the redistribution layer is exposed, and the ball mounting process is completed.

3. The method of claim 2, wherein the method further comprises: In step one, a carrier sheet with high light transmittance is taken, a metal redistribution layer is formed on the lower surface of the carrier sheet, and a protective film layer with high light transmittance covers the lower surface of the carrier sheet and the metal redistribution layer.

4. The method of claim 3, wherein the method further comprises: The upper surface of the carrier sheet forms two groove structures, i.e. a first groove structure and a second groove structure, two conductive copper columns, i.e. a first conductive copper column and a second conductive copper column, are respectively arranged on the carrier sheet and located on the two sides of the first groove structure; the material of the metal redistribution layer is one of aluminum, copper, gold, platinum, nickel and tin or a combination of two or more thereof, and the metal redistribution layer is formed through a photoetching or etching process and a deposition process.

5. The method of claim 4, wherein the method further comprises: In step two, the electrodes of the first chip are adhered together with the first conductive copper column through conductive glue in the first recess structure, the photosensitive region of the first chip is placed downward, there is a gap between the first chip and the inner wall of the first recess structure and a first gap is formed, the second chip is pasted on the bottom of the second recess structure through the adhesive film, the front surface of the second chip is placed upward, there is a gap between the second chip and the inner wall of the second recess structure and a second gap is formed.

6. The method of claim 5, wherein the method further comprises: In step three, a first insulating medium layer is formed on the back surface of the first chip and the front surface of the second chip, there is an opening on the first insulating medium layer, a first conductive via and a second conductive via are formed, the first conductive via is matched with the position of the second conductive copper column.

7. The method of claim 6, wherein the method further comprises: In step four, a rewiring layer is formed in the first conductive via and the second conductive via.

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