Chip-on-film and display device

Abstract

The present disclosure provides a COF film and a display device, wherein the COF film has a plurality of traces, each trace including at least a first metal layer for realizing communication between a display panel and a driving unit, the traces including at least a first type of traces, the first type of traces also including a second metal layer arranged in parallel with the first metal layer, the length of the second metal layer in each first type of trace being inversely proportional to the length of the first metal layer in the first type of trace, so that the capacitance value of each trace is the same. The present disclosure designs a partial double-layer metal layer for the traces inside the COF film, and arranges second metal layers of different lengths according to the lengths of the traces, so that the capacitance of each trace in the COF film is the same, achieving a capacitance compensation effect, making the charging conditions of each pixel column in the display panel the same, ensuring that the display panel presents a uniform display effect, and improving the user experience.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a chip-on-film and a display device. Background Art

[0002] With the continuous improvement of display technology and the continuous enrichment of user needs, the refresh rate of display devices has been continuously increasing from 120 Hz. In some devices used for large-scale games or media, the refresh rate requirements for the display have even reached 500 Hz or 1000 Hz. The increase in refresh rate also shortens the pixel charging time in the display panel. The problem of reduced pixel brightness due to insufficient charging time of some pixel columns will seriously affect the display effect of the display device, causing the display device to have "vertical black areas" with insufficient brightness at intervals, affecting the user experience. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a chip-on-film and a display device to solve the problem of vertical black areas caused by high refresh rates of display devices in the prior art.

[0004] The embodiments of the present disclosure adopt the following technical solution: a chip-on-chip film, the chip-on-chip film having multiple routing lines, each of the routing lines including at least a first metal layer, for realizing communication between the display panel and the driving unit, the routing lines including at least a first type of routing lines, the first type of routing lines also including a second metal layer arranged parallel to the first metal layer, the length of the second metal layer in each of the first type of routing lines is inversely proportional to the length of the first metal layer in the first type of routing lines, so that the capacitance value of each of the routing lines is the same.

[0005] In some embodiments, the first routing line having the longest length in the first metal layer does not have the second metal layer, the second routing line having the shortest length in the first metal layer has the same length of the second metal layer as the first metal layer of the second routing line; and the length L1 of the first metal layer of the first routing line and the length L2 of the first metal layer of the second routing line satisfy the following formula:

[0006]

[0007] Wherein, C is the maximum compensation capacitance value, and a is the correlation coefficient between the length of the first metal layer of the wiring of the COF and the capacitance of the wiring.

[0008] In some embodiments, the routing lines are arranged in sequence according to the length of the first metal layer, and the length differences between the second metal layers in adjacent routing lines are the same, and the length differences are determined according to the total number of routing lines.

[0009] In some embodiments, the length difference is expressed based on the following formula:

[0010]

[0011] Wherein, L′ is the length difference, and N is the total number of the traces in the chip-on-film.

[0012] In some embodiments, the first metal layer and the second metal layer in the first type of trace are connected through at least one via.

[0013] In some embodiments, it also includes: a base layer, the surface of which is used to set the first metal layer and / or the second metal layer; a first solder resist layer, which is used to encapsulate the first metal layer; and a second solder resist layer, which is used to encapsulate the second metal layer.

[0014] In some embodiments, the first metal layer is arranged on the first surface of the base layer, and the first solder resist layer is arranged on the side of the first metal layer away from the base layer; the second metal layer is arranged on the second surface of the base layer, and the second solder resist layer is arranged on the side of the second metal layer away from the base layer; the second surface is the side of the base layer opposite to the first surface.

[0015] In some embodiments, the first metal layer is arranged on the first surface of the base layer, and the first solder resist layer is arranged on the side of the first metal layer away from the base layer; the second metal layer is arranged on the side of the first solder resist layer away from the first metal layer, and the second solder resist layer is arranged on the side of the second metal layer away from the first solder resist layer.

[0016] In some embodiments, the second metal layer is arranged on the first surface of the base layer, and the second solder resist layer is arranged on the side of the second metal layer away from the base layer; the first metal layer is arranged on the side of the second solder resist layer away from the second metal layer, and the first solder resist layer is arranged on the side of the first metal layer away from the second solder resist layer.

[0017] An embodiment of the present disclosure further provides a display device, comprising at least: a display panel; a driving unit; and a chip-on-film as described above, wherein the chip-on-film is used to enable communication between the display panel and the driving unit.

[0018] The beneficial effects of the embodiments of the present disclosure are: by designing a partial double-layer metal layer for the internal wiring of the flip chip film, and setting a second metal layer of different lengths according to the length of the wiring, the capacitance of each wiring in the flip chip film is made the same, thereby achieving a capacitance compensation effect, making the charging conditions of each pixel column in the display panel the same, ensuring that the display panel presents a uniform display effect, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 Schematic diagram of the top view of the chip-on-film structure in the first embodiment of the present disclosure;

[0021] Figure 2 The first embodiment of the present disclosure Figure 1 Schematic diagram of the first cross-sectional structure at the AA′ position;

[0022] Figure 3 The second embodiment of the present disclosure Figure 1 Schematic diagram of the second cross-sectional structure at the AA′ position;

[0023] Figure 4 The second embodiment of the present disclosure Figure 1 Schematic diagram of the third cross-sectional structure at the AA′ position. DETAILED DESCRIPTION

[0024] Various aspects and features of the present disclosure are described herein with reference to the accompanying drawings.

[0025] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the above description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope and spirit of the present disclosure will occur to those skilled in the art.

[0026] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0027] These and other characteristics of the present disclosure will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0028] It should also be understood that although the present disclosure has been described with reference to certain specific examples, those skilled in the art will be able to realize many other equivalent forms of the present disclosure that have the features of the claims and are therefore within the scope of protection defined thereby.

[0029] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0030] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant detail. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but rather serve merely as a basis and representative basis for teaching those skilled in the art to variously employ the present disclosure with substantially any suitable detailed structure.

[0031] This description may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," each of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0032] With the continuous improvement of display technology and the continuous enrichment of user needs, the refresh rate of display devices has been continuously increasing from 120 Hz. In some devices used for large-scale games or media, the refresh rate requirements for the display have even reached 500 Hz or 1000 Hz. The increase in refresh rate also shortens the pixel charging time in the display panel. The problem of reduced pixel brightness due to insufficient charging time of some pixel columns will seriously affect the display effect of the display device, causing the display device to have "vertical black areas" with insufficient brightness at intervals, affecting the user experience.

[0033] To address the aforementioned issues, this embodiment provides a Chip On Film (COF), which is typically connected between a display panel and a driver unit (driver IC) to transmit the driver unit's output signal to the display panel, thereby achieving the display effect of the display panel. Multiple metal traces are arranged within the COF, each of which includes at least a first metal layer 10. One end of the first metal layer 10 is connected to a bonding pad in the display panel, and the other end is connected to a pin on the output terminal of the driver IC to achieve data communication.

[0034] Figure 1 FIG. 1 shows a schematic diagram of the top view of the flip chip film provided in this embodiment. Figure 1As shown, due to the size difference between the connection area of ​​the display panel and the output end of the driver IC, the connection position of each trace arranged in the flip chip film when connecting the display panel and the driver IC respectively is different, so the lengths of the various traces in the flip chip film are also different. The first metal layer 10 represents the original single-layer trace involved in the COF, and the length of the first metal layer 10 is the length of the trace.

[0035] In this embodiment, all the routing lines provided in the COF film include at least the first type of routing lines, and the first type of routing lines refer to routing lines provided with the second metal layer 20 in addition to the first metal layer 10, so that the first type of routing lines further form a compensation capacitor through the second metal layer 20 on the basis of the capacitance formed by the original first metal layer 10, thereby improving the overall capacitance of the routing lines. Specifically, the second metal layer 20 is provided in parallel with the first metal layer 10 of the routing lines to which it belongs. The formation of the additional capacitance is achieved through the design of the additional metal layer. When the second metal layer 20 is actually provided, it is preferably provided at a position completely corresponding to the first metal layer 10, that is, from a first direction perpendicular to the surface of the COF film, the orthographic projection of the second metal layer 20 in the first direction is completely covered by the orthographic projection of the first metal layer 10 of the routing lines to which it belongs in the first direction, thereby avoiding the situation where the capacitance of adjacent routing lines is affected by the offset between the position of the second metal layer 20 and the position of the first metal layer 10. It should be noted that the parameters such as the preparation material, preparation thickness, and routing width of the second metal layer 20 added in this embodiment are the same as those of the first metal layer 10. The only difference is the change in length, so as to ensure that the compensation capacitor is formed while the routing is unified as a whole.

[0036] For the routing of flip chip film, its capacitance in the case of single-layer routing (that is, only considering the first metal layer as the routing) increases continuously with the increase of the routing length. Through simulation, it can be seen that the capacitance y of the single-layer routing and the routing length x satisfy the linear law: y = ax + b, where a represents the correlation coefficient between the routing length and the routing capacitance. When reflected in the function graph, a represents the slope of the straight line in the coordinate system, and b is a constant, usually a fixed value. Therefore, the longer the routing length, the greater the capacitance value of the routing, which in turn causes the capacitance between routings of different lengths. In contrast, in this embodiment, the capacitance of the routing is compensated by setting the second metal layer 20. In order to achieve the same capacitance value for each routing, the shorter the routing, the greater the capacitance value that needs to be compensated. Therefore, the corresponding second metal layer 20 needs to be longer. That is, the length of the second metal layer 20 in each first-category routing is inversely proportional to the length of the corresponding first metal layer 10. The specific length of the second metal layer 20 in each routing is adjusted according to the length of the corresponding first metal layer 10 and the capacitance value that needs to be compensated.

[0037] When actually designing the first metal layer 10 and / or the second metal layer 20 of each routing line in the COF, for the first routing line with the longest length in the first metal layer 10 (i.e. Figure 1 The rightmost trace in the single-layer metal trace has the largest trace capacitance, and the first trace does not need to be set with a compensation capacitor. However, for the second trace with the shortest length of the first metal layer 10 (i.e. Figure 1 The leftmost trace in the figure has the smallest trace capacitance in the case of a single-layer metal trace, and requires the maximum compensation capacitance setting. In order to ensure the compensation capacitance effect of the second trace, the length of the second metal layer 20 of the second trace can be set to be exactly the same as the length of its first metal layer 10. In this case, when actually designing the trace, it is necessary to ensure that the length L1 of the first metal layer 10 of the first trace and the length L2 of the first metal layer 10 of the second trace satisfy the following formula (1):

[0038]

[0039] Where a is the correlation coefficient between the length of the first metal layer and the capacitance of the trace described above, C is the maximum compensation capacitance value required for the second trace, and 2 times L2 is actually used to represent the sum of the lengths of the first metal layer and the second metal layer of the second trace. Since the lengths of the first metal layer and the second metal layer of the second trace are the same, 2*L2 is used here to represent it. When the length L1 of the first metal layer 10 of the first trace and the length L2 of the first metal layer 10 of the second trace satisfy formula (1), it can be guaranteed that the capacitance value of the second trace after compensation is the same as the capacitance value of the first trace, achieving a good compensation effect.

[0040] It should be understood that the value of the maximum compensation capacitance C is determined based on the display panel model, size, design of the data line in the panel, and design of the routing in the chip-on-film. In different display panels, different power-on conditions will also lead to differences in the value of the maximum compensation capacitance C. Therefore, when determining the C value, multiple angles are usually considered and calculated before the final determination is made. In this embodiment, the delay at the vertical black area position of any display panel under the same power-on condition and the delay at the normal display area at its adjacent position can be determined, and the C value can be calculated based on the difference between the delay conditions at the two different positions. Of course, in actual implementation, the C value can also be determined according to other methods, and this embodiment does not impose specific restrictions.

[0041] When arranging the traces in the chip-on-film, they are usually arranged according to the length of each trace, for example Figure 1The length of the traces in the circuit increases from left to right, that is, the leftmost trace is the shortest and the rightmost trace is the longest. Since the trace capacitance of a single metal layer increases linearly with the trace length, the capacitance value that needs to be compensated for each trace should also conform to a linear relationship, that is, the set length of the second metal layer 20 in the first type of trace will decrease as the length of the first metal layer 10 increases, and the length difference (that is, the magnitude of the reduction) between the second metal layers 20 between adjacent traces is the same. The specific value of the length difference is determined according to the total number of traces included in the flip chip film.

[0042] Furthermore, the length difference can be expressed based on the following formula:

[0043]

[0044] Where L' is the length difference, N is the total number of traces in the COF, and although L2 represents the length of the first metal layer 10 in the second trace, since the second metal layer 20 of the second trace is the same length as the first metal layer 10, in formula (2), L2 actually represents the length of the second metal layer 20 of the second trace. When calculating the length of the second metal layer 20 of a particular trace, it is necessary to know the second metal layer length of the adjacent trace and then increase or decrease L' based on that. For example, a COF has a total of 11 traces (i.e., N=11), which are arranged in order of length. The first trace is the shortest, with a length of 10 mm. The corresponding second metal layer length is also 10 mm. The length difference L′ at this time is 1 mm. From this, it can be calculated that the second metal layer length of the second trace is 10-1=9 mm, the second metal layer length of the third trace is 9-1=8 mm, and so on. The second metal layer length of the tenth trace is 1 mm. The 11th trace is the longest trace, and it does not have a second metal layer set, but the difference in the second metal layer length between it and the tenth trace also satisfies the L′ value.

[0045] It should be noted that Figure 1 The number of traces, length, width, and spacing between adjacent traces shown in the figure are for reference only and should be set according to circuit design specifications and requirements during actual production. Figure 1 Indicated by the solid black area, Figure 1 For the leftmost trace in the COF shown, the length of the second metal layer 20 is the same as the length of the first metal layer 10, that is, the first metal layer of the trace cannot be directly observed from the top view. Figure 1 The first metal layer 10 of the leftmost trace is not marked, but this does not mean that the trace does not have the first metal layer 10.

[0046] Figure 2 Shown Figure 1 Schematic diagram of the cross-sectional structure at the AA′ position. Figure 2 As shown, in addition to the metal layer used for routing, the COF also includes a flexible PI substrate layer 30 for setting the metal layer, and a solder resist layer 40 for metal layer packaging, wherein the solder resist layer 40 includes a first solder resist layer 41 and a second solder resist layer 42, which are respectively used to package the first metal layer 10 and the second metal layer 20. Figure 2 The cross-sectional structure is one of the ones that can be realized when actually manufacturing a flip chip film. In this case, the first metal layer 10 is disposed on the first surface of the base layer 30 ( Figure 2 The first solder resist layer 41 is arranged on the side of the first metal layer 10 away from the base layer 30 (ie Figure 2 The second metal layer 20 is disposed on the second surface of the base layer, and the second surface is the surface opposite to the first surface (ie Figure 2 The second solder resist layer 42 is disposed on the side of the second metal layer 20 away from the base layer 30 (ie Figure 2 below the second metal layer).

[0047] At this time, the first metal layer 10 and the second metal layer 20 are connected through the via 50. Figure 2 As shown in the shaded area, the vias 50 can be drilled from the second surface after the first metal layer 10 is completed, and then the second metal layer 20 is formed. The material used to make the second metal layer 20 is connected to the first metal layer 10 through the vias 50, so that the first metal layer 10 and the second metal layer 20 of the same routing can be used to transmit the same signal. It should be understood that the number of vias 50 in a routing can be set according to the length of the second metal layer 20. Generally, vias are drilled at both ends of the second metal layer 20 to achieve connectivity between the first metal layer 10 and the second metal layer 20.

[0048] Figure 3 The figure shows a second cross-sectional structure that can be achieved during actual COF fabrication. In this case, the first metal layer 10 is disposed on the first surface of the base layer 30, and the first solder resist layer 41 is disposed on the side of the first metal layer 30 away from the base layer 30. The second metal layer 20 is disposed on the side of the first solder resist layer 41 away from the first metal layer 10 (i.e., above the first solder resist layer 41), and the second solder resist layer 42 is disposed on the side of the second metal layer 20 away from the first solder resist layer 41. Figure 4The third cross-sectional structure diagram that can be achieved in actual chip-on-film production is shown. In this case, the second metal layer 20 is arranged on the first surface of the base layer 30, and the second solder resist layer 42 is arranged on the side of the second metal layer 20 away from the base layer 30; the first metal layer 10 is arranged on the side of the second solder resist layer 42 away from the second metal layer 20 (i.e., on the upper side of the second solder resist layer 42), and the first solder resist layer 41 is arranged on the side of the first metal layer 10 away from the second solder resist layer 42. At the same time, Figure 3 and Figure 4 The hierarchical structure shown in FIG. 1 is also provided with a via 50 for conducting the first metal layer 10 and the second metal layer 20. Figure 2 The difference between the hierarchical structures shown is that Figure 2 The via hole 50 is made by punching through the base layer 30. Figure 3 and Figure 4 The via hole 50 shown is realized by punching through the first solder resist layer 41 or the second solder resist layer 42 during fabrication.

[0049] based on Figures 2 to 4 The three different flip chip film layer structures shown in the figure have the same actual functions and compensation capacitor effects. The only difference is the process sequence during production. Figure 3 and Figure 4 structure, Figure 2 The structure is simpler to manufacture, and the bonding effect between the metal layer and the base layer is also stronger. Figures 2 to 4 In the production process of each level of the three structures shown, the production processes and preparation materials used can directly use conventional materials in the existing technology. The production size and thickness, especially the wiring width of the metal layer, can also directly use conventional designs. This embodiment will not be described here.

[0050] This embodiment designs a partial double-layer metal layer for the internal wiring of the flip chip film, and sets the second metal layer of different lengths according to the length of the wiring, so that the capacitance of each wiring in the flip chip film is the same, achieving a capacitance compensation effect, and making the charging conditions of each pixel column in the display panel the same, ensuring that the display panel presents a uniform display effect, and improving the user experience.

[0051] The second embodiment of the present disclosure provides a display device, which mainly includes a display panel for presenting an image and a driving unit for driving the generation of a display image, and also includes a chip-on-chip film for realizing communication between the display panel and the driving unit. The chip-on-chip film used in this embodiment is the chip-on-chip film provided in the first embodiment of the present disclosure. By adding a second metal layer of different lengths to the routing of the chip-on-chip film, a compensation capacitor is formed, so that the capacitance value of each routing is the same. Even when a high-frequency refresh rate is achieved, the charging conditions between each pixel column can be guaranteed to be the same, thereby avoiding the occurrence of vertical black areas and other problems that affect the display effect of the picture.

[0052] The display device provided in this embodiment can be a device with display function such as a display screen, a television, a computer or a mobile phone. The display device can also include other units or modules for realizing different functions, such as a power supply module, a touch unit, an audio unit, etc., which can be added according to actual needs and are not limited in this embodiment.

[0053] The above describes in detail multiple embodiments of the present disclosure, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection claimed by the present disclosure.

Claims

1. A COF film having a plurality of traces, each of which comprises at least a first metal layer, for achieving communication between a display panel and a driving unit, characterized in that: The routing lines at least include first-type routing lines, the first-type routing lines further include a second metal layer arranged in parallel with the first metal layer, and the length of the second metal layer in each of the first-type routing lines is inversely proportional to the length of the first metal layer in the first-type routing lines, so that the capacitance value of each of the routing lines is the same; The first metal layer and the second metal layer in the first type of trace are connected through at least one via.

2. The chip-on-film according to claim 1, wherein: The length of the second metal layer of the second trace with the shortest length of the first metal layer is the same as the length of the first metal layer of the second trace The length L1 of the first metal layer of the first trace and the length L2 of the first metal layer of the second trace satisfy the following formula: Wherein, C is the maximum compensation capacitance value, and a is the correlation coefficient between the length of the first metal layer of the wiring of the COF and the capacitance of the wiring.

3. The chip-on-film according to claim 2, wherein: The routings are arranged in sequence according to the length of the first metal layer, and the length differences between the second metal layers in adjacent routings are the same, and the length differences are determined according to the total number of the routings.

4. The chip-on-film according to claim 3, wherein: The length difference is expressed based on the following formula: Wherein, L' is the length difference, and N is the total number of the traces in the chip-on-film.

5. The chip-on-film according to claim 1, wherein: Also includes: a base layer, wherein the first metal layer and / or the second metal layer is disposed on a surface of the base layer; a first solder resist layer, wherein the first solder resist layer is used to encapsulate the first metal layer; A second solder resist layer is used to encapsulate the second metal layer.

6. The chip-on-film according to claim 5, wherein: The first metal layer is arranged on the first surface of the base layer, and the first solder resist layer is arranged on a side of the first metal layer away from the base layer; The second metal layer is arranged on the second surface of the base layer, and the second solder resist layer is arranged on a side of the second metal layer away from the base layer; The second surface is a surface of the base layer opposite to the first surface.

7. The chip-on-film according to claim 5, wherein: The first metal layer is arranged on the first surface of the base layer, and the first solder resist layer is arranged on a side of the first metal layer away from the base layer; The second metal layer is arranged on a side of the first solder resist layer away from the first metal layer, and the second solder resist layer is arranged on a side of the second metal layer away from the first solder resist layer.

8. The chip-on-film according to claim 5, wherein: The second metal layer is arranged on the first surface of the base layer, and the second solder resist layer is arranged on a side of the second metal layer away from the base layer; The first metal layer is arranged on a side of the second solder resist layer away from the second metal layer, and the first solder resist layer is arranged on a side of the first metal layer away from the second solder resist layer.

9. A display device, characterized in that: At least: Display panel; Drive unit; The chip-on-film according to any one of claims 1 to 8, wherein the chip-on-film is used to enable communication between the display panel and the driving unit.

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