Vertical power mosfet based on n-type gallium oxide and p-type diamond and method of manufacturing the same

Abstract

This invention discloses a vertical power MOSFET based on n-type gallium oxide and p-type diamond, including n + -Ga2O3 substrate, n ‑ -Ga2O3 drift layer, p-type diamond matrix, n + Source region, source electrode, gate electrode, and drain electrode, where the drain electrode, n + -Ga2O3 substrate, n ‑ -Ga2O3 drift layer, p-type diamond matrix and n + The source regions are set sequentially from bottom to top; n + A gate slot is formed on the upper surface of the source region, and the gate slot extends to n ‑ - The upper surface or interior of the Ga2O3 drift layer; the interior of the gate trench is coated with a gate dielectric layer, and the gate electrode is disposed inside the gate trench and enclosed by the gate dielectric layer; the source electrode is disposed on the n + The upper surface of the source region, excluding n + The region outside the source region; n ‑ - The doping concentration of the Ga2O3 drift layer is less than n + - Doping concentration of the Ga2O3 substrate. This invention uses p-type diamond instead of the difficult-to-achieve p-type gallium oxide to form the p-type base region, which can enhance the breakdown voltage of MOSFET devices, reduce reverse leakage current, improve thermal conductivity, and increase device reliability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a vertical power MOSFET based on n-type gallium oxide and p-type diamond and a preparation method thereof. BACKGROUND

[0002] Semiconductor devices and application technologies are developing towards high speed and high energy efficiency. The application of traditional Si-based semiconductor devices in high frequency and high energy efficiency is increasingly approaching the physical limit due to the limitations of large on-resistance and high-temperature performance degradation. The third-generation semiconductor material gallium oxide (Ga2O3) has a wider band gap, higher thermal conductivity and greater breakdown field strength. The band gap of beta-Ga2O3 is about 4.9 eV, and the theoretical breakdown field strength can reach 8 MeV / cm. Gallium oxide material also has good electrical conductivity, luminescence characteristics and stable physical and chemical properties, and has broad development prospects in the fields of optoelectronic devices and power devices.

[0003] At present, the power device made of gallium oxide (Ga2O3) material is most commonly seen as a Schottky barrier diode (SBD). However, due to the low barrier height and thin reverse barrier of SBD, breakdown easily occurs on its surface, so the reverse breakdown voltage is relatively low. The reverse leakage current of SBD is large, and the heat generated by the leakage current is larger. The reverse leakage current is a positive temperature characteristic, which is easy to increase sharply with the rise of temperature. Therefore, the significant shortcomings of SBD limit its application in circuits.

[0004] The vertical power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a conduction path perpendicular to the chip surface, a short channel, a large cross-sectional area, and high current-carrying capacity and voltage-withstanding capacity. Meanwhile, it also has the advantages of high working frequency, small driving power, no thermoelectric feedback secondary breakdown, and high linearity of transconductance. In the traditional silicon-based power MOSFET, the current transmission capacity is limited by the contradiction between reducing the on-resistance and increasing the breakdown voltage, so the silicon-based MOSFET cannot fully exert its application potential. Since the Ga2O3 material has a higher critical breakdown field than the Si material, for a given breakdown voltage, a thin and lightly doped drift region is selected, and the on-resistance of the Ga2O3-based MOSFET is smaller, especially for high breakdown voltage, the Ga2O3-based MOSFET is more superior. However, the research on beta-Ga2O3 is mainly on the growth of materials, and beta-Ga2O3 material has a very high hole effective mass, and is easy to introduce oxygen vacancies and defects and other donor levels, so even the undoped gallium oxide material also presents the conduction characteristics of n-type material, and it is very difficult to obtain p-type gallium oxide material. SUMMARY

[0005] In order to improve the problems of the current gallium oxide-based power device mainly based on Schottky diode, such as low reverse bias, large reverse leakage current, and obvious thermal effect, the application provides a vertical power MOSFET based on n-type gallium oxide and p-type diamond and a preparation method thereof. The technical problems to be solved by the application are solved through the following technical scheme:

[0006] The application provides a vertical power MOSFET based on n-type gallium oxide and p-type diamond, which comprises an n + -Ga2O3 substrate layer, an n - -Ga2O3 drift layer, a p-type diamond-based region, an n + source region, a source electrode, a gate electrode and a drain electrode, wherein

[0007] The drain electrode, the n + -Ga2O3 substrate layer, the n - -Ga2O3 drift layer, the p-type diamond-based region and the n + source region are sequentially arranged from bottom to top;

[0008] The n + source region is provided with a gate slot on the upper surface, the gate slot extends to the upper surface or the inside of the n - -Ga2O3 drift layer; the inside of the gate slot is coated with a gate dielectric layer, the gate electrode is arranged in the inside of the gate slot and is wrapped by the gate dielectric layer; and the source electrode is arranged in the n+ The area on the upper surface of the source region other than the gate slot;

[0009] The n - -The doping concentration of the Ga2O3 drift layer is less than that of n + - Doping concentration of the Ga2O3 substrate.

[0010] In one embodiment of the present invention, the n + The source region is n + -Ga2O3 layer, doping concentration of 10 18 ~10 21 cm -3 .

[0011] In one embodiment of the present invention, the n - The doping concentration of the Ga2O3 drift layer is 10. 15 ~10 16 cm -3 The n + The doping concentration of the Ga2O3 substrate is 10. 18 ~10 21 cm -3 .

[0012] In one embodiment of the present invention, the p-type diamond base region is a boron-doped diamond material with a doping concentration of 10. 16 ~10 18 cm -3 .

[0013] In one embodiment of the present invention, the thickness of the p-type diamond base region is 1 to 2 μm.

[0014] In one embodiment of the present invention, the material of the gate dielectric layer is Si3N4, Al2O3, HfO2 or ZrO2.

[0015] Another aspect of the present invention provides a method for fabricating a vertical power MOSFET based on n-type gallium oxide and p-type diamond, comprising:

[0016] S1: Select n + -Ga2O3 substrate and cleaning;

[0017] S2: In the n + -Growing n on the upper surface of the Ga2O3 substrate - -Ga2O3 drift layer, and the n - -The doping concentration of the Ga2O3 drift layer is less than that of n + -Doping concentration of the Ga2O3 substrate;

[0018] S3: In the n -the upper surface of the Ga2O3 drift layer forms a p-type diamond base region;

[0019] S4: depositing an n + -Ga2O3 layer on the upper surface of the Ga2O3 substrate forms an n + source region;

[0020] S5: depositing a gate electrode in the gate trench of the n + -Ga2O3 drift layer; + depositing a source electrode on the upper surface of the n

[0021] S6: etching a gate trench on the upper surface of the n + source region so that the gate trench extends to the n - -Ga2O3 drift layer;

[0022] S7: sequentially depositing a gate dielectric layer and a gate electrode in the gate trench.

[0023] In one embodiment of the present application, the S3 comprises: + -Ga2O3 drift layer; - -Ga2O3 drift layer, comprising:

[0024] The metal-organic chemical vapor deposition process or the hydride vapor phase epitaxy process is used to epitaxially grow an n 18 -Ga2O3 drift layer with a thickness of 80-100 μm and a doping concentration of 10 20 cm -3 + -Ga2O3 drift layer with a thickness of 80-100 μm and a doping concentration of 10 15 cm 16 -3 - -Ga2O3 drift layer.

[0025] In one embodiment of the present application, the S3 comprises:

[0026] The microwave plasma chemical vapor deposition process is used to prepare a boron-doped p-type diamond epitaxial layer on the upper surface of the n - -Ga2O3 drift layer, forming a p-type diamond base region, with a doping concentration of 10 16 cm 18 -3

[0027] In one embodiment of the present application, the S5 comprises:

[0028] The n + ​​​​​The lower surface of the Ga2O3 substrate is deposited with metal to form a drain electrode, the material of the drain electrode is Ti / Au laminated metal, Ti / Al / Ni / Au laminated metal or Ti / Au / W laminated metal, and the thickness is 100-500nm;

[0029] The n + The source electrode pattern is photoetched above the source region and metal is deposited to form the source electrode, and then rapid thermal annealing is performed in a N2 environment at 450-600℃ for 40-60s to form an ohmic contact between the n + The source region and the source electrode form an ohmic contact.

[0030] Compared with the prior art, the present application has the beneficial effects that:

[0031] The present application uses the p-type diamond which is easier to prepare to replace the p-type gallium oxide which is difficult to realize to form the p-type base region of the vertical power MOSFET based on the n-type gallium oxide and the p-type diamond, the p-type diamond has higher thermal conductivity and wider band gap, and the device heat dissipation performance and voltage resistance performance can be improved. The p-type diamond is prepared by boron doping using the MPCVD method, the boron-doped diamond has wide band gap, high carrier mobility, low dielectric constant and excellent heat conduction performance, and has strong oxidation resistance, and the prepared device can work normally in extreme environment. The present application expands the application of gallium oxide and diamond materials in power devices, and improves the problems of the common gallium oxide-based power device, such as poor voltage resistance, large reverse leakage current and poor heat conduction performance.

[0032] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structure schematic diagram of a vertical power MOSFET based on n-type gallium oxide and p-type diamond provided by an embodiment of the present application;

[0034] Figure 2 is a preparation method flow chart of a vertical power MOSFET based on n-type gallium oxide and p-type diamond provided by an embodiment of the present application;

[0035] Figures 3a to 3f is a preparation process schematic diagram of a vertical power MOSFET based on n-type gallium oxide and p-type diamond provided by an embodiment of the present application.

[0036] Explanation of reference signs:

[0037] 1-n + -Ga2O3 substrate layer; 2-n - -Ga2O3 drift layer; 3-p type diamond base region; 4-n +5 - source region; 6 - gate electrode; 7 - drain electrode; 8 - gate trench; 9 - gate dielectric layer. DETAILED DESCRIPTION

[0038] In order to further clarify the technical means and effects taken by the present application to achieve the predetermined object, a vertical power MOSFET based on n-type gallium oxide and p-type diamond and a preparation method thereof according to the present application are described in detail below in combination with the drawings and specific embodiments.

[0039] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the detailed description of the specific embodiments below in combination with the drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined object can be more deeply and specifically understood. However, the attached drawings are provided for reference and illustration only, and are not intended to limit the technical solutions of the present application.

[0040] It should be noted that, in this document, relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by an "including a..." statement does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0041] Embodiment one

[0042] Please see Figure 1 , Figure 1 is a structure schematic diagram of a vertical power MOSFET based on n-type gallium oxide and p-type diamond provided by the embodiment of the present application. The vertical power MOSFET includes n + -Ga2O3 substrate layer 1, n - -Ga2O3 drift layer 2, p-type diamond base region 3, n + source region 4, source electrode 5, gate electrode 6 and drain electrode 7. The drain electrode 7, n + -Ga2O3 substrate layer 1, n - -Ga2O3 drift layer 2, p-type diamond base region 3 and n + source region 4 are sequentially arranged from bottom to top. n - The doping concentration of the n + -Ga2O3 substrate layer 1. The substrate selected in the embodiment is heavily doped n-type gallium oxide (n +-Ga2O3) substrate, n + The doping concentration of the Ga2O3 substrate layer 1 is 10 18 ~ 10 20 cm -3 , and the thickness is 80~120μm. n - - n - The Ga2O3 drift layer 2 is a low-doped n-type gallium oxide (n - -Ga2O3) layer, n - The doping concentration of the Ga2O3 drift layer 2 is 10 15 ~ 10 16 cm -3 , and the thickness is 80~100μm.

[0043] The p-type diamond base region 3 is boron-doped diamond material, and the doping concentration is 10 16 ~ 10 18 cm -3 , and the thickness is 1~2μm; n + The source region 4 is an n + -Ga2O3 layer, and the doping concentration is 10 18 ~ 10 21 cm -3 , and the thickness is 0.3~0.8μm. In this embodiment, the p-type diamond material with higher thermal conductivity is used to prepare the p-type diamond base region, which greatly improves the heat dissipation performance of the device, and also greatly improves the breakdown voltage and power capacity of the device. Compared with the p-type gallium oxide which is difficult to realize, the p-type diamond is easier to prepare, and the high hole mobility of the p-type diamond also improves the switching speed of the device.

[0044] Further, the upper surface of the n + source region 4 is provided with a gate slot 8, and the gate slot 8 extends to the upper surface or inside of the n - -Ga2O3 drift layer 2; the inside of the gate slot 8 is coated with a gate dielectric layer 9, and the gate electrode 6 is arranged inside the gate slot 8 and is wrapped by the gate dielectric layer 9; the source electrode 5 is arranged on the upper surface of the n + source region 4 except the gate slot 8.

[0045] In this embodiment, the gate slot 8 extends to the upper surface of the n - -Ga2O3 drift layer 2, and the material of the gate dielectric layer 9 is Si3N4, Al2O3, HfO2 or ZrO2, and the thickness is 5~20nm. The electrode material of the source electrode 5 and the drain electrode 7 is Ti / Au stacked metal, Ti / Al / Ni / Au stacked metal or Ti / Au / W stacked metal, and the thickness is 100~500nm; the electrode material of the gate electrode 6 is Ni / Au stacked metal, Pt / Au stacked metal or Ni / Pt / Au / Ti stacked metal, and the thickness is 50~300nm.

[0046] This embodiment uses p-type diamond, which is easier to fabricate, to form the p-type base region instead of the difficult-to-achieve p-type gallium oxide. P-type diamond has higher thermal conductivity and a wider bandgap, which can improve the device's heat dissipation and voltage withstand performance. Boron-doped diamond has a wide bandgap, high carrier mobility, low dielectric constant, and excellent thermal conductivity, and it also has strong oxidation resistance, which improves the problems of poor voltage withstand, large reverse leakage current, and poor thermal conductivity of common gallium oxide-based power devices—Schottky diodes.

[0047] Example 2

[0048] Based on Example 1, this example provides a method for fabricating a vertical power MOSFET based on n-type gallium oxide-p-type diamond. For example... Figure 2 , Figures 3a to 3f As shown, the preparation method includes:

[0049] S1: Select n + -Ga2O3 substrate 1 and cleaning.

[0050] Specifically, a doping concentration of 10 was selected. 18 ~10 20 cm -3 Heavily doped n-type gallium oxide (n) with a thickness of 80–120 μm + The substrate (Ga2O3) was cleaned according to standard procedures.

[0051] S2: In the n + -Growing n on the upper surface of Ga2O3 substrate 1 - -Ga2O3 drift layer 2, and the n - -The doping concentration of Ga2O3 drift layer 2 is less than that of n + -Doping concentration of Ga2O3 substrate layer 1.

[0052] Specifically, metal-organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE) processes are used to perform the above-mentioned heavily doped n + -Low-doped n-phase epitaxial growth on one side of Ga2O3 substrate 1 - -Ga2O3 thin film, forming n - -Ga2O3 drift layer 2, such as Figure 3a As shown, n - The thickness of the Ga2O3 drift layer 2 is 80–100 μm, and the doping concentration is 10. 15 ~10 16 cm -3 .

[0053] S3: In the n- The upper surface of the Ga2O3 drift layer 2 forms a p-type diamond-based region 3.

[0054] Specifically, a low-doped n - A boron-doped p-type diamond epitaxial layer is prepared on the Ga2O3 drift layer as a base region of the MOSFET, as shown in FIG. 1. Figure 3b The doping concentration is 10 16 ~ 10 18 cm -3 , and the thickness is 1 ~ 2 μm. Specifically, the main gases for the reaction are methane (CH4), hydrogen (H2) and diborane (B2H6), the mixed gases are introduced into the reaction cavity, and the doping amount of diborane is controlled by controlling the flow of the gases.

[0055] In this embodiment, the p-type diamond is used as the p-type base region, which is easier to prepare than the p-type gallium oxide, and the high hole mobility of the p-type diamond also improves the switching speed of the device.

[0056] S4: n + -Ga2O3 is deposited on the upper surface of the p-type diamond base region 3 to form an n + source region 4.

[0057] Specifically, n + Ga2O3 is deposited on the p-type base region 3, with a doping concentration of 10 18 ~ 10 21 cm -3 , and a thickness of 0.3 ~ 0.8 μm as an n + source region 4, as shown in FIG. 1. Figure 3c

[0058] S5: a drain electrode 7 is deposited on the lower surface of the n + -Ga2O3 substrate 1, and a source electrode 5 is deposited on the upper surface of the n + source region 4.

[0059] Specifically, the drain electrode 7 of the MOSFET device is deposited on the lower surface of the heavily doped n + -Ga2O3 substrate 1. The entire epitaxial material sample is placed in an electron beam evaporation station, and the drain electrode 7 is evaporated on the back surface of the heavily doped n + -Ga2O3 substrate 1. The electrode material is Ti / Au, Ti / Al / Ni / Au or Ti / Au / W stacked metal, with a thickness of 100 ~ 500 nm.

[0060] Subsequently, the n + ​The upper surface of source region 4 is photolithographically patterned with a source electrode and metal is deposited to fabricate source electrode 5. The deposition of source electrode 5 employs the same process as the drain electrode, and the electrode material is also a Ti / Au multilayer metal, Ti / Al / Ni / Au multilayer metal, or Ti / Au / W multilayer metal, with a thickness of 100–500 nm. After the electrode metal evaporates, it undergoes rapid thermal annealing in an N2 environment at 450–600 °C for 40–60 s, to achieve the desired thickness. + An ohmic contact is formed between the source region 4 and the source electrode 5, such as... Figure 3d As shown.

[0061] S6: In the n + A gate groove 8 is etched on the upper surface of the source region, such that the gate groove 8 extends to the n - -The upper surface or interior of the Ga2O3 drift layer 2.

[0062] Specifically, the photolithography and etching process creates a depth equal to the p-type diamond base region 3 and n. + The sum of the depths of the source region 4 and the gate slot 8, such as Figure 3e As shown. This embodiment uses oxygen plasma etching technology, with an upper electrode power of 280W, a lower electrode power of 60W, a chamber pressure of 10mTorr, and an etching rate of 0.75nm / s.

[0063] S7: A gate dielectric layer 9 and a gate electrode 6 are sequentially deposited in the gate trench 8, such as... Figure 3f As shown.

[0064] Specifically, a gate oxide layer dielectric is deposited on the inner surface of the gate trench 8 using metal-organic chemical vapor deposition (MOCVD) technology. The gate dielectric layer 9 can be Si3N4, Al2O3, HfO2, or ZrO2, with a thickness of 5–20 nm.

[0065] Next, gate metal is deposited inside the gate dielectric layer 9 using electron beam evaporation or sputter magnetron sputtering to form the gate electrode 6. The gate metal is a Ni / Au multilayer metal, a Pt / Au multilayer metal, or a Ni / Pt / Au / Ti multilayer metal, with a thickness of 50–300 nm.

[0066] This embodiment employs a vertical power MOSFET structure based on n-type gallium oxide and p-type diamond. Using p-type diamond, which has higher thermal conductivity, as the p-base region significantly improves the device's heat dissipation performance. It also plays a significant role in increasing the device's breakdown voltage and power capacity.

[0067] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A vertical power MOSFET based on n-type gallium oxide and p-type diamond, characterized in that, including n + - a Ga2O3 substrate layer (1), n - - a Ga2O3 drift layer (2), a p-type diamond-based region (3), n + - a source region (4), a source electrode (5), a gate electrode (6) and a drain electrode (7), wherein, said drain electrode (7), said n + - a Ga2O3 substrate layer (1), said n - - a Ga2O3 drift layer (2), said p-type diamond-based region (3) and said n + source region (4) are arranged in this order from bottom to top; the n + The upper surface of the source region (4) is provided with a gate trench (8) extending to the n - The upper surface or the inside of the Ga2O3 drift layer (2); the inside of the gate trench (8) is coated with a gate dielectric layer (9), the gate electrode (6) is arranged in the inside of the gate trench (8) and is wrapped by the gate dielectric layer (9); the source electrode (5) is arranged on the n + The region on the upper surface of the source region (4) except the gate trench (8) the n - - the doping concentration of the Ga2O3drift layer (2) is less than the n + - the doping concentration of the Ga2O3substrate layer (1); The p-type diamond base region (3) is boron-doped diamond material, the doping concentration is 10 16 ~10 18 cm -3 , the thickness of the p-type diamond base region (3) is 1~2 μm; The preparation process of the p-type diamond-based region (3) is: An n - - A boron-doped p-type diamond epitaxial layer is prepared on the upper surface of the Ga2O3 drift layer (2), forming a p-type diamond-based region (3).

2. The n-type gallium oxide and p-type diamond-based vertical power MOSFET of claim 1, wherein, The n + The source region (4) is n + - a Ga2O3 layer with a doping concentration of 10 18 ~10 21 cm -3 .

3. The n-type gallium oxide and p-type diamond-based vertical power MOSFET of claim 1, wherein, The n - The doping concentration of the Ga2O3 drift layer (2) is 10 15 ~10 16 cm -3 The n + The doping concentration of the Ga2O3 substrate layer (1) is 10 18 ~10 21 cm -3 .

4. The n-type gallium oxide and p-type diamond-based vertical power MOSFET of claim 1, wherein, The material of the gate dielectric layer (9) is Si3N4, Al2O3, HfO2 or ZrO2.

5. A method of fabricating a vertical power MOSFET based on n-type gallium oxide and p-type diamond, characterized by, A method for preparing the vertical power MOSFET based on n-type gallium oxide and p-type diamond according to any one of claims 1 to 4, the method comprising: S1: Select n + - Ga2O3substrate and clean; S2: growing an n + - an n - - an n - - a doping concentration of the n + - a doping concentration of the n S3: in the n - - the upper surface of the Ga2O3drift layer forms a p-type diamond-based region; S4: depositing n + -Ga2O3, forming n + source region; S5: depositing a drain electrode on a lower surface of the n + -Ga2O3 substrate, in the n + depositing a source electrode on an upper surface of the source region; S6: etching a gate trench in the upper surface of the n + etching a gate trench in the upper surface of the n - - the upper surface or the interior of the Ga2O3 drift layer S7: sequentially depositing a gate dielectric layer and a gate electrode in the gate slot.

6. The method of producing a vertical power MOSFET based on n-type gallium oxide and p-type diamond according to claim 5, characterized by, on the n + - growing an n - - a Ga2O3 drift layer, comprising: The metal organic chemical vapor deposition process or hydride vapor phase epitaxy process is adopted to epitaxially grow a n-Ga2O3 drift layer with a thickness of 80-100 μm and a doping concentration of 10 18 cm 20 - -3 The n-Ga2O3 substrate has a thickness of 80-120 μm. + -Ga2O3 drift layer with a thickness of 80-100 μm and a doping concentration of 10 15 cm 16 - -3 The n-Ga2O3 substrate has a thickness of 80-120 μm. - -Ga2O3 drift layer with a thickness of 80-100 μm and a doping concentration of 10 -3 cm - - 7. The method of producing a vertical power MOSFET based on n-type gallium oxide and p-type diamond according to claim 5, characterized by, The S3 comprises: An n - A boron-doped p-type diamond epitaxial layer is prepared on the upper surface of the Ga2O3 drift layer to form a p-type diamond-based region, with a doping concentration of 10 16 ~10 18 cm -3 , and a thickness of 1-2 μm.

8. The method of producing a vertical power MOSFET based on n-type gallium oxide and p-type diamond according to claim 5, characterized by, The S5 comprises: In the n + Depositing metal on the lower surface of the Ga2O3 substrate to form a drain electrode, the material of the drain electrode is Ti / Au stacked metal, Ti / Al / Ni / Au stacked metal or Ti / Au / W stacked metal, and the thickness is 100-500 nm; In the n + The source electrode pattern is photoetched above the source region and metal is deposited to form the source electrode, and then rapid thermal annealing is performed in a N2 environment at 450-600℃ for 40-60s to form an ohmic contact between the source region and the source electrode. + In the n

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