Method for manufacturing a semiconductor device

Abstract

The present application aims at providing a technology capable of suppressing peak current at recovery while ensuring pressure resistance. A manufacturing method of a semiconductor device includes the following steps: forming an anode layer and a first semiconductor layer by irradiation or implantation of n-type impurities in a semiconductor substrate having a constant p-type impurity concentration, the anode layer having a constant p-type impurity concentration, the first semiconductor layer having a distribution of n-type impurity concentration, the n-type impurity concentration of a portion of the first semiconductor layer on the anode layer side being lower than the p-type impurity concentration of the anode layer; and forming a second semiconductor layer, the second semiconductor layer being disposed with the first semiconductor layer interposed between the anode layer, the n-type impurity concentration of the second semiconductor layer being higher than the first semiconductor layer and constant.

Description

[0001] This application is a divisional application of Chinese National Application No. 201910155859.2 filed on March 1, 2019 (Semiconductor device and power conversion device), the contents of which are incorporated herein. TECHNICAL FIELD

[0002] The present application relates to a manufacturing method of a semiconductor device having an anode layer. BACKGROUND

[0003] In recent years, in order to improve the performance of a power semiconductor device, a configuration in which a back surface diffusion layer is provided by impurity diffusion from the back surface after a wafer substrate is polished thin has become mainstream. For example, in the technology of Patent Literature 1, after a p-type anode layer is formed by implantation and thermal diffusion of a p-type impurity in an n-type substrate in which the n-type impurity concentration is constant, the wafer substrate is polished to a desired thickness, and a proton is implanted from the back surface side, thereby forming an n-type buffer layer. Also, for example, in the technology of Patent Literature 2, an n-type impurity layer having a higher n-type impurity concentration is formed on the most back surface of a wafer substrate, and a p-type anode layer is formed by implantation and thermal diffusion of a p-type impurity in the wafer substrate. +

[0004] Patent Literature 1: International Publication No. 2016 / 203545

[0005] Patent Literature 2: Japanese Patent No. 5309360

[0006] However, in the above-described technology, in order to ensure the withstand voltage, it is necessary to increase the concentration of the p-type anode layer, and to extend the depletion layer from the p-type anode layer to the n - -type substrate side. However, in the case of such a configuration, there is a problem that the peak current at the time of recovery is large. SUMMARY

[0007] Therefore, the present application has been made in view of the above problems, and it is an object of the present application to provide a technology capable of suppressing the peak current at the time of recovery while ensuring the withstand voltage.

[0008] The manufacturing method of a semiconductor device according to the present application includes the steps of: forming an anode layer and a first semiconductor layer in a semiconductor substrate in which the p-type impurity concentration is constant, by irradiation or implantation of an n-type impurity, the p-type impurity concentration of the anode layer being constant, the n-type impurity concentration of the first semiconductor layer having a distribution, the n-type impurity concentration of a portion of the first semiconductor layer on the anode layer side being lower than the p-type impurity concentration of the anode layer; and forming a second semiconductor layer, the second semiconductor layer being disposed with the first semiconductor layer interposed therebetween with respect to the anode layer, the n-type impurity concentration being higher than the first semiconductor layer and being constant.

[0009] EFFECT OF THE INVENTION

[0010] ​According to the present application, there are provided: an anode layer whose p-type impurity concentration is constant; and a first semiconductor layer whose n-type impurity concentration has a distribution. According to such a structure, it is possible to set a pn junction composed of the anode layer and the first semiconductor layer at a deep position from the surface and the back surface side of the semiconductor substrate. Therefore, it is possible to suppress the peak current at the time of recovery while ensuring the withstand voltage. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a cross-sectional view showing the structure of a related semiconductor device.

[0012] Figure 2 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1.

[0013] Figure 3 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2.

[0014] Figure 4 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3.

[0015] Figure 5 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 4.

[0016] Figure 6 is a graph for explaining the characteristics of a semiconductor device according to Embodiment 4.

[0017] Figure 7 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 5.

[0018] Figure 8 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 6.

[0019] Figure 9 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 7.

[0020] Figure 10 is a block diagram showing the structure of a power conversion system in which a power conversion device according to Embodiment 8 is applied.

[0021] EXPLANATION OF REFERENCE NUMERALS

[0022] 1p - type anode layer, 2n - type layer, 3n + type layer, 4, 5p - type layer, 6p type layer, 8 end layer, 201 main conversion circuit, 203 control circuit. DETAILED DESCRIPTION

[0023] <RELATED SEMICONDUCTOR DEVICE>

[0024] Before describing the semiconductor device according to the embodiment of the present invention, a semiconductor device related thereto (referred to as a “related semiconductor device”) will be described.

[0025] Figure 1 This diagram shows the cross-sectional structure of a related semiconductor device, along with the corresponding net doping concentration, doping profile, and electric field strength. The net doping concentration is the effective concentration corresponding to the difference between the actual n-type impurity concentration and the actual p-type impurity concentration.

[0026] Figure 1 The related semiconductor device comprises a p-type anode layer 21, an n - type layer 22, n-type layer 23, n + type layer 24. By making the n type impurity concentration constant on one side - The p-type substrate is polished appropriately, and the p-type anode layer 21, the n-type layer 23, and the n-type layer 24 are selectively formed by impurity diffusion. + Type layer 24, the n - The remaining part of the substrate is used as n - In such a structure, it is necessary to extend the depletion layer from the p-type anode layer 21 to the n-type anode layer 22. - The concentration of the p-type anode layer 21 is increased by increasing the p-type layer 22 side. However, with this configuration, there is a problem of a large peak current during recovery. In contrast, the semiconductor device according to the embodiment of the present invention described below can solve this problem.

[0027] <Implementation Method 1>

[0028] Figure 2 1 is a diagram showing the cross-sectional structure of the semiconductor device according to the first embodiment of the present invention, and the corresponding net doping concentration, doping distribution, and electric field strength. Figure 2 The semiconductor device can be applied to, for example, RFC diode (Relaxed Field of Cathode Diode), RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor), etc.

[0029] Figure 2 The semiconductor device has a p-type anode layer. - type anode layer 1, n-type semiconductor layer 1 - type layer 2, n as the second semiconductor layer + Type layer 3. In addition, in this embodiment 1, p - The anode layer 1 is located on the surface side of the semiconductor substrate.+ The type layer 3 is located on the back side of the semiconductor substrate. The material of the semiconductor substrate can be, for example, silicon (Si), or a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. In addition, each layer can also be called a region.

[0030] In the following, the n-type impurity concentration and the p-type impurity concentration are described as net doping concentrations unless otherwise indicated as actual impurity concentrations.

[0031] In p - In the n-type anode layer 1, the p-type impurity concentration is constant. - The n-type layer 2 has a distribution of n-type impurity concentration. - p in type 2 - The n-type impurity concentration of the portion on the anode layer 1 side is higher than that of the - The p-type impurity concentration of the n-type anode layer 1 is low. - The n-type impurity concentration in all parts of the type layer 2 is higher than that in the p - The p-type anode layer 1 has a low p-type impurity concentration.

[0032] n + Type 3 is with p - n-type anode layer 1 is sandwiched between - Type layer 2 is configured. + Type layer 3, n-type impurity concentration ratio n - The profile layer 2 is high and constant.

[0033] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0034] First, prepare a semiconductor substrate with a constant actual p-type impurity concentration, and grind the semiconductor substrate to the desired thickness. After that, irradiate or inject protons or electron beams with a maximum energy of about 10MeV into the semiconductor substrate, and then perform a heat treatment process on the semiconductor substrate under the conditions of a temperature of 350-500°C and a time of 30-300 minutes. As a result, the donor-modified layer is formed in a deeper part of the semiconductor substrate. Here, the actual n-type impurity concentration of the donor-modified layer is set to offset the actual p-type impurity concentration of the semiconductor substrate. As a result, an n-type net doping concentration is formed that is lower than the p-type net doping concentration of the semiconductor substrate. - Type layer 2, semiconductor substrate and n - The part of the type layer 2 that is not donor-like and located on the surface side becomes p - Type anode layer 1. Then, by 1E14 ~ 1E17 [1 / cm 2Phosphorus is ion-implanted into the entire back surface of the semiconductor substrate, and the semiconductor substrate is heat-treated to form a constant concentration of n + Type layer 3. At this time, p - The net doping concentration of the anode layer 1 is, for example, 1×10 12 ~1×10 14 [1 / cm 3 ],n + The net doping concentration of the type layer 3 is, for example, 1×10 18 ~1×10 20 [1 / cm 3 ].

[0035] The semiconductor device according to the first embodiment configured as described above includes: - Type anode layer 1, the p-type impurity concentration of which is constant; and n - Type layer 2, its concentration gradient is relatively gentle. According to such a structure, it is possible to - Type anode layer 1 and n - The pn junction formed by the type layer 2 is provided at a deep position (eg, Figure 2 Therefore, it is possible to reduce the distance from the p to the p while ensuring the withstand voltage. - Type anode layer 1 to n - The hole injection of the type layer 2 reduces the peak current Irr during recovery. In addition, due to the adjustment of the concentration gradient of n - In addition, by having a high and constant n-type impurity concentration n + The type layer 3 can achieve two effects: suppressing unnecessary extension of the depletion layer during recovery and reducing ohmic contact resistance.

[0036] <Implementation Method 2>

[0037] Figure 3 This figure shows the cross-sectional structure of a semiconductor device according to a second embodiment of the present invention, along with the corresponding net doping concentration and doping profile. Hereinafter, the same reference numerals are assigned to the same or similar components as those described above, with the description focusing on the different components.

[0038] In this second embodiment, n - n in type 2 + The n-type impurity concentration of the portion on the type layer 3 side is higher than that of the p - The p-type impurity concentration of the anode layer 1 is high. Furthermore, a gradient is given to the concentration so that the n - The n-type impurity concentration of the type layer 2 increases with the change from p -n-type anode layer 1 is oriented toward n + The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side.

[0039] According to the semiconductor device of Embodiment 2 thus configured, the same effects as those of Embodiment 1 can be obtained. In addition, in Embodiment 2, since the n-type layer 2 is divided into the portion on the p-type anode layer 1 side and the portion on the p-type layer 3 side by the p-type layer 4 in the potential floating state, the time and the speed taken for the depletion at the time of recovery can be adjusted. - Since the n-type layer 2 is divided into the portion on the p-type anode layer 1 side and the portion on the p-type layer 3 side by the p-type layer 4 in the potential floating state, the time and the speed taken for the depletion at the time of recovery can be adjusted.

[0040] <Embodiment 3>

[0041] Figure 4 is a view showing a cross-sectional structure of a semiconductor device according to Embodiment 3 of the present application, and a net doping concentration and a doping distribution corresponding thereto. Hereinafter, the same or similar structural elements among structural elements according to Embodiment 3 will be designated by the same reference numerals, and a different structural element will mainly be described.

[0042] In Embodiment 3, the p-type layer 4 is added to the structure of Embodiment 1 as a third semiconductor layer. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. + The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side. Figure 4

[0043] According to the semiconductor device of Embodiment 3 thus configured, the same effects as those of Embodiment 1 can be obtained. In addition, in Embodiment 3, by the p-type layer 4 in the potential floating state, the time and the speed taken for the depletion at the time of recovery can be adjusted. - The p-type layer 4 is added to the structure of Embodiment 1. The p-type layer 4 is provided in the n-type layer 2 so as to divide the n-type layer 2 into a portion on the p-type anode layer 1 side and a portion on the p-type layer 3 side.

[0044] <Embodiment 4>

[0045] Figure 5 is a view showing a cross-sectional structure of a semiconductor device according to Embodiment 4 of the present application, and a net doping concentration and a doping distribution corresponding thereto. Hereinafter, the same or similar structural elements among structural elements according to Embodiment 4 will be designated by the same reference numerals, and a different structural element will mainly be described. In addition, Figure 5The net doping concentration and doping distribution of are the net doping concentration and doping distribution at line AA. The net doping concentration and doping distribution at line BB are the same as those in the first embodiment and the like.

[0046] In the fourth embodiment, the p-type semiconductor layer as the third semiconductor layer - The molded layer 5 is added to the structure of the first embodiment. - Type 5 relative to n - Type layer 2 is configured with n + Type layer 3 on the same side as n + The type layer 3 is arranged adjacent to each other. - Type layer 5, with p - Similar to the p-type anode layer 1, the p-type impurity concentration is constant.

[0047] According to the semiconductor device according to the fourth embodiment configured in this manner, the same effects as those of the first embodiment can be obtained. In addition, in the fourth embodiment, holes are injected from the back side at the time when the depletion layer reaches the back side during the recovery operation, thereby improving the oscillation resistance. Figure 6 As shown, by + The area of ​​the mold layer 3 relative to the total area (n + Type 3 and p - By adjusting the ratio of the area of ​​the type layer 5 to the power loss during recovery and the magnitude of the forward voltage VF, a semiconductor device can be realized that achieves a balance between the power loss during recovery and the magnitude of the forward voltage VF.

[0048] <Implementation Method 5>

[0049] Figure 7 This figure shows the cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention, as well as the corresponding net doping concentration and doping profile. Hereinafter, the same reference numerals are assigned to the same or similar components as those described above, and the description will focus on the different components.

[0050] In the fifth embodiment, a p-type layer 6 is added as a fourth semiconductor layer to the structure of the first embodiment. The p-type layer 6 is - Type anode layer 1 is arranged on the n - On the opposite side of the p-type layer 2. Moreover, in the p-type layer 6, the p-type impurity concentration is higher than that of the p-type layer 2. - The p-type anode layer 1 is high and has a distribution. Specifically, the p-type layer 6 has a - type anode layer 1 and the p-type impurity concentration is close to p - The concentration gradient of the p-type impurity concentration of the p-type anode layer 1 is shown in FIG. 1 . In addition, the maximum value of the net doping concentration of the p-type layer 6 is, for example, 1×10 15 ~1×10 18[1 / cm 3 ], n + The net doping concentration of the p-type layer 3 is, for example, 1 x 10 18 ~ 1 x 10 20 [1 / cm 3 ]. The depth of the p-type layer 6 is, for example, less than or equal to 3 μm, and the depth of the n + The depth of the p-type layer 3 is, for example, less than or equal to 1 μm.

[0051] According to the semiconductor device related to this Embodiment 5 thus configured, the same effects as Embodiment 1 can be obtained. In addition, in Embodiment 5, the ohmic contact resistance on the surface side of the semiconductor substrate can be reduced.

[0052] <Embodiment 6>

[0053] Figure 8 is a view showing the cross-sectional structure of the semiconductor device related to Embodiment 6 of the present application. Hereinafter, the same reference numerals are given to the structural elements similar or identical to those described above among the structural elements related to Embodiment 6, and only the different structural elements will be described.

[0054] In Embodiment 6, the n - type layer 2 is provided not only on the n - type layer 3 side of the p + type anode layer 1 but also on the end side of the p - type anode layer 1. The n - type layer 7 is provided between the n + type layer 2 and the n - type layer 3. The end layer 8 is provided on the n - type layer 2 on the end side of the p - type anode layer 1. Further, in the end layer 8, the p-type impurity concentration is constant as in the p - type anode layer 1.

[0055] Further, the semiconductor device related to Embodiment 6 is formed by the same manufacturing method as the manufacturing method described in Embodiment 1. For example, the n - type layer 2 is formed so as to partially cancel the p - type anode layer 1, and the end layer 8 is formed so as to partially cancel the n - type layer 2.

[0056] According to the semiconductor device related to Embodiment 6 thus configured, the same effects as Embodiment 1 can be obtained. In addition, in Embodiment 6, the hole injection to the end region can be limited by the end layer 8. Therefore, the endurance of the safe operating area (SOA) at the time of recovery can be improved. Further, the anode layer and the end layer are made p -The p-type semiconductor layer is not limited to this, and can be a p-type semiconductor layer.

[0057] <Embodiment 7>

[0058] Figure 9 is a diagram showing a cross-sectional structure of a semiconductor device to which Embodiment 7 of the present application is applied. Hereinafter, the same reference numerals are given to the structural elements similar or identical to those described above among the structural elements to which Embodiment 7 of the present application is applied, and only different structural elements will be mainly described.

[0059] In Embodiment 7, the p-type semiconductor layer 5 described in Embodiment 4 is added to the structure of Embodiment 6. According to the semiconductor device to which Embodiment 7 of the present application is thus configured, the effects described in Embodiment 4 and the effects described in Embodiment 6 are obtained. - Figure 5 ) of the p-type semiconductor layer 5 described in Embodiment 4 is added to the structure of Embodiment 6. According to the semiconductor device to which Embodiment 7 of the present application is thus configured, the effects described in Embodiment 4 and the effects described in Embodiment 6 are obtained.

[0060] <Embodiment 8>

[0061] The power conversion device to which Embodiment 8 of the present application is applied is a power conversion device provided with a main conversion circuit having the semiconductor device to which any one of Embodiments 1 to 7 is applied. The semiconductor device described above is not limited to the semiconductor device of a specific power conversion device, but hereinafter, as Embodiment 8, a case where the semiconductor device to which any one of Embodiments 1 to 7 is applied is applied to a three-phase inverter will be described.

[0062] Figure 10 is a block diagram showing a structure of a power conversion system in which the power conversion device to which Embodiment 8 of the present application is applied is applied.

[0063] Figure 10 The power conversion system shown in FIG. 8 is configured of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a direct-current power supply, and supplies direct-current power to the power conversion device 200. The power supply 100 can be configured of various power supplies, for example, can be configured of a direct-current system, a solar cell, a storage battery, or can be configured of a rectification circuit connected to an alternating-current system, an AC / DC converter. In addition, the power supply 100 can be configured of a DC / DC converter that converts direct-current power output from the direct-current system into prescribed power.

[0064] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, and converts direct-current power supplied from the power supply 100 into alternating-current power, and supplies the alternating-current power to the load 300. As shown in FIG. 8, the power conversion device 200 is configured of a plurality of semiconductor devices 210, 220, and 230. Figure 10 ​As shown, the power conversion device 200 includes a main conversion circuit 201 that converts direct-current power into alternating-current power and outputs the alternating-current power, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0065] The load 300 is a three-phase motor that is driven by the alternating-current power supplied from the power conversion device 200. Further, the load 300 is not limited to a specific use and is a motor mounted on various electric devices, for example, and is used as a motor for a hybrid automobile, an electric automobile, a railway vehicle, an elevator, or an air conditioning device.

[0066] Details of the power conversion device 200 will be described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown) and converts direct-current power supplied from the power supply 100 into alternating-current power by switching the switching elements to be on and off, and supplies the alternating-current power to the load 300. The specific circuit structure of the main conversion circuit 201 is various, but the main conversion circuit 201 related to the present embodiment 8 is a 2-level three-phase full-bridge circuit and can be configured by six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. At least any one of each switching element and each freewheeling diode of the main conversion circuit 201 is configured by the semiconductor module 202 to which the semiconductor device related to any of the above-described embodiments 1 to 7 is applied. The six switching elements are connected in series two by two to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, and W phase) of the full-bridge circuit. Further, the output terminals of each upper and lower arm, that is, three output terminals of the main conversion circuit 201 are connected to the load 300.

[0067] In addition, the main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element, but the drive circuit can be built into the semiconductor module 202, and the structure can also include a drive circuit separate from the semiconductor module 202. The drive circuit generates a drive signal that drives the switching elements of the main conversion circuit 201 and supplies the drive signal to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit outputs a drive signal that causes the switching elements to be in an on state and a drive signal that causes the switching elements to be in an off state to the control electrodes of each switching element in accordance with a control signal from the control circuit 203 described later. In the case where the switching elements are maintained in an on state, the drive signal is a voltage signal (on signal) that is greater than or equal to the threshold voltage of the switching elements, and in the case where the switching elements are maintained in an off state, the drive signal is a voltage signal (off signal) that is less than or equal to the threshold voltage of the switching elements.

[0068] The control circuit 203 controls the switching elements of the main conversion circuit 201 to supply desired electric power to the load 300. Specifically, the control circuit 203 calculates the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state, based on the electric power that should be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by PWM (Pulse Width Modulation) control that modulates the on time of the switching elements in correspondence with the voltage that should be output. Also, the control circuit 203 outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201, so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each timing. The drive circuit outputs the on signal or the off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

[0069] In the power conversion device according to the above-described Embodiment 8, since the semiconductor device according to any one of Embodiments 1 to 7 is applied to at least any one of the switching elements and the freewheeling diode of the main conversion circuit 201, the peak current at the time of recovery can be suppressed while the withstand voltage is ensured.

[0070] In the above-described Embodiment 8, an example in which the semiconductor device according to any one of Embodiments 1 to 7 is applied to a 2-level three-phase inverter is described, but Embodiment 8 is not limited to this, and can be applied to various power conversion devices. In Embodiment 8, the semiconductor device according to any one of Embodiments 1 to 7 is provided as a 2-level power conversion device, but can be a 3-level or a multi-level power conversion device, and can be applied to a single-phase inverter in the case where electric power is supplied to a single-phase load. In addition, in the case where electric power is supplied to a DC load or the like, the semiconductor device can be applied to a DC / DC converter or an AC / DC converter.

[0071] In addition, the power conversion device according to Embodiment 8 is not limited to the case where the load is a motor, and for example, can be used as a power supply device for an electric discharge machine, a laser machine, or an induction heating cooker, a non-contact power supply system, and can be used as a power conditioner for a solar power generation system, an electric storage system, or the like.

[0072] Furthermore, the present application can freely combine each embodiment within the scope of the present application, and appropriately modify or omit each embodiment.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: An anode layer and a first semiconductor layer are formed on a semiconductor substrate having a constant p-type impurity concentration by irradiating or implanting n-type impurities, wherein the p-type impurity concentration of the anode layer is constant, the n-type impurity concentration of the first semiconductor layer is not constant but has a distribution, and the n-type impurity concentration of a portion of the first semiconductor layer on the anode layer side is lower than the p-type impurity concentration of the anode layer; and A second semiconductor layer is formed. The second semiconductor layer is arranged with the anode layer with the first semiconductor layer interposed therebetween, and has a higher and more constant n-type impurity concentration than the first semiconductor layer.

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