A buried non-oxidized aperture VCSEL epitaxial structure and its preparation process

Abstract

The present invention provides an epitaxial structure of a buried non-oxidized aperture VCSEL, belonging to the technical field of novel semiconductor lasers, comprising a substrate; a MOCVD deposition buffer layer, a first distributed Bragg reflector, a resonant cavity, a second distributed Bragg reflector, and an ohmic contact layer are sequentially disposed on the substrate. The resonant cavity, the second distributed Bragg reflector, and the ohmic contact layer are all III-V compound materials. A mesa including a quantum well layer is formed on the top surface of the resonant cavity; the epitaxial structure further includes a homogeneous semi-insulating layer, and the homogeneous semi-insulating layer wraps around the outer peripheral surface of the mesa. The homogeneous semi-insulating layer is Al x Ga 1‑x As layer or InP layer. In the present invention, the homogeneous semi-insulating layer regrown by the second epitaxy is buried around the resonant cavity. The semi-insulating layer regrown by the second epitaxy and the epitaxial layer in contact with it are homogeneous materials, with fewer surface defects and no difference in thermal expansion coefficient at the contact interface, enabling better epitaxial crystal quality and improving device reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and more specifically to an epitaxial structure of a buried non-oxidized aperture VCSEL and a preparation process thereof. Background Art

[0002] The thermal properties of vertical-cavity surface-emitting lasers (VCSELs) are very important to achieve continuous emission from the chip at room temperature.

[0003] At present, most VCSEL chips use an oxide confinement structure, that is, a layer of AlGaAs or AlAs of a certain thickness is inserted between the quantum well and the upper DBR (distributed Bragg reflector). The AlGaAs layer with a high Al content reacts with H2O at high temperature to convert into native aluminum oxide. Since aluminum oxide is an insulator, it can achieve good electrical confinement. At the same time, the high refractive index difference between aluminum oxide (refractive index of about 1.7) and semiconductor (refractive index of about 3.0) also provides good optical confinement, which can enable VCSEL to achieve extremely low threshold continuous emission. However, the thermal conductivity of the aluminum oxide layer (0.7W / (m•K)) is lower than that of the semiconductor (about 20-50W / (m•K)), which reduces the heat conduction inside the chip and increases the thermal resistance. Therefore, the maximum output power and modulation bandwidth of the oxide aperture VCSEL are fundamentally limited due to early thermal roll-off. In addition, the oxide layer is closely adjacent to the active area. Due to the difference in thermal expansion coefficients, internal strain is formed when the chip is working. The internal temperature rises, and the strain field will push point defects and dislocations to migrate to the active area, eventually leading to chip failure, thereby reducing the reliability of the chip.

[0004] From the perspective of manufacturing yield, during the oxidation process, point defects and dislocations will be generated at the interface between the oxide layer and the semiconductor, and the thermal expansion coefficients of the oxide layer and the semiconductor are different, which makes the oxidation process usually very difficult to control, the process window is ultra-narrow, and the oxide layer-semiconductor interface is prone to cracking or peeling after the oxidation process. In addition, the lateral geometry and size of the oxidation aperture are difficult to control, and lead to changes in the size of the oxidation aperture within and between chips. In the current mature commercial manufacturing process, the absolute change in the oxidation aperture within and between chips is at least 1μm, which limits the manufacturing yield, especially the manufacturing yield of small-aperture chips. Therefore, VCSELs with traditional oxidation apertures face many problems in actual production environments: laser performance and reliability issues related to thermal conduction; and manufacturability issues related to the controllability of the oxidation aperture.

[0005] The Japanese invention patent with the publication number TW229338B discloses a surface-emitting semiconductor laser, which is mainly a semiconductor laser that can emit light in a vertical direction toward a semiconductor substrate, and has: an optical resonator, a pair of reflectors with different reflectivities and a plurality of semiconductor layers located therebetween, and at least the contact layer and the coating layer of the semiconductor layer are formed into one or more columns; a II-VI compound semiconductor crystal film layer buried in the columnar semiconductor layer to the surrounding; an electrode on the light-emitting side is formed by contacting a part of the contact layer, and an opening is provided at a position opposite to a range of more than 10% and less than 90% of the surface area of ​​the contact layer in a range including the contact layer to the geometric center, and a light-emitting side reflector of the pair of reflectors is formed in the opening. The II-VI compound semiconductor crystal film layer can use a semiconductor crystal film layer that combines two, three or four elements of Zn, Cd, Hg of the II group elements and O, S, Se, Te of the VI group elements. In addition, the semiconductor layer that constitutes the resonator is preferably a III-V group compound semiconductor crystal film layer, and GaAs, GaAlAs, GaAsP, InGaP, InGaAxP, etc. can be used.

[0006] This patent buries II-VI compound semiconductors around columnar III-V surface-emitting semiconductors to achieve optical and electrical confinement. This method of growing II-VI compounds on III-V semiconductors is heteroepitaxial, which is difficult and can produce at least 1e5 / cm -2 The defect density is too high to be used as epitaxial wafers for laser chips in high-reliability fields such as communications. At the same time, since the current needs to be injected from the top contact layer to the slender pillars in the active area, the resistance of this VCSEL is much greater than that of the traditional oxide aperture VCSEL, which affects the performance of the VCSEL. Summary of the invention

[0007] In view of the above problems existing in the prior art, an object of the present invention is to provide a vertical cavity surface emitting laser epitaxial structure and a preparation process thereof.

[0008] The present invention adopts the following technical solution:

[0009] An epitaxial structure of a buried non-oxidized aperture VCSEL, the epitaxial structure comprising a substrate, on which an MOCVD deposited buffer layer, a first distributed Bragg reflection layer, a resonant cavity, a second distributed Bragg reflection layer and an ohmic contact layer are sequentially arranged, the top surface of the resonant cavity forms a table including a quantum well layer, the resonant cavity, the second distributed Bragg reflection layer and the ohmic contact layer are all made of III-V group compound materials; the epitaxial structure also comprises a homogeneous semi-insulating layer, the homogeneous semi-insulating layer is wrapped around the outer peripheral surface of the table, the thickness of the homogeneous semi-insulating layer is greater than the distance from the quantum well to the second distributed Bragg reflection layer; the homogeneous semi-insulating layer is Al x Ga 1-x As layer or InP layer; the doping atoms of the homogeneous semi-insulating layer include one of Fe, Ti, Ti+Zn, Ti+Cd, Ti+Hg, V, Cr, Mn, Co, Ni, Au, Rh, Hf, Zr, Ru, Cu, Os, O, In, Sb or any combination thereof.

[0010] In a preferred embodiment, the homogeneous semi-insulating layer is obtained by a second epitaxial growth through a mesa etching process, and the mesa hole diameter specification range is 2-100 µm.

[0011] In a preferred embodiment, the substrate is GaAs or InP; the GaAs or InP is N- or P-type doped and the doping concentration is 10 18 Order of magnitude; the doping atoms for N-type doping include Si, Te, S, and Se, and the doping atoms for P-type doping include C, Mg, Zn, and Be.

[0012] In a preferred embodiment, the resonant cavity is composed of a confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, and a symmetric confinement layer, wherein the upper and middle parts of the first waveguide layer, the quantum well layer, the second waveguide layer, and the symmetric confinement layer form the table.

[0013] Furthermore, the doping type of the confinement layer is consistent with the doping type of the substrate, while the doping type of the symmetric confinement layer is opposite to the doping type of the substrate.

[0014] In a preferred embodiment, the second waveguide layer material is GaAs, AlGaAs, and InP; the quantum well layer material is GaInAs / GaAs, GaInAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlGaInAs / AlGaAs, InGaAsP / AlGaAs, AlGaInP / GaAs, InAsP / InGaAsP, InGaAsP / InGaAsP, InAlGaAs / InAlGaAs, GaAsSb / GaAs, AlGaInAs / InP, and InGaAsP / InP; the symmetric confinement layer material is GaAs, AlGaAs, or InP; the second distributed Bragg reflection layer is AlGaAs / GaAs, AlAs / GaAs, InGaAlAs / InP, InGaAsP / InP, or AlGaInAs / AlInAs; and the ohmic contact layer material is GaAs, InGaAs, or InP.

[0015] In a preferred embodiment, the first distributed Bragg reflector layer and the second distributed Bragg reflector layer are both formed by periodically stacking two or more materials.

[0016] In a preferred embodiment, the second distributed Bragg reflection layer is composed of a periodic stack of a high refractive index material and a low refractive index material, wherein the high refractive index material is Al doped with Si / C and a gradient aluminum composition. x Ga 1-x As layer, the Al component gradient range is 10%-30%; the low refractive index material is Al doped with Si / C and the aluminum component gradient x Ga 1-x As layer, the Al component gradient range is 90%-60%. x Ga 1-x As material can reduce the potential barrier at the heterojunction interface, which helps to reduce the series resistance of DBR and thus improve the conversion efficiency of the chip.

[0017] In a preferred embodiment, the ohmic contact layer is P-doped, and the doping concentration is 10 19 -10 20 The epitaxial structure adopts a P-type substrate and an N-type distributed Bragg reflection layer as the light-emitting surface, or adopts an N-type substrate and a P-type distributed Bragg reflection layer as the light-emitting surface.

[0018] The present invention also provides a process for preparing an epitaxial structure of a buried non-oxidized aperture VCSEL, comprising the following steps: (1) depositing a buffer layer, a first distributed Bragg reflector layer, and a resonant cavity in sequence on a substrate by MOCVD; (2) forming a resonant cavity etching mask SiNx or SiO2 by an enhanced plasma chemical vapor deposition method, photolithography, and reactive ion etching process, and then forming a table with a certain aperture and depth by inductively coupled plasma etching and wet etching of the resonant cavity; (3) utilizing the selective growth characteristics of the SiNx or SiO2 mask, using MOCVD to perform a second epitaxial growth of a homogeneous semi-insulating layer buried around the table; (4) removing the resonant cavity etching mask SiNx or SiO2 by BOE; (5) performing a third epitaxial growth of a second distributed Bragg reflector layer and an ohmic contact layer by MOCVD.

[0019] It can be seen from the above description of the present invention that, compared with the prior art, the present invention has the following advantages:

[0020] 1. The present invention uses a second epitaxially grown homogeneous semi-insulating layer to be buried on the outer peripheral surface of the top table of the resonant cavity. The homogeneous semi-insulating layer is Al x Ga 1-x The As layer or InP layer, the resonant cavity, the second distributed Bragg reflector layer and the ohmic contact layer are all group III-V compound materials. Since the homogeneous semi-insulating layer grown by the second epitaxial regrowth and the epitaxial layer in contact with it are homogeneous materials (group III-V compounds), there are fewer surface defects between the contact interfaces and there is no difference in thermal expansion coefficients, which can achieve better epitaxial crystal quality and ensure its high reliability.

[0021] 2. The present invention adopts a homogeneous semi-insulating layer to bury the active area structure to reduce parasitic capacitance, which is helpful for bandwidth and high-speed modulation.

[0022] 3. The present invention does not involve a wet oxidation process (the source of defects and strains), ensuring that the active area is defect-free and strain-free, and has better reliability.

[0023] 4. The present invention replaces the oxidation aperture with a homogeneous semi-insulating layer. Similar to the oxidation aperture, the homogeneous semi-insulating layer has excellent electrical confinement. The use of a low-refractive index semi-insulating material can simultaneously achieve good optical confinement. Getting rid of the oxidation process is equivalent to getting rid of the biggest yield killer in VCSEL production.

[0024] 5. The aperture of the VCSEL of the present invention is defined by a photolithography machine or a more precise method, so the aperture size control and uniformity can be within + / - 0.1 micron or better, which is crucial for higher yield and future high-speed VCSEL applications.

[0025] 6. In the preparation process of the present invention, a homogeneous semi-insulating layer is buried around the resonant cavity, and then a second distributed Bragg reflector layer and an ohmic contact layer are grown above the resonant cavity to replace the oxidized aperture. Compared with the oxide layer of the traditional oxidized aperture VCSEL, the homogeneous semi-insulating layer provides a better thermal conductivity, which can improve the thermal characteristics of the VCSEL, and is conducive to better high-temperature performance and reliability of the chip. Compared with the comparative patent with publication number TW229338B, which uses a heterogeneous epitaxial layer buried around the resonant cavity, the second DBR layer and the ohmic contact layer, resulting in a much larger series resistance than the traditional oxidized aperture VCSEL, the innovative design of this patent helps to further reduce the device resistance, achieve a series resistance similar to that of the traditional oxidized aperture VCSEL, and improve the photoelectric conversion efficiency of the device.

[0026] Further advantages of the present invention will be further reflected in detail in the specific embodiments section in conjunction with the drawings of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the main structure of the epitaxial structure of a buried non-oxidized aperture VCSEL of the present invention.

[0028] Figure 2 yes Figure 1 Schematic diagram of the layered structure of the epitaxial structure of a buried non-oxidized aperture VCSEL.

[0029] Figure 3 yes Figure 2 Schematic diagram of the layered structure of the resonant cavity in the epitaxial structure of a buried non-oxidized aperture VCSEL.

[0030] Figure 4 The present invention is a schematic diagram of a specific method for preparing the epitaxial structure of a buried non-oxidized aperture VCSEL.

[0031] Figure 5 It is a schematic diagram comparing the current distribution when a homogeneous semi-insulating layer is buried around the resonant cavity and when a homogeneous semi-insulating layer is buried around the resonant cavity, the second DBR layer and the ohmic contact layer. DETAILED DESCRIPTION

[0032] The invention is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0033] It should be pointed out that the descriptions of the drawings in the specification of various embodiments of the present invention are merely schematic and do not represent all specific structures.

[0034] The structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size shall fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0035] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0036] Figure 1 First, the main layered structure of the epitaxial structure of a buried non-oxidized aperture VCSEL according to one embodiment of the present invention is generally introduced.

[0037] exist Figure 1 In FIG. 1 , a non-oxidized aperture low thermal resistance vertical cavity surface emitting laser epitaxial structure is shown.

[0038] The epitaxial structure of the present invention comprises a substrate 1, on which a buffer layer 2, a first DBR 3, and a resonant cavity 4 are sequentially deposited, and then a mesa etching process is performed and then a second epitaxial growth homogeneous semi-insulating layer 5 is performed. The depth of the mesa etching should be greater than the distance from the quantum well to the surface of the epitaxial wafer.

[0039] Finally, a second DBR layer 6 and an ohmic contact layer 7 are grown on the resonant cavity buried by the homogeneous semi-insulating layer 5 .

[0040] More specifically, the epitaxial wafer is subjected to mesa etching, the etching depth is to the N-type confinement layer, the mesa aperture is 4 µm, and then a second epitaxial regrowth of a homogeneous semi-insulating layer is performed, the homogeneous semi-insulating layer is a Cr-doped AlGaAs material, and finally a second DBR layer 6 and an ohmic contact layer 7 are grown above the resonant cavity buried in the homogeneous semi-insulating layer.

[0041] exist Figure 1 In the DBR, it means distributed Bragg reflector, which is a reflector used in waveguides. When light passes through different media, it will be reflected at the interface. The magnitude of the reflectivity is related to the magnitude of the refractive index between the media. Therefore, if we stack films with different refractive indices interactively and periodically, when light passes through these films with different refractive indices, the light reflected from each layer will constructively interfere due to the change in phase angle, and then combine with each other to obtain strong reflected light.

[0042] If the number of multi-film layers becomes very large, and the difference in the refractive index n1, n2, n3, etc. of the thin films becomes very small, the light is like traveling in the same medium, and the reflection coefficient becomes very small. The interference effect caused by the multiple interference of light is very obvious, so the selection of wavelength is very sensitive. When using a grating-like situation, such a periodic structure is called a distributed Bragg reflector.

[0043] exist Figure 1 In the embodiment, the buffer layer 2 is a MOCVD deposited buffer layer.

[0044] Metal-organic chemical vapor deposition system (MOCVD) is a chemical vapor deposition (CVD) process that uses metal organic compounds as source materials. It uses metal organic sources and process gases involved in the reaction to deposit in a low-pressure and high-temperature reaction chamber to grow chips with complex doping layers.

[0045] exist Figure 1 Based on Figure 2 . Figure 2 More specifically given Figure 1 A hierarchical architecture diagram of the epitaxial structure of the high-speed vertical cavity surface emitting laser.

[0046] exist Figure 2 In the embodiment, a MOCVD-deposited buffer layer 2, a first distributed Bragg reflector layer 3, a resonant cavity 4, a second distributed DBR layer 6 and an ohmic contact layer 7 are sequentially arranged on a substrate. The top surface of the resonant cavity 4 forms a table 401 including a quantum well layer.

[0047] Furthermore, the epitaxial structure further includes a homogeneous semi-insulating layer 5. The homogeneous semi-insulating layer 5 is epitaxially grown for the second time by a mesa etching process and wraps around the outer peripheral surface of the mesa 401. The thickness of the homogeneous semi-insulating layer 5 is greater than the distance from the quantum well to the second distributed Bragg reflector.

[0048] As a specific implementation method, the homogeneous semi-insulating layer 5 is Al x Ga 1-x As or InP, and the doping atoms include but are not limited to Fe, Ti, Ti+Zn, Ti+Cd, Ti+Hg, V, Cr, Mn, Co, Ni, Au, Rh, Hf, Zr, Ru, Cu, Os, O, In, Sb or a combination thereof.

[0049] The substrate 1 may preferably be made of GaAs or InP, which is N- or P-type doped and has a doping concentration of 10 18 Order of magnitude.

[0050] The buffer layer 2 may preferably be made of GaAs or InP, which is consistent with the material of the substrate 1 .

[0051] The buffer layer 2 has a thickness range of 200-300 nm and can be N-type or P-type doped. The doping type is consistent with the substrate and the doping concentration is 10 18 The N-type doping atoms include but are not limited to Si, Te, S, and Se, and the P-type doping atoms include but are not limited to C, Mg, Zn, and Be.

[0052] The first DBR layer 3 is preferably formed by periodically stacking two or more materials of a certain thickness.

[0053] The material of the first DBR layer 3 can be a semiconductor material such as AlGaAs / GaAs, AlAs / GaAs, InGaAlAs / InP, InGaAsP / InP, AlGaInAs / AlInAs, and the lattice constant of the material matches the lattice constant of the substrate material.

[0054] The first DBR layer 3 preferably has a period pair number of 10-30 half-integer pairs.

[0055] Preferably, the first DBR layer 3 may be N-type or P-type doped, the doping type is consistent with the substrate 1, and the doping concentration is within 10 18 Order of magnitude.

[0056] The ohmic contact layer 7 may be made of GaAs, InGaAs or InP. Preferably, the ohmic contact layer 7 is P-doped, and the doping concentration is between 10 19 -10 20 Order of magnitude.

[0057] Preferably, the thickness of the ohmic contact layer 7 is in the range of 100-300 nm.

[0058] In the first embodiment, the substrate 1 is a GaAs substrate doped with Si, and the doping concentration is 10 18 The buffer layer is a Si-doped GaAs layer with a doping concentration of 10 18 The first DBR is a high refractive index / low refractive index / high refractive index / low refractive index... / high refractive index structure, and the high refractive index material is Si-doped Al 0.1 Ga 0.9 As layer, the low refractive index material is Si-doped Al 0.9 Ga 0.1 As layer. Si-doped Al 0.1 Ga 0.9 The As layer thickness is 77 nm and the doping concentration is 10 18 Order of magnitude; Si-doped Al 0.9 Ga0.1 The As layer thickness is 88 nm and the doping concentration is 10 18 Order of magnitude.

[0059] The second DBR layer 6 has a high refractive index / low refractive index / high refractive index / low refractive index... / high refractive index structure, and the high refractive index material is C-doped Al 0.1 Ga 0.9 As layer, the low refractive index material is C-doped Al 0.9 Ga 0.1 As layer. C-doped Al 0.1 Ga 0.9 The thickness of the As layer is 77 nm and the doping concentration is 10 18 Order of magnitude; C-doped Al 0.9 Ga 0.1 The thickness of the As layer is 88 nm and the doping concentration is 10 18 Order of magnitude.

[0060] In the second embodiment, the substrate 1 is a Zn-doped GaAs substrate, and the doping concentration is 10 18 The buffer layer is a C-doped GaAs layer with a doping concentration of 10 18 The first DBR layer 6 is a high refractive index / low refractive index / high refractive index / low refractive index... / high refractive index structure, and the high refractive index material is C-doped Al 0.1 Ga 0.9 As layer, the low refractive index material is C-doped Al 0.9 Ga 0.1 As layer. C-doped Al 0.1 Ga 0.9 The As layer thickness is 77 nm and the doping concentration is 10 18 Order of magnitude; C-doped Al 0.9 Ga 0.1 The As layer thickness is 88 nm and the doping concentration is 10 18 Order of magnitude.

[0061] The second DBR layer 6 has a high refractive index / low refractive index / high refractive index / low refractive index... / high refractive index structure, and the high refractive index material is Si-doped Al 0.1 Ga 0.9 As layer, the low refractive index material is Si-doped Al 0.9 Ga 0.1 As layer. Si-doped Al 0.1 Ga 0.9 The thickness of the As layer is 77 nm and the doping concentration is 10 18 Order of magnitude; Si-doped Al 0.9 Ga 0.1 The thickness of the As layer is 88 nm and the doping concentration is 1018 Order of magnitude.

[0062] In the third embodiment, the first DBR layer 3 and the second DBR layer 6 are both high refractive index / low refractive index / high refractive index / low refractive index ... / high refractive index structures. The high refractive index material is Al doped with Si / C with a gradient aluminum composition. x Ga 1-x As layer, the Al component gradient range is 10%-30%; the low refractive index material is Al doped with Si / C and the aluminum component gradient x Ga 1-x As layer, Al composition gradient range is 90%-60%. High / low refractive index material doped with Si / C concentration is 10 18 Order of magnitude.

[0063] In this embodiment, Al x Ga 1-x As material can reduce the potential barrier at the heterojunction interface, which helps to reduce the series resistance of DBR and thus improve the conversion efficiency of the chip.

[0064] Figure 3 Given Figure 2 Schematic diagram of the layered structure of the resonant cavity in the epitaxial structure of a buried non-oxidized aperture VCSEL.

[0065] exist Figure 3 The resonant cavity length is an integer multiple of half a wavelength. The resonant cavity 4 is composed of a confinement layer 41, a first waveguide layer 42, a quantum well layer 43, a second waveguide layer 44, and a symmetric confinement layer 45. The upper and middle parts of the first waveguide layer 42, the quantum well layer 43, the second waveguide layer 44, and the symmetric confinement layer 45 form a table 401.

[0066] The above-mentioned confinement layer material 41 can be GaAs, AlGaAs, InP, the lattice constant of the material matches the lattice constant of the substrate material, the doping type is consistent with the substrate, and the doping concentration is within 10 17 -10 18 Order of magnitude.

[0067] The materials of the first waveguide layer 42 and the second waveguide layer 44 may be, but are not limited to, GaAs, AlGaAs, and InP, and the lattice constant of the material matches the lattice constant of the substrate material.

[0068] The quantum well layer material 43 may be, but is not limited to, GaInAs / GaAs, GaInAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlGaInAs / AlGaAs, InGaAsP / AlGaAs, AlGaInP / GaAs, InAsP / InGaAsP, InGaAsP / InGaAsP, InAlGaAs / InAlGaAs, GaAsSb / GaAs, AlGaInAs / InP, InGaAsP / InP, and the lattice constant of the material matches the lattice constant of the substrate material. The quantum well layer 43 is preferably placed at the antinode of the resonant cavity standing wave field.

[0069] The material of the symmetric confinement layer 45 may be GaAs, AlGaAs, or InP, and the lattice constant of the material matches the lattice constant of the substrate material.

[0070] The doping type of the symmetric confinement layer 45 is opposite to that of the substrate material, and the doping concentration is 10 17 -10 18 Order of magnitude.

[0071] The second DBR layer 6 is formed by periodically stacking two or more materials with a certain thickness.

[0072] The material of the second DBR layer 6 may be, but is not limited to, AlGaAs / GaAs, AlAs / GaAs, InGaAlAs / InP, InGaAsP / InP, AlGaInAs / AlInAs, and the lattice constant of the material matches that of the substrate material.

[0073] The second DBR layer 6 has a growth pair number of 10-30 half-integer pairs.

[0074] Preferably, the doping type of the doping atoms in the second DBR layer 6 is opposite to that of the substrate material, and the doping concentration is within 10 18 Order of magnitude.

[0075] against Figure 3 Resonant cavity, combined with the introduction of the aforementioned first embodiment, second embodiment and third embodiment, continues to give the introduction of the structural embodiments of the first embodiment, second embodiment and third embodiment related to the resonant cavity.

[0076] In the first embodiment, the resonant cavity 4 comprises Si-doped Al from bottom to top. 0.6 Ga 0.4 As confinement layer 41, Al 0.3 Ga 0.7 As first waveguide layer 42, GaAs 0.8 P 0.2 In0.28 Ga 0.72 As is the barrier / well / barrier / well / barrier quantum well layer 43 of the well, Al 0.3 Ga 0.7 As second waveguide layer 44, C-doped Al 0.6 Ga 0.4 As confinement layer 45. The Si-doped Al 0.6 Ga 0.4 The As confinement layer thickness is 70 nm and the doping concentration is 10 17 Order of magnitude, Al 0.3 Ga 0.7 The thickness of the first waveguide layer of As is 160 nm, and that of GaAs 0.8 P 0.2 The thickness of the barrier layer is 15 nm, In 0.28 Ga 0.72 As thickness is 9 nm, Al 0.3 Ga 0.7 The thickness of the second waveguide layer is 167 nm, and the Al doped with C 0. 6Ga 0.4 The As confinement layer thickness is 70 nm and the doping concentration is 10 17 Order of magnitude.

[0077] In this embodiment, after the resonant cavity 4 is grown, the epitaxial wafer is subjected to mesa etching, the etching depth is to the N-type confinement layer, and the mesa aperture is 4 μm. Then, a second epitaxial growth is performed to re-grow a homogeneous semi-insulating layer, and the homogeneous semi-insulating layer is a Cr-doped AlGaAs material. Finally, a second DBR layer 6 and an ohmic contact layer 7 are grown above the resonant cavity 4 buried in the homogeneous semi-insulating layer.

[0078] In the second embodiment, the resonant cavity 4 comprises C-doped Al from bottom to top. 0.6 Ga 0.4 As confinement layer 41, Al 0.3 Ga 0.7 As first waveguide layer 42, GaAs 0.8 P 0.2 In 0.28 Ga 0.72 As is the barrier / well / barrier / well / barrier quantum well layer 43 of the well, Al 0.3 Ga 0.7 As second waveguide layer 44, Si-doped Al 0.6 Ga 0.4 As confinement layer 45. The C-doped Al 0.6 Ga 0.4 The As confinement layer thickness is 70 nm and the doping concentration is 10 17 Order of magnitude, Al 0.3 Ga 0.7The thickness of the first waveguide layer of As is 160 nm, and that of GaAs 0.8 P 0.2 The thickness of the barrier layer is 15 nm, In 0.28 Ga 0.72 As thickness is 9 nm, Al 0.3 Ga 0.7 The thickness of the second waveguide layer of As is 167 nm, and the Si-doped Al 0. 6Ga 0.4 The As confinement layer thickness is 70 nm and the doping concentration is 10 17 Order of magnitude.

[0079] At this time, after the resonant cavity 4 is grown, the epitaxial wafer is subjected to mesa etching, the etching depth is to the P-type confinement layer, and the mesa hole diameter is 4 μm. Then, a second epitaxial growth is performed to re-grow a homogeneous semi-insulating layer, which is a Cr-doped AlGaAs material. Finally, a second DBR layer 6 and an ohmic contact layer 7 are grown above the resonant cavity buried in the homogeneous semi-insulating layer.

[0080] In this embodiment, a P-type substrate is used and an N-type DBR is used as the light emitting surface, which is beneficial to reducing the resistance during current injection, thereby further improving the threshold current and conversion efficiency of the chip.

[0081] In the third embodiment, Al x Ga 1-x As material can reduce the potential barrier at the heterojunction interface, which helps to reduce the series resistance of DBR and thus improve the conversion efficiency of the chip.

[0082] In this embodiment, after the resonant cavity 4 is grown, the epitaxial wafer is subjected to table etching, and the etching depth reaches the N / P type confinement layer, and the table aperture is 4 µm. Then, a second epitaxial regrowth of a homogeneous semi-insulating layer 5 is performed, and the homogeneous semi-insulating layer 5 is a CrAlGaAs-doped material. The homogeneous semi-insulating layer grown by the second epitaxial regrowth is buried around the resonant cavity. The homogeneous semi-insulating layer grown by the second epitaxial regrowth and the epitaxial layer in contact with it are homogeneous materials, and there are fewer surface defects between the contact interfaces and no difference in thermal expansion coefficients, so that better epitaxial crystal quality can be achieved. Similar to the oxidized aperture, the buried structure of the homogeneous semi-insulating layer has an excellent electrical confinement effect, and the low-refractive-index semi-insulating material can simultaneously achieve good optical confinement.

[0083] It should be noted that, although the above three embodiments are introduced separately, the corresponding parts thereof can be combined as needed without violating the basic principles of the present invention.

[0084] The present invention provides a specific preparation process for the epitaxial structure of a buried non-oxidized aperture VCSEL, such as Figure 4 As shown, the following steps are included:

[0085] (a) The buffer layer, the first DBR layer, and the resonant cavity are deposited on the substrate in sequence using MOCVD.

[0086] (b) The resonant cavity etching mask SiNx is formed by enhanced plasma chemical vapor deposition, photolithography and reactive ion etching processes, and then the resonant cavity is etched by inductively coupled plasma etching and wet etching to form a table with a certain aperture and depth.

[0087] (c) Utilizing the selective growth characteristics of the SiNx mask, MOCVD is used to perform a second epitaxial growth of a homogeneous semi-insulating layer buried around the mesa.

[0088] (d) Removal of the cavity etching mask SiNx by BOE.

[0089] (e) The second DBR layer and the ohmic contact layer are grown epitaxially for the third time using MOCVD.

[0090] From the above embodiments, it can be seen that in the prior art, the thermal conductivity of the aluminum oxide layer in the traditional oxidation aperture process (0.7 W / (m•K)) is lower than that of the semiconductor (about 20-50 W / (m•K)), which reduces the heat conduction inside the chip and increases the thermal resistance.

[0091] like Figure 5 As shown, Figure 5 (a) with Figure 5 (b) The current distribution diagrams of the case where the homogeneous semi-insulating layer is buried around the resonant cavity and the case where the homogeneous semi-insulating layer is buried around the resonant cavity, the second DBR layer and the ohmic contact layer. For the two buried structures with the same mesa diameter, Figure 5 (a) Compared to Figure 5 (b) has a smaller resistance.

[0092] It can be seen from the above embodiments of the present invention that the homogeneous semi-insulating layer grown by the second epitaxial regrowth is buried around the resonant cavity, and the homogeneous semi-insulating layer grown by the second epitaxial regrowth and the epitaxial layer in contact with it are homogeneous materials, and there are fewer surface defects between the contact interfaces and no difference in thermal expansion coefficients, so that better epitaxial crystal quality can be achieved. At the same time, the homogeneous semi-insulating layer burying the active area structure can reduce parasitic capacitance, which is helpful for bandwidth and high-speed modulation. In addition, the table aperture is defined by a photolithography machine or a more precise method, so the aperture size control and uniformity can be within + / -0.1 micron or better, which is crucial for higher yield and future high-speed VCSEL applications. The method of using a homogeneous semi-insulating layer buried around the resonant cavity and then growing a second DBR layer 6 and an ohmic contact layer 7 above the resonant cavity replaces the oxidation aperture. The excellent thermal conductivity of the semi-insulating layer can improve the thermal characteristics of the VCSEL, which is conducive to achieving continuous emission of the chip at room temperature, and compared with the use of a homogeneous semi-insulating layer buried around the resonant cavity, the second DBR layer and the ohmic contact layer, it helps to further reduce the device resistance.

[0093] Therefore, through the above-mentioned low thermal resistance high-speed vertical cavity surface emitting laser epitaxial structure with electrical and optical confinement of the present invention, the homogeneous semi-insulating layer grown by the second epitaxial regrowth is used to replace the oxidized aperture. The excellent thermal conductivity of the homogeneous semi-insulating layer can improve the thermal characteristics of the VCSEL, which is conducive to achieving continuous emission of the chip at room temperature. At the same time, based on the replacement of the oxidized aperture by the homogeneous semi-insulating layer, similar to the oxidized aperture, the homogeneous semi-insulating layer has an excellent electrical confinement effect. The use of a low refractive index semi-insulating material can simultaneously achieve good optical confinement, and getting rid of the oxidation process is equivalent to getting rid of the biggest yield killer in VCSEL production. Specifically, the use of a homogeneous semi-insulating layer to bury the active area structure can reduce parasitic capacitance, which is conducive to bandwidth and high-speed modulation. The wet-free oxidation process (the source of defects and strain) used in the manufacturing process of the above-mentioned structure ensures that the active area is defect-free and strain-free, and has better reliability.

[0094] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. An epitaxial structure of a buried non-oxidized aperture VCSEL, the epitaxial structure comprising a substrate, characterized in that: An MOCVD-deposited buffer layer, a first distributed Bragg reflection layer, a resonant cavity, a second distributed Bragg reflection layer and an ohmic contact layer are sequentially arranged on the substrate, the top surface of the resonant cavity forms a table including a quantum well layer, and the resonant cavity, the second distributed Bragg reflection layer and the ohmic contact layer are all made of III-V compound materials; The epitaxial structure further includes a homogeneous semi-insulating layer, the homogeneous semi-insulating layer is wrapped around the outer peripheral surface of the table, and the thickness of the homogeneous semi-insulating layer is greater than the distance from the quantum well to the second distributed Bragg reflection layer; The homogeneous semi-insulating layer is Al x Ga 1-x As layer or InP layer; The doping atoms of the homogeneous semi-insulating layer include one of Fe, Ti, Ti+Zn, Ti+Cd, Ti+Hg, V, Cr, Mn, Co, Ni, Au, Rh, Hf, Zr, Ru, Cu, Os, O, In, Sb or any combination thereof; The epitaxial structure preparation process comprises the following steps: (1) depositing a buffer layer, a first distributed Bragg reflection layer, and a resonant cavity in sequence on a substrate by MOCVD; (2) Forming a resonant cavity etching mask SiNx or SiO2 by enhanced plasma chemical vapor deposition, photolithography and reactive ion etching processes, and then forming a table with a certain aperture and depth by inductively coupled plasma etching and wet etching of the resonant cavity; (3) Utilizing the selective growth characteristics of SiNx or SiO2 mask, MOCVD is used to perform a second epitaxial growth of a homogeneous semi-insulating layer buried around the mesa; (4) Removing the resonant cavity etching mask SiNx or SiO2 by BOE; (5) The second distributed Bragg reflection layer and the ohmic contact layer are grown epitaxially for the third time using MOCVD.

2. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 1, characterized in that: The homogeneous semi-insulating layer is obtained by performing a second epitaxial growth through a mesa etching process, and the mesa hole diameter specification range is 2-100µm.

3. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 1, characterized in that: The substrate is GaAs or InP; the GaAs or InP is N- or P-type doped and the doping concentration is 10 18 Order of magnitude; the N-type doping atoms include Si, Te, S, and Se, and the P-type doping atoms include C, Mg, Zn, and Be.

4. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 1, characterized in that: The resonant cavity is composed of a confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, and a symmetric confinement layer, wherein the upper and middle parts of the first waveguide layer, the quantum well layer, the second waveguide layer, and the symmetric confinement layer form the table.

5. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 4, characterized in that: The doping type of the confinement layer is consistent with the doping type of the substrate, and the doping type of the symmetric confinement layer is opposite to the doping type of the substrate.

6. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 4, characterized in that: The second waveguide layer material is GaAs, AlGaAs, and InP; the quantum well layer material is GaInAs / GaAs, GaInAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlGaInAs / AlGaAs, InGaAsP / AlGaAs, AlGaInP / GaAs, InAsP / InGaAsP, InGaAsP / InGaAsP, InAlGaAs / InAlGaAs, GaAsSb / GaAs, AlGaInAs / InP, and InGaAsP / InP; the symmetric confinement layer material is GaAs, AlGaAs or InP; the second distributed Bragg reflection layer is AlGaAs / GaAs, AlAs / GaAs, InGaAlAs / InP, InGaAsP / InP or AlGaInAs / AlInAs; the ohmic contact layer material is GaAs, InGaAs or InP.

7. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 1, characterized in that: The first distributed Bragg reflector layer and the second distributed Bragg reflector layer are both formed by periodically stacking two or more materials.

8. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 7, characterized in that: The second distributed Bragg reflection layer is composed of a periodic stack of a high refractive index material and a low refractive index material, wherein the high refractive index material is Al doped with Si / C and a gradient aluminum composition. x Ga 1-x As layer, the Al component gradient range is 10%-30%; the low refractive index material is Al doped with Si / C and the aluminum component gradient x Ga 1-x In the As layer, the gradient range of Al component is 90%-60%.

9. The epitaxial structure of a buried non-oxidized aperture VCSEL according to claim 1, characterized in that: The ohmic contact layer is P-doped, and the doping concentration is 10 19 -10 20 The epitaxial structure adopts a P-type substrate and an N-type distributed Bragg reflection layer as the light-emitting surface, or adopts an N-type substrate and a P-type distributed Bragg reflection layer as the light-emitting surface.

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