Motor drive control device, fan, and motor drive control method

Abstract

The present invention provides a motor drive control device capable of determining the driving state of a motor. The motor drive control device (1) is characterized in that it comprises: a plurality of motor drive circuits (10_1, 10_2) for controlling the power supply to the motor based on a drive control signal (Sca1, Sca2) for controlling the rotation speed of the motor, and outputting an FG signal (fg1, fg2) having a period corresponding to the actual rotation speed of the motor; a synthetic signal generating circuit (21) for inputting each of the FG signals output from the motor drive circuits and generating a synthetic signal obtained by synthesizing the input signals; and a drive control circuit (20) for generating the drive control signal based on a speed instruction signal indicating a target rotation speed of the motor and outputting the drive control signal to each of the motor drive circuits, wherein the FG signals output from each of the motor drive circuits have a phase difference with each other.

Description

Technical Field

[0001] The present invention relates to a motor drive control device, a fan and a motor drive control method, for example, to a motor drive control device having two systems of drive circuits. Background Art

[0002] Conventionally, a motor driving device that drives a single-phase motor has been disclosed (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-77543 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, sometimes the drive circuit of the motor drive control device fails and cannot drive the motor. For example, in the application of driving the motor in a specified rotation direction (positive direction), when the motor cannot be driven as described above, when an external force acts to force the motor to rotate in the direction opposite to the specified rotation direction (reverse rotation), problems may sometimes occur.

[0008] For example, in the case where a fan (hereinafter also referred to as a "fan motor") is driven by a motor drive control device, when a drive circuit of the motor drive control device fails due to a fuse in the power line blowing, etc., the fan motor stops. In this case, for example, when wind flows into the fan motor along with the action of other fan motors used together with the fan motor, the fan motor may reverse. For example, in the case where a plurality of fan motors are used for cooling a device surrounded by a housing, when a fan motor reverses as described above, it may cause the internal pressure of the device to decrease and reduce the cooling function, thereby affecting the function of the device. Therefore, it is necessary to keep the fan motor rotating in the forward direction as much as possible.

[0009] As a method for solving the above-mentioned problem, a motor drive control device is provided with two drive circuits so that even if one drive circuit fails, the fan motor can continue to be driven using the other drive circuit.

[0010] However, as described above, when two systems of drive circuits are provided in the motor drive control device, as long as it is possible to determine whether the motor is in a normal driving state, whether the motor is locked, or which drive circuit has a fault, etc., appropriate control corresponding to the state of the fan motor can be performed, which is very convenient.

[0011] An object of the present invention is to provide a motor drive control device capable of determining a driving state of a motor.

[0012] Solutions for solving problems

[0013] A motor drive control device according to a representative embodiment of the present invention is characterized in that it comprises: a plurality of motor drive circuits, which control the power supply to the motor based on a drive control signal for controlling the rotational speed of the motor and output an FG signal having a period corresponding to the actual rotational speed of the motor; a synthetic signal generating circuit, which inputs the FG signals output from the motor drive circuits and generates a synthetic signal by synthesizing the input signals; and a drive control circuit, which generates the drive control signal based on a speed instruction signal indicating a target rotational speed of the motor and outputs the drive control signal to each of the motor drive circuits, wherein the FG signals output from each of the motor drive circuits have a phase difference with each other.

[0014] Effects of the Invention

[0015] According to the motor drive control device of the present invention, the drive state of the motor can be determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing the configuration of a fan according to the first embodiment.

[0017] Figure 2 This is a diagram showing the configuration of a synthetic signal generating circuit and its peripheral circuits according to the first embodiment.

[0018] Figure 3 1 is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the first embodiment.

[0019] Figure 4 1 is a timing chart showing the signals fg1 and fg2 and the synthesized signal Si when the motor of the fan according to the first embodiment rotates normally.

[0020] Figure 5 1 is a timing chart showing signals fg1 , fg2 and a synthesized signal Si when an open circuit failure occurs at the terminal FG1 of the motor drive circuit in the fan according to the first embodiment.

[0021] Figure 6 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when a short-circuit failure occurs at the terminal FG1 of the motor drive circuit in the fan according to the first embodiment.

[0022] Fig. 7A 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when the motor is in a locked state in the fan according to the first embodiment.

[0023] Figure 7B 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when the motor is in a locked state in the fan according to the first embodiment.

[0024] Figure 8 This is a flowchart showing the flow of a process for determining a drive state of a fan by the motor drive control device according to the first embodiment.

[0025] Fig. 9 This is a diagram showing the configuration of a fan according to the second embodiment.

[0026] Fig.10 This is a diagram showing the configuration of a synthetic signal generating circuit and its peripheral circuits according to the second embodiment.

[0027] Fig.11 This is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the second embodiment.

[0028] Fig.12 1 is a timing chart showing signals fg1 and fg2 , lock detection signals ld1 and ld2 , and a composite signal Si when the motor of the fan according to the second embodiment rotates normally.

[0029] Fig.13 1 is a timing chart showing signals fg1 and fg2 , lock detection signals ld1 and ld2 , and synthesized signal Si when an open-circuit failure occurs in terminal FG1 of motor drive circuit 10A_1 in the fan of Embodiment 2. FIG.

[0030] Fig.14 1 is a timing chart showing signals fg1 and fg2 , lock detection signals ld1 and ld2 , and synthesized signal Si when a short-circuit failure occurs at terminal FG1 of motor drive circuit 10A_1 in the fan of Embodiment 2. FIG.

[0031] Fig.15 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when the motor is in a locked state in the fan according to the second embodiment.

[0032] Fig.16 This is a flowchart showing the flow of a process for determining a drive state of a fan by the motor drive control device according to the second embodiment.

[0033] Fig.17 It is a diagram showing the structure of a fan according to another embodiment of the present invention.

[0034] Fig.18 It is a diagram showing the structure of a fan according to still another embodiment of the present invention.

[0035] Fig.19 This is a block diagram showing the configuration of a fan according to the third embodiment.

[0036] Fig. 20 This is a block diagram showing the internal configuration of the control circuits 12D_1 and 12D_2 and the synthetic signal generating circuit 21 according to the third embodiment.

[0037] Fig.21 This is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the third embodiment.

[0038] Fig. 22 This is a flowchart showing the flow of a process for determining a drive state of a fan by the motor drive control device according to the third embodiment.

[0039] Fig.23 This is a flowchart showing the flow of a process for determining a drive state of a fan (a first FG failure determination process) by the motor drive control device according to the third embodiment.

[0040] Fig.24 This is a flowchart showing the flow of a process for determining a drive state of a fan (a second FG failure determination process) by the motor drive control device according to the third embodiment.

[0041] Fig.25A This is a flowchart showing the flow of a process for determining a drive state of a fan (third FG failure determination process) by the motor drive control device according to the third embodiment.

[0042] Fig.25B This is a flowchart showing the flow of a process for determining a drive state of a fan (third FG failure determination process) by the motor drive control device according to the third embodiment.

[0043] Fig.25C This is a flowchart showing the flow of a fan drive state determination process (first system one-side failure drive process) by the motor drive control device according to the third embodiment.

[0044] Fig.25D This is a flowchart showing the flow of a fan drive state determination process (second system one-side failure drive process) by the motor drive control device according to the third embodiment.

[0045] Fig.26 It is a timing chart showing the drive control signals Sca1 and Sca2 (terminals SCA1 and SCA2 ), the signals fg1 and fg2 (terminals FG1 and FG2 ), and the synthesized signal Si when the motor drive circuits 10D_1 and 10D_2 are in the normal state and the motor 50 is in the unlocked state.

[0046] Fig. 27It is a timing chart showing the drive control signals Sca1 and Sca2 (terminals SCA1 and SCA2 ), the signals fg1 and fg2 (terminals FG1 and FG2 ), and the synthesized signal Si when the motor drive circuits 10D_1 and 10D_2 are in the normal state and the motor 50 is in the locked state.

[0047] Fig.28 It is a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG failure state caused by an FG short circuit failure.

[0048] Fig.29 It is a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and synthesized signal Si when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG failure state caused by an FG open circuit failure.

[0049] Fig.30 It is a timing diagram showing the driving control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor driving circuit 10D_1 in the normal state is driven on one side when the motor driving circuit 10D_1 in the normal state is in the FG fault state caused by the FG short circuit fault.

[0050] Fig.31 It is a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor drive circuit 10D_1 is driven unilaterally when the motor drive circuit 10D_1 in the FG fault state is in the FG fault state, and when the motor drive circuit 10D_2 is in the normal state.

[0051] Fig.32 It is a timing diagram showing the driving control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor driving circuit 10D_1 in the normal state is driven on one side when the motor driving circuit 10D_1 in the normal state is in the FG fault state caused by the FG open circuit fault.

[0052] Fig.33 This is a block diagram showing the configuration of a fan according to a fourth embodiment.

[0053] Fig.34 12E_1 and 12E_2 and the internal configuration of the synthetic signal generating circuit 21A according to the fourth embodiment.

[0054] Fig.35 1 is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the fourth embodiment.

[0055] Fig.36 This is a block diagram showing the structure of a fan according to another embodiment of the present invention. DETAILED DESCRIPTION

[0056] 1. Overview of implementation methods

[0057] First, a typical embodiment of the invention disclosed in this application will be briefly described. It should be noted that in the following description, as an example, reference numerals on the drawings corresponding to the components of the invention are described with parentheses added.

[0058] [1] A motor drive control device (1, 1A, 1D, 1E) according to a representative embodiment of the present invention is characterized in that it comprises: a plurality of motor drive circuits for controlling the energization of the motor based on a drive control signal for controlling the rotational speed of the motor and outputting an FG signal having a period corresponding to the actual rotational speed of the motor; a synthetic signal generating circuit for inputting the respective FG signals output from the motor drive circuits and generating a synthetic signal by synthesizing the input signals; and a drive control circuit for generating the drive control signal based on a speed instruction signal indicating a target rotational speed of the motor and outputting the drive control signal to the respective motor drive circuits, wherein the FG signals output from the respective motor drive circuits have a phase difference with each other.

[0059] [2] In the motor drive control device (1, 1A) described in [1] above, it is possible that the multiple motor drive circuits include: a first motor drive circuit (10_1, 10A_1), which controls the power supply to the motor based on the drive control signal, and outputs a first FG signal (fg1) having a frequency corresponding to the actual rotational speed of the motor; and a second motor drive circuit (10_2, 10A_2), which controls the power supply to the motor based on the drive control signal, and outputs a second FG signal (fg2) having a frequency corresponding to the actual rotational speed of the motor and a phase shifted relative to the first FG signal, and the synthetic signal generating circuit (21, 21A) synthesizes the first FG signal and the second FG signal to generate the synthetic signal (Si).

[0060] [3] In the motor drive control device (1, 1A) described in [2] above, it is possible that the first FG signal (fg1) and the second FG signal (fg2) are rectangular wave signals having a specified duty cycle, and the synthetic signal generating circuit generates the synthetic signal based on the logical product of the first FG signal and the second FG signal.

[0061] [4] In the motor drive control device (1) described in [3] above, it is possible that the first motor drive circuit (10_1) includes: a first output terminal (FG1) for outputting the first FG signal (fg1); and a first output transistor (Q1) connected between the first output terminal and a first fixed potential (ground voltage GND), the second motor drive circuit (10_2) includes: a second output terminal (FG2) for outputting the second FG signal (fg2); and a second output transistor (Q2) connected between the second output terminal and the first fixed potential, and the synthetic signal generating circuit includes a load (R1), and the load (R1) is connected between a connection point (N1) to which the first output terminal and the second output terminal are commonly connected and a second fixed potential (power supply voltage Vcc) different from the first fixed potential.

[0062] [5] In the motor drive control device (1) described in [3] or [4] above, it is possible that the drive control circuit (20) inputs the synthetic signal (Si), and when the synthetic signal is a signal with a duty cycle corresponding to the phase difference (for example, 90 degrees) between the first FG signal and the second FG signal, it is determined that the motor is driven normally.

[0063] [6] In the motor drive control device (1) described in [5] above, it is possible that the drive control circuit (20) inputs the synthetic signal, and when the synthetic signal is the specified duty cycle, it is determined that either the first motor drive circuit or the second motor drive circuit has an open circuit fault.

[0064] [7] In the motor drive control device (1) described in [5] or [6] above, it is possible that the drive control circuit inputs the synthetic signal, and when the synthetic signal is a specified logical value, it is determined that at least one of the first motor drive circuit and the second motor drive circuit is in a short-circuit fault or the motor is in a locked state.

[0065] [8] In the motor drive control device (1A) described in [2] above, it is possible that the first motor drive circuit (10A_1) outputs a first lock detection signal (ld1), the first lock detection signal (ld1) is a binary signal indicating whether the motor is in a locked state, the second motor drive circuit (10A_2) outputs a second lock detection signal (ld2), the second lock detection signal (ld2) is a binary signal indicating whether the motor is in a locked state, and the synthetic signal generating circuit synthesizes the first FG signal, the second FG signal, the first lock detection signal and the second lock detection signal to generate the synthetic signal.

[0066] [9] In the motor drive control device (1A) described in [8] above, it is possible that the first FG signal (fg1) and the second FG signal (fg2) are rectangular wave signals having a specified duty cycle, and the synthetic signal generating circuit (21A) generates the synthetic signal (Si) based on the logical product of a signal based on the logical product of the first FG signal (fg1) and the second FG signal (fg2) and a signal based on the logical product of the first lock detection signal (ld1) and the second lock detection signal (ld2).

[0067]

[10] In the motor drive control device (1A) described in [9] above, it is possible that the first motor drive circuit (10A_1) includes: a first output terminal (FG1) for outputting the first FG signal (fg1); a second output terminal (LD1) for outputting the first lock detection signal (ld1); a first output transistor (Q1) connected between the first output terminal and a first fixed potential (ground voltage GND); and a second output transistor (Q1A) connected between the second output terminal and the first fixed potential, and the second motor drive circuit (10A_2) includes a third output terminal (FG2) for outputting the second FG signal (fg2); a fourth output terminal (LD2) for outputting the second lock detection signal (ld2); a third output transistor (Q2) connected between the third output terminal (FG2) and the first fixed potential (GND); and a fourth output terminal (LD2) for outputting the second lock detection signal (ld2). D2) and the first fixed potential (GND), the synthetic signal generating circuit (21A) includes: a first load (R1) connected between a first connection point (N1) to which the first output terminal and the third output terminal are commonly connected and a second fixed potential (Vcc) different from the first fixed potential; a second load (R2) connected between a second connection point (N2) to which the second output terminal and the fourth output terminal are commonly connected and the second fixed potential (Vcc); a third load (R3) one end of which is connected to the second fixed potential; a first switch element (SW1) connected between the first fixed potential (GND) and the other end of the third load, the on / off of which is controlled based on the voltage of the first connection point; and a second switch element (SW2) connected between the first fixed potential (GND) and the other end of the third load, the on / off of which is controlled based on the voltage of the second connection point.

[0068]

[11] In the motor drive control device (1A) described in [9] or

[10] above, it is possible that the drive control circuit (20) determines that the motor is driven normally when the composite signal (Si) has a duty cycle corresponding to the phase difference between the first FG signal and the second FG signal.

[0069]

[12] In the motor drive control device (1A) described in

[11] above, it is possible that the drive control circuit (20) determines that either the first motor drive circuit or the second motor drive circuit has an open circuit fault when the synthetic signal (Si) is the specified duty cycle.

[0070]

[13] In the motor drive control device (1A) described in

[12] above, it is possible that when the synthetic signal (Si) is at a first logic level (high level), the drive control circuit (20) determines that either the first motor drive circuit or the second motor drive circuit has a short circuit fault.

[0071]

[14] In the motor drive control device (1A) described in

[13] above, it is possible that the drive control circuit (20) determines that the motor is in a locked state when the synthetic signal (Si) is a second logic level (low level) different from the first logic level.

[0072]

[15] A fan (100, 100A) in a representative embodiment of the present invention may include: a motor drive control device (1, 1A) as described in any one of [2] to

[14] above; and the motor (50) including a coil (80_1) of a first system and a coil (80_2) of a second system, wherein the first motor drive circuit (10_1, 10A_1) controls the energization of the coil (80_1) of the first system, and the second motor drive circuit (10_2, 10A_2) controls the energization of the coil (80_2) of the second system.

[0073]

[16] A fan (100B, 100C) according to a representative embodiment of the present invention may include: a motor drive control device (1, 1A) as described in any one of [2] to

[14] above; and two motors (50B_1, 50B_2) including at least one coil (80B_1, 80B_2), wherein the first motor drive circuit (10A_1) controls the energization of the coil (80B_1) of one of the motors (50B_1), and the second motor drive circuit (10A_2) controls the energization of the coil (80B_2) of the other motor (50B_2).

[0074]

[17] In the motor drive control device (1D, 1E) described in [1] above, it is possible that, when the synthetic signal (Si) indicates a specified logical value, the drive control circuit (20) causes at least one of the multiple motor drive circuits (10D_1, 10D_2, 10E_1, 10E_2) to be converted into a high-level state that cannot output the FG signal (fg1, fg2), and a first determination process is performed based on the synthetic signal at this time. The first determination process determines whether any one of the multiple motor drive circuits is in an FG fault state where the FG signal cannot be output normally, or in a locked state where the motor cannot rotate.

[0075]

[18] In the motor drive control device described in

[17] above, it is possible that each of the motor drive circuits can be converted into a power saving state in which at least a part of the internal circuit thereof stops operating and the output of the FG signal is fixed at a high level. When the composite signal indicates the specified logical value, the drive control circuit converts at least one of the plurality of motor drive circuits into the power saving state and performs the first determination process based on the composite signal at this time.

[0076]

[19] In the motor drive control device described in

[17] or

[18] above, it is possible that each of the motor drive circuits has: an internal power supply circuit (121) that generates and outputs an internal power supply voltage (Vdd); an FG signal generating unit (124) that is configured to be able to operate by power supply from the internal power supply voltage, and to generate and output the FG signal based on a position detection signal (hp, hn) corresponding to the rotational position of the rotor of the motor; and a control unit (122) that controls the supply and cutoff of the internal power supply voltage to the FG signal generating unit, and generates a drive signal (Sd1, Sd2) for energizing the motor based on the drive control signal, and when the synthetic signal indicates the specified logical value, the drive control circuit stops outputting the drive control signal, and when the drive control signal is not input and the FG signal is not switched within a specified period of time, the control unit cuts off the supply of the internal power supply voltage to the FG signal generating unit.

[0077]

[20] In the motor drive control device described in

[19] above, it is possible that, in the first judgment process, when the drive control circuit detects a specified change in the synthetic signal, it is determined that any one of the multiple motor drive circuits is in the FG fault state, and when it is fixed at the specified logical value, it is determined that the motor is in the locked state.

[0078]

[21] In the motor drive control device described in

[20] above, it is possible that, when it is determined that any one of the multiple motor drive circuits is in the FG fault state, the drive control circuit drives the multiple motor drive circuits one by one in sequence, and based on the synthetic signal at this time, performs a second determination process to determine which one of the motor drive circuits is in the FG fault state.

[0079]

[22] In the motor drive control device described in

[21] above, it is possible that the drive control circuit stops outputting the drive control signal for the motor drive circuit determined to be in the FG fault state through the second determination processing, and outputs the drive control signal for the motor drive circuit determined to be in the normal state.

[0080]

[23] In the motor drive control device described in any one of

[17] to

[22] above, it is possible that the FG signal is a rectangular wave signal having a specified duty cycle within a period corresponding to the rotational speed of the motor, and the synthetic signal generating circuit generates the synthetic signal based on the logical product of the FG signals output from each of the motor drive circuits.

[0081]

[24] In the motor drive control device (1E) described in any one of

[17] to

[22] above, it is possible that each of the motor drive circuits (10E_1, 10E_2) outputs a lock detection signal (ld1, ld2) respectively, and the lock detection signal (ld1, ld2) is a binary signal indicating whether the motor is in a locked state, and the FG signal is a rectangular wave signal having a specified duty cycle within a period corresponding to the rotational speed of the motor, and the synthetic signal generating circuit (21A) generates the synthetic signal based on the logical product of a signal (sf12) based on the logical product of the FG signals output from each of the motor drive circuits and a signal (sl11) based on the logical product of the lock detection signals output from each of the motor drive circuits.

[0082]

[25] A fan (100D, 100E) according to a representative embodiment of the present invention is characterized in that it comprises: a motor drive control device (1D, 1E) as described in any one of

[17] to

[24] above; the motor (50, 50B_1, 50B_2); and an impeller (90, 90_1, 90_2) configured to rotate by the rotational force of the motor.

[0083]

[26] A method according to a representative embodiment of the present invention is a motor drive control method based on a motor drive control device (1D, 1E), wherein the motor drive control device (1D, 1E) comprises: a plurality of motor drive circuits (10D_1, 10D_2, 10E_1, 10E_2), which control the energization of the motor (50) based on a drive control signal (Sca1, Sca2) for controlling the rotation speed of the motor (50), and output an FG signal (fg1, fg2) having a period corresponding to the actual rotation speed of the motor; a synthetic signal generating circuit (21, 21A), which inputs each of the FG signals output from the motor drive circuit and generates a synthetic signal (Si) obtained by synthesizing the input signals; and a drive control circuit (20), which generates the drive control signal based on a speed instruction signal (Sc) indicating a target rotation speed of the motor and outputs it to each of the motor drive circuits, and determines the state of the motor and the motor drive circuit based on the synthetic signal. In the present motor drive control method, the FG signals outputted from the respective motor drive circuits have a phase difference with each other. The present motor drive control method is characterized in that it comprises: a first step (S101-S103), in which, when the synthetic signal indicates a specified logical value, the drive control circuit causes at least one of the plurality of motor drive circuits to be converted into a high level state that cannot output the FG signal; and a second step (S104, S105, S108), in which the drive control circuit performs a first determination process based on the synthetic signal in the first step to determine whether any one of the plurality of motor drive circuits is in an FG fault state that cannot normally output the FG signal, or in a locked state that the motor cannot rotate.

[0084] 2. Specific examples of implementation methods

[0085] Hereinafter, specific examples of the embodiments of the present invention will be described with reference to the drawings. It should be noted that in the following description, the same reference numerals are given to the common components in each embodiment, and repeated descriptions are omitted.

[0086] Figure 1 This is a block diagram showing the configuration of the fan according to the first embodiment.

[0087] The fan (fan motor) 100 of the first embodiment is a device that generates wind by rotating an impeller. The fan 100 can be used as one of cooling devices that discharge heat generated inside a device to the outside to cool the inside of the device. For example, in addition to information processing devices such as servers, the fan 100 can also be mounted on machine tools used in an environment where oil mist, cutting chips, smoke, dust, etc. are generated. The fan 100 is, for example, an axial flow fan.

[0088] like Figure 1 As shown, the fan 100 includes a motor 50 , an impeller 90 , position detectors 41_1 and 41_2 , and a motor drive control device 1 .

[0089] In the present embodiment, the motor 50 is, for example, a single-phase brushless motor having two systems of coils 80_1 and 80_2 wound around teeth (not shown). The impeller 90 is configured to be rotatable by the rotational force of the motor 50. For example, the impeller 90 is connected to an output shaft (not shown) of the motor 50.

[0090] The motor drive control device 1 is a device for controlling the rotation of the motor 50. The motor drive control device 1 causes the motor 50 to rotate by causing a current to flow periodically through the single-phase coils 80_1 and 80_2 constituting the motor 50.

[0091] The position detectors 41_1 and 41_2 output position detection signals according to the position of the rotor of the motor 50. The position detectors 41_1 and 41_2 are, for example, Hall elements, which output Hall signals having positive polarity as position detection signals.

[0092] The position detector 41_1 is arranged at a position corresponding to the coil 80_1 of the first system, and outputs a position detection signal to the control circuit 12_1 of the motor drive circuit 10_1 described later. The position detector 41_2 is arranged at a position corresponding to the coil 80_2 of the second system, and outputs a position detection signal to the control circuit 12_2 of the motor drive circuit 10_2 described later. The position detector 41_1 and the position detector 41_2 are arranged at positions where the relative position is π / 2 (90 degrees) in electrical angle, for example.

[0093] The motor drive control device 1 is supplied with a DC power supply voltage Vdc from the outside.

[0094] The motor drive control device 1 is connected to the host device 500. The speed command signal Sc outputted from the host device 500 is inputted to the motor drive control device 1. The motor drive control device 1 drives the motor 50 according to the inputted speed command signal Sc. In addition, the motor drive control device 1 outputs information related to the state of the motor 50 to the host device 500. For example, as described later, the motor drive control device 1 outputs a signal corresponding to the actual rotation speed of the motor 50 and a signal indicating an abnormal state of the motor described later as a state signal So to the host device 500. Thus, the host device 500 can know the rotation state of the motor 50, whether the motor 50 has an abnormality, and the like.

[0095] Specifically, the motor drive control device 1 includes: a plurality of motor drive circuits 10 ; a drive control circuit 20 that controls the operations of the plurality of motor drive circuits 10 ; and a synthetic signal generation circuit 21 .

[0096] In the motor drive control device 1 of the present embodiment, as the plurality of motor drive circuits 10 , for example, two systems of motor drive circuits 10_1 and 10_2 are provided.

[0097] The drive control circuit 20 is a circuit for controlling the drive of the motor 50 via each motor drive circuit 10_1, 10_2. The drive control circuit 20 is composed of, for example, a program processing device (e.g., a microcontroller: MCU), which has hardware elements such as a processor such as a CPU (central processing unit), various memories such as a ROM (random access memory) or a RAM (read-only memory), a timer (counter), an A / D conversion circuit, an input / output I / F circuit, and a clock generation circuit, and each component is connected to each other via a bus or a dedicated line.

[0098] In the present embodiment, the drive control circuit 20 is packaged as one semiconductor device (IC: Integrated Circuit), but the present invention is not limited thereto.

[0099] The drive control circuit 20 generates a drive control signal Sca for controlling the rotation speed of the motor 50 based on the speed command signal Sc, and outputs it to each motor drive circuit 10. Specifically, the drive control circuit 20 generates drive control signals Sca1 and Sca2 based on the speed command signal Sc input from the upper device 500, and provides them to each motor drive circuit 10_1 and 10_2 respectively. It should be noted that the drive control circuit 20 can output a drive control signal and branch it into two lines, so that the drive control signal is provided to the motor drive circuits 10_1 and 10_2. In this case, a switch that invalidates the drive control signal can be set by grounding each drive control signal provided to the motor drive circuits 10_1 and 10_2.

[0100] Here, the speed command signal Sc is a signal indicating the target rotation speed (target rotation speed) of the motor 50, for example, a PWM (pulse width modulation) signal having a duty ratio corresponding to the target rotation speed of the motor. It should be noted that the speed command signal Sc may also be a signal of other forms such as a PFM signal having a frequency corresponding to the target rotation speed.

[0101] Like the speed command signal Sc, the drive control signals Sca1 and Sca2 are signals that indicate a target rotation speed (target rotation speed) of the motor 50 , and are, for example, PWM signals having a duty ratio corresponding to the target rotation speed of the motor.

[0102] In addition, the drive control circuit 20 has a function of controlling the drive of the motor 50 according to the speed command signal Sc from the host device 500, and also has a function of determining whether the fan 100 (the motor 50 and the motor drive circuits 10_1 and 10_2) has an abnormality and outputting the determination result. The drive control circuit 20 determines whether the fan 100 has an abnormality based on the synthetic signal Si generated by the synthetic signal generating circuit 21, and outputs a state signal So indicating the state of the fan 100 to the host device 500 based on the determination result.

[0103] The plurality of motor drive circuits 10 are circuits that control the energization of the motor 50 based on the drive control signal Sca, and output an FG signal having a period corresponding to the actual rotation speed of the motor 50. The FG signals output from the respective motor drive circuits 10 have a phase difference. In the present embodiment, the motor drive circuit 10_1 and the motor drive circuit 10_2 as the plurality of motor drive circuits 10 have, for example, the same circuit configuration.

[0104] The motor driving circuit 10_1 includes a control circuit 12_1 and an inverter circuit (power-on circuit) 15_1 for energizing the coil 80_1 based on the control of the control circuit 12_1. The motor driving circuit 10_2 includes a control circuit 12_2 and an inverter circuit (power-on circuit) 15_2 for energizing the coil 80_2 based on the control of the control circuit 12_2. In this case, the control circuits 12_1 and 12_2 may include inverter circuits 15_1 and 15_2, respectively.

[0105] The motor drive circuits 10_1 and 10_2 each have a fuse 19 connected at one end to the power supply voltage Vdc. In the motor drive circuits 10_1 and 10_2, the power supply voltage Vdc is supplied to the inverter circuits 15_1 and 15_2 and the control circuits 12_1 and 12_2 of the motor drive circuits 10_1 and 10_2 through the fuse 19.

[0106] The inverter circuit 15_1 energizes the coil 80_1 of the motor 50 connected to the output terminals 16_1 and 17_1 based on the drive signal Sd1 output from the control circuit 12_1. Similarly to the inverter circuit 15_1, the inverter circuit 15_2 controls the energization of the coil 80_2 of the motor 50 connected to the output terminals 16_2 and 17_2 based on the drive signal Sd2 output from the control circuit 12_2. The drive signals Sd1 and Sd2 are, for example, PWM (pulse width modulation) signals.

[0107] like Figure 1As shown, the inverter circuits 15_1 and 15_2 are, for example, H-bridge circuits, and have two pairs of series circuits of two switching elements (for example, transistors) arranged at both ends of the power supply voltage Vdc. The connection points between the two switching elements of each series circuit are output terminals 16_1, 17_1, 16_2, and 17_2 for energizing the coils 80_1 and 80_2, respectively. The on / off of each switching element constituting the inverter circuits 15_1 and 15_2 is controlled by the drive signals (PWM signals) Sd1 and Sd2 outputted from the control circuits 12_1 and 12_2, respectively. Thus, the energization of the coil 80_1 connected to the output terminals 16_1 and 17_1 of the inverter circuit 15_1 and the energization of the coil 80_2 connected to the output terminals 16_2 and 17_2 of the inverter circuit 15_2 are controlled, respectively.

[0108] The control circuit 12_1 generates a drive signal Sd1 based on the drive control signal Sca1 provided by the drive control circuit 20 and the position detection signal output from the position detector 41_1, and controls the inverter circuit 15_1. The control circuit 12_2 generates a drive signal Sd2 based on the drive control signal Sca2 provided by the drive control circuit 20 and the position detection signal output from the position detector 41_2, and controls the inverter circuit 15_2.

[0109] For example, the control circuit 12_1 detects the actual rotation speed of the motor 50 based on the position detection signal, generates a PWM signal obtained by adjusting the duty ratio in a manner that makes the actual rotation speed of the motor 50 consistent with the rotation speed specified by the drive control signal Sca1, and provides it as the drive signal Sd1 to the inverter circuit 15_1, thereby controlling the on and off actions of each switching element of the inverter circuit 15_1. In addition, the control circuit 12_2 also generates a PWM signal in a manner that makes the actual rotation speed of the motor 50 based on the position detection signal consistent with the rotation speed specified by the drive control signal Sca2, and provides it as the drive signal Sd2 to the inverter circuit 15_2. It should be noted that the control circuits 12_1 and 12_2 can also generate PWM signals of duty ratios corresponding to the rotation speeds specified by the drive control signals Sca1 and Sca2, respectively, regardless of the actual rotation speed, and provide them as the drive signals Sd1 and Sd2 to the inverter circuits 15_1 and 15_2.

[0110] Furthermore, the control circuit 12_1 generates and outputs a first FG signal (hereinafter referred to as “signal fg1”) corresponding to the actual rotation speed of the motor 50 based on the position detection signal from the position detector 41_1. The control circuit 12_2 generates and outputs a second FG signal (hereinafter referred to as “signal fg2”) corresponding to the actual rotation speed of the motor 50 based on the position detection signal from the position detector 41_2.

[0111] Signals fg1 and fg2 are rectangular wave signals having a predetermined duty ratio and have different phases. For example, signals fg1 and fg2 have a frequency corresponding to the actual rotation speed of motor 50 and are binary signals (digital signals) generated so that the duty ratio is 50% when the rotation speed is fixed.

[0112] The phase difference between the signal fg1 and the signal fg2 is, for example, π / 2 (90 degrees). In this case, the phase difference between the position detection signal from the position detector 41_1 and the position detection signal from the position detector 41_2 is π / 2 (90 degrees). It should be noted that the phase difference between the signal fg1 and the signal fg2 is not limited to π / 2 (90 degrees), and can also be around π / 2 (90 degrees) (for example, π / 2±10%).

[0113] The synthesized signal generating circuit 21 inputs the respective FG signals outputted from the plurality of motor driving circuits 10, and generates a synthesized signal Si obtained by synthesizing the inputted signals. Specifically, the synthesized signal generating circuit 21 inputs the signals fg1 and fg2 generated by the control circuits 12_1 and 12_2, respectively, and generates a synthesized signal Si obtained by synthesizing the inputted signals fg1 and fg2. For example, the synthesized signal generating circuit 21 generates the synthesized signal Si based on the logical product of the signal fg1 and the signal fg2. The synthesized signal generating circuit 21 and its peripheral circuits are described in detail below.

[0114] Figure 2 FIG. 2 is a diagram showing the structure of the synthesized signal generating circuit 21 and its peripheral circuits according to the first embodiment. Figure 2 Only the peripheral structure of the composite signal generating circuit 21 is shown in the figure.

[0115] The control circuit 12_1 and the control circuit 12_2 are each implemented by an integrated circuit (IC). In the present embodiment, the control circuit 12_1 and the control circuit 12_2 are both configured as hardware using a general-purpose IC having the same circuit configuration. It should be noted that the control circuit 12_1 and the control circuit 12_2 are not limited to configurations implemented by general-purpose ICs. For example, the control circuit may be configured by a microcontroller (MCU).

[0116] The control circuit 12_1 and the control circuit 12_2 respectively include: internal circuits 120_1 and 120_2 for realizing the functions of the control circuits 12_1 and 12_2; and multiple external terminals for inputting and outputting signals between the internal circuits 120_1 and 120_2 and the outside (in this embodiment, the drive control circuit 20).

[0117] As the above-mentioned external terminals, the control circuits 12_1, 12_2 have, for example: a ground terminal for inputting a ground voltage GND as a first fixed potential, a power terminal for inputting a power supply voltage Vdc (>GND), a control signal input terminal for inputting drive control signals Sca1, Sca2, an FG signal output terminal for outputting signals fg1, fg2 as FG signals, a position detection signal input terminal for inputting position detection signals from position detectors 41_1, 41_2, a drive signal output terminal for outputting drive signals Sd1, Sd2, etc.

[0118] It should be noted that, in the following description, the FG signal output terminals for outputting signals fg1 and fg2 are referred to as terminals (an example of the first output terminal) FG1 and terminals (an example of the second output terminal) FG2. Figure 2 In FIG. 1 , only terminals FG1 and FG2 are shown as external terminals of control circuits 12A_1 and 12A_2 .

[0119] like Figure 2 As shown, the control circuit 12_1 has an output transistor Q1 for outputting a first FG signal fg1 generated by the internal circuit 120_1 based on a position detection signal from the position detector 41_1 from a terminal FG1. The output transistor Q1 is connected between the terminal FG1 and a ground voltage GND as a first fixed potential.

[0120] Similar to the control circuit 12_1, the control circuit 12_2 has an output transistor Q2 for outputting, from the terminal FG2, a second FG signal fg2 generated by the internal circuit 120_2 based on the position detection signal from the position detector 41_2. The output transistor Q2 is connected between the terminal FG2 and the ground voltage GND. The output transistors Q1 and Q2 are, for example, FETs (Field Effect Transistors).

[0121] The power supply voltage Vcc (≤ the power supply voltage Vdc, an example of the second fixed potential) for driving the circuit is applied to the synthetic signal generating circuit 21. The synthetic signal generating circuit 21 is a circuit that generates the synthetic signal Si based on the logical product of the first FG signal fg1 and the second FG signal fg2. In the present embodiment, the synthetic signal generating circuit 21 is formed on the same circuit substrate on which the general-purpose IC as the control circuits 12_1 and 12_2 and the MCU as the drive control circuit 20 are mounted.

[0122] The synthesized signal generating circuit 21 has, for example, a load R1. The load R1 is, for example, a resistor. The load R1 is connected between a node (connection point) N1 to which the terminal FG1 of the control circuit 12_1 and the terminal FG2 of the control circuit 12_2 are commonly connected and the power supply voltage Vcc. The voltage of the node N1 of the synthesized signal generating circuit 21 is input to the drive control circuit 20 as a synthesized signal Si.

[0123] The waveform of the synthesized signal Si changes according to the state of the fan 100 (the motor 50 and the motor drive circuits 10_1 and 10_2). The synthesized signal Si will be described in detail below.

[0124] Figure 3 1 is a diagram showing the relationship between the state of the fan 100 and the pattern of the synthetic signal Si according to the first embodiment.

[0125] Figure 4 1 is a timing chart showing signals fg1 , fg2 and composite signal Si when motor 50 rotates normally in fan 100 according to Embodiment 1. FIG.

[0126] First, consider the case where the fan 100 is driven normally, that is, the motor 50 is rotating normally. Figure 4 As shown, the terminals FG1 and FG2 of the control circuits 12_1 and 12_2 respectively output signals fg1 and fg2 (binary signals) with a duty cycle of 50%. In addition, as described above, the signal fg1 and the signal fg2 have a phase difference of 90 degrees. Therefore, Figure 4 As shown, the synthesized signal Si output from the synthesized signal generating circuit 21 is a binary signal having a duty ratio of 25% in the same period as the signals fg1 and fg2.

[0127] Next, consider a case where a fault occurs in which one of the terminals FG1 and FG2 of the motor drive circuits 10_1 and 10_2 is in an open state. For example, when the output transistor Q1 connected to the terminal FG1 of the control circuit 12_1 fails and the output transistor Q1 is not turned on, or when the wiring connecting the terminal FG1 and the output transistor Q1 is broken, the terminal FG1 is an open circuit fault. In addition, for example, when the position detector 41_1 connected to the control circuit 12_1 fails and the signal ifg1 output from the internal circuit 120_1 is fixed at a low level, the output transistor Q1 is not turned on, so the terminal FG1 is also an open circuit fault. Hereinafter, the fault in which the terminals FG1 and FG2 of the motor drive circuits 10_1 and 10_2 are in an open state is also referred to as an open circuit fault of the motor drive circuits 10_1 and 10_2.

[0128] Figure 51 is a timing chart showing signals fg1 , fg2 and a composite signal Si when an open-circuit failure occurs in the terminal FG1 of the motor drive circuit 10_1 in the fan 100 according to the first embodiment.

[0129] like Figure 5 As shown in FIG. 1 , when the terminal FG1 is in an open state, the terminal FG1 is in a high impedance state (Hi-Z). On the other hand, the motor drive circuit 10_1 operates normally, so the signal fg2 output from the terminal FG2 is a binary signal with a duty cycle of 50%. Figure 5 As shown, the synthesized signal Si output from the synthesized signal generating circuit 21 is a binary signal having a duty ratio of 50%.

[0130] It should be noted that, also when the terminal FG2 of the motor drive circuit 10_2 is in an open-circuit fault, the synthetic signal Si having a duty ratio of 50% is output from the synthetic signal generation circuit 21 .

[0131] Next, consider a case where a fault occurs in which one of the terminals FG1 and FG2 of the motor drive circuits 10_1 and 10_2 is in a short-circuit state. For example, when the output transistor Q1 connected to the terminal FG1 of the control circuit 12_1 fails and the emitter and collector of the output transistor Q1 are short-circuited, the terminal FG1 is in a short-circuit fault. In addition, for example, when the position detector 41_1 connected to the control circuit 12_1 fails and the signal ifg1 output from the internal circuit 120_1 is fixed at a high level, the output transistor Q1 is not disconnected, so the terminal FG1 is also in a short-circuit fault. Hereinafter, the fault in which the terminals FG1 and FG2 of the motor drive circuits 10_1 and 10_2 are in a short-circuit state is also referred to as a short-circuit fault of the motor drive circuits 10_1 and 10_2.

[0132] Figure 6 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when a short-circuit failure occurs at the terminal FG1 of the motor drive circuit 10_1 in the fan 100 according to the first embodiment.

[0133] like Figure 6 As shown, when the terminal FG1 is in a short-circuited state, the voltage of the terminal FG1 (signal fg1) is the ground voltage GND (low (Lo) level). On the other hand, the motor drive circuit 10_2 operates normally, so the signal fg2 with a duty ratio of 50% is output from the terminal FG2, but the node N1 is short-circuited via the terminal FG1, so the synthesized signal Si output from the synthesized signal generating circuit 21 is a low level (an example of the second logic level).

[0134] Next, consider a case where the motor 50 is in a locked state.

[0135] Fig. 7Aand Figure 7B 1 is a timing chart showing signals fg1 , fg2 and a composite signal Si when the motor 50 is in the locked state in the fan 100 according to the first embodiment.

[0136] When the motor 50 is in the locked state, the signals ifg1 and ifg2 output from the internal circuits 120_1 and 120_2 are fixed to either a low level (ground voltage GND) or a high (Hi) level (power supply voltage Vcc).

[0137] For example, when the motor 50 is in the locked state and the signals ifg1 and ifg2 outputted from the internal circuits 120_1 and 120_2 are both at low levels, Fig. 7A As shown, both the signals fg1 and fg2 are at a high level (an example of a first logic level), and the synthesized signal Si output from the synthesized signal generating circuit 21 is at a high level (power supply voltage Vcc).

[0138] In addition, for example, when the motor 50 is in the locked state and the signals ifg1 and ifg2 outputted from the internal circuits 120_1 and 120_2 are both at high levels, as shown in FIG. Figure 7B As shown, both signals fg1 and fg2 are at low level, and the synthesized signal Si output from the synthesized signal generating circuit 21 is at low level (ground voltage GND). In addition, when the motor 50 is in the locked state and the signals ifg1 and ifg2 output from the internal circuits 120_1 and 120_2 are at different levels, either one of the signals fg1 and fg2 is at low level, and therefore the synthesized signal Si output from the synthesized signal generating circuit 21 is at low level (ground voltage GND).

[0139] As described above, the waveform of the composite signal Si changes according to the driving state of the fan 100 (the motor 50 and the motor driving circuits 10_1 and 10_2 ). Therefore, the driving state of the fan 100 can be determined by observing the composite signal Si.

[0140] In the present embodiment, the drive control circuit 20 receives the synthetic signal Si generated by the synthetic signal generating circuit 21 and determines the drive state of the fan 100 based on the synthetic signal Si.

[0141] Figure 8 This is a flowchart showing the flow of a process for determining the driving state of the fan 100 by the motor drive control device 1 according to the first embodiment.

[0142] like Figure 8As shown, first, the drive control circuit 20 determines whether the duty cycle of the synthetic signal Si is 25% (step S10). When the duty cycle of the synthetic signal Si is 25% (step S10: yes), the drive control circuit 20 determines that the fan 100 (motor 50 and motor drive circuits 10_1, 10_2) are driven normally (step S11). Thereafter, the drive control circuit 20 outputs the state signal So indicating that the fan 100 (motor 50) is driven normally to the host device 500 (step S12). For example, based on the synthetic signal Si generated according to the signals fg1 and fg2, the drive control circuit 20 outputs the FG signal with a duty cycle of 50% as the state signal So to the host device 500 at a frequency corresponding to the actual rotation speed of the motor 50.

[0143] Next, the drive control circuit 20 determines whether the duty cycle of the synthesized signal Si has changed (step S13). If the duty cycle of the synthesized signal Si has not changed (step S13: No), it is determined that the fan 100 (motor 50 and motor drive circuits 10_1, 10_2) continues to be driven normally (step S11), and the state signal So indicating that the fan 100 is operating normally is continuously output to the host device 500 (step S12).

[0144] On the other hand, when the duty ratio of the synthesized signal Si changes (step S13: Yes), or when the duty ratio of the synthesized signal Si is not 25% in step S10 (step S10: No), the drive control circuit 20 determines the waveform of the synthesized signal Si (step S14).

[0145] Specifically, when the duty ratio of the composite signal Si is 50%, the drive control circuit 20 determines that either the motor drive circuit 10_1 or 10_2 has an open circuit failure (step S15, see Figure 5 )

[0146] When the synthesized signal Si is at a high level (the same level as the power supply voltage Vcc), the drive control circuit 20 determines that the motor 50 is in a locked state (step S16, see Fig. 7A On the other hand, when the synthesized signal Si is at a low level (the same level as the ground voltage), the drive control circuit 20 determines that at least one of the motor drive circuits 10_1 and 10_2 is short-circuited or the motor 50 is locked (step S17, see Figure 7B ).

[0147] After that, the drive control circuit 20 generates a state signal So indicating the state of the fan 100 based on the determination results of steps S15, S16, and S17, and outputs it to the host device 500 (step S18). For example, the drive control circuit 20 outputs the state signal So as the power supply voltage Vcc (high (Hi) level) or the ground voltage GND (low (Lo) level) to the host device 500. Thus, the host device 500 can know the driving state of the fan 100.

[0148] As described above, the motor drive control device 1 of embodiment 1 comprises: a drive control circuit 20, which generates drive control signals Sca1 and Sca2 for controlling the rotation speed of the motor based on a speed command signal Sc indicating a target rotation speed of the motor 50; motor drive circuits 10_1 and 10_2, which control the power supply to the motor 50 based on the drive control signals Sca1 and Sca2, and respectively output signals fg1 and fg2 having a frequency corresponding to the actual rotation speed of the motor 50 and having different phases; and a synthetic signal generating circuit 21, which generates a synthetic signal Si obtained by synthesizing the signals fg1 and fg2.

[0149] Thus, two FG signals having different phases and whose schemes (waveforms) change according to the driving state of the motor 50 are synthesized to generate a synthesized signal Si. Therefore, by determining the waveform of the synthesized signal Si, the driving state of the fan 100 (motor 50 and motor drive circuits 10_1, 10_2) can be determined.

[0150] Specifically, when signals fg1 and fg2 are rectangular wave signals with a specified duty cycle (for example, binary signals with a duty cycle of 50%) and their phase difference is 90 degrees, the synthetic signal generating circuit 21 generates a synthetic signal Si based on the logical product of signals fg1 and fg2.

[0151] Thus, when the synthesized signal Si is a binary signal with a duty ratio (e.g., 25%) corresponding to the phase difference between the signal fg1 and the signal fg2, it can be determined that the motor 50 is driven normally. In addition, when the synthesized signal Si is a predetermined duty ratio, that is, the same duty ratio as the signals fg1 and fg2 (e.g., 50%), it can be determined that one of the motor drive circuits 10_1 and 10_2 (terminals FG1 and FG2 for outputting the signals fg1 and fg2) is in an open circuit fault. In addition, when the synthesized signal Si is fixed to the ground voltage GND (low level), it can be determined that at least one of the motor drive circuits 10_1 and 10_2 (terminals FG1 and FG2) is in a short circuit fault or the motor 50 is in a locked state. Moreover, when the synthesized signal Si is fixed to the power supply voltage Vcc (high level), it can be determined that the motor 50 is in a locked state.

[0152] Thus, according to the motor drive control device 1 of the first embodiment, the driving state of the motor 50 (fan 100) can be notified to the outside (for example, the host device 500). In addition, the motor drive control device 1 can reduce the number of signal lines output from the motor drive circuits 10_1 and 10_2 to the drive control circuit 20 by configuring the synthetic signal generation circuit 21, and can reduce the signal processing in the drive control circuit 20.

[0153] Implementation Method 2

[0154] Fig. 9 This is a block diagram showing the configuration of a fan according to Embodiment 2 of the present invention.

[0155] The motor drive control device 1A of the fan 100A of embodiment 2 is different from the motor drive control device 1 of embodiment 1 in that it generates a synthetic signal Si using a lock detection signal indicating whether the motor 50 is in a locked state in addition to the FG signal, but is the same as the motor drive control device 1 of embodiment 1 in other points.

[0156] like Fig. 9 As shown, the control circuits 12A_1 and 12A_2 of the motor drive circuits 10A_1 and 10A_2 of the motor drive control device 1A generate and output lock detection signals ld1 and ld2 , respectively, in addition to the signals fg1 and fg2 .

[0157] Here, the lock detection signals ld1 and ld2 are signals indicating whether the motor 50 is in a state where it cannot rotate, that is, in a locked state. The lock detection signals ld1 and ld2 are, for example, binary signals. For example, when the lock detection signal ld1 is at a low level (ground voltage GND), it indicates that the motor 50 is in an unlocked state (normal state), and when the lock detection signal ld1 is at a high level (power supply voltage Vcc), it indicates that the motor 50 is in a locked state (locked state).

[0158] For example, when a general-purpose IC is used as the control circuits 12A_1 and 12A_2, a signal output by a lock detection function of the general-purpose IC can be used as the lock detection signals ld1 and ld2.

[0159] Fig.10 This is a diagram showing the configuration of a synthetic signal generating circuit 21A and its peripheral circuits according to the second embodiment.

[0160] It should be noted that for the convenience of explanation, Fig.10 Only the peripheral structure of the composite signal generating circuit 21A is shown in the figure.

[0161] Control circuit 12A_1 and control circuit 12A_2 respectively include: internal circuits 120A_1 and 120A_2 for realizing the functions of control circuits 12A_1 and 12A_2; and multiple external terminals for inputting and outputting signals between internal circuits 120A_1 and 120A_2 and the outside (in this embodiment, drive control circuit 20).

[0162] The internal circuits 120A_1 and 120A_2 have the same functions as the internal circuits 120_1 and 120_2 of the first embodiment, and further have functions of generating lock detection signals ld1 and ld2 , respectively, based on the position detection signal.

[0163] The control circuits 12A_1 and 12A_2 have LD signal output terminals for outputting lock detection signals ld1 and ld2 in addition to the same external terminals as the control circuits 12_1 and 12_2 according to the first embodiment.

[0164] It should be noted that, in the following description, the LD signal output terminals that output the lock detection signals ld1 and ld2 are referred to as terminals LD1 and LD2. Fig.10 In FIG. 1 , only the terminals FG1 and FG2 and the terminals LD1 and LD2 are shown as external terminals of the control circuits 12A_1 and 12A_2 .

[0165] like Fig.10 As shown, the control circuit 12A_1 has an output transistor Q1A for outputting a first lock detection signal ld1 generated by the internal circuit 120A_1 based on a position detection signal from the position detector 41_1 from a terminal LD1. The output transistor Q1A is connected between the terminal LD1 and a ground voltage GND as a first fixed potential.

[0166] The control circuit 12A_2 has an output transistor Q2A for outputting, from the terminal LD2, a second lock detection signal ld2 generated by the internal circuit 120A_2 based on the position detection signal from the position detector 41_2. The output transistor Q2A is connected between the terminal LD2 and the ground voltage GND as the first fixed potential. The output transistors Q1A and Q2A are, for example, FETs.

[0167] The synthesized signal generating circuit 21A inputs the signals fg1 and fg2 generated by the control circuits 12A_1 and 12A_2 and the lock detection signals ld1 and ld2, respectively, and generates a synthesized signal Si obtained by synthesizing the input signals. For example, the synthesized signal generating circuit 21A generates the synthesized signal Si based on the logical product of the signals fg1 and fg2 and the logical product of the lock detection signals ld1 and ld2.

[0168] In the second embodiment, the composite signal generating circuit 21A is formed, for example, similarly to the composite signal generating circuit 21 in the first embodiment, on the same circuit board on which the general-purpose IC as the control circuits 12A_1 and 12A_2 and the MCU as the drive control circuit 20 are mounted.

[0169] The synthesized signal generating circuit 21A includes, for example, loads R1 to R3 and switch elements SW1 and SW2. The loads R1 to R3 are, for example, resistors. The load R1 is connected between a node (connection point) N1 to which the terminal FG1 of the control circuit 12A_1 and the terminal FG2 of the control circuit 12A_2 are connected and the power supply voltage Vcc. The load R2 is connected between a node (connection point) N2 to which the terminal LD1 of the control circuit 12A_1 and the terminal LD2 of the control circuit 12A_2 are connected and the power supply voltage Vcc. One end of the load R3 is connected to the power supply voltage Vcc.

[0170] The switch element SW1 is connected between the ground voltage GND and the other end of the load R3, and its on / off is controlled based on the voltage of the node N1. The switch element SW1 includes, for example, a transistor (bipolar transistor). In the transistor as the switch element SW1, the emitter electrode is connected to the ground voltage GND, and the collector electrode is connected to the other end (node ​​N3) of the load R3.

[0171] The switch element SW2 is connected between the ground voltage GND and the other end of the load R3, and its on / off is controlled based on the voltage of the node N2. The switch element SW2 includes, for example, a transistor (bipolar transistor). In the transistor as the switch element SW2, the emitter electrode is connected to the ground voltage GND, and the collector electrode is connected to the other end (node ​​N3) of the load R3.

[0172] It should be noted that if Fig.10 As shown, in the transistors constituting the switch elements SW1 and SW2, a resistor may be connected between the emitter electrode and the base electrode, or a resistor may be connected between the base electrode and the nodes N1 and N2.

[0173] In the synthetic signal generating circuit 21A, the node N3 is an output terminal, and the voltage of the node N3 is input to the drive control circuit 20 as the synthetic signal Si.

[0174] Fig.11 1 is a diagram showing the relationship between the state of the fan 100A and the pattern of the synthetic signal Si according to the second embodiment.

[0175] Fig.121 is a timing chart showing signals fg1 , fg2 , signal SF12 , lock detection signals ld1 , ld2 , signal SL12 , and synthesized signal Si when motor 50 rotates normally in fan 100A according to Embodiment 2. FIG.

[0176] First, consider the case where the fan 100A is driven normally, that is, the motor 50 is rotating normally. Fig.12 As shown, the terminals FG1 and FG2 of the control circuits 12A_1 and 12A_2 output signals fg1 and fg2 (binary signals) with a duty cycle of 50% respectively. In addition, as described above, the signal fg1 and the signal fg2 have a phase difference of 90 degrees. Therefore, Fig.12 As shown, the voltage of the node N1 (signal SF12) is a binary signal with a duty cycle of 25%.

[0177] In addition, when the motor 50 rotates normally, the internal circuits 120A_1 and 120A_2 of each control circuit 12A_1 and 12A_2 respectively output signals ild1 and ild2 indicating whether the motor 50 is in the locked state as high level (power supply voltage Vcc). Fig.12 As shown, the lock detection signals ld1 and ld2 outputted from the terminals LD1 and LD2 are respectively at a low level (ground voltage GND), and the voltage of the node N2 (signal SL12) is at a low level.

[0178] At this time, the node N2 as the input signal is at a low level, so the switch element SW2 is not turned on. On the other hand, a binary signal with a duty cycle of 25% is input from the node N1 as an input signal, so the on / off of the switch element SW1 is controlled according to the duty cycle. Therefore, when the motor 50 rotates normally, Fig.12 As shown, the voltage of the node N3, that is, the synthesized signal Si, is a binary signal with a duty ratio of 75%.

[0179] Next, consider a case where one of the terminals FG1 and FG2 of the motor drive circuits 10A_1 and 10A_2 fails (open circuit failure). Here, the output transistor Q1 connected to the terminal FG1 of the control circuit 12A_1 of the motor drive circuit 10A_1 fails and the terminal FG1 fails.

[0180] Fig.13 This is a timing chart showing signals fg1 , fg2 , signal SF12 , lock detection signals ld1 , ld2 , signal SL12 , and synthesized signal Si when an open circuit failure occurs in terminal FG1 of motor drive circuit 10A_1 in fan 100A of Embodiment 2.

[0181] like Fig.13As shown in FIG. 1 , when the terminal FG1 is in an open state, the terminal FG1 is in a high impedance state (Hi-Z). On the other hand, the motor drive circuit 10A_2 operates normally, so the signal fg2 output from the terminal FG2 is a binary signal with a duty cycle of 50%. Fig.13 As shown, the signal SF12 output from the node N1 is a binary signal with a duty ratio of 50%.

[0182] In addition, at this time, the pattern of the lock detection signal ld1 output from the terminal LD1 of the motor drive circuit 10A_1 depends on the fault content of the motor drive circuit 10A_1. For example, as described above, when only the output transistor Q1 of the control circuit 12A_1 fails, the internal circuit 120A_1 outputs a high-level signal ild1, and therefore the lock detection signal ld1 output from the terminal LD1 is low.

[0183] On the other hand, when the internal circuit 120A_1 of the control circuit 12A_1 fails and the signal ild1 is at a low level, the terminal LD1 is in a high impedance state (Hi-Z).

[0184] Thus, when the terminal FG1 is in the open state, the terminal LD1 is in the low level or high impedance state (see Fig.11 ).

[0185] On the other hand, the motor drive circuit 10A_2 operates normally, so the lock detection signal ld2 output from the terminal LD2 is at a low level (ground voltage GND) similarly to the case where the motor 50 rotates normally. Fig.13 As shown, the signal SL12 output from the node N2 is at a low level regardless of the state of the terminal LD1.

[0186] At this time, the node N2 as the input signal is at a low level, so the switch element SW2 is not turned on. On the other hand, a binary signal with a duty ratio of 50% is input from the node N1 as an input signal, so the on / off of the switch element SW1 is controlled according to the duty ratio.

[0187] Therefore, when an open circuit failure occurs in the terminal FG1 of the motor drive circuit 10A_1 and the motor drive circuit 10A_2 is normal, Fig.13 As shown, the synthesized signal Si is a binary signal with a duty cycle of 50%.

[0188] It should be noted that, when an open circuit failure occurs at the terminal FG2 of the motor drive circuit 10A_2 and the motor drive circuit 10A_1 is normal, the synthesized signal Si is a binary signal with a duty cycle of 50% (see Fig.11 ).

[0189] Next, consider a case where a fault (short-circuit fault) occurs in which one of the terminals FG1 and FG2 of the motor drive circuits 10A_1 and 10A_2 is in a short-circuited state. Here, an example is given in which the output transistor Q1 connected to the terminal FG1 of the control circuit 12A_1 of the motor drive circuit 10A_1 fails and the emitter and collector of the output transistor Q1 are short-circuited.

[0190] Fig.14 This is a timing chart showing signals fg1 , fg2 , signal SF12 , lock detection signals ld1 , ld2 , signal SL12 , and synthesized signal Si when a short-circuit failure occurs in terminal FG1 of motor drive circuit 10A_1 in fan 100A of Embodiment 2.

[0191] like Fig.14 As shown in FIG. 1 , when the terminal FG1 is in a short-circuited state, the voltage of the terminal FG1 (signal fg1) is the ground voltage GND (low level). On the other hand, the motor drive circuit 10A_2 operates normally, and thus a signal fg2 with a duty ratio of 50% is to be output from the terminal FG2, but the node N1 is short-circuited via the terminal FG1, and therefore the signal SF12 output from the node N1 is the ground voltage GND (low level).

[0192] In addition, at this time, the lock detection signal ld1 output from the terminal LD1 of the motor drive circuit 10A_1 depends on the fault content of the motor drive circuit 10A_1 as described above, so the terminal LD1 is in a low level or high impedance state (see Fig.11 ).

[0193] On the other hand, the motor drive circuit 10A_2 operates normally, so the lock detection signal ld2 output from the terminal LD2 is at a low level (ground voltage GND) similarly to the case where the motor 50 rotates normally. Fig.14 As shown, the signal SL12 output from the node N2 is at a low level regardless of the state of the terminal LD1.

[0194] At this time, the signal SL12 output from the node N2 is at a low level, so the switch element SW2 is not turned on. Similarly, the signal SF12 output from the node N1 is at a low level, so the switch element SW1 is not turned on.

[0195] Therefore, when a short circuit occurs at the terminal FG1 of the motor driving circuit 10A_1 and the motor driving circuit 10A_2 is normal, Fig.14 As shown, the synthesized signal Si is fixed at a high level (power supply voltage Vcc). In addition, when a short circuit occurs in the terminal FG2 of the motor drive circuit 10A_2 and the motor drive circuit 10A_1 is normal, the synthesized signal Si is fixed at a high level (power supply voltage Vcc) (see Fig.11 ).

[0196] Next, consider the case where the motor 50 is in the locked state.

[0197] Fig.15 1 is a timing chart showing signals fg1 and fg2 , signal SF12 , lock detection signals ld1 and ld2 , signal SL12 , and synthesized signal Si when the motor 50 is in the locked state in the fan 100A according to the second embodiment.

[0198] When the motor 50 is in the locked state, the signals ifg1 and ifg2 output from the internal circuits 120A_1 and 120A_2 are fixed to either a low level (ground voltage GND) or a high level (power supply voltage Vcc).

[0199] For example, when the motor 50 is in the locked state, the signals ifg1 and ifg2 outputted from the internal circuits 120A_1 and 120A_2 are both fixed at a high level. Fig.15 As shown, the signals fg1 and fg2 are both at a low level, and the signal SF12 output from the node N1 is at a low level.

[0200] On the other hand, the internal circuits 120A_1 and 120A_2 determine that the motor 50 is in the locked state, and output low-level signals ild1 and ild2. Fig.15 As shown, both signals ld1 and ld2 are high level, and the signal SL12 output from the node N2 is high level (power supply voltage Vcc), so the switch element SW2 is turned on. Therefore, regardless of whether the switch element SW1 is turned on or not, the synthesized signal Si is low level (refer to Fig.11 ). Thus, when the motor 50 is in the locked state, the synthesized signal Si is at a low level.

[0201] As described above, the waveform of the composite signal Si changes according to the driving state of the fan 100A (the motor 50 and the motor driving circuits 10A_1 and 10A_2 ), and therefore the driving state of the fan 100A can be determined.

[0202] In the present embodiment, drive control circuit 20 determines the drive state of fan 100A based on synthetic signal Si generated by synthetic signal generation circuit 21A.

[0203] Fig.16 This is a flowchart showing the flow of a process for determining the driving state of the fan 100A by the motor drive control device 1A according to the second embodiment.

[0204] like Fig.16As shown, first, the drive control circuit 20 determines whether the duty cycle of the synthetic signal Si is 75% (step S10A). When the duty cycle of the synthetic signal Si is 75% (step S10A: yes), the drive control circuit 20 determines that the fan 100A (motor 50 and motor drive circuits 10A_1, 10A_2) are driven normally (step S11A). After that, the drive control circuit 20 outputs the state signal So indicating that the fan 100A (motor 50) is driven normally to the host device 500 (step S12A). For example, the drive control circuit 20 outputs the FG signal with a duty cycle of 50% as the state signal So to the host device 500 at a frequency corresponding to the actual rotation speed of the motor 50 based on the synthetic signal Si generated according to the signals fg1, fg2 and the signals ld1, ld2.

[0205] Next, the drive control circuit 20 determines whether the duty cycle of the synthesized signal Si has changed (step S13A). If the duty cycle of the synthesized signal Si has not changed (step S13A: No), it is determined that the fan 100A (motor 50 and motor drive circuits 10A_1, 10A_2) continues to be driven normally (step S11A), and the state signal So indicating that the fan 100A is operating normally is continuously output to the host device 500 (step S12A).

[0206] On the other hand, when the duty cycle of the synthesized signal Si changes (step S13A: Yes), or when the duty cycle of the synthesized signal Si is not 75% in step S10A (step S10A: No), the drive control circuit 20 determines the waveform of the synthesized signal Si (step S14A).

[0207] Specifically, when the duty ratio of the composite signal Si is 50%, the drive control circuit 20 determines that one of the motor drive circuits 10A_1 and 10A_2 has an open circuit failure (step S15A, see Fig.13 ). In addition, when the synthesized signal Si is at a low level (ground voltage GND), the drive control circuit 20 determines that the motor 50 is in a locked state (step S17A, see Fig.15 ). In addition, when the synthesized signal Si is at a high level (power supply voltage Vcc), the drive control circuit 20 determines that either the motor drive circuit 10A_1 or 10A_2 is short-circuited (step S16A, see Fig.14 ).

[0208] After that, the drive control circuit 20 generates a state signal So indicating the state of the fan 100A based on the determination results of steps S15A, S16A, and S17A, and outputs it to the host device 500 (step S18A). For example, when either of the motor drive circuits 10A_1 and 10A_2 is in an open circuit fault or a short circuit fault, the drive control circuit 20 outputs the state signal So as the ground voltage GND (low (Lo) level) to the host device 500, and when the motor 50 is in a locked state, the drive control circuit 20 outputs the state signal So as the power supply voltage Vcc (high (Hi) level) to the host device 500. Thus, the host device 500 can know the driving state of the fan 100A in more detail.

[0209] As described above, in the motor drive control device 1A of embodiment 2, the motor drive circuits 10A_1 and 10A_2 respectively output lock detection signals ld1 and ld2 which are binary signals indicating whether the motor 50 is in a locked state, and the synthetic signal generating circuit 21A synthesizes the signals fg1 and fg2 and the lock detection signals ld1 and ld2 to generate a synthetic signal Si.

[0210] Thus, not only the two FG signals fg1 and fg2 but also the two lock detection signals ld1 and ld2 are synthesized to generate a synthesized signal Si. Therefore, by determining the waveform of the synthesized signal Si, the driving state of the fan 100A (motor 50 and motor drive circuits 10A_1 and 10A_2) can be determined in more detail.

[0211] Specifically, by generating a synthetic signal Si based on the logical product of the signal fg1 and the signal fg2 and the logical product of the lock detection signal ld1 and the lock detection signal ld2, it is possible to accurately determine whether an open circuit fault has occurred in either of the motor drive circuits 10A_1 and 10A_2, whether a short circuit fault has occurred in either of the motor drive circuits 10A_1 and 10A_2, and whether the motor 50 is locked.

[0212] For example, when the synthesized signal Si is a binary signal with a duty ratio (e.g., 75%) corresponding to the phase difference between the signal fg1 and the signal fg2, it can be determined that the motor 50 is normally driven. In addition, when the synthesized signal Si is a prescribed duty ratio, that is, the same duty ratio as the signals fg1 and fg2 (e.g., 50%), it can be determined that one of the motor drive circuits 10A_1 and 10A_2 (terminals FG1 and FG2 for outputting the signals fg1 and fg2) is an open circuit fault. In addition, when the synthesized signal Si is fixed to the power supply voltage Vcc (high level), it can be determined that one of the motor drive circuits 10A_1 and 10A_2 (terminals FG1 and FG2) is a short circuit fault. Moreover, when the synthesized signal Si is fixed to the ground voltage GND (low level), it can be determined that the motor 50 is in a locked state.

[0213] Thus, the motor drive control device 1A of the second embodiment can notify the outside (e.g., the host device 500) of a more accurate drive state of the fan 100A (motor 50). In addition, the motor drive control device 1A can reduce the number of signal lines output from the motor drive circuits 10A_1 and 10A_2 to the drive control circuit 20 by including the synthetic signal generating circuit 21A, and can reduce the signal processing in the drive control circuit 20.

[0214] 《Expansion of Implementation Methods 1 and 2》

[0215] As mentioned above, the invention completed by the present inventors has been specifically described based on the first and second embodiments, but the present invention is not limited to these and various modifications can be made without departing from the scope of the invention.

[0216] For example, in Embodiments 1 and 2, the motor drive control device 1 and 1A are applied to a fan system having a single-phase brushless motor with two coil systems 80_1 and 80_2, but the present invention is not limited thereto. For example, the motor drive control device 1 and 1A may be applied to a fan system having two single-phase brushless motors with one coil system.

[0217] For example, Fig.17As shown, the motor drive control device 1 can be applied to a fan 100B having a system structure in which two impellers 90_1 and 90_2 are rotated separately by motors 50B_1 and 50B_2 each having a coil of a system. In this case, the drive control circuit 20 generates drive control signals Sca1 and Sca2 in such a way that the phases of signals fg1 and fg2 output from each motor drive circuit 10_1 and 10_2 (control circuits 12_1 and 12_2) are different from each other (for example, the phase difference is 90 degrees). The motor drive circuit 10_1 controls the energization of the coil 80B_1 of the motor 50B_1 on one side based on the drive control signal Sca1, and the motor drive circuit 10_2 controls the energization of the coil 80B_2 of the motor 50B_2 on the other side based on the drive control signal Sca2.

[0218] Thus, similarly to the fan 100 according to the first embodiment, the driving state of the fan 100B (the motors 50B_1 and 50B_2 ) can be determined and notified to the host device 500 .

[0219] In addition, for example, Fig.18 As shown, the motor drive control device 1A can be applied to a fan 100C having a system structure in which two impellers 90_1 and 90_2 are rotated separately by motors 50B_1 and 50B_2 each having a coil of a system. In this case, the drive control circuit 20 generates drive control signals Sca1 and Sca2 in such a way that the phases of signals fg1 and fg2 output from each motor drive circuit 10A_1 and 10A_2 (control circuits 12A_1 and 12A_2) are different from each other (for example, the phase difference is 90 degrees). The motor drive circuit 10A_1 controls the energization of the coil 80B_1 of one motor 50B_1 based on the drive control signal Sca1, and the motor drive circuit 10A_2 controls the energization of the coil 80B_2 of the other motor 50B_2 based on the drive control signal Sca2.

[0220] Thus, similarly to the fan 100A of the second embodiment, the driving state of the fan 100C (the motors 50B_1 and 50B_2 ) can be determined and notified to the host device 500 .

[0221] In the above embodiment, the motors 50, 50B_1, 50B_2 are single-phase brushless motors, but the type and number of phases of the motors 50, 50B_1, 50B_2 are not limited thereto. For example, they may be three-phase brushless motors.

[0222] In addition, each flowchart in Embodiments 1 and 2 shows an example for explaining an action, and is not limited to this. That is, the steps shown in each figure of the flowchart are specific examples and are not limited to the process. For example, the order of a part of the processing can be changed, other processing can be inserted between each processing, and a part of the processing can be performed in parallel.

[0223] Implementation Method 3

[0224] Fig.19 This is a block diagram showing the configuration of a fan according to the third embodiment.

[0225] The fan (fan motor) 100D of the third embodiment is a device that generates wind by rotating an impeller. The fan 100D can be used as one of cooling devices that discharge heat generated inside a device to the outside to cool the inside of the device. For example, in addition to information processing devices such as servers, it can also be installed in machine tools used in an environment where oil mist, cutting chips, smoke, dust, etc. are generated. The fan 100D is, for example, an axial flow fan.

[0226] like Fig.19 As shown, the fan 100D includes a motor 50, an impeller 90, position detectors 41_1 and 41_2, and a motor drive control device 1D.

[0227] In the present embodiment, the motor 50 is, for example, a single-phase brushless motor having two systems of coils 80_1 and 80_2 wound around teeth (not shown). The impeller 90 is configured to be rotatable by the rotational force of the motor 50. For example, the impeller 90 is connected to an output shaft (not shown) of the motor 50.

[0228] The motor drive control device 1D is a device for controlling the rotation of the motor 50. The motor drive control device 1D causes the motor 50 to rotate by periodically flowing current through the single-phase coils 80_1 and 80_2 constituting the motor 50.

[0229] The position detectors 41_1 and 41_2 output position detection signals according to the position of the rotor of the motor 50. The position detectors 41_1 and 41_2 are, for example, Hall elements. The Hall element is an element that detects a magnetic field using the Hall effect, and generates and outputs Hall signals hp and hn having positive polarity as voltage values ​​as position detection signals for the magnet of the rotor. Hereinafter, the position detection signals are also described as "position detection signals hp and hn".

[0230] It should be noted that in this embodiment, as an example, the Hall elements serving as position detectors 41_1 and 41_2 are configured to be driven by a DC voltage (power supply voltage) generated by control circuits 12D_1 and 12D_2, and when the supply of the DC voltage is cut off, the output of the Hall signals (position detection signals) hp and hn is stopped and reduced to the same level as the ground voltage GND.

[0231] The position detector 41_1 is arranged at a position corresponding to the coil 80_1 of the first system, and outputs a position detection signal to the control circuit 12D_1 of the motor drive circuit 10D_1 described later. The position detector 41_2 is arranged at a position corresponding to the coil 80_2 of the second system, and outputs a position detection signal to the control circuit 12D_2 of the motor drive circuit 10D_2 described later. The position detector 41_1 and the position detector 41_2 are arranged at positions where the relative position is π / 2 (90 degrees) in electrical angle, for example.

[0232] The motor drive control device 1D is provided with DC power supply voltages Vin and Vcc from the outside. It should be noted that the power supply voltage Vcc (≤ the power supply voltage Vin) may be provided from the outside, or may be generated based on the power supply voltage Vin by a power supply circuit (not shown) such as a DC / DC converter provided separately in the motor drive control device 1D.

[0233] The motor drive control device 1D is connected to the host device 500. The speed command signal Sc outputted from the host device 500 is inputted to the motor drive control device 1D. The motor drive control device 1D drives the motor 50 according to the inputted speed command signal Sc. In addition, the motor drive control device 1D outputs information related to the state of the motor 50 to the host device 500. For example, as described later, the motor drive control device 1D outputs a signal corresponding to the actual rotation speed of the motor 50 and a signal indicating an abnormal state of the motor described later as a state signal So to the host device 500. Thus, the host device 500 can know the rotation state of the fan 100D, whether the fan 100D has an abnormality, and the like.

[0234] Specifically, the motor drive control device 1D includes: a plurality of motor drive circuits 10D; a drive control circuit 20 that controls the operations of the plurality of motor drive circuits 10D; and a synthetic signal generation circuit 21 .

[0235] The motor drive control device 1D according to the present embodiment includes, for example, two systems of motor drive circuits 10D_1 and 10D_2 as the plurality of motor drive circuits 10D.

[0236] The drive control circuit 20 is a circuit for controlling the drive of the motor 50 via the first motor drive circuit 10D_1 and the second motor drive circuit 10D_2. The drive control circuit 20 is composed of a program processing device (for example, a microcontroller: MCU) having hardware elements such as a processor such as a CPU (central processing unit), various memories such as a ROM (random access memory) or a RAM (read-only memory), a timer (counter), an A / D conversion circuit, an input / output I / F circuit, and a clock generation circuit, and each component is connected to each other via a bus or a dedicated line.

[0237] In the present embodiment, the drive control circuit 20 is packaged as one semiconductor device (IC: Integrated Circuit), but the present invention is not limited thereto.

[0238] The drive control circuit 20 generates a drive control signal Sca for controlling the rotation speed of the motor 50 based on the speed command signal Sc, and outputs it to each motor drive circuit 10D. Specifically, the drive control circuit 20 generates drive control signals Sca1 and Sca2 based on the speed command signal Sc input from the upper device 500, and outputs them to each motor drive circuit 10D_1 and 10D_2, respectively. It should be noted that the drive control circuit 20 can output a drive control signal and branch it into two lines, thereby outputting the drive control signal to the motor drive circuits 10D_1 and 10D_2. In this case, a switch that invalidates the drive control signal can be set by grounding each drive control signal output to the motor drive circuits 10D_1 and 10D_2.

[0239] Here, the speed command signal Sc is a signal indicating the target speed (target rotation speed) of the motor 50, for example, a PWM (pulse width modulation) signal having a duty cycle corresponding to the target speed of the motor. It should be noted that the speed command signal Sc may be, for example, a PFM signal having a period corresponding to the target speed, or other forms of signals.

[0240] Like the speed command signal Sc, the drive control signals Sca1 and Sca2 are signals that indicate a target rotation speed (target rotation speed) of the motor 50 , and are, for example, PWM signals having a duty ratio corresponding to the target rotation speed of the motor.

[0241] In addition to the function of controlling the driving of the motor 50 based on the speed command signal Sc from the host device 500 , the drive control circuit 20 also has the function of determining whether the fan 100D (the motor 50 and the motor drive circuits 10D_1 and 10D_2 ) has abnormality and outputting the determination result.

[0242] Specifically, the drive control circuit 20 determines the normal state in which the motor 50 operates normally, the FG fault state in which any one of the motor drive circuits 10D_1 and 10D_2 cannot normally output the FG signal (signals fg1 and fg2), and the locked state in which the motor 50 cannot rotate, based on the synthetic signal Si generated by the synthetic signal generation circuit 21, and outputs the state signal So indicating the state of the fan 100D to the host device 500. For example, when the fan 100D (the motor 50 and the motor drive circuits 10D_1 and 10D_2) is in the normal state, the drive control circuit 20 outputs the FG signal with a duty ratio of 50% as the state signal So in a period corresponding to the actual rotation speed of the motor 50 based on the synthetic signal Si generated by the synthetic signal generation circuit 21. In the case of the stop state including the FG fault state and the locked state, the drive control circuit 20 outputs the power supply voltage Vcc (high level) or the ground voltage GND (low level) as the state signal So. Thus, the host device 500 can know the driving state of the fan 100D according to the cycle of the state signal So.

[0243] The plurality of motor drive circuits 10D are circuits that control the energization of the motor 50 based on the drive control signal Sca, and output an FG signal having a period corresponding to the actual rotation speed of the motor 50. The FG signals output from the respective motor drive circuits 10D have a phase difference with each other. In the present embodiment, the motor drive circuit 10D_1 and the motor drive circuit 10D_2 as the plurality of motor drive circuits 10D have, for example, the same circuit configuration as each other.

[0244] The motor drive circuits 10D_1 and 10D_2 control energization of the motor 50 based on the drive control signals Sca1 and Sca2 , and output FG signals (signals fg1 and fg2 ) having a period corresponding to the actual rotation speed of the motor 50 .

[0245] As described later, the motor driving circuits 10D_1 and 10D_2 can be switched to a power saving state in which at least a part of the internal circuit thereof stops operating and the output of the FG signal (signal fg1 or fg2) is fixed at a high level.

[0246] The motor drive circuit 10D_1 includes a control circuit 12D_1 and an inverter circuit (power-on circuit) 15_1 for energizing the coil 80_1 based on the control of the control circuit 12D_1. The motor drive circuit 10D_2 includes a control circuit 12D_2 and an inverter circuit (power-on circuit) 15_2 for energizing the coil 80_2 based on the control of the control circuit 12D_2. It should be noted that the control circuits 12D_1 and 12D_2 may include inverter circuits 15_1 and 15_2, respectively.

[0247] The motor drive circuits 10D_1 and 10D_2 each have a fuse 19 connected at one end to the power supply voltage Vin. In the motor drive circuits 10D_1 and 10D_2, the power supply voltage Vin is supplied to the inverter circuits 15_1 and 15_2 and the control circuits 12D_1 and 12D_2 of the motor drive circuits 10D_1 and 10D_2 through the fuse 19.

[0248] The inverter circuit 15_1 energizes the coil 80_1 of the motor 50 connected to the output terminals 16_1 and 17_1 based on the drive signal Sd1 output from the control circuit 12D_1. Similar to the inverter circuit 15_1, the inverter circuit 15_2 controls the energization of the coil 80_2 of the motor 50 connected to the output terminals 16_2 and 17_2 based on the drive signal Sd2 output from the control circuit 12D_2. The drive signals Sd1 and Sd2 are, for example, PWM (pulse width modulation) signals.

[0249] like Fig.19 As shown, the inverter circuits 15_1 and 15_2 are, for example, H-bridge circuits having two pairs of series circuits of two switching elements (e.g., transistors) arranged at both ends of the power supply voltage Vin. The connection points between the two switching elements of each series circuit are output terminals 16_1, 17_1, 16_2, and 17_2 for energizing the coils 80_1 and 80_2, respectively.

[0250] The switching elements constituting the inverter circuits 15_1 and 15_2 are turned on and off by drive signals Sd1 and Sd2 outputted from the control circuits 12D_1 and 12D_2, respectively. Thus, the energization of the coil 80_1 connected to the output terminals 16_1 and 17_1 of the inverter circuit 15_1 and the energization of the coil 80_2 connected to the output terminals 16_2 and 17_2 of the inverter circuit 15_2 are controlled, respectively.

[0251] The control circuit 12D_1 determines the energization direction of the coil 80_1 based on the drive control signal Sca1 output from the drive control circuit 20 and the position detection signals hp and hn output from the position detector 41_1, generates a drive signal Sd1, and controls the inverter circuit 15_1. The control circuit 12D_2 determines the energization direction of the coil 80_2 based on the drive control signal Sca2 output from the drive control circuit 20 and the position detection signals hp and hn output from the position detector 41_2, generates a drive signal Sd2, and controls the inverter circuit 15_2.

[0252] For example, the control circuit 12D_1 detects the actual rotational speed of the motor 50 based on the position detection signals hp and hn, generates a PWM signal by adjusting the duty cycle in a manner that makes the actual rotational speed of the motor 50 consistent with the rotational speed specified by the drive control signal Sca1, and provides it to the inverter circuit 15_1 as the drive signal Sd1, thereby controlling the connection and disconnection actions of each switching element of the inverter circuit 15_1.

[0253] Similarly, the control circuit 12D_2 generates a PWM signal so that the actual rotation speed of the motor 50 based on the position detection signals hp and hn matches the rotation speed specified by the drive control signal Sca2, and supplies it to the inverter circuit 15_2 as the drive signal Sd2.

[0254] It should be noted that the control circuits 12D_1 and 12D_2 may generate PWM signals of duty ratios corresponding to the rotation speeds specified by the drive control signals Sca1 and Sca2 respectively regardless of the actual rotation speeds, and provide them as the drive signals Sd1 and Sd2 to the inverter circuits 15_1 and 15_2.

[0255] Furthermore, the control circuit 12D_1 generates and outputs a first FG signal (hereinafter referred to as “signal fg1”) corresponding to the actual rotation speed of the motor 50 based on the position detection signal from the position detector 41_1. The control circuit 12D_2 generates and outputs a second FG signal (hereinafter referred to as “signal fg2”) corresponding to the actual rotation speed of the motor 50 based on the position detection signal from the position detector 41_2.

[0256] Signals fg1 and fg2 are rectangular wave signals having a predetermined duty ratio and have different phases. For example, signals fg1 and fg2 have a period corresponding to the actual rotation speed of motor 50 and are binary signals (digital signals) generated so that the duty ratio is 50% when the rotation speed is fixed.

[0257] The phase difference between the signal fg1 and the signal fg2 is determined by the relative position of the electrical angle of the position detector 41_1 and the position detector 41_2, for example, π / 2 (90 degrees). It should be noted that when the phase difference between the signal fg1 and the signal fg2 is π / 2 (90 degrees), it can also be around π / 2 (90 degrees) (for example, π / 2±10%).

[0258] The synthesized signal generating circuit 21 receives the signals fg1 and fg2 generated by the control circuits 12D_1 and 12D_2, respectively, and generates a synthesized signal Si obtained by synthesizing the input signals. For example, the synthesized signal generating circuit 21 generates the synthesized signal Si based on the logical product of the signal fg1 and the signal fg2. The synthesized signal generating circuit 21 and its peripheral circuits are described in detail below.

[0259] Fig. 20 1 is a block diagram showing the internal structure of the control circuits 12D_1 and 12D_2 and the synthesized signal generating circuit 21 according to the third embodiment. Fig. 20 Only the internal configuration of the control circuits 12D_1 and 12D_2 related to the generation of the FG signals (signals fg1 and fg2 ) is shown in the figure.

[0260] It should be noted that in the following description, regarding the components marked with suffixes such as the motor drive circuit 10D_1, 10D_2, the control circuit 12D_1, 12D_2, and the drive control signals Sca1, Sca2, the suffixes are sometimes omitted and described as "motor drive circuit 10D", "control circuit 12D" and "drive control signal Sca" etc., when the components that only differ in the suffixes are not to be distinguished from each other or are to be collectively referred to.

[0261] The control circuit 12D_1 and the control circuit 12D_2 are each implemented by an integrated circuit (IC). In the present embodiment, the control circuit 12D_1 and the control circuit 12D_2 are both configured as hardware using a general-purpose IC having the same circuit configuration. It should be noted that the control circuit 12D_1 and the control circuit 12D_2 are not limited to configurations implemented by general-purpose ICs. For example, the control circuit may be configured by a microcontroller (MCU).

[0262] The control circuit 12D_1 and the control circuit 12D_2 each include an internal power supply circuit 121 , a control unit 122 , an FG signal generation unit 124 , and a plurality of external terminals as functional units related to generation of FG signals (signals fg1 , fg2 ).

[0263] As the above-mentioned external terminals, the control circuits 12D_1, 12D_2 have, for example: a ground terminal GND for inputting a ground voltage GND as a first fixed potential; a power terminal VIN for inputting a power supply voltage Vin (>GND); terminals SCA1, SCA2 for inputting drive control signals Sca1, Sca2; FG signal output terminals FG1, FG2 for outputting signals fg1, fg2 as FG signals; terminals HP1, HN1, HP2, HN2 for inputting position detection signals hp, hn from position detectors 41_1, 41_2; terminals SD1, SD2 for outputting drive signals Sd1, Sd2; and external output power terminals HB1, HB2 for providing an external output power voltage Vhb to the position detectors 41_1, 41_2.

[0264] It should be noted that, for the convenience of explanation, as the external terminals of the control circuits 12D_1 and 12D_2, Fig. 20 Only external terminals related to FG signals (signals fg1 and fg2) are shown in the figure. In this embodiment, as an example, it is assumed that the control circuit 12D_1 and the control circuit 12D_2 have the same circuit configuration, and the circuit configuration of the control circuit 12D_1 will be described in detail as a representative.

[0265] The internal power supply circuit 121 is a circuit that generates and outputs an internal power supply voltage. The internal power supply circuit 121 generates a predetermined DC voltage based on the DC voltage Vin supplied to the power supply terminal VIN, and supplies it as the internal power supply voltage Vdd (≤ the power supply voltage Vin) to the circuit in the control circuit 12D_1. In addition, the internal power supply circuit 121 generates a predetermined DC voltage based on the internal power supply voltage Vdd, and supplies it as the external output power supply voltage Vhb (≤ the power supply voltage Vdd) to the position detector 41_1.

[0266] The control unit 122 is a functional unit for overall control of the circuits in the control circuit 12D_1. The control unit 122 is composed of, for example, a dedicated hardware logic circuit or a program processing device such as an MCU, and a pre-driving circuit for generating the driving signal Sd1.

[0267] The control unit 122 controls the supply and cutoff of the internal power supply voltage Vdd to the FG signal generating unit 124. Specifically, the control unit 122 controls the supply and cutoff of the internal power supply voltage Vdd to the FG signal generating unit 124 based on whether the input of the drive control signal Sca1 and the input of the position detection signals hp and hn have changed. For example, when the state in which the drive control signal Sca1 is not input, the input of the position detection signals hp and hn has not changed, and the output of the comparator 1241 has not switched (that is, the state in which the next switching of the signal fg1 has not occurred) continues for only a prescribed power saving waiting time (an example of a prescribed period, the third period Ts3), the control unit 122 determines that the motor 50 is intentionally stopped, and thus changes to the power saving state, controls the internal power supply circuit 121, and cuts off the supply of the internal power supply voltage Vdd to the FG signal generating unit 124. At this time, at the same time, the supply of the external output power supply voltage Vhb to the position detector 41_1 is cut off.

[0268] In the present embodiment, a state in which the control circuit 12D cuts off the supply of the internal power supply voltage Vdd of the internal power supply circuit 121 is referred to as a power saving state of the motor drive circuit 10D.

[0269] The control unit 122 generates a drive signal Sd1 for energizing the motor 50 based on the drive control signal Sca1. Specifically, the control unit 122 determines the energization direction of the coil 80_1 based on the signal generated according to the position detection signals hp and hn through the comparator 1241 built into the FG signal generating unit 124, detects the actual rotation speed of the motor 50, generates a PWM signal obtained by adjusting the duty ratio in a manner that makes the actual rotation speed of the motor 50 consistent with the rotation speed specified by the drive control signal Sca1, such as the duty ratio of the PWM signal, and outputs it as the drive signal Sd1 to the inverter circuit 15_1. The on and off actions of each switching element of the inverter circuit 15_1 are controlled by the drive signal Sd1. In addition, the control unit 122 can output the drive signal Sd1 with a duty ratio of the PWM signal equal to the drive control signal Sca1.

[0270] The FG signal generating unit 124 is a circuit that generates an FG signal based on the position detection signals hp and hn input to the terminals HP1 and HN1 and outputs the FG signal from the terminal FG1. The FG signal generating unit 124 is configured to be operable by power supply from the internal power supply voltage Vdd.

[0271] The output of the Hall element as the position detector 41_1 changes in accordance with the magnetic flux density. Therefore, the position detector 41_1 outputs position detection signals hp and hn as periodic sine wave signals corresponding to the rotation speed of the rotor through analog voltage according to the rotation of the rotor of the motor 50. The phases of the position detection signals hp and hn differ from each other by 180 degrees. The FG signal generation unit 124 generates a binary signal (digital signal) corresponding to the polarity (positive or negative) of the difference (hp-hn) between the voltage of the position detection signal hp and the voltage of the position detection signal hn, converts it into a binary signal fg1 and outputs it.

[0272] For example, Fig. 20 As shown, the FG signal generating section 124 includes an output transistor Q1 , a comparator (voltage comparator) 1241 , and a pre-driving circuit 1242 .

[0273] The comparator 1241 is a circuit that generates a binary signal corresponding to the positive or negative difference (hp-hn) between the position detection signals hp and hn input to the terminals HP1 and HN1. The pre-driving circuit 1242 is a circuit that drives the output transistor Q1 based on the binary signal generated by the comparator 1241.

[0274] The output transistor Q1 is a circuit element for outputting the signal fg1 from the terminal FG1 , and is connected between the terminal FG1 and the ground voltage GND which is a first fixed potential.

[0275] In this embodiment, the output transistor of the FG signal generating unit 124 of the control circuit 12D_1 is referred to as “output transistor Q1 ”, and the output transistor of the FG signal generating unit 124 of the control circuit 12D_2 is referred to as “output transistor Q2 .” The output transistors Q1 and Q2 are, for example, FETs (Field Effect Transistors).

[0276] The synthetic signal generating circuit 21 inputs each FG signal output from a plurality of motor driving circuits 10D, and generates a synthetic signal Si obtained by synthesizing the input signals. Specifically, the synthetic signal generating circuit 21 generates a synthetic signal Si obtained by synthesizing the signal fg1 and the signal fg2. The power supply voltage Vcc is provided to the synthetic signal generating circuit 21 as a second fixed potential for the driving circuit. The synthetic signal generating circuit 21 generates the synthetic signal Si based on, for example, the logical product of the signals fg1 and fg2. The synthetic signal generating circuit 21 has, for example, a load R1. The load R1 is, for example, a resistor. The load R1 is connected between a node (connection point) N1 to which the terminal FG1 of the control circuit 12D_1 and the terminal FG2 of the control circuit 12D_2 are commonly connected and the power supply voltage Vcc. The voltage of the node N1 of the synthetic signal generating circuit 21 is input to the drive control circuit 20 as the synthetic signal Si.

[0277] In the present embodiment, the synthetic signal generating circuit 21 is mounted on one circuit board together with, for example, a general-purpose IC as the control circuits 12D_1 and 12D_2 and an MCU as the drive control circuit 20 .

[0278] The waveform of the synthesized signal Si changes according to the state of the fan 100D (the motor 50 and the motor drive circuits 10D_1 and 10D_2). The drive control circuit 20 determines the drive state of the fan 100D based on the synthesized signal Si. The synthesized signal Si will be described in detail below.

[0279] Fig.21 This is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the third embodiment.

[0280] Fig.21 2 shows a pattern of the synthesized signal Si during normal operation of the fan 100D, that is, when the drive control circuit 20 outputs the drive control signals Sca1 and Sca2 corresponding to the speed command signal Sc to the motor drive circuits 10D_1 and 10D_2 to drive the motor 50 .

[0281] First, a case where the fan 100D (motor 50 ) operates normally, that is, a normal state is considered.

[0282] In this case, the terminals fg1 and fg2 of the control circuits 12D_1 and 12D_2 are pulled up to the power supply voltage Vcc of the composite signal generating circuit 21, so that the signals fg1 and fg2 (binary signals) with a duty ratio of 50% are outputted from the terminals fg1 and fg2 of the control circuits 12D_1 and 12D_2, respectively, with the voltage same as the power supply voltage Vcc being set to a high (Hi) level (an example of a prescribed logic value) and the voltage same as the ground voltage GND being set to a low (Lo) level (an example of a prescribed logic value). In addition, as described above, the signal fg1 and the signal fg2 have a phase difference of 90 degrees. Therefore, when the fan 100D (motor 50) is in a normal state, the composite signal Si outputted from the composite signal generating circuit 21 (node ​​N1) is a binary signal with the same period as the signals fg1 and fg2, but a duty ratio of 25%.

[0283] Next, as an FG fault state, consider a case where a fault occurs in which one of the terminals FG1 and FG2 of the motor drive circuits 10D_1 and 10D_2 is in an open state. For example, a Hall element as the position detector 41_1 fails, and the position detection signal hp is fixed at the same level as the external output power supply voltage Vhb and / or the position detection signal hn is fixed at the same level as the ground voltage GND. In this case, the polarity of the difference (hp-hn) is always positive, the output of the comparator 1241 is fixed at a high level, and the output transistor Q1 is disconnected, so the terminal FG1 is in an open state. In addition, for example, in the case where the power supply to the position detector 41_1 is disconnected / grounded during the process of the comparator 1241 outputting a high level, the terminal FG1 is also in an open state.

[0284] Hereinafter, a failure in which the terminals FG1 and FG2 of the motor drive circuits 10D_1 and 10D_2 are in a high impedance (Hi-Z) state (open state) is also referred to as an “FG open failure”.

[0285] When the terminal FG1 is in an open state, a high-level signal fg1 is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 operates normally, so when the motor 50 rotates, a signal fg2 with a duty ratio of 50% is output from the terminal FG2. Therefore, the composite signal Si output from the composite signal generation circuit 21 (node ​​N1) is a binary signal with a duty ratio of 50% corresponding to the signal fg2.

[0286] It should be noted that, similarly, when only the terminal FG2 of the motor driving circuit 10D_2 is in the FG open fault, the synthetic signal Si having a duty ratio of 50% corresponding to the signal fg1 is output from the synthetic signal generating circuit 21 .

[0287] Next, as an FG fault state, consider a case where a fault occurs in which one of the terminals FG1 and FG2 of the motor drive circuits 10D_1 and 10D_2 is in a short-circuit state. For example, a Hall element as the position detector 41_1 fails, and the position detection signal hp is fixed at the same level as the ground voltage GND and / or hn is fixed at the same level as the external output power supply voltage Vhb. In this case, the polarity of the difference (hp-hn) is always negative, the output of the comparator 1241 is fixed at a low level, and the output transistor Q1 is turned on, so that the terminal FG1 is in a short-circuit state.

[0288] Furthermore, for example, even when the power supply to the opposing detector 41_1 is disconnected or grounded while the comparator 1241 is outputting a low level, the terminal FG1 is short-circuited.

[0289] Hereinafter, a failure in which the terminals FG1 and FG2 of the motor drive circuits 10D_1 and 10D_2 are in a short-circuited state is also referred to as an “FG short-circuit failure”.

[0290] When the terminal FG1 is in a short-circuited state, a low-level signal fg1 is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 operates normally, so a signal fg2 with a duty ratio of 50% is output from the terminal FG2, but the node N1 is short-circuited via the terminal FG1, so the synthesized signal Si output from the synthesized signal generating circuit 21 (node ​​N1) is low-level.

[0291] It should be noted that, also in the case where only the terminal FG2 of the motor driving circuit 10D_2 is in the FG short-circuit fault, the synthesized signal Si output from the synthesized signal generating circuit 21 is at a low level.

[0292] Next, consider the case where the motor 50 is in the locked state.

[0293] When the motor 50 is in a locked state where it cannot rotate due to rotor lock caused by external mechanical reasons, the position detection signals hp and hn from the input terminals HP1, HN1, HP2, and HN2 of the position detectors 41_1 and 41_2 do not change periodically, so the signals fg1 and fg2 are fixed at either a low level or a high level.

[0294] For example, when the motor 50 is locked by the rotor and at least one of the signals fg1 and fg2 output from the control circuits 12D_1 and 12D_2 is at a low level, the synthesized signal Si output from the synthesized signal generating circuit 21 (node ​​N1) is at a low level.

[0295] For example, when the motor 50 is locked in the rotor and the signals fg1 and fg2 outputted from the control circuits 12D_1 and 12D_2 are both at high level, the synthesized signal Si outputted from the synthesized signal generating circuit 21 (node ​​N1) is at high level.

[0296] As described above, the waveform of the composite signal Si changes according to the driving state of the fan 100D (motor 50 and motor drive circuits 10D_1, 10D_2), so by monitoring the composite signal Si during normal operation of the fan 100D, the drive control circuit 20 can determine the driving state of the fan 100D.

[0297] Specifically, a synthetic signal Si is generated based on the logical product of signals fg1 and fg2 output from motor drive circuits 10D_1 and 10D_2, thereby making it possible to determine whether one of motor drive circuits 10D_1 and 10D_2 has an FG open circuit fault, or whether at least one of motor drive circuits 10D_1 and 10D_2 has an FG short circuit fault or motor 50 is rotor locked.

[0298] However, if Fig.21 As shown, when the composite signal Si is at a low level, it is impossible to determine whether the fan 100D is in the "FG failure state caused by the FG short-circuit failure" or the "locked state".

[0299] Therefore, in the motor drive control device 1D of the present embodiment, when the synthetic signal Si is at a low level, it is determined whether the fan 100D is in the "FG fault state caused by an FG short-circuit fault" or the "locked state" based on the synthetic signal Si that converts the output of the FG signal based on at least one of the motor drive circuits 10D_1 and 10D_2 into a high level state.

[0300] Specifically, when the synthesized signal Si indicates a predetermined logical value, for example, when the synthesized signal generating circuit 21 generates a signal having a predetermined logical value, Fig. 20 When the synthetic signal Si obtained by synthesizing the FG signal generated by the FG signal generating unit 124 of the circuit structure shown in the figure indicates a low level, the drive control circuit 20 causes at least one of the motor drive circuits 10D_1 and 10D_2 to be converted into a high level state in which the signals fg1 and fg2 cannot be output, and based on the synthetic signal Si at this time, performs the first FG fault judgment processing (an example of the first judgment processing) to determine whether any one of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state or the motor 50 is in the locked state.

[0301] Specifically, when the composite signal Si is fixed at a predetermined logic value (low level or high level), the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 to shift at least one of the motor drive circuits 10D_1 and 10D_2 to the power saving state.

[0302] As described above, the control circuit 12D (control unit 122) of the motor drive circuit 10D cuts off the supply of the internal power supply voltage Vdd to the FG signal generating unit 124 when the state in which the drive control signal Sca is not input and the next switching of the FG signal does not occur (the input of the position detection signals hp and hn does not change) only lasts for the third period Ts3.

[0303] Therefore, the motor drive circuit 10D on one side of the FG short-circuit fault or on both sides of the rotor lock changes to the power saving state from the state where the drive control signal Sca from the drive control circuit 20 is not input and the next switching of the FG signal does not occur after the third period Ts3. As a result, the output transistor Q1 is turned off, and the terminal FG (FG1 or FG2) of the motor drive circuit 10D is in a high impedance state.

[0304] That is, the drive control circuit 20 makes a detailed determination on the state of the fan 100D based on the synthesized signal Si when the terminals FG1 , FG2 of at least one of the motor drive circuits 10D_1 , 10D_2 are in the high impedance state.

[0305] For example, when a predetermined change in the composite signal Si is detected when at least one of the motor drive circuits 10D_1 and 10D_2 is in the power saving state, the drive control circuit 20 determines that one of the motor drive circuits 10D_1 and 10D_2 is in the FG failure state caused by the FG short circuit failure, and the motor 50 rotates due to inertia. On the other hand, when the composite signal Si is fixed at a predetermined logic value (for example, a high level), the drive control circuit 20 determines that the motor 50 is in a locked state where it cannot rotate.

[0306] Here, the predetermined change of the synthesized signal Si means, for example, that the logical value of the synthesized signal Si switches two or more times.

[0307] It should be noted that, when the drive control signal Sca is input, the control circuit 12D (control unit 122) of the motor drive circuit 10D cancels the power saving state and restarts the supply of the internal power supply voltage Vdd and the external output power supply voltage Vhb to the FG signal generating unit 124. As a result, the motor drive circuit 10D restarts the output of the FG signal based on the position detection signal from the position detector 41 corresponding to the rotation position of the rotor of the motor 50. At this time, the motor drive circuit 10D in the FG fault state may be switched to the other FG fault state by the re-output of the comparator 1241.

[0308] Next, the flow of the process of determining the driving state of the fan 100D by the motor drive control device 1D will be described.

[0309] Fig. 22 , Fig.23 , Fig.24 , FIG. 25A to FIG. 25D This is an example of a flowchart showing the flow of a process for determining the driving state of the fan 100D by the motor drive control device 1D according to the third embodiment.

[0310] like Fig. 22As shown, when the motor drive control device 1D is powered on, first, the drive control circuit 20 (MCU) and the like are initialized (step S1). Next, the drive control circuit 20 is in a stop mode in which the motor 50 is not driven (step S2). Here, in the stop mode, the motor drive circuits 10D_1 and 10D_2 may be in a power saving state. In the stop mode, the drive control circuit 20 determines whether a speed command signal Sc is input from the host device 500 (step S3). In the case where the speed command signal Sc is not input (step S3: No), the drive control circuit 20 continues to operate in the stop mode and monitors whether the speed command signal Sc is input.

[0311] On the other hand, when the speed command signal Sc is input (step S3: Yes), the drive control circuit 20 enters the start-up waiting mode (step S10). In the start-up waiting mode, first, in order to reliably start the rotation of the motor 50, the drive control circuit 20 outputs the drive control signals Sca1 and Sca2 of the preset fixed duty ratio (start-up duty ratio) regardless of the speed command signal Sc (step S11).

[0312] It should be noted that, for example, when the switching (commutation) of the energization direction of the coil 80 does not occur due to an FG failure of one motor drive circuit 10D, and the rotation of the motor 50 is braked, the other normal motor drive circuit 10D generates a drive control signal Sca of a duty ratio specified by the speed command signal Sc, whereby the motor 50 may be in a state where it can rotate. In this case, the duty ratio corresponding to the speed command signal Sc can be set as the start duty ratio.

[0313] Next, the drive control circuit 20 determines whether the motor 50 rotates within the time period (first time period Ts1) of the predetermined start waiting time and detects the predetermined change of the synthesized signal Si, in other words, whether the synthesized signal Si is fixed at a predetermined logic value (high level or low level) (step S12). At this time, the first time period Ts1 is set to a time longer than the second time period Ts2 described later.

[0314] When the specified change of the composite signal Si is not detected within the first time period Ts1 (the composite signal Si is fixed at a high level or a low level) (step S12: No), the drive control circuit 20 determines that the motor 50 is unintentionally in a rotor lock or FG short circuit fault from the time of startup, and starts the first FG fault judgment process (step S100).

[0315] Here, the first falling edge of the composite signal Si is sometimes generated by the recovery of the internal power supply voltage due to the release of the power saving state, and therefore is not processed as the input of the composite signal Si. That is, the drive control circuit 20 starts processing as an input from the time point when the specified change of the composite signal Si is detected, and starts measuring the period and duty ratio of the composite signal Si.

[0316] Here, the first FG failure determination process is a process for determining the locked state of the motor 50 and the FG failure state of the motor drive circuit 10D. The specific content of the first FG failure determination process will be described later.

[0317] On the other hand, when a predetermined change in the synthesized signal Si is detected (step S12 : Yes), the drive control circuit 20 determines whether the duty ratio of the synthesized signal Si is 50% (step S13 ).

[0318] Here, "50%" may include some errors. For example, if the duty cycle of the composite signal Si is within the range of "50% ± 10%", it can be determined that the duty cycle of the composite signal Si is "50%". In addition, when the motor 50 starts to rotate from a stopped state, the rotation speed changes greatly, and the duty cycle of the first few pulses of the composite signal Si is unstable. In this case, the measurement of the duty cycle can be skipped. Moreover, multiple pulses of the composite signal Si can be used for the determination of the duty cycle.

[0319] When the duty ratio of the composite signal Si is 50% (step S13 : YES), the drive control circuit 20 determines which motor drive circuit 10D is in the FG failure state due to the FG open circuit failure, and starts the second FG failure determination process (step S200 ).

[0320] Here, the second FG failure determination process is a process for determining an FG failure state caused by an FG open-circuit failure of the motor drive circuit 10D. The specific content of the second FG failure determination process will be described later.

[0321] On the other hand, when the duty cycle of the synthetic signal Si is not 50% (step S13: No), the drive control circuit 20 determines that the fan 100D (motor 50 and motor drive circuits 10D_1, 10D_2) are normal (normal state), and outputs the state signal So indicating the normal driving state of the fan 100D to the host device 500 (step S14).

[0322] If the speed command signal Sc is input (step S15: Yes), the drive control circuit 20 proceeds to step S20. On the other hand, if the speed command signal Sc is not input (step S15: No), the drive control circuit 20 stops driving the motor 50 and enters a stop waiting mode (step S30).

[0323] Thereafter, the drive control circuit 20 controls the motor drive circuits 10D_1 and 10D_2 to rotate the motor 50 at the speed specified by the speed command signal Sc, thereby causing the motor 50 to enter a drive mode corresponding to "rotor lock" or "FG fault" during driving (step S20).

[0324] In the driving mode, first, the driving control circuit 20 outputs the driving control signals Sca1 and Sca2 of the duty ratio corresponding to the speed command signal Sc (step S21). Next, the driving control circuit 20 determines whether the prescribed change of the synthetic signal Si and the speed obtained according to the cycle of the synthetic signal Si are detected within the period of the prescribed minimum speed time (the second period Ts2) (step S22). At this time, the second period Ts2 is set to be shorter than the third period Ts3.

[0325] When the specified change in the composite signal Si is not detected or the speed is less than the minimum speed (step S22: No), the drive control circuit 20 determines that the motor 50 has accidentally fallen into a rotor lock or FG short circuit fault during driving, and starts the first FG fault determination process (step S100).

[0326] On the other hand, when the predetermined change of the composite signal Si is detected (step S22: YES), the drive control circuit 20 determines whether the duty ratio of the composite signal Si is 50% (step S23). Here, as in step S13, "50%" means that the determination process can be performed.

[0327] When the duty ratio of the composite signal Si is 50% (step S23: Yes), the drive control circuit 20 determines which motor drive circuit 10D is in the FG fault state caused by the FG open circuit fault, and starts the second FG fault determination process (step S200). On the other hand, when the duty ratio of the composite signal Si is not 50% (step S23: No), the drive control circuit 20 determines that the motor 50 and the motor drive circuits 10D_1 and 10D_2 are normal (normal state), and outputs the state signal So indicating the state of the fan 100D being driven normally to the host device 500 (step S24).

[0328] Thereafter, the drive control circuit 20 determines again whether the speed command signal Sc is input (step S25 ).

[0329] When the speed command signal Sc is input (step S25: Yes), the drive control circuit 20 repeats steps S21 to S25. On the other hand, when the speed command signal Sc is not input (step S25: No), the drive control circuit 20 stops driving the motor 50 and enters a stop waiting mode (step S30).

[0330] In the stop waiting mode, the drive control circuit 20 stops the output of the drive control signals Sca1 and Sca2 (step S31). As a result, the motor 50 continues to rotate due to inertia and then stops. At this time, when the fan 100D (motor 50 and motor drive circuits 10D_1 and 10D_2) is in a normal state, the drive control circuit 20 outputs a FG signal with a duty cycle of 50% as a state signal So to the host device 500 in a period corresponding to the actual rotation speed of the motor 50 based on the synthetic signal Si generated by the synthetic signal generating circuit 21.

[0331] After step S31, the drive control circuit 20 determines whether the speed command signal Sc is input from the host device 500 (step S32). If the speed command signal Sc is input (step S32: Yes), the drive control circuit 20 enters the startup waiting mode and executes the processing of steps S10 to S25 again.

[0332] On the other hand, when the speed command signal Sc is not input (step S32: No), the drive control circuit 20 waits for the rotation of the motor 50 due to inertia to be less than the minimum speed. That is, the drive control circuit 20 determines whether the specified change of the composite signal Si and the speed obtained according to the cycle of the composite signal Si are detected in the second time period Ts2 (step S33). When the specified change of the composite signal Si is not detected or it is less than the minimum speed (step S33: No), the drive control circuit 20 determines that the motor 50 has stopped and enters the stop mode (step S2).

[0333] On the other hand, when a prescribed change in the composite signal Si is detected and the speed is above the minimum speed (step S33: yes), the drive control circuit 20 determines that the motor 50 is rotating due to inertia, enters step S32, and determines again whether the speed command signal Sc is input from the host device 500.

[0334] Fig.26 This is an example of a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor drive circuits 10D_1, 10D_2 are in a normal state and the motor 50 is in an unlocked state. Fig.26 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0335] like Fig.26 As shown, at time t1, when the speed command signal Sc output from the host device 500 is input, the start waiting mode is entered from the stop mode ( Fig. 22 In step S10), the drive control circuit 20 outputs drive control signals Sca1 and Sca2 that specify the start-up duty ratio (step S11).

[0336] After that, the motor driving circuits 10D_1 and 10D_2 drive the motor 50 based on the driving control signals Sca1 and Sca2, so that the motor 50 starts to rotate. At this time, the motor driving circuits 10D_1 and 10D_2 are both in normal state, so the position detection signals hp and hn are input to the motor driving circuits 10D_1 and 10D_2 according to the rotation of the motor 50. As a result, the motor driving circuits 10D_1 and 10D_2 output signals fg1 and fg2 with a duty cycle of 50% from the terminals FG1 and FG2, respectively. As described above, the signal fg1 and the signal fg2 have a phase difference of 90 degrees, so the synthesized signal Si is a signal with the same period as the signals fg1 and fg2, but a duty cycle of 25%.

[0337] like Fig.26 As shown, after entering the startup waiting mode, the drive control circuit 20 detects the specified change of the synthetic signal Si within the first time period Ts1, and determines that at the moment ta when the duty cycle is detected to be 25% (not 50%), the motor drive circuits 10D_1 and 10D_2 are in a normal state (steps S12 to S14).

[0338] Then, at time t2, the drive control circuit 20 enters the drive mode (step S20), generates drive control signals Sca1 and Sca2 corresponding to the speed command signal Sc, and outputs them to the motor drive circuits 10D_1 and 10D_2 (step S21). At this time, the drive control circuit 20 can enter the drive mode immediately after the determination at time ta without waiting for the first period Ts1 to end.

[0339] Next, use Fig.23 , the first FG failure determination process (S100) is described.

[0340] As described above, the first FG failure determination process is a process for determining the locked state of the motor 50 and the FG failure state of the motor drive circuit 10D.

[0341] like Fig.23As shown, in the first FG fault determination process, the drive control circuit 20 first stops the output of the drive control signals Sca1 and Sca2 (step S101). After that, the drive control circuit 20 waits for the third period Ts3 to pass, and then the motor drive circuits 10D_1 and 10D_2 (control circuits 12D_1 and 12D_2) are switched to the power saving state (step S102).

[0342] After the third period Ts3 has passed, the drive control circuit 20 enters the power saving mode (step S103 ). The power saving mode is an operation mode in which the motor drive circuits 10D_1 , 10D_2 (control circuits 12D_1 , 12D_2 ) are switched to a power saving state.

[0343] As described above, in order to shift the two systems of motor drive circuits 10D_1 and 10D_2 (control circuits 12D_1 and 12D_2 ) to the power saving state, the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 .

[0344] In the case where the motor 50 rotates due to inertia (in the case of FG short-circuit fault), for the control circuit 12D in a normal state, even if the input of the drive control signal Sca stops, the input of the position detection signals hp and hn will change, and the output of the comparator 1241 will be switched, so the FG signal with a duty cycle of 50% is output, and it does not change to the power saving state. However, for the control circuit 12D in the FG short-circuit fault, the input of the position detection signals hp and hn does not change, and the output of the comparator 1241 does not switch (low level), so after the third period Ts3, it changes to the power saving state from the state where the input of the drive control signal Sca stops and the next switching of the output of the comparator 1241 does not occur. As a result, the synthesized signal Si is a duty cycle of 50% corresponding to the FG output from the normal motor drive circuit 10D.

[0345] On the other hand, when the motor 50 is not rotating (when the rotor is locked), the input of the position detection signals hp and hn does not change, so the control circuits 12D_1 and 12D_2 stop the input of the drive control signals Sca1 and Sca2, and quickly start timing, and after the third period Ts3, the power saving state is changed, so that the terminals FG1 and FG2 are in a high impedance state (making the signals fg1 and fg2 high level). As a result, the synthesized signal Si is high level.

[0346] After entering the power saving mode, the drive control circuit 20 determines whether a specified change of the synthetic signal Si is detected within the period of the specified rotation detection time (the fourth period Ts4) (step S104). For example, the fourth period Ts4 is a time longer than the second period Ts2. In the following description, the fourth period Ts4 is set to be equal to the second period Ts2.

[0347] Here, the first rising edge of the composite signal Si is generated by the cutoff of the supply of the internal power supply voltage due to the transition to the power saving state, and is therefore processed as a change in the input of the composite signal Si.

[0348] When the predetermined change of the composite signal Si is not detected (step S104 : No), the drive control circuit 20 determines that the motor 50 is in the locked state, and outputs the state signal So indicating that the fan 100D is in the locked state to the host device 500 (step S105 ).

[0349] Here, in order to distinguish between the locked state and the FG fault state, the drive control circuit 20 may output the state signal So as the power supply voltage Vcc (high level) in the locked state. After that, the drive control circuit 20 enters the rotor locked mode (step S106), and after waiting for the passage of the period (fifth period Ts5) of the prescribed rotor locked restart time (step S107), the rotor locked restart process (step S900) is started. Specifically, as the rotor locked restart process, the drive control circuit 20 enters the stop waiting mode (step S30), and the motor 50 is automatically restored from the start.

[0350] On the other hand, when a predetermined change in the composite signal Si is detected within the fourth period Ts4 (step S104: Yes), the drive control circuit 20 determines that either the motor drive circuit 10D_1 or 10D_2 is in the FG failure state caused by the FG short-circuit failure (step S108). Thereafter, the drive control circuit 20 executes the third FG failure determination process (S300).

[0351] Here, the third FG fault determination process (an example of the second determination process) refers to a process for determining the motor drive circuit 10D in the FG fault state among the two systems of the motor drive circuits 10D, and continuing the forward rotation of the motor 50 while monitoring the rotation speed of the motor 50 using only the motor drive circuit 10D in the normal state. The specific content of the third FG fault determination process will be described later.

[0352] Fig. 271 is an example of a timing diagram showing drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and synthesized signal Si when the motor drive circuits 10D_1, 10D_2 are in a normal state and the motor 50 is in a locked state. Fig. 27 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0353] like Fig. 27 As shown, at time t1, when entering the startup waiting mode from the stop mode ( Fig. 22 In step S10), the drive control circuit 20 outputs drive control signals Sca1 and Sca2 that specify the start-up duty ratio (step S11).

[0354] After that, the motor driving circuits 10D_1 and 10D_2 drive the motor 50 based on the driving control signals Sca1 and Sca2, and the motor 50 starts to rotate. At this time, the motor driving circuits 10D_1 and 10D_2 are in a normal state, but the motor 50 is in a locked state, and the input of the position detection signals hp and hn does not change, so the signals fg1 and fg2 are fixed to either a high level or a low level.

[0355] like Fig. 22 As shown, after the drive control circuit 20 enters the startup waiting mode, if the specified change of the composite signal Si is not detected within the first time period Ts1, the first FG fault determination process (step S100) is started. Fig. 27 As shown, after entering the startup waiting mode, at time t2 after the first period Ts1 has passed, the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 and enters the power saving waiting mode ( Fig.23 Step S101).

[0356] As described above, the motor drive circuits 10D_1 and 10D_2 are in a normal state, but the motor 50 is in a locked state, so the output of the signals fg1 and fg2 does not change. As a result, at the time t3 after the third period Ts3 from the time t2 when the input of the drive control signals Sca1 and Sca2 stops, the drive control circuit 20 enters the power saving mode, and the motor drive circuits 10D_1 and 10D_2 (control circuits 12D_1 and 12D_2) are both converted to the power saving state (steps S102 and S103). As a result, the terminals FG1 and FG2 of the motor drive circuits 10D_1 and 10D_2 are in a high impedance state, and the synthesized signal Si is at a high level.

[0357] After entering the power saving mode, if the specified change of the composite signal Si is not detected in the fourth period Ts4, but the composite signal Si fixed at the high level is detected, at time t4 after the fourth period Ts4 has passed, the drive control circuit 20 determines that the motor 50 is in the locked state (step S105). Thereafter, the drive control circuit 20 starts the rotor locked restart process at time t4 (S900).

[0358] In this way, after the drive control circuit 20 detects that the composite signal Si is a signal fixed at either a high level or a low level, it does not detect the specified change of the composite signal Si after stopping the output of the drive control signals Sca1 and Sca2 to the motor drive circuits 10D of the two systems and converting the motor drive circuits 10D of the two systems into a power saving state. When it is a high level, it can be determined that the motor 50 is in a locked state.

[0359] Fig.28 This is an example of a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG fault state caused by an FG short circuit fault. Fig.28 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0360] like Fig.28 As shown, at time t1, when the stop mode enters the start-up waiting mode ( Fig. 22 In step S10), the drive control circuit 20 outputs drive control signals Sca1 and Sca2 that specify the start-up duty ratio (step S11).

[0361] After that, the motor driving circuits 10D_1 and 10D_2 drive the motor 50 based on the driving control signals Sca1 and Sca2, and the motor 50 starts to rotate. At this time, the motor driving circuit 10D_1 is in a normal state, so the input changes of the position detection signals hp and hn are input to the motor driving circuit 10D_1 according to the rotation of the motor 50, and the motor driving circuit 10D_1 outputs a signal fg1 with a duty ratio of 50% from the terminal FG1.

[0362] On the other hand, the motor driving circuit 10D_2 is in the FG failure state due to the FG short-circuit failure, and therefore outputs a low-level signal fg2 from the terminal FG2. As a result, the composite signal Si output from the composite signal generating circuit 21 is at a low level.

[0363] like Fig. 22As shown, after the drive control circuit 20 enters the startup waiting mode, if the specified change of the composite signal Si is not detected within the first time period Ts1, the first FG fault determination process (step S100) is started. Fig.28 As shown, after entering the startup waiting mode, at time t2 after the first period Ts1, the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 and enters the power saving waiting mode ( Fig.23 Step S101).

[0364] like Fig.28 As shown, after time t2, the motor 50 rotates due to inertia, so the motor driving circuit 10D_1 is in a normal state and outputs a signal fg1 with a duty ratio of 50%. Therefore, the motor driving circuit 10D_1 does not switch to the power saving state while outputting the signal fg1.

[0365] On the other hand, the motor drive circuit 10D_2 is in the FG fault state caused by the FG short-circuit fault, so the output of the signal fg2 is fixed at a low level. As a result, at the time t3 after the third period Ts3 from the time t2 when the input of the drive control signal Sca2 stops, the drive control circuit 20 enters the power saving mode, and the motor drive circuit 10D_2 is converted into the power saving state (steps S102, S103). As a result, the terminal FG2 of the motor drive circuit 10D_2 is in a high impedance state, and the synthesized signal Si is a duty ratio of 50% corresponding to the signal fg1.

[0366] After entering the power saving mode, at the time tb when the specified change of the composite signal Si is detected in the fourth time period Ts4, the drive control circuit 20 determines that either the motor drive circuit 10D_1 or 10D_2 is in the FG fault state caused by the FG short circuit fault (step S108). After that, the drive control circuit 20 starts the third FG fault determination process (S300) described later at the time t4. At this time, the drive control circuit 20 can start the third FG fault determination process immediately after the determination at the time tb without waiting for the end of the fourth time period Ts4.

[0367] In this way, after the drive control circuit 20 detects that the synthetic signal Si is at a low level, it stops outputting the drive control signals Sca1 and Sca2 to the motor drive circuits 10D of the two systems. When a specified change in the synthetic signal Si is detected after the motor drive circuit 10D in the FG fault state is switched to the power saving state, it can be determined that either of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state caused by the FG short-circuit fault.

[0368] Next, use Fig.24 , the second FG failure determination process (S200) is described.

[0369] As described above, the second FG failure determination process is a process for determining the FG failure state caused by the FG open-circuit failure of the motor drive circuit 10D.

[0370] like Fig.24 As shown, in the second FG fault determination process, first, the duty cycle of the composite signal Si is 50% (refer to Fig. 22 Therefore, the drive control circuit 20 determines that one of the motor drive circuits 10D_1 and 10D_2 is in the FG failure state caused by the FG open circuit failure (step S201).

[0371] Next, in the same process as the first FG fault determination process, the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 (step S202). After that, the drive control circuit 20 waits for the third period Ts3 to pass (step S203). After the third period Ts3 has passed, the drive control circuit 20 enters the power saving mode (step S204). After that, the drive control circuit 20 performs the third FG fault determination process (S300).

[0372] It should be noted that in Fig.24 In the embodiment, after step S201, the driving control circuit 20 may not execute steps S202 to S204, but execute the third FG failure determination process (S300), instead of sharing the processing flow with the first FG failure determination process.

[0373] Fig.29 This is an example of a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the synthesized signal Si when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG fault state caused by an FG open circuit fault. Fig.29 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0374] like Fig.29 As shown, at time t1, when the stop mode enters the start-up waiting mode ( Fig. 22 In step S10), the drive control circuit 20 outputs drive control signals Sca1 and Sca2 that specify the start-up duty ratio (step S11).

[0375] After that, the motor drive circuits 10D_1 and 10D_2 drive the motor 50 based on the drive control signals Sca1 and Sca2, and the motor 50 starts to rotate. At this time, the motor drive circuit 10D_1 is in a normal state, so the changes in the input of the position detection signals hp and hn are input to the motor drive circuit 10D_1 according to the rotation of the motor 50, and the motor drive circuit 10D_1 outputs a signal fg1 with a duty ratio of 50% from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in an FG fault state caused by an FG open circuit fault, so a high-level signal fg2 is output from the terminal FG2. As a result, the synthesized signal Si output from the synthesized signal generation circuit 21 is a signal with a duty ratio of 50% corresponding to the signal fg1.

[0376] like Fig.29 As shown, after entering the startup waiting mode, the drive control circuit 20 detects the specified change of the synthetic signal Si within the first time period Ts1, and at the moment tc1 when the duty cycle is detected to be 50%, it is determined that either the motor drive circuit 10D_1 or 10D_2 is in the FG fault state caused by the FG open circuit fault (step S201).

[0377] Then, at time t2, the drive control circuit 20 stops outputting the drive control signals Sca1 and Sca2 and enters a power saving standby mode (step S202). Fig.29 As shown, after time t2, the motor 50 rotates due to inertia, so the motor driving circuit 10D_1 is in a normal state and outputs a signal fg1 with a duty ratio of 50%. Therefore, the motor driving circuit 10D_1 does not switch to the power saving state while outputting the signal fg1.

[0378] On the other hand, the motor driving circuit 10D_2 is in the FG fault state caused by the FG open circuit fault, so the output of the signal fg2 is fixed at a high level. As a result, at the time t3 after the third period Ts3 from the time t2 when the input of the driving control signal Sca2 stops, the driving control circuit 20 enters the power saving mode, and the motor driving circuit 10D_2 is converted into the power saving state ( Fig.24 Then, at time t4, the drive control circuit 20 starts the third FG fault determination process (S300) described later. At this time, the drive control circuit 20 can start the third FG fault determination process immediately after the determination at time tc1 without waiting for the first period Ts1 to end.

[0379] In this way, the specified change of the synthetic signal Si is detected during the time period when the drive control signals Sca1 and Sca2 are output to the motor drive circuits 10D of the two systems. When the duty cycle is detected to be 50%, the drive control circuit 20 determines that either one of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state caused by the FG open circuit fault.

[0380] It should be noted that if Fig.29 As shown, not only during the startup waiting mode period, the drive control circuit 20 can also detect the time tc2 of the composite signal Si with a duty cycle of 50% after entering the power saving mode in the process of sharing the processing with the first FG fault determination process, and determine that either of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state caused by the FG open circuit fault. In this case, the drive control circuit 20 can start the third FG fault determination process described later immediately after the determination at the time tc2, without waiting for the end of the fourth period Ts4.

[0381] Next, use FIG. 25A to FIG. 25D , the third FG failure determination process (S300) is described.

[0382] As described above, the third FG fault determination process is a process for determining the motor drive circuit 10D in the FG fault among the motor drive circuits 10D of the two systems, and continuing the forward rotation of the motor 50 while monitoring the rotation speed using only the motor drive circuit 10D in the normal state. Through this process, the motor drive circuit 10D in the FG fault can be determined regardless of whether the FG fault state is the FG short-circuit fault or the FG open-circuit fault, or even if the FG fault state is switched.

[0383] As described above, when it is determined by the first FG fault determination processing (S100) that either of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state caused by an FG short-circuit fault, or when it is determined by the second FG fault determination processing (S200) that either of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state caused by an FG open-circuit fault, the drive control circuit 20 performs the third FG fault determination processing (S300).

[0384] like Fig.25A As shown, in the third FG failure determination process, first, the drive control circuit 20 enters the first system single-side trial mode (step S301).

[0385] Here, the first system unilateral trial mode refers to an operation mode in which the motor drive circuit 10D of one (the first system) of the two systems' motor drive circuits 10D_1 and 10D_2 is operated at a predetermined fixed duty cycle (trial duty cycle) in order to determine the location where the FG fault occurs, and the motor drive circuit 10D of the other (the second system) is switched to a power saving state.

[0386] In the following description, operating one of the two motor drive circuits 10D_1 and 10D_2 and shifting the other motor drive circuit 10D to a power saving state is referred to as “one-side driving”.

[0387] In the following description, as the first system one-side test mode, the case where the motor drive circuit 10D_1 of the motor drive circuits 10D_1 and 10D_2 is driven on one side is described as an example.

[0388] In the first system unilateral trial mode, first, the drive control circuit 20 outputs the drive control signal Sca1 that specifies the trial duty cycle (step S302). At this time, the drive control signal Sca2 is not output. Here, the trial duty cycle can be the same as the startup duty cycle. After that, the drive control circuit 20 waits for the time period (sixth time period Ts6) that specifies the unilateral trial time to pass (step S303). At this time, the sixth time period Ts6 is set to a time longer than the second time period Ts2. In the following description, the sixth time period Ts6 is set to a time equal to the third time period Ts3.

[0389] Next, the drive control circuit 20 determines whether a specified change in the composite signal Si is detected within the time period (seventh time period Ts7) of the specified single-side rotation detection time (step S304). For example, the seventh time period Ts7 is set to a time period longer than the second time period Ts2. When a specified change in the composite signal Si is detected (step S304: yes), the drive control circuit 20 temporarily determines that the first motor drive circuit 10D_1 is in a normal state, sets a first normal flag, and acquires a first starting speed according to the cycle of the composite signal Si.

[0390] Here, the first falling edge of the composite signal Si is sometimes generated by restoring the internal power supply voltage due to the release of the power saving state, and therefore is not processed as the input of the composite signal Si. That is, the drive control circuit 20 determines that the composite signal Si is input from the time point when the specified change of the composite signal Si is detected, and starts measuring the period and duty cycle of the composite signal Si. After that, the drive control circuit 20 obtains the first final speed according to the final period of the composite signal Si in the seventh time period Ts7, calculates the first speed ratio (step S305), and enters step S307.

[0391] The first speed ratio is a ratio of the first final speed to the first starting speed when the first starting speed is obtained. For example, the first speed ratio is a percentage (%) obtained by dividing the first final speed by the first starting speed. Therefore, when the rotation speed of the motor 50 is decelerated from the beginning to the end of the seventh period Ts7, it is a value less than 100.

[0392] On the other hand, when the specified change of the composite signal Si is not detected in the seventh period Ts7 (step S304: No), the drive control circuit 20 determines that the first motor drive circuit 10D_1 is in the FG fault state caused by the FG short circuit fault, clears the first normal flag, and proceeds to step S307. At this time, the drive control circuit 20 does not calculate the first speed ratio.

[0393] At step S307 when the seventh period Ts7 ends, the drive control circuit 20 stops outputting the drive control signal Sca1. Thereafter, the drive control circuit 20 enters the second system single-side trial mode (step S311).

[0394] Here, the second system unilateral trial mode refers to an operation mode in which, in order to determine the location of occurrence of an FG fault, the motor drive circuit 10D of one of the two systems' motor drive circuits 10D_1 and 10D_2 that operates in the first system unilateral trial mode (the first system) is switched to a power saving state, and the motor drive circuit 10D of the other side (the second system) different from the motor drive circuit 10D is operated by specifying a trial duty cycle.

[0395] Here, as the second system one-side test mode, a case where the motor driving circuit 10D_2 of the motor driving circuits 10D_1 and 10D_2 is driven on one side will be described as an example.

[0396] In the second system single-side trial mode, first, the drive control circuit 20 outputs the drive control signal Sca2 of the prescribed trial duty ratio (step S312). At this time, the drive control signal Sca1 is not outputted. The drive control circuit 20 waits for the sixth period Ts6 to pass (step S313).

[0397] Next, the drive control circuit 20 determines whether a prescribed change in the synthetic signal Si is detected in the seventh period Ts7 (step S314). When a prescribed change in the synthetic signal Si is detected (step S314: yes), the drive control circuit 20 temporarily determines that the second motor drive circuit 10D_2 is in a normal state, sets a second normal flag, and acquires a second starting speed according to the cycle of the synthetic signal Si.

[0398] Here, the first falling edge of the composite signal Si is sometimes generated by restoring the internal power supply voltage due to the release of the power saving state, and is therefore not processed as the input of the composite signal Si. That is, the drive control circuit 20 determines that the composite signal Si is input from the time point when the specified change of the composite signal Si is detected, and starts measuring the period and duty cycle of the composite signal Si. After that, the drive control circuit 20 obtains the second final speed based on the final period of the composite signal Si in the seventh time period Ts7, calculates the second speed ratio (step S315), and proceeds to step S317.

[0399] The second speed ratio is a ratio of the second final speed to the second starting speed when the second starting speed is acquired. For example, the second speed ratio is a percentage (%) obtained by dividing the second final speed by the second starting speed. Therefore, when the rotation speed of the motor 50 is decelerated from the beginning to the end of the seventh period Ts7, it is a value less than 100.

[0400] On the other hand, if the specified change of the composite signal Si is not detected in the seventh period Ts7 (step S314: No), the drive control circuit 20 determines that the second motor drive circuit 10D_2 is in the FG fault state caused by the FG short circuit fault, clears the second normal flag, and proceeds to step S317. At this time, the second speed ratio is not calculated.

[0401] At step S317 at the end of the seventh period Ts7, the drive control circuit 20 stops outputting the drive control signal Sca2. Thereafter, the drive control circuit 20 enters the FG fault side determination mode ( Fig.25B Step S320).

[0402] like Fig.25B As shown, the FG fault side determination mode refers to a determination mode for determining the occurrence location of the FG fault based on the normal flag and speed ratio obtained in the first system and the second system. Specifically, when the single-side drive is in a normal state, the normal flag is set, and the speed is stabilized by specifying a trial duty ratio, so the speed ratio is improved. On the other hand, in the case of an FG fault, the normal flag is cleared, and for the motor 50 whose speed is decelerated due to inertia, it is sometimes in a state where the switching (commutation) to the energization direction of the coil 80 does not occur, but the rotation of the motor 50 is braked, so the speed ratio is reduced.

[0403] As the FG fault side determination mode, the drive control circuit 20 checks the first normal flag and the second normal flag or compares the first speed ratio with the second speed ratio in step S321 to determine whether the second system is in the FG fault state. When the first normal flag is set and the second normal flag is cleared (step S321: yes), the drive control circuit 20 determines that the first system is in the normal state and the second system is in the FG fault state caused by the FG short circuit fault, and enters step S322 to enter the single-side fault drive mode, thereby executing the first system single-side fault drive processing (S400). In addition, when the first speed ratio is greater than the second speed ratio and greater than the specified threshold value (step S321: yes), the drive control circuit 20 also determines that the first system is in the normal state and the second system is in the FG fault state caused by the FG open circuit fault, and enters step S322.

[0404] When the second system is not in the FG failure state (step S321 : No), the drive control circuit 20 proceeds to step S323 .

[0405] Next, as the FG fault side determination mode, when the second system is not in the FG fault state, the drive control circuit 20 checks the first normal flag and the second normal flag or compares the first speed ratio with the second speed ratio in step S323 to determine whether the first system is in the FG fault state.

[0406] When the first normal flag is cleared and the second normal flag is set (step S323: yes), the drive control circuit 20 determines that the first system is in an FG fault state caused by an FG short circuit fault, and the second system is in a normal state, and enters step S324 to enter the single-sided fault drive mode, thereby executing the second system single-sided fault drive processing (S500).

[0407] In addition, when the second speed ratio is greater than the first speed ratio and greater than the specified threshold (step S323: Yes), the drive control circuit 20 also determines that the first system is in the FG failure state caused by the FG open circuit failure, and the second system is in the normal state, and enters step S324.

[0408] Here, the single-side fault drive mode refers to an operation mode in which only the motor drive circuit 10D in the normal state of the two systems is operated, and the motor 50 is forced to rotate at a rotation speed that is not dependent on the speed command signal Sc. At this time, the motor drive circuit 10D in the normal state outputs an FG signal with a duty cycle of 50%, and the motor drive circuit 10D in the FG fault state is in a power saving state, so it outputs a high-level FG signal, and the synthetic signal generation circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the FG signal of the motor drive circuit 10D in the normal state. As a result, the drive control circuit 20 can continue the forward rotation of the fan motor while monitoring the rotation speed.

[0409] As the FG fault side determination mode, the drive control circuit 20 proceeds to step S325 to determine whether both sides are in the FG fault state or whether both sides have undergone the second FG fault determination process in the case where the normal flags of both sides are the same or the speed ratios are not significantly different in steps S321 and S323. When both sides are in the FG fault state, that is, when there is no normal operation (the first normal flag and the second normal flag are both cleared) or when the second FG fault determination process has been undergone (step 325: yes), the drive control circuit 20 determines that the motor 50 does not rotate due to rotor lock in each single-side trial mode, and thus determines that it is in the single-side fault lock state (step S326), and after waiting for the fifth period Ts5 to pass (step S327), the third FG fault determination process (S300) is restarted.

[0410] When both are driven normally (the first normal flag and the second normal flag are both set) and the first FG failure determination process is performed (step 325: No), the drive control circuit 20 considers that the fourth period Ts4 of the power saving mode of the first FG failure determination process ( Fig.23 In step S104 of FIG. 104, the rotor lock of the motor 50 is released for some reason, and the state of rotation due to inertia is mistakenly determined as an FG fault state caused by an FG short-circuit fault, and the motor 50 is re-determined to be in a locked state, and a state signal So indicating that the fan 100D is in a locked state is output to the host device 500 (step S330). After that, the drive control circuit 20 enters the rotor lock mode (step S331), and after waiting for the fifth period Ts5 to pass (step S332), the rotor lock restart process (S900) is performed.

[0411] Next, use Fig.25C , the first system single-side fault driving process (S400) is explained.

[0412] In step S401 , the drive control circuit 20 enters a single-side fault start-up waiting mode to operate the motor drive circuit 10D_1 operating in the first system single-side trial mode, and outputs a state signal So indicating that the motor drive circuit 10D_2 is in the FG fault state to the host device 500 .

[0413] Here, in order to distinguish between the locked state and the FG fault state, the drive control circuit 20 can output the state signal So as the ground voltage GND (low level) when in the FG fault state. In addition, at this time, the motor 50 can be driven by the single-sided motor drive circuit 10D, so the drive control circuit 20 can output the FG signal with a duty ratio of 50% as the state signal So in a period corresponding to the actual rotation speed of the motor 50 based on the synthetic signal Si generated by the synthetic signal generation circuit 21.

[0414] Next, the drive control circuit 20 generates a drive control signal Sca1 of a preset fixed duty ratio (single-side fault drive duty ratio) and supplies it to the motor drive circuit 10D_1 (step S402). Here, the single-side fault drive duty ratio may be the same as the trial duty ratio.

[0415] Afterwards, the drive control circuit 20 enters the single-side fault drive mode (step S404 ) after waiting for the third period Ts3 to elapse (step S403 ).

[0416] Next, the drive control circuit 20 outputs the drive control signal Sca1 of the prescribed single-side fault drive duty ratio (step S405 ). Thereafter, the drive control circuit 20 determines whether a prescribed change in the composite signal Si is detected within the second period Ts2 (step S406 ).

[0417] When the specified change of the composite signal Si is detected (step S406: Yes), the drive control circuit 20 determines that it is in a single-side fault drive state (step S407), and repeats steps S405 to S407. On the other hand, when the specified change of the composite signal Si is not detected (step S406: No), it is assumed that the motor 50 stops due to rotor lock (less than the minimum speed), and the drive control circuit 20 stops the output of the drive control signal Sca1 (step S408), determines that it is in a single-side fault lock state (step S409), and restarts the single-side fault drive after waiting for the fifth period Ts5 to pass (step S410).

[0418] Next, use Fig.25D , the second system single-side fault driving process (S500) is explained.

[0419] In step S501 , the drive control circuit 20 enters a single-side fault start-up waiting mode to activate the motor drive circuit 10D_2 operating in the second system single-side trial mode, and outputs a state signal So indicating that the motor drive circuit 10D_1 is in the FG fault state to the host device 500 .

[0420] Next, the drive control circuit 20 generates a drive control signal Sca2 that specifies the single-side fault drive duty ratio and provides it to the motor drive circuit 10D_2 (step S502). After that, the drive control circuit 20 waits for the third period Ts3 to pass (step S503) and then enters the single-side fault drive mode (step S504).

[0421] Next, the drive control circuit 20 outputs the drive control signal Sca2 of the prescribed single-side fault drive duty ratio (step S505 ). Thereafter, the drive control circuit 20 determines whether a prescribed change in the composite signal Si is detected within the second period Ts2 (step S506 ).

[0422] When the specified change of the composite signal Si is detected (step S506: Yes), the drive control circuit 20 determines that it is in a single-side fault drive state (step S507), and repeats steps S505 to S507. On the other hand, when the specified change of the composite signal Si is not detected (step S506: No), it is assumed that the motor 50 stops due to rotor lock (less than the minimum speed), and the drive control circuit 20 stops the output of the drive control signal Sca2 (step S508), determines that it is in a single-side fault locked state (step S509), and restarts the single-side fault drive after waiting for the fifth period Ts5 to pass (step S510).

[0423] Fig.30 This is an example of a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the composite signal Si when the motor drive circuit 10D_1 in the normal state is driven from one side, when the motor drive circuit 10D_1 in the normal state is in the FG fault state caused by the FG short circuit fault. Fig.30 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0424] like Fig.30 As shown, at time t10, the third FG failure determination process is started, whereby the drive control circuit 20 enters the first system single-side test mode ( Fig.25AIn the first system single-side trial mode, the drive control circuit 20 outputs the drive control signal Sca1 of the prescribed trial duty ratio (step S302). At this time, the drive control circuit 20 does not output the drive control signal Sca2.

[0425] Thus, the motor drive circuit 10D_1 is in a normal state, and the motor 50 is driven based on the drive control signal Sca1, and the motor 50 that rotates or stops due to inertia enters a rotation speed corresponding to the trial duty cycle. At this time, the input of the position detection signals hp and hn changes due to the rotation of the motor 50, so the motor drive circuit 10D_1 outputs a signal fg1 with a duty cycle of 50% from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in an FG fault state caused by an FG short-circuit fault, but maintains a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthetic signal generation circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg1. After that, the drive control circuit 20 waits for the sixth period Ts6 to pass (step S303).

[0426] Then, if Fig.30 As shown, at time t11 after the sixth period Ts6 has passed, the drive control circuit 20 waits for the seventh period Ts7 to pass, and determines whether the specified change of the synthesized signal Si is detected in the seventh period Ts7 (step S304). At this time, the motor drive circuit 10D_1 is in a normal state, and a signal fg1 with a duty cycle of 50% is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthesized signal generation circuit 21 outputs a synthesized signal Si with a duty cycle of 50% corresponding to the signal fg1. As a result, a specified change of the synthesized signal Si is detected in the seventh period Ts7 (step S304: Yes), and at time td1 when the specified change of the synthesized signal Si is detected, the drive control circuit 20 temporarily determines that the first motor drive circuit 10D_1 is in a normal state, sets the first normal flag, and obtains the first starting speed according to the cycle of the synthesized signal Si. Furthermore, at the final time td2 of detecting the cycle of the synthetic signal Si in the seventh period Ts7, the drive control circuit 20 obtains the first final speed according to the cycle of the synthetic signal Si and calculates the first speed ratio (step S305).

[0427] Then, if Fig.30 As shown, at time t12 after the seventh time period Ts7, the drive control circuit 20 stops the output of the drive control signal Sca1 (step S307), and enters the second system unilateral trial mode of unilaterally driving the second motor drive circuit 10D_2 from the first system unilateral trial mode of unilaterally driving the first motor drive circuit 10D_1 (step S311).

[0428] In the second system one-side trial mode, the drive control circuit 20 outputs the drive control signal Sca2 that specifies the trial duty ratio (step S312 ).

[0429] Thus, the motor 50 is attempted to be driven by the motor driving circuit 10D_2 instead of the motor driving circuit 10D_1, but the rotation of the motor 50 is not driven due to the FG fault, but continues due to inertia. At this time, the motor driving circuit 10D_1 is in a normal state, and the drive control signal Sca1 is not input, but the input of the position detection signals hp and hn changes, so it does not change to the power saving state, but outputs a signal fg1 with a duty cycle of 50% from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in an FG fault state caused by an FG short circuit fault, and the power saving state is released by inputting the drive control signal Sca2, so a low-level signal fg2 is output from the terminal FG2. Therefore, the synthesized signal Si output from the synthesized signal generating circuit 21 is a low level. The drive control circuit 20 waits for the sixth period Ts6 to pass (step S313).

[0430] Then, if Fig.30 As shown, at time t13 after the sixth period Ts6 has passed, the drive control circuit 20 waits for the seventh period Ts7 to pass, and determines whether a prescribed change in the composite signal Si is detected in the seventh period Ts7 (step S314). At this time, the motor drive circuit 10D_1 is in a normal state, and during the period when the motor 50 rotates due to inertia, the input of the position detection signals hp and hn changes, so the signal fg1 with a duty cycle of 50% is output from the terminal FG1.

[0431] On the other hand, the motor drive circuit 10D_2 is in the FG fault state caused by the FG short-circuit fault, and the low-level signal fg2 is output from the terminal FG2. Therefore, the synthesized signal Si output from the synthesized signal generation circuit 21 is low-level. As a result, the prescribed change of the synthesized signal Si is not detected in the seventh period Ts7 (step S314: No).

[0432] Then, if Fig.30 As shown in FIG. 1 , at time t14 after the seventh period Ts7 has passed, the drive control circuit 20 clears the second normal flag and determines that the second motor drive circuit 10D_2 is in the FG fault state caused by the FG short circuit fault (step S316). After that, the drive control circuit 20 stops outputting the drive control signal Sca2 (step S317) and enters the FG fault side determination mode ( Fig.25B Step S320).

[0433] In the FG fault side determination mode, after setting the first normal flag and clearing the second normal flag (step S321: Yes), the drive control circuit 20 determines that the motor drive circuit 10D_2 is in the FG fault state (step S322), and executes the first system single-side fault drive processing ( Fig.25C S400).

[0434] In the first system single-side fault drive process, the drive control circuit 20 enters the single-side fault start-up waiting mode (step S401), generates a drive control signal Sca1 that specifies the single-side fault drive duty ratio for the motor drive circuit 10D_1 and provides it to the motor drive circuit 10D_1 (step S402). As a result, the motor drive circuit 10D_1 drives the motor 50 based on the drive control signal Sca1. After that, the drive control circuit 20 waits for the third period Ts3 to pass (step S403).

[0435] Then, if Fig.30 As shown, at time t15 after the third period Ts3, the motor driving circuit 10D_2 changes to the power saving state. At this time, the motor driving circuit 10D_1 is in a normal state, and a signal fg1 with a duty cycle of 50% is output from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthetic signal generating circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg1. As a result, after time t15, the synthetic signal Si is a signal with a duty cycle of 50% corresponding to the signal fg1 until the motor 50 stops (less than the minimum speed).

[0436] Afterwards, the drive control circuit 20 enters the single-sided fault drive mode (step S404), continues to output the drive control signal Sca1 of the specified single-sided fault drive duty cycle (step S405), and continues the forward rotation of the motor 50 (steps S405 to S407) while only using the normal motor drive circuit 10D_1 to monitor the rotation speed.

[0437] Thus, when one of the two systems of motor drive circuits 10D has an FG short-circuit fault, even when the motor drive circuit 10D_1 in a normal state is driven from one side first, the drive control circuit 20 can distinguish between the normal motor drive circuit 10D and the FG short-circuit fault motor drive circuit 10D based on the composite signal Si. Thus, the drive control circuit 20 can continue the forward rotation of the motor 50 while monitoring the rotation speed using only the normal motor drive circuit 10D.

[0438] Fig.31This is an example of a timing diagram showing the FG fault state of the motor drive circuit 10D_1 caused by the FG short-circuit fault, and when the motor drive circuit 10D_2 is in a normal state, the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the composite signal Si when the motor drive circuit 10D_1 in the FG fault state is driven from one side. Fig.31 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0439] like Fig.31 As shown, at time t10, the third FG failure determination process is started, whereby the drive control circuit 20 enters the first system single-side test mode ( Fig.25A In the first system single-side trial mode, the drive control circuit 20 outputs the drive control signal Sca1 of the prescribed trial duty ratio (step S302). At this time, the drive control circuit 20 does not output the drive control signal Sca2.

[0440] Thus, the motor drive circuit 10D_1 is in the FG fault state caused by the FG short-circuit fault, and the power saving state is released by inputting the drive control signal Sca1, so the low-level signal fg1 is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in a normal state. Therefore, during the period when the drive control signal Sca2 is not input to the motor drive circuit 10D_2, but the motor 50 rotates due to inertia, the input of the position detection signals hp and hn changes due to the rotation of the motor 50, so the motor drive circuit 10D_2 does not change to the power saving state, but outputs a signal fg2 with a duty cycle of 50% from the terminal FG2. Therefore, the synthetic signal Si output from the synthetic signal generation circuit 21 is low. After that, the drive control circuit 20 waits for the sixth period Ts6 to pass (step S303).

[0441] Then, if Fig.31As shown, at time t11 after the sixth time period Ts6 has passed, the drive control circuit 20 waits for the seventh time period Ts7 to pass, and determines whether the specified change of the composite signal Si is detected in the seventh time period Ts7 (step S304). At this time, the motor drive circuit 10D_1 is in the FG fault state caused by the FG short circuit fault, and the low-level signal fg1 is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in a normal state. During the period when the motor 50 rotates due to inertia, the input of the position detection signals hp and hn changes, so the signal fg2 with a duty cycle of 50% is output from the terminal FG2. Therefore, the composite signal Si output from the composite signal generation circuit 21 is low. As a result, the specified change of the composite signal Si is not detected in the seventh time period Ts7 (step S304: No).

[0442] Then, if Fig.31 As shown, at time t12 after the seventh period Ts7, the drive control circuit 20 clears the first normal flag and determines that the motor drive circuit 10D_1 on the first system side is in the FG fault state caused by the FG short circuit fault (step S306). After that, the drive control circuit 20 stops outputting the drive control signal Sca1 (step S307), and enters the second system single-side trial mode of single-side driving the second motor drive circuit 10D_2 from the first system single-side trial mode of single-side driving the first motor drive circuit 10D_1 (step S311).

[0443] In the second system one-side trial mode, the drive control circuit 20 outputs the drive control signal Sca2 that specifies the trial duty ratio (step S312 ).

[0444] Thus, the motor 50 is driven by the motor driving circuit 10D_2 instead of the motor driving circuit 10D_1, so that the rotation of the motor 50 continues. At this time, the motor driving circuit 10D_1 is in the FG fault state caused by the FG short circuit fault, and the low-level signal fg1 is output from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in a normal state, and the motor 50 is driven based on the drive control signal Sca2, and the motor 50 that rotates or stops due to inertia enters the rotation speed under this duty cycle. At this time, the input of the position detection signals hp and hn changes due to the rotation of the motor 50, so the motor driving circuit 10D_2 outputs a signal fg2 with a duty cycle of 50% from the terminal FG2. Therefore, the synthetic signal Si output from the synthetic signal generating circuit 21 is low. The drive control circuit 20 waits for the sixth period Ts6 to pass (step S313).

[0445] Then, if Fig.31As shown, at time t13 after the sixth period Ts6 has passed, the motor driving circuit 10D_1 changes to the power saving state, and the driving control circuit 20 waits for the seventh period Ts7 to pass, and determines whether the specified change of the synthetic signal Si is detected in the seventh period Ts7 (step S314). At this time, the motor driving circuit 10D_1 is in the power saving state, so the high-level signal fg1 is output from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in the normal state, and the signal fg2 with a duty ratio of 50% is output from the terminal FG2. Therefore, the synthetic signal generating circuit 21 outputs the synthetic signal Si with a duty ratio of 50% corresponding to the signal fg2. As a result, the specified change of the synthetic signal Si is detected in the seventh period Ts7 (step S314: Yes), and at the time te1 when the specified change of the synthetic signal Si is detected, the driving control circuit 20 temporarily determines that the second motor driving circuit 10D_2 is in the normal state, sets the second normal flag, and obtains the second starting speed according to the cycle of the synthetic signal Si. Furthermore, at the time te2 when the final period of the cycle of the synthetic signal Si in the seventh period Ts7 is detected, the drive control circuit 20 obtains the second final speed according to the cycle of the synthetic signal Si and calculates the second speed ratio (step S315 ).

[0446] Then, if Fig.31 As shown, at time t14 after the seventh period Ts7 has passed, the drive control circuit 20 stops outputting the drive control signal Sca2 (step S317) and enters the FG fault side determination mode ( Fig.25B Step S320).

[0447] In the FG fault side determination mode, after clearing the first normal flag and setting the second normal flag (step S323: Yes), the drive control circuit 20 determines that the motor drive circuit 10D_1 is in the FG fault state (step S324), and executes the second system single-side fault drive processing ( Fig.25D S500).

[0448] In the first system single-side fault drive process, the drive control circuit 20 enters the single-side fault start-up waiting mode (step S501), generates a drive control signal Sca2 that specifies the single-side fault drive duty ratio for the motor drive circuit 10D_2 and provides it to the motor drive circuit 10D_12 (step S502). As a result, the motor drive circuit 10D_2 drives the motor 50 based on the drive control signal Sca2. After that, the drive control circuit 20 waits for the third period Ts3 to pass (step S503).

[0449] Then, if Fig.31As shown, at time t15 after the third period Ts3 has passed, the motor driving circuit 10D_1 maintains the power saving state. At this time, the motor driving circuit 10D_1 is in the power saving state, so the high-level signal fg1 is output from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in the normal state, and the signal fg2 with a duty cycle of 50% is output from the terminal FG2. Therefore, the synthetic signal generating circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg2. As a result, after time t15, the synthetic signal Si is a signal with a duty cycle of 50% corresponding to the signal fg2 until the motor 50 stops (less than the minimum speed).

[0450] Afterwards, the drive control circuit 20 enters the single-sided fault drive mode (step S504), continues to output the drive control signal Sca2 that specifies the single-sided fault drive duty cycle (step S505), and continues the forward rotation of the motor 50 (steps S505 to S507) while only using the normal motor drive circuit 10D_2 to monitor the rotation speed.

[0451] Thus, when one of the two systems of motor drive circuits 10D is in the FG short-circuit fault, even when the motor drive circuit 10D_1 in the FG fault state is driven from one side first, the drive control circuit 20 can distinguish between the normal motor drive circuit 10D and the motor drive circuit 10D in the FG short-circuit fault based on the synthetic signal Si. Thus, the drive control circuit 20 can continue the forward rotation of the motor 50 only by the normal motor drive circuit 10D while monitoring the rotation speed.

[0452] Fig.32 This is an example of a timing diagram showing the drive control signals Sca1, Sca2 (terminals SCA1, SCA2), signals fg1, fg2 (terminals FG1, FG2) and the composite signal Si when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG fault state caused by an FG open circuit fault. Fig.32 In the diagram, the vertical axis represents the voltage or logic value of each signal, and the horizontal axis represents time.

[0453] like Fig.32 As shown, at time t10, the third FG failure determination process is started, whereby the drive control circuit 20 enters the first system single-side test mode ( Fig.25A In the first system single-side trial mode, the drive control circuit 20 outputs the drive control signal Sca1 of the prescribed trial duty ratio (step S302). At this time, the drive control circuit 20 does not output the drive control signal Sca2.

[0454] Thus, the motor drive circuit 10D_1 is in a normal state, and the motor 50 is driven based on the drive control signal Sca1, and the motor 50 that rotates or stops due to inertia enters the rotation speed under the duty cycle. At this time, the input of the position detection signals hp and hn changes due to the rotation of the motor 50, so the motor drive circuit 10D_1 outputs a signal fg1 with a duty cycle of 50% from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in an FG fault state caused by an FG open circuit fault, and maintains a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthetic signal generation circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg1. After that, the drive control circuit 20 waits for the sixth period Ts6 to pass (step S303).

[0455] Then, if Fig.32 As shown, at time t11 after the sixth period Ts6 has passed, the drive control circuit 20 waits for the seventh period Ts7 to pass, and determines whether the specified change of the synthesized signal Si is detected in the seventh period Ts7 (step S304). At this time, the motor drive circuit 10D_1 is in a normal state, and a signal fg1 with a duty cycle of 50% is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthesized signal generation circuit 21 outputs a synthesized signal Si with a duty cycle of 50% corresponding to the signal fg1. As a result, a specified change of the synthesized signal Si is detected in the seventh period Ts7 (step S304: Yes), and at time tf1 when the specified change of the synthesized signal Si is detected, the drive control circuit 20 temporarily determines that the first motor drive circuit 10D_1 is in a normal state, sets the first normal flag, and obtains the first starting speed according to the cycle of the synthesized signal Si. Furthermore, at the final time tf2 of detecting the cycle of the synthetic signal Si in the seventh period Ts7, the drive control circuit 20 obtains the first final speed according to the cycle of the synthetic signal Si and calculates the first speed ratio (step S305).

[0456] Then, if Fig.32 As shown, at time t12 after the seventh time period Ts7, the drive control circuit 20 stops the output of the drive control signal Sca1 (step S307), and enters the second system unilateral trial mode of unilaterally driving the second motor drive circuit 10D_2 from the first system unilateral trial mode of unilaterally driving the first motor drive circuit 10D_1 (step S311).

[0457] In the second system one-side trial mode, the drive control circuit 20 outputs the drive control signal Sca2 that specifies the trial duty ratio (step S312 ).

[0458] Thus, the motor 50 is attempted to be driven by the motor driving circuit 10D_2 instead of the motor driving circuit 10D_1, but the rotation of the motor 50 is not driven due to the FG fault, but continues due to inertia. At this time, the motor driving circuit 10D_1 is in a normal state, and the drive control signal Sca1 is not input, but the input of the position detection signals hp and hn changes, so the signal fg1 with a duty cycle of 50% is input from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in an FG fault state caused by an FG open circuit fault, and the drive control signal Sca2 is input, thereby releasing the power saving state, but a high-level signal fg2 is output from the terminal FG2. Therefore, the synthetic signal generation circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg1. The drive control circuit 20 waits for the sixth period Ts6 to pass (step S313).

[0459] Then, if Fig.32 As shown, at time t13 after the sixth period Ts6 has passed, the drive control circuit 20 waits for the seventh period Ts7 to pass, and determines whether a prescribed change in the composite signal Si is detected within the seventh period Ts7 (step S314). At this time, the motor drive circuit 10D_1 is in a normal state, and the input of the position detection signals hp and hn changes during the period when the motor 50 rotates due to inertia, so it does not change to a power saving state, and a signal fg1 with a duty cycle of 50% is output from the terminal FG1. On the other hand, the motor drive circuit 10D_2 is in an FG fault state caused by an FG open circuit fault, and a high-level signal fg2 is output from the terminal FG2. Therefore, the composite signal generation circuit 21 outputs a composite signal Si with a duty cycle of 50% corresponding to the signal fg1. As a result, a prescribed change of the synthetic signal Si is detected in the seventh period Ts7 (step S314: Yes), and at the time tf3 when the prescribed change of the synthetic signal Si is detected, the drive control circuit 20 temporarily determines that the second motor drive circuit 10D_2 is in a normal state, sets a second normal flag, and obtains a second starting speed according to the cycle of the synthetic signal Si. In addition, at the time tf4 when the final cycle of the synthetic signal Si in the seventh period Ts7 is detected, the drive control circuit 20 obtains a second final speed according to the cycle of the synthetic signal Si and calculates a second speed ratio (step S315).

[0460] Then, if Fig.32 As shown, at time t14 after the seventh period Ts7 has passed, the drive control circuit 20 stops outputting the drive control signal Sca2 (step S317) and enters the FG fault side determination mode ( Fig.25B Step S320).

[0461] In the FG fault side determination mode, the first normal flag is set, and the second normal flag is set, but the rotation speed is stable due to driving, so the first speed ratio is high, and the rotation speed is decelerated due to inertia, so the second speed ratio is low (step S321: yes), so the drive control circuit 20 determines that the motor drive circuit 10D_2 is in the FG fault state (step S322), and executes the first system single-side fault drive processing ( Fig.25C S400).

[0462] In the first system single-side fault drive process, the drive control circuit 20 enters the single-side fault start-up waiting mode (step S401), generates a drive control signal Sca1 that specifies the single-side fault drive duty ratio for the motor drive circuit 10D_1 and provides it to the motor drive circuit 10D_1 (step S402). As a result, the motor drive circuit 10D_1 drives the motor 50 based on the drive control signal Sca1. After that, the drive control circuit 20 waits for the third period Ts3 to pass (step S403).

[0463] Then, if Fig.32 As shown, at time t15 after the third period Ts3, the motor driving circuit 10D_2 changes to the power saving state. At this time, the motor driving circuit 10D_1 is in a normal state, and a signal fg1 with a duty cycle of 50% is output from the terminal FG1. On the other hand, the motor driving circuit 10D_2 is in a power saving state, so a high-level signal fg2 is output from the terminal FG2. Therefore, the synthetic signal generating circuit 21 outputs a synthetic signal Si with a duty cycle of 50% corresponding to the signal fg1. As a result, after time t15, the synthetic signal Si is a signal with a duty cycle of 50% corresponding to the signal fg1 until the motor 50 stops (less than the minimum speed).

[0464] Afterwards, the drive control circuit 20 enters the single-sided fault drive mode (step S404), and continues to output the drive control signal Sca1 of the specified single-sided fault drive duty cycle (step S405). While monitoring the rotation speed, the forward rotation of the motor 50 is continued only through the normal motor drive circuit 10D_1 (steps S405 to S407).

[0465] In this way, when either of the motor drive circuits 10D of the two systems has an FG open circuit fault, the motor drive circuits 10D are driven one after another in the single-sided trial mode, so that the drive control circuit 20 can determine the motor drive circuit 10D that is normal and the motor drive circuit 10D that is in the FG open circuit fault based on the synthetic signal Si, and can continue the forward rotation of the motor 50 only through the motor drive circuit 10D that is normal while monitoring the rotation speed.

[0466] As described above, the motor drive control device 1D of embodiment 3 causes at least one of the motor drive circuits 10D_1, 10D_2 to be converted into a high level state where it cannot output signals fg1, fg2 when the synthetic signal Si indicates a specified logical value (low level or high level). Based on the synthetic signal Si at this time, the first FG fault judgment processing is performed to determine whether any one of the motor drive circuits 10D_1, 10D_2 is in an FG fault state (for example, an FG short circuit fault) where it cannot normally output signals fg1, fg2, or is in a locked state where the motor 50 cannot rotate.

[0467] Thus, when at least one of the plurality of motor drive circuits 10D is in an FG short-circuit fault, by making the motor drive circuit 10D turn to a high level state in which the FG signal cannot be output, it is possible to generate a synthetic signal Si without being affected by the FG signal of the motor drive circuit 10D in the FG short-circuit fault. That is, it is possible to generate a synthetic signal Si corresponding only to the FG signal from the motor drive circuit 10D in which the FG short-circuit fault has not occurred. Thus, it is possible to appropriately determine whether any of the motor drive circuits 10D_1 and 10D_2 is in an FG fault state (for example, an FG short-circuit fault) in which the signals fg1 and fg2 cannot be normally output, or in a locked state in which the motor 50 cannot rotate.

[0468] like Fig.28 As shown, when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG fault state caused by an FG short circuit fault, after time t3, the motor drive circuit 10D_2 is converted into a high level state in which the FG signal cannot be output, thereby the synthetic signal Si is a signal corresponding to the FG signal from the motor drive circuit 10D in which the FG short circuit fault does not occur.

[0469] On the other hand, Fig. 27 As shown, when the motor 50 is in rotor lock, the motor drive circuits 10D_1 and 10D_2 are switched to a high level state where they cannot output the FG signal after time t3, whereby the synthesized signal Si is fixed at a high level.

[0470] Thus, when the composite signal Si is at a low level, by switching at least one of the motor drive circuits 10D to a high level state where the FG signal cannot be output, it is possible to appropriately determine whether one of the motor drive circuits 10D_1 and 10D_2 has an FG short circuit fault or the motor 50 is in rotor lock.

[0471] In addition, as described above, when the motor drive control device 1D of embodiment 3 determines that any one of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state, it drives the motor drive circuits 10D_1 and 10D_2 one by one in sequence, and performs the third FG determination processing based on the synthetic signal Si at this time to determine which one of the motor drive circuits 10D_1 and 10D_2 is in the FG fault state.

[0472] For example, Fig.30 As shown, when the motor drive circuit 10D_1 is in a normal state and the motor drive circuit 10D_2 is in an FG fault state caused by an FG short-circuit fault, the motor drive circuit 10D_1 is driven unilaterally during the period from time t10 to time t12, so that the motor drive circuit 10D_2 is maintained in a high level state (power saving state) where the FG signal cannot be output, and thus the synthesized signal Si is a signal corresponding to the signal fg1 from the motor drive circuit 10D_1 in the normal state. Next, during the period from time t12 to time t14, the motor drive circuit 10D_2 is driven unilaterally and the power saving state is released, but it is in an FG fault state caused by an FG short-circuit fault, so the synthesized signal Si is a low level.

[0473] In this way, by sequentially monitoring the synthesized signal Si when the motor driving circuits 10D_1 and 10D_2 are driven on one side, it is possible to easily determine which of the motor driving circuits 10D_1 and 10D_2 has an FG short-circuit fault.

[0474] Furthermore, after distinguishing the motor drive circuit 10D in the FG failure state caused by the FG short-circuit failure and the motor drive circuit 10D in the normal state in the third FG determination process, the motor drive control device 1D drives the motor 50 using only the motor drive circuit 10D in the normal state.

[0475] Thus, even when an abnormality occurs in the fan 100D (motor 50), the driving state of the motor 50 can be determined, and the normal rotation of the fan 100D can be continued while the rotation speed is monitored.

[0476] In addition, if Fig. 20As described above, each motor driving circuit 10D_1, 10D_2 is configured to be able to switch to a power saving state in which at least a part of its internal circuit is operated and the output of the FG signal is fixed at a high level. Therefore, by switching the motor driving circuit 10D to the power saving state, the motor driving circuit 10D can be easily switched to a high level state in which the FG signal cannot be output. In addition, when the FG signal (signal fg1, fg2) from each motor driving circuit 10D_1, 10D_2 is not switched within a predetermined period of time, and the synthetic signal Si generated by the synthetic signal generating circuit 21 indicates a predetermined logical value, the drive control circuit 20 stops the output of the drive control signals Sca1, Sca2, so that the drive control signals Sca1, Sca2 are not input, and the input of the position detection signals hp, hn does not change, thereby the control unit 122 of each motor driving circuit 10D_1, 10D_2 can cut off the supply of the internal power supply voltage Vdd to the FG signal generating unit 124. Furthermore, the motor drive control device 1D can reduce the number of signal lines output from the motor drive circuits 10D_1 and 10D_2 to the drive control circuit 20 by including the synthetic signal generating circuit 21 , and can also reduce signal processing in the drive control circuit 20 .

[0477] Implementation Method 4

[0478] Fig.33 This is a block diagram showing the configuration of a fan according to a fourth embodiment.

[0479] The motor drive control device 1E of the fan 100E of embodiment 4 is different from the motor drive control device 1D of embodiment 3 in that it generates a synthetic signal Si using a lock detection signal indicating whether the motor 50 is in a locked state where it cannot rotate, in addition to the FG signal. It is the same as the motor drive control device 1D of embodiment 3 in other points.

[0480] like Fig.33 As shown, the control circuits 12E_1 and 12E_2 of the motor drive circuits 10E_1 and 10E_2 of the motor drive control device 1E generate and output lock detection signals ld1 and ld2 , respectively, in addition to the signals fg1 and fg2 .

[0481] Here, the lock detection signals ld1 and ld2 are signals indicating the result of determination of whether the motor 50 is locked. The control circuits 12E_1 and 12E_2 of the motor drive circuits 10E_1 and 10E_2 determine whether the motor 50 is locked based on the drive control signals Sca1 and Sca2 and the position detection signals hp and hn, for example, and output the determination result as the lock detection signals ld1 and ld2.

[0482] The lock detection signals ld1 and ld2 are binary signals, for example, when the lock detection signal ld1 pulled up by the power supply voltage Vcc is at a low level (ground voltage GND), it indicates that the motor 50 is in an unlocked state, and when the lock detection signal ld1 is at a high level (power supply voltage Vcc), it indicates that the motor 50 is in a locked state where it cannot rotate.

[0483] For example, when a general-purpose IC is used as the control circuits 12E_1 and 12E_2, a signal output by a lock detection function of the general-purpose IC can be used as the lock detection signals ld1 and ld2.

[0484] Fig.34 1 is a block diagram showing the internal structure of the control circuits 12E_1 and 12E_2 and the synthesized signal generating circuit 21A according to the fourth embodiment. Fig.34 1 , only the internal configuration of the control circuits 12E_1 and 12E_2 related to the generation of the FG signal and the lock detection signal is shown.

[0485] In addition to the functions of the control circuit 12D of the third embodiment, the control circuit 12E has the functions of generating the lock detection signals ld1 and ld2 based on the position detection signal. Specifically, the control circuit 12E_1 also has: a terminal LD1 for outputting the lock detection signal ld1; a lock detection circuit 125 for detecting the lock state in which the motor 50 cannot rotate and outputting the detection signal; and an output transistor Q1A for outputting the lock detection signal ld1 based on the detection signal. Similarly, the control circuit 12E_2 also has: a terminal LD2 for outputting the lock detection signal ld2; a lock detection circuit 125 for detecting the lock state in which the motor 50 cannot rotate and outputting the detection signal; and an output transistor Q2A for outputting the lock detection signal ld2 based on the detection signal.

[0486] The output transistor Q1A is connected between the terminal LD1 and the ground voltage GND as a first fixed potential, and the output transistor Q2A is connected between the terminal LD2 and the ground voltage GND. The output transistors Q1A and Q2A are, for example, FETs.

[0487] The synthesized signal generating circuit 21A inputs the signals fg1 and fg2 generated by the control circuits 12E_1 and 12E_2 and the lock detection signals ld1 and ld2, respectively, and generates a synthesized signal Si obtained by synthesizing the input signals. For example, the synthesized signal generating circuit 21A generates the synthesized signal Si based on the logical product of the signal sf12 based on the logical product of the signal fg1 and the signal fg2 and the signal sl12 based on the logical product of the lock detection signal ld1 and the lock detection signal ld2.

[0488] In the fourth embodiment, the composite signal generating circuit 21A is formed, for example, similarly to the composite signal generating circuit 21 in the third embodiment, on the same circuit board on which the general-purpose IC as the control circuits 12E_1 and 12E_2 and the MCU as the drive control circuit 20 are mounted.

[0489] The synthesized signal generating circuit 21A includes, for example, loads R1 to R3 and switch elements SW1 and SW2. The loads R1 to R3 are, for example, resistors. The load R1 is connected between a node (connection point) N1 to which the terminal FG1 of the control circuit 12E_1 and the terminal FG2 of the control circuit 12E_2 are connected and a power supply voltage Vcc as a second fixed potential. The load R2 is connected between a node (connection point) N2 to which the terminal LD1 of the control circuit 12E_1 and the terminal LD2 of the control circuit 12E_2 are connected and the power supply voltage Vcc. One end of the load R3 is connected to the power supply voltage Vcc.

[0490] The switch element SW1 is connected between the ground voltage GND and the other end of the load R3, and its on / off is controlled based on the voltage of the node N1. The switch element SW1 includes, for example, a transistor (bipolar transistor). In the transistor as the switch element SW1, the emitter electrode is connected to the ground voltage GND, and the collector electrode is connected to the other end (node ​​N3) of the load R3.

[0491] The switch element SW2 is connected between the ground voltage GND and the other end of the load R3, and its on / off is controlled based on the voltage of the node N2. The switch element SW2 includes, for example, a transistor (bipolar transistor). In the transistor as the switch element SW2, the emitter electrode is connected to the ground voltage GND, and the collector electrode is connected to the other end (node ​​N3) of the load R3.

[0492] It should be noted that if Fig.34 As shown, in the transistors constituting the switch elements SW1 and SW2, a resistor may be connected between the emitter electrode and the base electrode, or a resistor may be connected between the base electrode and the nodes N1 and N2.

[0493] In the synthetic signal generating circuit 21A, the node N3 is an output terminal, and the voltage of the node N3 is input to the drive control circuit 20 as the synthetic signal Si.

[0494] Fig.35 This is a diagram showing the relationship between the state of the fan and the pattern of the synthetic signal Si according to the fourth embodiment.

[0495] Fig.352 shows a pattern of the synthesized signal Si during normal operation of the fan 100E, that is, when the drive control circuit 20 outputs the drive control signals Sca1 and Sca2 corresponding to the speed command signal Sc to the motor drive circuits 10E_1 and 10E_2 to drive the motor 50 .

[0496] It should be noted that in Embodiments 3 and 4, attention should be paid to the logic inversion of the synthesized signal Si. For example, when the motor 50 and the motor drive circuits 10E_1 and 10E_2 are normal, the synthesized signal Si output from the synthesized signal generating circuit 21A (node ​​N3) is a binary signal having the same period as the signals fg1 and fg2 but a duty cycle of 75%.

[0497] As described above, the motor drive control device 1E of the fourth embodiment generates the synthetic signal Si using the lock detection signal in addition to the FG signal. Fig.35 As shown, by monitoring the synthetic signal Si during normal operation, it is possible to determine whether the motor 50 is in the locked state or whether the motor drive circuit 10E of either the motor drive circuits 10E_1 or 10E_2 is in the FG failure state.

[0498] However, the motor drive control device 1E of the fourth embodiment, like the motor drive control device 1D of the third embodiment, can not only monitor the synthetic signal Si in normal operation (drive mode), but also determine which of the motor drive circuits 10E_1 and 10E_2 has an FG fault.

[0499] Therefore, in the motor drive control device 1E of the fourth embodiment, the drive control circuit 20 performs the third FG fault determination process when it is determined that either of the motor drive circuits 10E_1 and 10E_2 is in the FG fault state (FG short-circuit fault or FG open-circuit fault), similarly to the drive control circuit 20 of the third embodiment. That is, the drive control circuit 20 sequentially changes the motor drive circuits 10E_1 and 10E_2 to a state capable of outputting FG signals one by one, and determines which of the motor drive circuits 10E_1 and 10E_2 is in the FG fault state based on the composite signal Si at this time.

[0500] In the process of the determination process based on the drive control circuit 20, it can be determined that the motor 50 is in the locked state and that the motor drive circuit 10E of either the motor drive circuit 10E_1 or 10E_2 is in the FG fault state caused by the FG short-circuit fault, thereby simplifying the first FG fault determination process. However, it may be the same as the process of the determination process based on the drive control circuit 20 of the third embodiment (refer to Fig. 22 , Fig.23 , Fig.24 , FIG. 25A to FIG. 25D ).

[0501] As described above, according to the motor drive control device 1E of implementation mode 4, in addition to the two FG signals, two lock detection signals ld1 and ld2 are synthesized to generate a synthetic signal Si. Therefore, by determining the waveform of the synthetic signal Si, the driving state of the fan 100E (motor 50 and motor drive circuits 10E_1 and 10E_2) can be determined in more detail.

[0502] Specifically, a synthetic signal Si is generated based on the logical product of the signal fg1 and the signal fg2 and the logical product of the lock detection signal ld1 and the lock detection signal ld2, thereby accurately determining whether either of the motor drive circuits 10E_1 and 10E_2 has an FG open circuit fault, whether either of the motor drive circuits 10E_1 and 10E_2 has an FG short circuit fault, and whether the motor 50 has a rotor locked.

[0503] Furthermore, the motor drive control device 1E can reduce the number of signal lines output from the motor drive circuits 10E_1 and 10E_2 to the drive control circuit 20 by including the synthetic signal generation circuit 21A, and can also reduce signal processing in the drive control circuit 20 .

[0504] 《Expansion of implementation methods》

[0505] As mentioned above, the invention accomplished by the present inventors has been specifically described based on the embodiments, but the present invention is not limited to these, and various modifications can be made without departing from the scope of the invention.

[0506] For example, in the above-mentioned embodiment, the synthesized signal generating circuits 21 and 21A may generate the synthesized signal Si by synthesizing the FG signals outputted from at least the motor drive circuits 10D and 10E. Fig. 20 and Fig.34 The logic value of the synthesized signal Si can be appropriately changed according to the circuit configuration of the input interface circuit of the MCU as the drive control circuit 20 to which the synthesized signal Si is input.

[0507] In addition, Fig. 22 In the determination process flow shown in , when the drive control circuit 20 detects the input of the speed command signal Sc in the stop mode, it can skip the startup waiting mode and enter the drive mode.

[0508] In addition, in the above-mentioned embodiment, the motor drive control device 1D, 1E is applied to a fan system having a single-phase brushless motor with two coils 80_1, 80_2, but the present invention is not limited thereto. For example, the motor drive control device 1D, 1E may be applied to a fan system having two single-phase brushless motors with one coil.

[0509] For example, Fig.36 As shown, the motor drive control device 1D can be applied to a fan 100F having a system structure in which two impellers 90_1 and 90_2 are rotated separately by motors 50B_1 and 50B_2 each having a coil of a system. In this case, the drive control circuit 20 generates drive control signals Sca1 and Sca2 in such a way that the phases of signals fg1 and fg2 output from each motor drive circuit 10D_1 and 10D_2 (control circuits 12D_1 and 12D_2) are different from each other (for example, the phase difference is 90 degrees). The motor drive circuit 10D_1 controls the energization of the coil 80B_1 of one motor 50B_1 based on the drive control signal Sca1, and the motor drive circuit 10D_2 controls the energization of the coil 80B_2 of the other motor 50B_2 based on the drive control signal Sca2.

[0510] Thus, similarly to the fan 100D of the third embodiment, the driving state of the fan 100F (the motors 50B_1 and 50B_2 ) can be determined, and the normal rotation of the fan 100F can be continued while monitoring the rotation speeds of the motors 50B_1 and 50B_2 .

[0511] In the above embodiment, the motors 50, 50B_1, 50B_2 are single-phase brushless motors, but the type and number of phases of the motors 50, 50B_1, 50B_2 are not limited thereto. For example, they may be three-phase brushless motors.

[0512] In addition, each flowchart in Embodiments 3 and 4 shows an example for explaining an action, and is not limited to this. That is, the steps shown in each figure of the flowchart are specific examples and are not limited to the process. For example, the order of a part of the processing can be changed, other processing can be inserted between each processing, and a part of the processing can be performed in parallel.

[0513] Description of Reference Numerals

[0514] 1, 1A, 1D, 1E...Motor drive control device

[0515] 10_1, 10_2, 10A_1, 10A_2, 10D_1, 10D_2, 10E_1, 10E_2...motor drive circuit

[0516] 12_1, 12_2, 12A_1, 12A_2, 12D_1, 12D_2, 12E_1, 12E_2...control circuit

[0517] SW1, SW2...Switching elements

[0518] 15_1, 15_2... Inverting circuit

[0519] 16_1, 16_2, 17_1, 17_2... output terminals

[0520] 19...Fuse

[0521] 20...Drive control circuit

[0522] 21, 21A...Synthetic signal generation circuit

[0523] 41_1, 41_2...Position detector

[0524] 50, 50B_1, 50B_2...Motor

[0525] 80_1, 80_2, 80B_1, 80B_2... coils

[0526] 90, 90_1, 90_2...Impeller

[0527] 100, 100A, 100B, 100C, 100D, 100E, 100F...Fans

[0528] 120_1, 120_2, 120A_1, 120A_2...Internal circuit

[0529] 121...Internal power circuit

[0530] 122……Control Department

[0531] 124……FG signal generation unit

[0532] 125...Lock detection circuit

[0533] 500...upper device

[0534] 1241……Comparator

[0535] 1242... Pre-driver circuit

[0536] fg1, fg2...FG signal

[0537] FG1, FG2...FG signal output terminals

[0538] GND... Ground voltage (an example of the first fixed potential)

[0539] hp, hn...Hall signal (position detection signal)

[0540] HP1, HN1, HP2, HN2... terminals

[0541] HB1, HB2...External output power terminals

[0542] ld1, ld2...lock detection signal

[0543] LD1, LD2...LD signal output terminal

[0544] N1, N2, N3... connection points (nodes)

[0545] Q1, Q1A, Q2, Q2A... output transistors

[0546] R1, R2, R3... load (resistance)

[0547] Sc...Speed ​​command signal

[0548] Sca1, Sca2...driving control signal

[0549] SCA1, SCA2...terminals

[0550] Sd1, Sd2...driving signal

[0551] SD1, SD2...terminals

[0552] sf12, sl12...signal

[0553] SF12...Signal (output from node N1)

[0554] SL12...Signal (output from node N2)

[0555] Si...Synthetic Signal

[0556] So...status signal

[0557] Vin...Power supply voltage

[0558] VIN...Power supply terminal

[0559] Vdc...power supply voltage

[0560] Vcc...Power supply voltage (an example of the second fixed potential)

[0561] Vdd...Internal power supply voltage

[0562] Vhb...External output power supply voltage

Claims

1. A motor drive control device, comprising: a plurality of motor drive circuits for controlling the energization of the motors based on drive control signals for controlling the rotational speeds of the motors and outputting FG signals having a period corresponding to the actual rotational speeds of the motors; a composite signal generating circuit which receives the FG signals output from the motor driving circuit and generates a composite signal by synthesizing the input signals; and a drive control circuit that generates the drive control signal based on a speed instruction signal indicating a target rotation speed of the motor and outputs the drive control signal to each of the motor drive circuits; The FG signals output from the respective motor drive circuits have phase differences with each other. The plurality of motor drive circuits include: a first motor drive circuit that controls the energization of the motor based on the drive control signal and outputs a first FG signal having a frequency corresponding to an actual rotation speed of the motor; and a second motor driving circuit that controls the energization of the motor based on the driving control signal and outputs a second FG signal having a frequency corresponding to an actual rotation speed of the motor and having a phase shifted relative to the first FG signal, The synthesized signal generating circuit generates the synthesized signal by synthesizing the first FG signal and the second FG signal. The first FG signal and the second FG signal are rectangular wave signals having a predetermined duty ratio. The synthetic signal generation circuit generates the synthetic signal based on a logical product of the first FG signal and the second FG signal.

2. The motor drive control device according to claim 1, wherein: The first motor driving circuit includes: a first output terminal for outputting the first FG signal; and a first output transistor connected between the first output terminal and a first fixed potential. The second motor driving circuit includes: a second output terminal for outputting the second FG signal; and a second output transistor connected between the second output terminal and the first fixed potential. The synthetic signal generating circuit includes a load connected between a connection point where the first output terminal and the second output terminal are commonly connected and a second fixed potential different from the first fixed potential.

3. The motor drive control device according to claim 1 or 2, wherein: The drive control circuit receives the synthesized signal as input, and determines that the motor is being driven normally when the synthesized signal is a signal having a duty ratio corresponding to a phase difference between the first FG signal and the second FG signal.

4. The motor drive control device according to claim 3, wherein: The drive control circuit receives the synthesized signal as input, and determines that one of the first motor drive circuit and the second motor drive circuit has an open-circuit fault when the synthesized signal has the predetermined duty ratio.

5. The motor drive control device according to claim 3, wherein: The drive control circuit receives the synthesized signal as input, and determines that at least one of the first motor drive circuit and the second motor drive circuit is in a short-circuit fault or the motor is in a locked state when the synthesized signal has a predetermined logic value.

6. A motor drive control device, comprising: a plurality of motor drive circuits for controlling the energization of the motors based on drive control signals for controlling the rotational speeds of the motors and outputting FG signals having a period corresponding to the actual rotational speeds of the motors; a composite signal generating circuit which receives the FG signals output from the motor driving circuit and generates a composite signal by synthesizing the input signals; and a drive control circuit that generates the drive control signal based on a speed instruction signal indicating a target rotation speed of the motor and outputs the drive control signal to each of the motor drive circuits; The FG signals output from the respective motor drive circuits have phase differences with each other. The plurality of motor drive circuits include: a first motor drive circuit that controls the energization of the motor based on the drive control signal and outputs a first FG signal having a frequency corresponding to an actual rotation speed of the motor; and a second motor driving circuit that controls the energization of the motor based on the driving control signal and outputs a second FG signal having a frequency corresponding to an actual rotation speed of the motor and having a phase shifted relative to the first FG signal, The synthesized signal generating circuit generates the synthesized signal by synthesizing the first FG signal and the second FG signal. The first motor driving circuit outputs a first lock detection signal, wherein the first lock detection signal is a binary signal indicating whether the motor is in a locked state. The second motor driving circuit outputs a second lock detection signal, which is a binary signal indicating whether the motor is in a locked state. The synthesized signal generating circuit synthesizes the first FG signal, the second FG signal, the first lock detection signal, and the second lock detection signal to generate the synthesized signal.

7. The motor drive control device according to claim 6, wherein: The first FG signal and the second FG signal are rectangular wave signals having a predetermined duty ratio. The synthetic signal generating circuit generates the synthetic signal according to a logical product of a signal based on a logical product of the first FG signal and the second FG signal and a signal based on a logical product of the first lock detection signal and the second lock detection signal.

8. The motor drive control device according to claim 7, wherein: The first motor drive circuit includes: a first output terminal for outputting the first FG signal; a second output terminal for outputting the first lock detection signal; a first output transistor connected between the first output terminal and a first fixed potential; and a second output transistor connected between the second output terminal and the first fixed potential. The second motor drive circuit includes: a third output terminal for outputting the second FG signal; a fourth output terminal for outputting the second lock detection signal; a third output transistor connected between the third output terminal and the first fixed potential; and a fourth output transistor connected between the fourth output terminal and the first fixed potential. The synthetic signal generating circuit comprises: a first load connected between a first connection point where the first output terminal and the third output terminal are commonly connected and a second fixed potential different from the first fixed potential; a second load connected between a second connection point commonly connected to the second output terminal and the fourth output terminal and the second fixed potential; a third load, one end of which is connected to the second fixed potential; a first switching element connected between the first fixed potential and the other end of the third load, whose on / off is controlled based on the voltage of the first connection point; and The second switch element is connected between the first fixed potential and the other end of the third load, and its on / off is controlled based on the voltage of the second connection point.

9. The motor drive control device according to claim 7 or 8, wherein: The drive control circuit determines that the motor is normally driven when the composite signal has a duty ratio corresponding to the phase difference between the first FG signal and the second FG signal.

10. The motor drive control device according to claim 9, wherein: The drive control circuit determines that one of the first motor drive circuit and the second motor drive circuit has an open-circuit failure when the combined signal has the predetermined duty ratio.

11. The motor drive control device according to claim 10, wherein: The drive control circuit determines that one of the first motor drive circuit and the second motor drive circuit has a short-circuit failure when the combined signal is at a first logic level.

12. The motor drive control device according to claim 11, wherein: The drive control circuit determines that the motor is in the locked state when the combined signal is at a second logic level different from the first logic level.

13. A fan, comprising: The motor drive control device according to claim 1 or 6; and the motor comprising a first system of coils and a second system of coils, The first motor drive circuit controls the energization of the coils of the first system, The second motor drive circuit controls energization of the coils of the second system.

14. A fan, comprising: The motor drive control device according to claim 1 or 6; and two of said motors comprising at least one coil, The first motor driving circuit controls the energization of the coil of one of the motors. The second motor drive circuit controls energization of the coil of the other motor.

15. A motor drive control device, comprising: a plurality of motor drive circuits for controlling the energization of the motors based on drive control signals for controlling the rotational speeds of the motors and outputting FG signals having a period corresponding to the actual rotational speeds of the motors; a composite signal generating circuit which receives the FG signals output from the motor driving circuit and generates a composite signal by synthesizing the input signals; and a drive control circuit that generates the drive control signal based on a speed instruction signal indicating a target rotation speed of the motor and outputs the drive control signal to each of the motor drive circuits; The FG signals output from the respective motor drive circuits have phase differences with each other. When the composite signal indicates a specified logical value, the drive control circuit causes at least one of the multiple motor drive circuits to be converted into a high-level state where it cannot output the FG signal, and performs a first determination process based on the composite signal at this time. The first determination process determines whether any one of the multiple motor drive circuits is in an FG fault state where it cannot normally output the FG signal, or in a locked state where the motor cannot rotate.

16. The motor drive control device according to claim 15, wherein: Each of the motor drive circuits can be switched to a power saving state in which at least a part of the internal circuit thereof stops operating and the output of the FG signal is fixed at a high level. When the composite signal indicates the prescribed logic value, the drive control circuit causes at least one of the plurality of motor drive circuits to shift to the power saving state, and performs the first determination process based on the composite signal at this time.

17. The motor drive control device according to claim 15 or 16, wherein: Each of the motor drive circuits comprises: an internal power supply circuit that generates and outputs an internal power supply voltage; an FG signal generating unit that is configured to be operable by power supply from the internal power supply voltage and generates and outputs the FG signal based on a position detection signal corresponding to the rotational position of the rotor of the motor; and a control unit that controls the supply and cutoff of the internal power supply voltage to the FG signal generating unit and generates a drive signal for energizing the motor based on the drive control signal. When the synthetic signal indicates the prescribed logic value, the drive control circuit stops outputting the drive control signal. The control unit cuts off supply of the internal power supply voltage to the FG signal generating unit when the drive control signal is not input and the FG signal is not switched within a predetermined period of time.

18. The motor drive control device according to claim 17, wherein: In the first determination process, when the drive control circuit detects a specified change in the synthetic signal, it determines that any one of the plurality of motor drive circuits is in the FG failure state, and when it is fixed at the specified logic value, it determines that the motor is in the locked state.

19. The motor drive control device according to claim 18, wherein: When it is determined that any one of the multiple motor drive circuits is in the FG fault state, the drive control circuit drives the multiple motor drive circuits one by one in sequence, and performs a second determination process based on the synthetic signal at this time to determine which one of the motor drive circuits is in the FG fault state.

20. The motor drive control device according to claim 19, wherein: The drive control circuit stops outputting the drive control signal to the motor drive circuit determined to be in the FG failure state through the second determination process, and outputs the drive control signal to the motor drive circuit determined to be in the normal state.

21. The motor drive control device according to claim 15, wherein: The FG signal is a rectangular wave signal having a predetermined duty ratio within a period corresponding to the rotation speed of the motor. The composite signal generating circuit generates the composite signal based on a logical product of the FG signals output from the respective motor driving circuits.

22. The motor drive control device according to claim 15, wherein: Each of the motor drive circuits outputs a lock detection signal, which is a binary signal indicating whether the motor is in a locked state. The FG signal is a rectangular wave signal having a predetermined duty ratio within a period corresponding to the rotation speed of the motor. The synthetic signal generating circuit generates the synthetic signal based on a logical product of a signal based on a logical product of the FG signals output from the respective motor drive circuits and a signal based on a logical product of the lock detection signals output from the respective motor drive circuits.

23. A fan, comprising: The motor drive control device according to claim 15; the motor; and The impeller is configured to be rotatable by the rotational force of the motor.

24. A motor drive control method, the motor drive control method is a motor drive control method based on a motor drive control device, the motor drive control device comprising: a plurality of motor drive circuits, which control the power supply to the motor based on a drive control signal for controlling the rotational speed of the motor and output an FG signal having a period corresponding to the actual rotational speed of the motor; a synthetic signal generating circuit, which inputs the respective FG signals output from the motor drive circuits and generates a synthetic signal obtained by synthesizing the input signals; and a drive control circuit, which generates the drive control signal based on a speed instruction signal indicating a target rotational speed of the motor and outputs the drive control signal to each of the motor drive circuits, The FG signals output from the respective motor drive circuits have phase differences with each other. The motor drive control method comprises: In the first step, when the synthetic signal indicates a specified logic value, the drive control circuit causes at least one of the plurality of motor drive circuits to be switched to a high level state in which the FG signal cannot be output; and In the second step, the drive control circuit performs a first determination process based on the synthetic signal in the first step, and the first determination process determines whether any one of the multiple motor drive circuits is in an FG failure state where the FG signal cannot be output normally, or in a locked state where the motor cannot rotate.

Images