Speaker driver system

Abstract

A system (100) for driving a speaker (110) having a plurality of coils (112, 114, 116), the system comprising: a modulator (120) configured to receive an input signal and output a pulse width modulated (PWM) output signal representative of the received input signal; a delay element (130) for receiving the PWM output signal and applying a delay to the PWM output signal to generate a first delayed signal; a first output terminal (152) configured to be coupled to a first coil (112) of the plurality of coils of the speaker, wherein the first output terminal is coupled to the output terminal of the modulator (120); and a second output terminal (154) configured to be coupled to a second coil (114) of the plurality of coils of the speaker, wherein the second output terminal is coupled to the output terminal of the delay element (130).

Description

Technical Field

[0001] The present disclosure relates to the field of loudspeaker driver systems. In particular, the present disclosure relates to systems and methods for driving a loudspeaker having multiple coils. Background Art

[0002] In portable electronic devices such as mobile phones, tablets and laptops, portable speakers, headsets, headphones, earbuds, etc., there is a continuous demand for speaker systems that can produce high-volume audio output while occupying the smallest possible physical volume.

[0003] One approach to generating high-volume audio output in portable electronic devices is to use a boosted power supply to drive a relatively large speaker. However, larger speakers have reduced sensitivity, which means that an increase in electrical power input to the speaker does not necessarily result in a corresponding increase in the loudness of the audio output produced by the speaker.

[0004] Another approach is to use two speakers mounted in a back-to-back configuration. While this may increase the loudness of the resulting audio output, a disadvantage of this dual-speaker arrangement is that the resistance of the speakers is presented in parallel to the speaker driver circuit. This arrangement also increases (e.g., doubles) the physical volume occupied by the speakers, which can be a problem in small devices that may lack sufficient space for two speakers.

[0005] Loudspeakers with multiple coils are known. Typically, such multi-coil loudspeakers are used in one of two different configurations. In the first configuration, the loudspeaker includes multiple different coils, each of which responds to input signals in a different frequency band. In this type of loudspeaker, each coil must be driven by a drive signal that carries a frequency within the coil's frequency band. One way to achieve this is to encode the input audio signal using a pulse density modulator and apply appropriate digital filtering to generate multiple digital signals corresponding to the respective frequency bands of the loudspeaker coils, where each of the multiple digital signals is used to drive an appropriate one of the loudspeaker coils.

[0006] A second multi-coil speaker configuration includes a drive coil for driving the speaker cone and a sense coil for sensing the excursion of the speaker cone by detecting a current induced in the sense coil due to movement of the speaker cone. This type of speaker is often coupled to a speaker protection system that monitors the excursion of the speaker cone detected by the sense coil and limits the amplitude of the signal driving the drive coil if excessive cone excursion is detected.

[0007] What is needed is a system for increasing the loudness of audio output through a single speaker without requiring a boost power supply. Summary of the Invention

[0008] According to a first aspect, the present invention provides a system for driving a loudspeaker having a plurality of coils, the system comprising:

[0009] a modulator configured to receive an input signal and output a pulse width modulated (PWM) output signal representative of the received input signal;

[0010] a delay element for receiving a PWM output signal and applying a delay to the PWM output signal to generate a first delayed signal;

[0011] a first output configured to be coupled to a first coil of the plurality of coils of the speaker, wherein the first output is coupled to an output of the modulator; and

[0012] A second output is configured to be coupled to a second coil of the plurality of coils of the speaker, wherein the second output is coupled to an output of the delay element.

[0013] For example, the modulator may include a class D amplifier.

[0014] The input signal may include an audio signal.

[0015] The input signal may comprise a digital signal and the modulator may comprise a digital modulator.

[0016] The modulator and the delay element may be configured to receive a clock signal.

[0017] The delay element may include a clock buffer.

[0018] The delay element may alternatively comprise a counter.

[0019] The delay element may also include an edge detector and an edge generator, wherein:

[0020] The edge detector is configured to detect an edge of the input PWM signal and trigger the counter when the edge is detected;

[0021] the counter being configured to count pulses of the clock signal until a predetermined number is reached and output a signal to the edge generator when the predetermined number is reached; and

[0022] The edge generator is configured to output a delayed and inverted version of the input PWM signal in response to receiving a signal from the counter.

[0023] The delay element may be configured to apply a delay to the output PWM signal that is equal to one period of the output PWM signal.

[0024] The delay element may form at least part of a finite impulse response (FIR) filter arrangement.

[0025] The FIR filter arrangement may be configured to receive a configuration signal and, based on the configuration signal, adapt in response to a change in the frequency of the PWM output signal output.

[0026] In response to the configuration signal, the FIR filter arrangement may be operable to adjust a predetermined value used by a counter of the FIR filter arrangement.

[0027] The FIR filter arrangement may be configured to suppress a carrier wave of the PWM output signal.

[0028] The FIR filter arrangement may be configured to provide a zero at a carrier frequency of the PWM output signal.

[0029] The carrier frequency of the PWM output signal may be modulated based on the control signal.

[0030] The control signal may be based on an operating mode of the system or based on an input signal level of the input signal.

[0031] According to a second aspect, the present invention provides an integrated circuit comprising a system according to the first aspect.

[0032] According to a third aspect, the invention provides a device comprising the system according to the first aspect, wherein the device comprises a portable device, a battery powered device, a mobile phone, a notebook, a laptop or tablet computing device, a smart watch or an accessory device.

[0033] According to a fourth aspect, the present invention provides a method for driving a loudspeaker having multiple coils, the method comprising:

[0034] receiving an input signal and outputting a pulse width modulated (PWM) output signal representative of the received input signal; and

[0035] applying a delay to the PWM output signal to generate a first delayed signal;

[0036] outputting a PWM modulated output signal to a first coil among the plurality of coils; and

[0037] The first delayed signal is output to a second coil among the plurality of coils.

[0038] The method may include modulating an input signal with a class D amplifier to generate a PWM output signal.

[0039] For example, the input signal may include an audio signal.

[0040] The input signal may comprise a digital signal and the method may comprise modulating the input signal with a digital modulator to generate a PWM output signal.

[0041] The method may further include synchronizing the modulated PWM output signal and the first delayed signal to a clock signal.

[0042] A clock buffer can be used to apply a delay to the PWM output signal.

[0043] Alternatively, a counter may be used to apply a delay to the PWM output signal.

[0044] Application delays can include:

[0045] Detect the edge of the input PWM signal and trigger the counter when the edge is detected;

[0046] counting pulses of the clock signal until a predetermined number is reached; and

[0047] In response to receiving a signal from the counter indicating that the predetermined number has been reached, a delayed and inverted version of the input PWM signal is output.

[0048] The delay may be equal to one cycle of the output PWM signal to the output PWM signal.

[0049] According to a fifth aspect, the present invention provides a system for driving a loudspeaker having a plurality of coils, the system comprising:

[0050] a modulator for receiving an input signal and outputting a first PWM output signal for driving a first coil of the plurality of coils;

[0051] a finite impulse filter (FIR) device for receiving the PWM output signal and outputting a second PWM output signal for driving a second coil of the plurality of coils,

[0052] The FIR device is configured to adapt to frequency variations of the PWM output signal so as to suppress the carrier of the PWM output signal.

[0053] According to a sixth aspect, the present invention provides a system for driving a transducer having a plurality of coils, the system comprising:

[0054] a modulator for outputting a digital output signal representative of the received analog input signal at a modulator output;

[0055] a clocked delay element for applying a delay to the digital output signal to generate a first delayed signal at an output of the delay element;

[0056] The modulator output may be coupled to a first coil among the plurality of coils of the transducer, and the delay element output may be coupled to a second coil among the plurality of coils of the transducer.

[0057] The system may further include a clock signal generator operable to generate a clock signal for the clocked delay element.

[0058] According to a seventh aspect, the present invention provides an integrated circuit comprising the system of the sixth aspect.

[0059] According to an eighth aspect, the present invention provides a system for driving a transducer, the system comprising:

[0060] a modulator for outputting a digital output signal representative of the received analog input signal at a modulator output;

[0061] a delay element for applying a delay to the digital output signal to generate a first delayed signal at an output of the delay element;

[0062] a first inductor having a first terminal coupled to the modulator output; and

[0063] a second inductor having a first terminal coupled to the delay element output,

[0064] The second terminal of the first inductor is coupled to the second terminal of the second inductor to provide an output node for a drive signal to drive the transducer.

[0065] The first and second inductors may include first and second coils of a transducer.

[0066] For example, the transducer may include a speaker.

[0067] According to a ninth aspect, the present invention provides a module comprising the system of the eighth aspect and a transducer.

[0068] According to a tenth aspect, the present invention provides the integrated circuit according to the eighth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Embodiments of the present invention will now be described, strictly by way of example only, with reference to the accompanying drawings, in which:

[0070] Figure 1 is a schematic diagram of a system for driving a loudspeaker having multiple coils;

[0071] Figure 2 This is a simplified schematic diagram of a FIR DAC;

[0072] Figure 3 is a schematic diagram of a system for driving a speaker having multiple coils, the system using a class D amplifier to generate a pulse width modulated signal to drive the coils of the speaker;

[0073] Figure 4 is a schematic diagram of a system for driving a speaker having multiple coils, the system using a digital modulator to generate a pulse width modulated signal to drive the coils of the speaker;

[0074] Figure 5 is a schematic diagram of a digital delay unit;

[0075] Figure 6 is a schematic diagram of a digital delay implemented using a counter;

[0076] Figure 7 is a schematic diagram of a system for driving a speaker having multiple coils, wherein the system uses a digital modulator to generate a pulse width modulated signal to drive the coils of the speaker, wherein the PWM repetition signal is variable;

[0077] Figure 8 is a schematic diagram of a system for driving a multi-coil transducer;

[0078] Figure 9 is a schematic diagram of a system for driving a single-coil loudspeaker; and

[0079] Figure 10 is a schematic diagram of a system for driving a single-coil transducer. DETAILED DESCRIPTION

[0080] refer to Figure 1 A system for driving a loudspeaker having multiple coils (also known as a multi-coil loudspeaker) is shown generally at 100 . Figure 1 The system 100 shown in FIG. 1 is configured to drive a speaker 110 having a first coil 112 , a second coil 114 , and a third coil 116 , but it should be understood that the principles described herein are applicable to multi-coil speakers having any number of coils.

[0081] The system 100 includes a modulator 120 configured to receive an analog input signal, such as an audio signal, and convert it into a pulse width modulated (PWM) output signal. For example, the modulator 120 can be a class D modulator. The modulator 120 can be implemented, for example, in a circuit (e.g., a discrete circuit or an integrated circuit) or by a processing circuit (e.g., a digital signal processor) executing appropriate software code.

[0082] The output of the modulator 120 is coupled to the input of the first delay element 130, so that the PWM signal output by the modulator 120 is input to the first delay element 130. The output of the modulator 120 is also connected to the first output terminal 152 of the system 100, which is configured to be coupled to the first coil 112 of the speaker 110, so that when the speaker is coupled to the system 100, the PWM signal output by the modulator 120 is also input to the first coil 112 of the speaker 110.

[0083] The first delay element 130 is configured to apply a delay to the input PWM signal and output a delayed version of the PWM signal.

[0084] The output of the first delay element 130 is coupled to the input of the second delay element 140, such that a delayed version of the PWM signal output by the first delay element 130 is input to the second delay element 140. The output of the first delay element 130 is also connected to a second output terminal 154, which is configured to be coupled to the second coil 114 of the speaker 110, such that the delayed version 130 of the PWM signal output by the first delay element is also input to the second coil 114 of the speaker 110.

[0085] The second delay element 140 is configured to apply a further delay to the input PWM signal and output a further delayed version of the PWM signal. The output of the second delay element 140 is connected to a third output terminal 156, which is configured to be coupled to the third coil 116 of the speaker 110, so that the further delayed version 140 of the PWM signal output by the second delay element is input to the third coil 116 of the speaker 110.

[0086] The first delay element and the second delay element can be implemented, for example, in discrete circuits or integrated circuits, or in processing circuitry that executes appropriate software code. Where the delay elements are implemented in an integrated circuit, they can be integrated with the modulator circuit in a single integrated circuit (IC), or alternatively can be integrated together as separate ICs. Alternatively, each delay element can be integrated as a separate IC.

[0087] As will be understood by those skilled in the art, the combination of the first and second delay elements 130, 140, the first, second, and third coils 112, 114, 116 of the speaker 110, and the cone 118 acts as a FIR DAC (Finite Impulse Response Digital-to-Analog Converter), which will now be referred to. Figure 2 Provide explanation.

[0088] like Figure 2As generally shown at 200 in FIG. 1 , a FIR DAC generally includes a plurality (three in this example) of digital delay elements 202, 204, and 206. A first one of the digital delay elements 202 is configured to receive a digital signal at its input, apply a delay to the received digital signal, and output a first delayed digital signal to a second one of the digital delay elements 204. The first delayed digital signal is also output to a first digital-to-analog converter (DAC) 208.

[0089] The second digital delay element 204 is configured to receive the first delayed digital signal at its input, apply a delay to the received first delayed digital signal, and output a second delayed digital signal to a third digital delay element 206. The second delayed digital signal is also output to the second DAC 210.

[0090] The third digital delay element 206 is configured to receive the second delayed digital signal at its input, to apply a delay to the received second delayed digital signal, and to output a third delayed digital signal to the third DAC 212 .

[0091] The first DAC 208, the second DAC 210, and the third DAC 212 are configured to convert the received first delayed digital signal, the second delayed digital signal, and the third delayed digital signal into a first analog signal, a second analog signal, and a third analog signal, respectively, and output the first analog signal, the second analog signal, and the third analog signal to the summing unit 214. The summing unit 214 sums the received first analog signal, the second analog signal, and the third analog signal, and outputs the summed result as an analog output signal.

[0092] As will be appreciated, the combination of digital delay elements 202, 204, 206, DAC 208, DAC 210, DAC 212 and summing unit 214 performs the functions of a finite impulse response filter and a digital-to-analog converter such that the analog output signal constitutes a filtered analog version of the digital input signal.

[0093] exist Figure 1 In the system 100, the delay elements 130, 140 perform the digital delay function of the FIR DAC, while the coils 112, 114, 116 of the speaker 110 (in conjunction with any additional filtering components associated with the coils 112, 114, 116) perform the digital-to-analog conversion of the digital signals input to the coils 112, 114, 116. The function of summing the analog signals is performed by the cone 118 of the speaker 110, the movement of which is controlled by the combination of the magnetic fields generated by the coils 112, 114, 116, thereby outputting an analog audio signal representing the sum of the analog signals generated by the coils 112, 114, 116.

[0094] The arrangement of delay elements 130, 140, coils 112, 114, 116, and cone 118 in a FIR DAC configuration helps reduce the effects of out-of-band signals (i.e., signals outside the audio band) and jitter in the audio signal output by speaker 110. For example, the FIR DAC arrangement helps suppress the carrier signal of the PWM signal output by modulator 120.

[0095] PWM signals can be generated in many different ways. For example, as will now be referred to Figure 3 As described, modulator 120 may be a class D amplifier.

[0096] Figure 3 The system shown in FIG includes Figure 1 similar components of the system, so in Figure 1 and Figure 3 The same reference numerals have been used to denote the same components. Figure 3 The system 300 includes a class D amplifier 310, which is composed of a comparator 312, a carrier signal generator 314, a first switching device 316, and a second switching device 318. The class D amplifier 310 can be implemented as a discrete circuit, or alternatively, can be implemented as an integrated circuit. The class D amplifier 310 in this example is configured to receive an analog input signal and output a PWM output signal at its output 320 in a manner familiar to those skilled in the art, but it should be understood that a digital class D amplifier can be used when the input signal is a digital signal.

[0097] An output 320 of the class-D amplifier 310 is coupled to the first delay element 130 and is also connected to a first output terminal 152 of the system 300, which is configured to be coupled to the first coil 112 of the speaker 110, such that when the speaker is coupled to the system 300, the PWM signal output by the modulator 310 to the first delay element 320 is also input to the first coil 112 of the speaker 110. The first delay element 130 outputs a first delayed version of the PWM signal output by the class-D amplifier to a second output terminal 154, which is configured to be coupled to the second coil 114 and a second delay element 140, and the second delay element 140 outputs a second delayed version of the PWM signal output by the class-D amplifier to a third output terminal 156, which is configured to be coupled to the third coil 116, as described above with reference to FIG. Figure 1 described.

[0098] Figure 4 is a schematic diagram of a system 400 for driving a multi-coil loudspeaker having multiple coils, the system using a digital modulator to generate a pulse width modulated signal to drive the coils of the loudspeaker. Figure 4 The system shown in FIG includes Figure 1 and Figure 3 similar components of the system, so in Figure 1 、 Figure 3 and Figure 4 The same reference numerals are used throughout to denote the same components.

[0099] Figure 4 The system shown includes a digital modulator 410 having an input 420 and an output 430. A digital input signal D is received at the input 420. IN (eg digital audio signal), and outputs a digital input signal D at the output terminal 430. IN The output 430 of the digital modulator 410 is coupled to the first delay element 130 and the first output terminal 152 of the system 400, which is configured to be coupled to the first coil 112 of the multi-coil loudspeaker 110. The first delay element 130 outputs a first delayed version of the PWM output by the digital modulator 400 to the second output terminal 154, which is configured to be coupled to the second coil 114 of the multi-coil loudspeaker 110.

[0100] For simplicity, the speaker 110 is shown as having two coils, but it is understood that the speaker 110 may include more than two coils.

[0101] exist Figure 4 In the system shown, the digital modulator 410 and the first delay element 130 receive a signal having a frequency F s A clock signal CLK (eg, generated by a clock of a host device providing the system 400 ) is provided to ensure synchronous operation of the digital modulator 410 and the first delay element 130 .

[0102] In the operation of the system, relative to the frequency F of the clock signal CLK s , the delay β-α between the output terminal 430 (α) of the digital modulator 410 and the output terminal (β) of the first delay element 130 may be large. For example, the frequency F of the clock signal CLK s It can be 6.144MHz, while the PWM repetition (carrier) frequency can be 384kHz. Therefore, in this example, in order to filter the PWM carrier frequency from the output of the first delay element 130, the delay applied by the first delay element 130 should be one PWM period of the PWM signal output by the digital modulator 410, that is, 1 / 384kHz≈2.6μs. Figure 4 In the example shown, the first delay element 130 delays the input signal by one PWM period and inverts it.

[0103] The delay elements 130, 140 described above can be implemented in many different ways. Figure 5 In one example shown, a simple delay element may include one or more clock buffers.

[0104] Alternatively, the delay element may be implemented more efficiently as a counter which counts to a predetermined number before switching the output. Figure 6 is a schematic diagram of such a delay element.

[0105] Figure 6 The delay element 600 is a digital delay element, which includes an edge detector 610 , a counter 620 and an edge generator 630 .

[0106] The edge detector 610 is configured to receive an input PWM signal (e.g., Figure 1 、 Figure 3 or Figure 4 The edge detector 610 detects an edge (e.g., a rising edge) of the input PWM signal, and outputs a signal to the counter 620 to cause the counter 620 to begin counting clock pulses of the clock signal CLK. The counter 620 continues counting pulses until a predetermined number equal to the number of clock pulses in one period of the input PWM signal (e.g., 2.6 μs x 6.144 MHz = 16) is reached.

[0107] For example, as described above, when the PWM repetition frequency is 384 kHz and the frequency F of the clock signal CLK is s When the frequency is 6.144 MHz, one cycle of the PWM signal will last about 2.6 μs, so the predetermined number of clock pulses is 16 (ie, 2.6 μs x 6.144 MHz = 16).

[0108] When the predetermined number is reached, the counter 620 outputs a signal to the edge generator 630, which outputs an inverted and delayed version of the input PWM signal as the output PWM signal. For example, if the counter 620 is triggered by detecting a rising edge of the input PWM signal, the edge generator 630 will output a delayed version of the input PWM signal starting from the falling edge as the output PWM signal.

[0109] Typically, the PWM repetition frequency can be varied. For example, when the modulator is idle, the PWM repetition frequency can be reduced to save power. The delay element(s) that make up the FIR filter of the system can therefore be reconfigured to accommodate different PWM repetition frequencies.

[0110] Figure 7is a schematic diagram of a system 700 for driving a multi-coil loudspeaker, wherein the system uses a digital modulator to generate a pulse width modulated signal to drive the coils of the loudspeaker, wherein the PWM repetition signal is variable. Figure 7 The system 700 shown in FIG. 1 includes Figure 4 similar components of the system, so in Figure 4 and Figure 7 The same reference numerals have been used to denote the same components.

[0111] Figure 7 The system 700 includes the above reference Figure 4 A digital modulator 410 of the type described above is provided which outputs a PWM output signal to a FIR filter arrangement 710 which may comprise, for example, the filter arrangement described above with reference to Figures 1 to 6 The FIR filter arrangement outputs a plurality of signals to an output terminal 720 of the system 700 , which is configured to be coupled to the coils of the multi-coil loudspeaker 110 , each of the plurality of signals driving a different coil 112 , 114 , 116 of the multi-coil loudspeaker 110 .

[0112] The FIR filter device 710 receives a configuration signal Config, which may be provided, for example, by the digital modulator 400 or by a controller of a host device incorporating the system 700. The configuration signal causes the FIR filter device 710 to adapt or reconfigure in response to changes in the PWM repetition frequency of the PWM signal output by the modulator 410, for example by adjusting a predetermined value used by a counter of the FIR filter device to adapt to changes in the PWM repetition frequency.

[0113] The FIR filter device 710 can be optimized to suppress the carrier of the PWM signal. For example, the FIR filter device 710 can be configured to provide a zero at the PWM carrier frequency. The PWM carrier frequency can be modulated based on some control signal, which can be based on, for example, the operating mode of the system 700 (e.g., high power / low power) or based on the input signal D IN The FIR filter device 710 can be reconfigured to adapt to changes in the PWM carrier frequency in response to the configuration signal Config.

[0114] The above discussion relates to driving a multi-coil loudspeaker. However, those skilled in the art will readily appreciate that the principles discussed above are equally applicable to other multi-coil transducers.

[0115] Figure 8 is a schematic diagram of a system for driving a multi-coil transducer (ie, a transducer having multiple coils). Figure 8The system 800 shown in FIG. 8 is configured to drive a speaker 810 having a first coil 812 and a second coil 814 , but it will be understood that the principles described herein are applicable to multi-coil transducers having any number of coils.

[0116] System 800 includes a modulator 820 configured to receive an analog input signal (such as an audio signal) and convert it into a digital output signal (such as a pulse-width modulated (PWM) signal). Modulator 820 can be, for example, an asynchronous or self-oscillating PWM modulator. For example, modulator 820 can be a class-D modulator. Modulator 820 can be implemented, for example, in a circuit (e.g., a discrete circuit or an integrated circuit) or by a processing circuit (e.g., a digital signal processor) executing appropriate software code.

[0117] The output of the modulator 820 is coupled to the input of the clocked delay element 830, such that the digital signal output by the modulator 820 is input to the clocked delay element 830. The output of the modulator 820 is also connected to a first output terminal 852 of the system 800, which is configured to be coupled to the first coil 812 of the transducer 810, such that when the transducer 810 is coupled to the system 800, the digital signal output by the modulator 820 is also input to the first coil 812 of the transducer 810.

[0118] The clocked delay element 830 is configured to apply a delay to an input digital signal and output a delayed version of the digital signal. The clocked delay element 830 may include, for example, Figure 5 and Figure 6 Describes a type of clock buffer or digital delay element.

[0119] The output of the clocked delay element 830 is coupled to a second output terminal 854 of the system 800, which is configured to be coupled to the second coil 814 of the transducer 810, such that a delayed version of the digital signal output by the modulator 820 output by the clocked delay element 830 is input to the second coil 814 of the speaker 810.

[0120] The system 800 also includes a clock signal generator 840 operable to generate a clock signal and output the clock signal to the clocked delay element 830 .

[0121] The clocked delay element 830 can be implemented, for example, in a discrete circuit or an integrated circuit, or in a processing circuit that executes appropriate software code. Where the clocked delay element 830 is implemented in an integrated circuit, it can be integrated with the modulator circuit in a single integrated circuit (IC), or alternatively can be integrated as a separate IC. Alternatively, the clocked delay element 830 can be integrated as a separate IC.

[0122] exist Figure 8 In the example shown, one clocked delay element 830 is provided, but it will be appreciated that a greater number of such delay elements may be provided, each delay element having an output supplying a delayed version of the digital signal output by the modulator 820 to a different coil of the multi-coil transducer.

[0123] As will be appreciated by those skilled in the art, the combination of the clocked delay element 830 and the first and second coils 812, 814 of the transducer 810 is described above with reference to Figure 2 The described approach acts as a FIR DAC (Finite Impulse Response Digital-to-Analog Converter).

[0124] The present disclosure also extends to systems (eg, circuits) for driving a loudspeaker or other transducer having a single coil.

[0125] Figure 9 is a schematic diagram of a system 900 for driving a single-coil loudspeaker 910 .

[0126] The system 900 includes a modulator 920 configured to receive an analog input signal, such as an audio signal, and convert it into a digital (e.g., PWM) output signal. For example, the modulator 920 can be a class D modulator and / or an asynchronous or self-oscillating PWM modulator. The modulator 920 can be implemented, for example, in a circuit (e.g., a discrete circuit or an integrated circuit) or by a processing circuit (e.g., a digital signal processor) executing appropriate software code.

[0127] The output of the modulator 920 is coupled to the input of the first delay element 930 so that the PWM signal output by the modulator 920 is input to the first delay element 930. The output of the modulator 920 is also coupled to a first terminal of a first inductor 950 of the system 900.

[0128] The first delay element 930 is configured to apply a delay to an input digital signal and output a delayed version of the digital signal. The output of the first delay element 1930 is coupled to the input of the second delay element 940, such that the delayed version of the digital signal output by the first delay element 930 is input to the second delay element 940. The output of the first delay element 930 is also coupled to a first terminal of a second inductor 960.

[0129] The second delay element 940 is configured to apply a further delay to the input digital signal and output a further delayed version of the digital signal. An output of the second delay element 940 is coupled to a first terminal of a third inductor 970 .

[0130] The first delay element and the second delay element can be implemented, for example, in discrete circuits or integrated circuits, or in processing circuitry that executes appropriate software code. Where the delay elements are implemented in an integrated circuit, they can be integrated with the modulator circuit in a single integrated circuit (IC), or alternatively can be integrated together as separate ICs. Alternatively, each delay element can be integrated as a separate IC.

[0131] The second terminals of the first inductor 950, the second inductor 960, and the third inductor 970 are coupled together and to an output terminal or node 980 of the system 900, which is configured to be coupled to an input terminal of the loudspeaker 910. Thus, the output terminal or node 980 provides an output node for a drive signal to drive the transducer 910.

[0132] As will be understood by those skilled in the art, the combination of the first and second delay elements 930, 940, the first, second, and third inductors 950, 960, 970, and the cone 912 of the speaker 910 acts as a FIR DAC (Finite Impulse Response Digital-to-Analog Converter), as described above with reference to FIG. Figure 2 As described.

[0133] System 900 can be implemented as a single integrated circuit, in which case inductors 950, 960, 970 can be embedded or on-chip inductors. Alternatively, system 900 can be implemented as a module comprising one or more integrated circuits implementing modulator 920 and delay elements 930, 940 mounted on a substrate such as a printed circuit board (PCB), with inductors 950, 960, 970 also mounted on the substrate external to the integrated circuit(s). In some examples, speaker 910 can also be mounted on the substrate so as to form part of the module. Alternatively, the speaker can be provided separately and therefore may not form part of the module.

[0134] Figure 10 is a schematic diagram of a system for driving a single-coil transducer.

[0135] System 1000 includes a modulator 1020 configured to receive an analog input signal (such as an audio signal) and convert it into a digital output signal (such as a pulse-width modulated (PWM) signal). For example, modulator 1020 can be, for example, an asynchronous or self-oscillating PWM modulator and / or a Class-D modulator. Modulator 1020 can be implemented, for example, in a circuit (e.g., a discrete circuit or an integrated circuit) or by a processing circuit (e.g., a digital signal processor) executing appropriate software code.

[0136] The output of the modulator 1020 is coupled to the input of the clocked delay element 1030, so that the digital signal output by the modulator 1020 is input to the clocked delay element 1030. The output of the modulator 1020 is also connected to a first output terminal 1052 of the system 1000, which is configured to be coupled to a first terminal of a first inductor 1060.

[0137] The clocked delay element 1030 is configured to apply a delay to an input digital signal and output a delayed version of the digital signal. The clocked delay element 1030 may include, for example, the delay element 1030 described above with reference to FIG. Figure 5 and Figure 6 Describes a type of clock buffer or digital delay element.

[0138] An output of the clocked delay element 1030 is coupled to a second output terminal 1054 of the system 1000 , which is configured to be coupled to a first terminal of a second inductor 1060 .

[0139] The second terminals of the first inductor 1060 and the second inductor 1070 are coupled together and to an output terminal or node 1052 of the system 1000, which is configured to be coupled to an input terminal of the transducer 1010. Thus, the output terminal or node 1052 provides an output node for a drive signal to drive the transducer 1010.

[0140] The clocked delay element 1030 can be implemented, for example, in a discrete circuit or an integrated circuit, or in a processing circuit that executes appropriate software code. Where the clocked delay element 1030 is implemented in an integrated circuit, it can be integrated with the modulator circuit in a single integrated circuit (IC), or alternatively can be integrated as a separate IC. Alternatively, the clocked delay element 1030 can be integrated as a separate IC.

[0141] The system 1000 also includes a clock signal generator 1040 operable to generate a clock signal and output the clock signal to the clocked delay element 1030 .

[0142] exist Figure 10 In the example shown, one clocked delay element 1030 is provided, but it will be appreciated that a greater number of such delay elements may be provided, with the output of each delay element supplying a delayed version of the digital signal output by the modulator 1020 to a different inductor.

[0143] As will be appreciated by those skilled in the art, the combination of the clocked delay element 1030, the first and second inductors 1060, 1070, and the transducer 1010 is described above with reference to FIG. Figure 2 The described approach acts as a FIR DAC (Finite Impulse Response Digital-to-Analog Converter).

[0144] System 1000 may be implemented as an integrated circuit, in which case inductors 1060, 1070 may be embedded or on-chip inductors. Alternatively, system 1000 may be implemented as a module comprising one or more integrated circuits implementing modulator 1020, clocked delay element 1030, and clock 1040 mounted on a substrate such as a printed circuit board (PCB), with inductors 1060, 1070 also mounted on the substrate external to the integrated circuit(s). In some examples, transducer 1010 may also be mounted on the substrate so as to form part of the module. Alternatively, transducer 1010 may be provided separately and therefore may not form part of the module.

[0145] Embodiments may be implemented in a range of applications and are particularly well suited for audio applications.

[0146] Embodiments may be implemented as integrated circuits, which in some examples may be codecs or audio DSPs, for example. Embodiments may be incorporated into electronic devices, such as portable devices and / or devices that can operate on battery power. The device may be a communication device, such as a mobile phone or smartphone. The device may be a computing device, such as a notebook computer, laptop computer, or tablet computing device. The device may be a wearable device, such as a smartwatch. The device may be a device with voice control or activation capabilities. In some cases, the device may be an accessory device used with some other product, such as a head-mounted device.

[0147] Those skilled in the art will recognize that some aspects of the above-described apparatus and methods, such as the discovery and configuration methods, may be implemented as processor control code, for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, a program memory such as a read-only memory (firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications, the embodiments will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or code for setting up or controlling an ASIC or FPGA, for example. The code may also include code for dynamically configuring a reconfigurable apparatus such as a reprogrammable logic gate array. Similarly, the code may include code for programming a program such as a Verilog processor. TM The embodiment of the present invention may be implemented using code written in a hardware description language such as VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language). As will be appreciated by those skilled in the art, the code may be distributed among multiple coupled components that communicate with each other. Where appropriate, embodiments may also be implemented using code running on a field (re)programmable analog array or similar device to configure the analog hardware.

[0148] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may perform the functions of several units listed in the claims. Any reference signs or labels in the claims should not be construed as limiting the scope.

Claims

1. A system for driving a speaker having a plurality of coils, the system comprising: a modulator configured to receive an input signal and output a pulse width modulated (PWM) output signal representative of the received input signal; a delay element for receiving the PWM output signal and applying a delay to the PWM output signal to generate a first delayed signal, the delay element comprising a clock buffer or a counter; a first output configured to be coupled to a first coil of the plurality of coils of the speaker, wherein the first output is coupled to an output of the modulator; as well as a second output configured to be coupled to a second coil of the plurality of coils of the speaker, wherein the second output is coupled to an output of the delay element; Wherein the modulator and the delay element are configured to receive a clock signal.

2. The system of claim 1, wherein the modulator comprises a class D amplifier. The system of claim 1 , wherein the input signal comprises an audio signal.

4. The system of claim 1, wherein the input signal comprises a digital signal and the modulator comprises a digital modulator.

5. The system of claim 1, wherein the delay element further comprises an edge detector and an edge generator, wherein: The edge detector is configured to detect an edge of an input PWM signal and trigger the counter when the edge is detected; The counter is configured to count pulses of the clock signal until a predetermined number is reached and output a signal to the edge generator when the predetermined number is reached; and The edge generator is configured to output a delayed and inverted version of the input PWM signal in response to receiving the signal from the counter. 6 . The system of claim 1 , wherein the delay element is configured to apply a delay to the PWM output signal that is equal to one period of the PWM output signal.

7. The system of claim 1, wherein the delay element forms at least a portion of a finite impulse response (FIR) filter arrangement.

8. The system of claim 7, wherein the FIR filter device is configured to receive a configuration signal and, based on the configuration signal, adapt in response to a change in the frequency of the PWM output signal output.

9. The system of claim 8, wherein the FIR filter device is operable to adjust a predetermined value used by a counter of the FIR filter device in response to the configuration signal.

10. The system of claim 9, wherein the FIR filter device is configured to suppress a carrier wave of the PWM output signal.

11. The system of claim 10, wherein the FIR filter arrangement is configured to provide a zero at a carrier frequency of the PWM output signal.

12. The system of claim 1, wherein a carrier frequency of the PWM output signal is modulatable based on a control signal.

13. The system of claim 12, wherein the control signal is based on an operating mode of the system.

14. The system of claim 12, wherein the control signal is based on an input signal level of the input signal.

15. An integrated circuit comprising the system according to claim 1.

16. A device comprising the system of claim 1, wherein the device comprises a portable device, a battery powered device, a mobile phone, a notebook, a laptop or tablet computing device, a smart watch, or an accessory device.

17. A method for driving a speaker having a plurality of coils, the method comprising: receiving a clock signal and an input signal at a modulator and outputting a pulse width modulated (PWM) output signal representative of the received input signal; as well as applying a delay to the PWM output signal using a delay element including a clock buffer or a counter to generate a first delayed signal, wherein the delay element receives the clock signal; Outputting the PWM modulated output signal to a first coil among the plurality of coils; as well as The first delayed signal is output to a second coil among the plurality of coils.

18. A system for driving a speaker having a plurality of coils, the system comprising: a modulator for receiving an input signal and outputting a first pulse width modulation (PWM) output signal for driving a first coil among the plurality of coils; a finite pulse filter (FIR) device for receiving the first PWM output signal and outputting a second PWM output signal for driving a second coil among the plurality of coils, The FIR device is configured to adapt to frequency variation of the first PWM output signal so as to suppress a carrier of the first PWM output signal.

19. An integrated circuit comprising the system according to claim 18.

20. A system for driving a transducer, the system comprising: a modulator for outputting a digital output signal representative of the received analog input signal at a modulator output; a delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; a first inductor having a first terminal coupled to the modulator output; as well as a second inductor having a first terminal coupled to the delay element output, Wherein a second terminal of the first inductor is coupled to a second terminal of the second inductor to provide an output node for a drive signal to drive the transducer.

21. The system of claim 20, wherein the first inductor and the second inductor comprise a first coil and a second coil of the transducer.

22. A system according to claim 20 or claim 21, wherein the transducer comprises a speaker.

23. A module comprising a system according to any one of claims 20 to 22 and a transducer.

24. An integrated circuit comprising a system according to any one of claims 20 to 22.

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