Instruction decoding method and device, electronic device, and storage medium

Abstract

The embodiment of the present invention discloses an instruction decoding method and device, an electronic device, and a storage medium, which relate to the field of computer technology and can effectively improve the usability of a model on computers of different manufacturers. The method includes: when the host running the program does not belong to the preset host type, determining respectively whether the execution of each target instruction in the program will set the preset register bit in the preset register; in response to the execution of the first instruction in each target instruction, the preset register bit in the preset register will be set, and the first instruction is decoded using a first decoding method; or, in response to the execution of the first instruction in each target instruction, the preset register bit in the preset register will not be set, and the first instruction is decoded using a second decoding method; the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to an instruction decoding method and device, electronic equipment, and a storage medium. Background Art

[0002] After an integrated circuit is designed, its correctness needs to be verified using modeling. The primary purpose of modeling is to implement the target chip's key functions using low-cost computer software before committing significant manpower. This allows for evaluation of the chip's performance, verification of the design logic and functionality, and serves as a benchmark for subsequent development activities. After modeling is complete, the model's results are compared with the target circuit's design requirements to verify the correctness of the digital logic design.

[0003] Running a model on a computer requires support from the computer's instruction set. Since its introduction, the x86 architecture has become the standard platform for personal computers and one of the most successful CPU (central processing unit) architectures ever. System registers (such as the rFLAGS register) play a crucial role in instruction execution in the x86 architecture. For most registers, computers from different manufacturers set the status bits in the same way after running the same instruction. However, for some registers, computers from different manufacturers set the status bits differently when running the same instructions. For example, the rFLAGS register provides the behavior basis for executing related instructions in the x86 instruction set and stores the status results after executing related instructions. However, for some status bits in the rFLAGS register, computers from different manufacturers set them differently after running the same instructions. These differently set status bits are often referred to as "undefined flags" in the rFLAGS register.

[0004] Because different manufacturers' computers set the status bits in these registers differently, the status bits in these registers are inconsistent when the circuit model is run on different manufacturers' computers. Since these inconsistent register status bits further affect the subsequent calculation results of the circuit model, the results of running the circuit model on different manufacturers' computers are inconsistent, making it difficult to compare with the design specifications of the target circuit, thus greatly reducing the usability of the model on different manufacturers' computers. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an instruction decoding method and apparatus, an electronic device, and a computer-readable storage medium, which can effectively improve the usability of the model on computers from different manufacturers.

[0006] In a first aspect, an embodiment of the present invention provides an instruction decoding method, comprising: when a host running a program does not belong to a preset host type, determining separately whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register; in response to the execution of a first instruction among the target instructions, a setting operation will be performed on the preset register bit in the preset register, decoding the first instruction using a first decoding method; or, in response to the execution of the first instruction among the target instructions, a setting operation will not be performed on the preset register bit in the preset register, decoding the first instruction using a second decoding method; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

[0007] In one embodiment, determining whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register includes: determining whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register based on the instruction type of each target instruction in the program.

[0008] In one embodiment, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and decoding the first instruction using the first decoding method includes: determining the decoding strategy of the first decoding method according to the instruction type of the first instruction; and decoding the first instruction using the determined decoding strategy.

[0009] In one embodiment, determining the decoding strategy of the first decoding method based on the instruction type of the first instruction includes: in response to the instruction type of the first instruction being the first type, determining that the decoding strategy of the first decoding method is a completely customized strategy; in response to the instruction type of the first instruction being the second type, determining that the decoding strategy of the first decoding method is a partially customized strategy.

[0010] In one embodiment, the decoding strategy of the first decoding method is the partially customized strategy; the use of the determined decoding strategy to decode the first instruction includes: using the second decoding method to decode the first instruction, and modifying the preset register bit in the preset register according to the preset modification rule.

[0011] In one embodiment, the use of the second decoding method to decode the first instruction and modifying the preset register bit in the preset register according to a preset modification rule includes: adding a preset register modification code after the code of the first instruction; calling the second decoding method to decode the code of the first instruction and the register modification code.

[0012] In one embodiment, the target instruction includes at least one of the following: a binary instruction, a hexadecimal instruction, and an assembly instruction.

[0013] In one embodiment, before determining whether the execution of each target instruction in the program will set a preset register bit in a preset register, the method further includes: converting the program from a high-level language to a language based on the target instruction.

[0014] In one embodiment, before determining whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register, the method further includes: determining whether the host running the program belongs to a preset host type; if the host running the program belongs to the preset host type, using the second decoding method to decode each target instruction in the program.

[0015] In one embodiment, determining whether the host running the program belongs to a preset host type includes: running a preset type acquisition instruction to obtain type information of the host; and determining whether the host belongs to the preset host type based on the host type information.

[0016] In a second aspect, an embodiment of the present invention further provides an instruction decoding device, comprising: a first determination unit, for determining, when a host running a program does not belong to a preset host type, whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register; a first decoding unit, for decoding the first instruction using a first decoding method in response to the fact that the execution of the first instruction among the target instructions will perform a setting operation on the preset register bit in the preset register; or, a second decoding unit, for decoding the first instruction using a second decoding method in response to the fact that the execution of the first instruction among the target instructions will not perform a setting operation on the preset register bit in the preset register; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

[0017] In one embodiment, the first determining unit is specifically configured to determine, based on the instruction type of each target instruction in the program, whether execution of each target instruction will perform a setting operation on a preset register bit in a preset register.

[0018] In one embodiment, the first decoding unit includes: a strategy determination module, which determines a decoding strategy of the first decoding method according to the instruction type of the first instruction; and a decoding module, which is used to decode the first instruction using the determined decoding strategy.

[0019] In one embodiment, the strategy determination module is specifically used to: in response to the instruction type of the first instruction being the first type, determine that the decoding strategy of the first decoding method is a completely customized strategy; in response to the instruction type of the first instruction being the second type, determine that the decoding strategy of the first decoding method is a partially customized strategy.

[0020] In one embodiment, the decoding strategy of the first decoding method is the partially customized strategy; the decoding module is specifically used to decode the first instruction using the second decoding method, and modify the preset register bit in the preset register according to a preset modification rule.

[0021] In one embodiment, the decoding module includes: an adding submodule for adding a preset register modification code after the code of the first instruction; and a decoding submodule for calling the second decoding method to decode the code of the first instruction and the register modification code.

[0022] In one embodiment, the target instruction includes at least one of the following: a binary instruction, a hexadecimal instruction, and an assembly instruction.

[0023] In one embodiment, the instruction decoding device further includes: a conversion unit for converting the program from a high-level language into a language on which the target instruction is based before determining whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register.

[0024] In one embodiment, the instruction decoding device also includes: a second determination unit, which is used to determine whether the host running the program belongs to a preset host type before determining whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register; the second decoding unit is also used to use the second decoding method to decode each target instruction in the program when the second determination unit determines that the host running the program belongs to the preset host type.

[0025] In one embodiment, the second determining unit includes: an acquisition module for executing a preset type acquisition instruction to obtain type information of the host; and a type determination module for determining whether the host belongs to the preset host type based on the host type information.

[0026] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute any one of the instruction decoding methods provided by the embodiments of the present invention.

[0027] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any instruction decoding method provided by an embodiment of the present invention.

[0028] The instruction decoding method and device, electronic device, and computer-readable storage medium provided by the embodiments of the present invention can, when the host running the program does not belong to the preset host type, that is, when it is uncertain according to what rules the host running the program will set the preset register bit in the preset register, determine which decoding method to use for each target instruction based on whether the execution of each target instruction included in the program will perform a setting operation on the preset register bit in the preset register. For the first instruction that will perform a setting operation on the preset register bit in the preset register, where the first instruction can be any target instruction, the first decoding method can be used for decoding, so that the preset register bit in the preset register can be uniformly set through a customized decoding method, effectively avoiding the problem of inconsistent setting methods for the preset register bit in the preset register by computers of different host types. For the first instruction that will not perform a setting operation on the preset register bit in the preset register, the second decoding method can be used for decoding, so that the host's own decoding method can be used for fast decoding, effectively improving decoding efficiency. In this way, with instructions as the granularity, each target instruction can be decoded by calling the first decoding method or the second decoding method, which is more appropriate. This effectively ensures that computers of different host types set the preset register bits in the preset register in a consistent manner, while maximizing the decoding efficiency of the program and effectively improving the usability of the model on computers from different manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A flow chart of an instruction decoding method provided by an embodiment of the present invention;

[0031] Figure 2 A detailed flow chart of an instruction decoding method provided by an embodiment of the present invention;

[0032] Figure 3 A schematic structural diagram of an instruction decoding device provided by an embodiment of the present invention;

[0033] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0036] In order to enable those skilled in the art to better understand the technical concepts, implementation plans and beneficial technical effects of the embodiments of the present invention, the following is a detailed description through specific examples.

[0037] As mentioned in the background, different manufacturers' computers use different methods to set the status bits in certain registers. This results in inconsistent settings of these register status bits when a circuit model is run on computers from different manufacturers. These inconsistent register status bits further affect the subsequent calculations of the circuit model, resulting in inconsistent results when the circuit model is run on computers from different manufacturers, making it difficult to compare the results with the design specifications of the target circuit. This significantly reduces the usability of the model across computers from different manufacturers.

[0038] To address this issue, improvements can be made during the instruction decoding phase of program execution. For example, the computer's native decoding program can be disabled, and an improved decoding program can be used to decode the instructions. Because the improved decoding method has unified register and bit setting rules, it can effectively address the problem of inconsistent setting methods for preset bits in preset registers in computers from different manufacturers.

[0039] However, the improvement of the decoding program not only consumes a lot of resources, but also because the improved decoding program is not the computer's own decoding program, the decoding efficiency will be greatly reduced, thereby greatly reducing the execution efficiency of the program.

[0040] In order to further solve this problem, the inventors found in the research that when the host running the program does not belong to the preset host type, it is possible to determine separately whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register, and accordingly use a user-defined decoding method or the host's own decoding method to decode each instruction. This effectively ensures that computers of different host types have consistent settings of the preset register bits in the preset register, while maximizing the decoding efficiency of the program, thereby effectively improving the availability of the model on computers from different manufacturers.

[0041] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present invention, a detailed description is given below through specific examples.

[0042] In a first aspect, an embodiment of the present invention provides an instruction decoding method that can effectively improve the usability of a model on computers from different manufacturers.

[0043] like Figure 1 As shown, an embodiment of the present invention provides an instruction decoding method, which may include:

[0044] S11. When the host running the program does not belong to the preset host type, determining whether the execution of each target instruction in the program will set a preset register bit in the preset register;

[0045] The host computer running the program can refer to the computer running various programs. Since the CPU is the core of the computer, the host computer running the program can also refer to the CPU running the program. The program running on the host computer can be, for example, various circuit models that need to be simulated or verified on the computer.

[0046] The host type may refer to different types of central processing units of the host. According to different type classification standards, the host types are also divided accordingly, for example, they can be divided according to the manufacturer, according to the architecture, according to the main frequency, etc. In the embodiment of the present invention, different host types mainly refer to computer types that use different setting methods for the preset register bits in the computer preset register. For example, different CPU manufacturers usually have some of their own unique processing logic to set the preset register bits of the preset register. Therefore, computers from different manufacturers usually belong to different host types. Among them, the preset register and the preset register bit can be set as needed. For example, in one embodiment of the present invention, the preset register can be a status register, and the preset register bit can be CF (carry flag), PF (parity flag), etc.

[0047] In embodiments of the present invention, the preset host type may refer to a host type for which the rules for setting the preset register bits of the preset register are known. Therefore, if the host running the program does not belong to the preset host type, it means that the rules for setting the preset register bits of the preset register of the host running the program are unknown.

[0048] In this step, before each target instruction is executed, it can be determined whether the execution of the target instruction will result in setting the preset register bit in the preset register.

[0049] S12. In response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and the first instruction is decoded using a first decoding method; or, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will not be set, and the first instruction is decoded using a second decoding method; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

[0050] In this step, the first instruction can be any one of the target instructions in the program. If the execution of the first instruction will set the preset register bit in the preset register, the first decoding method can be used to decode the first instruction. If the execution of the first instruction will not set the preset register bit in the preset register, the second decoding method can be used to decode the first instruction.

[0051] The instruction decoding method provided by an embodiment of the present invention can, when the host computer running the program does not belong to the preset host type, determine whether the execution of each target instruction in the program will set the preset register bit in the preset register. In response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and the first instruction is decoded using a first decoding method; or, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will not be set, and the first instruction is decoded using a second decoding method. In this way, when the host computer running the program does not belong to the preset host type, that is, when it is uncertain what rules the host computer running the program will follow to set the preset register bit in the preset register, it is possible to determine which decoding method to use for each target instruction based on whether the execution of each target instruction included in the program will set the preset register bit in the preset register. For a first instruction that will set a preset register bit in a preset register, where the first instruction can be any target instruction, a first decoding method can be used for decoding, so that the preset register bit in the preset register can be uniformly set through a custom decoding method, effectively avoiding the problem of inconsistent setting methods of the preset register bit in the preset register for computers of different host types. For a first instruction that will not set a preset register bit in the preset register, a second decoding method can be used for decoding, so that the host's own decoding method can be used for fast decoding, effectively improving decoding efficiency. In this way, with the instruction as the granularity, a more appropriate decoding method of the first decoding method or the second decoding method can be called for decoding for each target instruction, thereby effectively ensuring that different host types of computers have consistent setting methods for the preset register bit in the preset register, while maximizing the decoding efficiency of the program and effectively improving the availability of the model on computers from different manufacturers.

[0052] Optionally, in an embodiment of the present invention, the target instruction may include one or more of the following: binary instructions, hexadecimal instructions, assembly instructions, etc. Based on this, if the program running on the host is written based on a high-level language such as C language, then before determining in step S11 whether the execution of each target instruction in the program will set the preset register bit in the preset register, the instruction decoding method provided by the embodiment of the present invention may further include: converting the program from the high-level language into the language on which the target instruction is based. For example, in one embodiment of the present invention, if a circuit model is written based on C language, each instruction based on C language can first be converted into, for example, hexadecimal instructions.

[0053] Typically, a high-level language instruction is converted into several target instructions and stored in memory. When executing each target instruction, the CPU sequentially retrieves each target instruction, decodes it into the corresponding machine code, and stores the machine code in memory for execution.

[0054] In a specific implementation, before step S11 determines whether the execution of each target instruction in the program will set the preset register bit in the preset register, the instruction decoding method provided by the embodiment of the present invention may also include: determining whether the host running the program belongs to the preset host type; if the host running the program belongs to the preset host type, using the second decoding method to decode each target instruction in the program. In other words, if it is determined that the host running the program belongs to the preset host type, the rule for setting the preset register bit of the preset register by the host is known. Therefore, directly using the second decoding method, that is, using the host's own decoding method to decode the target instruction will not cause the setting method of the preset register bit to be inconsistent with the known setting method. Therefore, for such a host, the second decoding method can be directly used to decode the target instruction.

[0055] Alternatively, various methods may be used to determine whether the host running the program belongs to a preset host type. For example, in one embodiment of the present invention, determining whether the host running the program belongs to a preset host type may include: executing a preset type acquisition instruction to obtain type information of the host; and determining whether the host belongs to the preset host type based on the host type information. Exemplarily, the type acquisition instruction may be, for example, a cpuid instruction, thereby obtaining various relevant information such as the host manufacturer.

[0056] On the contrary, if the host running the program does not belong to the preset host type, that is, the rule for setting the preset register bit of the preset register of the host is unknown, then after using the second decoding method to decode each target instruction of the program, it is possible that the setting method of the preset register bit of the preset register will be inconsistent with the known setting method. For this reason, corresponding processing can be performed in step S11.

[0057] Specifically, in one embodiment of the present invention, when the host computer running the program does not belong to the preset host type, step S11 determines whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register. Specifically, it can include: determining whether the execution of each target instruction will perform a setting operation on the preset register bit in the preset register according to the instruction type of each target instruction in the program. For example, a list or table of instructions that will perform a setting operation on the preset register bit in the preset register can be established in advance, and an instruction identification operation (such as identifying the operation code of the target instruction) can be performed on the target instruction. If it is found that the target instruction is an instruction in the list or table, it can be determined that the execution of the target instruction will perform a setting operation on the preset register bit in the preset register. Otherwise, if it is found that the target instruction is not an instruction in the list or table, it can be determined that the execution of the target instruction will not perform a setting operation on the preset register.

[0058] After determining whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register, different decoding methods can be used to decode the corresponding target instructions accordingly. For example, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and the first decoding method can be used to decode the first instruction.

[0059] Optionally, in one embodiment of the present invention, the first decoding method may be a user-defined decoding method. However, depending on the degree of customization or the customization method, the first decoding method may also have different decoding strategies. Therefore, while still using the first decoding method for decoding, different decoding strategies may be used. In this embodiment of the present invention, the most suitable decoding strategy may be selected to decode the corresponding first instruction.

[0060] Specifically, in one embodiment of the present invention, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and decoding the first instruction using the first decoding method may specifically include: determining the decoding strategy of the first decoding method according to the instruction type of the first instruction; and decoding the first instruction using the determined decoding strategy.

[0061] Optionally, based on the instruction type of the first instruction, determining the decoding strategy of the first decoding method may specifically include: in response to the instruction type of the first instruction being the first type, determining that the decoding strategy of the first decoding method is a completely customized strategy; in response to the instruction type of the first instruction being the second type, determining that the decoding strategy of the first decoding method is a partially customized strategy.

[0062] Optionally, in the above embodiment, the first type and the second type can be divided according to various rules such as instruction length, instruction execution cycle, instruction mnemonics, etc., and the embodiments of the present invention do not limit this. In one embodiment of the present invention, in order to further improve the instruction decoding efficiency, the first type and the second type can be divided according to the different complexities of the setting algorithms for the preset register bits of the preset register in each instruction, wherein the first type of instruction can be an instruction with a relatively complex setting algorithm for the preset register bits of the preset register in the host's own decoding method, and the second type of instruction can be an instruction with a relatively simple setting algorithm for the preset register bits of the preset register in the host's own decoding method. Since the setting algorithm for the preset register bits of the preset register in the first type of instruction is relatively complex and it is not easy to sort out the specific setting logic, the decoding operation of the host's own decoding method on the first type of instruction can be shielded, and the first type of instruction can be directly decoded using a completely customized strategy. On the contrary, since the setting algorithm of the preset register bits of the preset register for the second type of instructions is relatively simple and the specific setting logic is easier to understand, it can be slightly modified based on the host's own decoding method, that is, a partially customized decoding strategy is used to decode the second type of instructions, so that the host's own decoding method can be more fully utilized to further improve the decoding efficiency.

[0063] Specifically, in one embodiment of the present invention, it is determined that the first instruction is decoded using a first decoding method, and the decoding strategy of the first decoding method is a partially customized strategy; based on this, using the determined decoding strategy, decoding the first instruction can specifically include: using the second decoding method to decode the first instruction, and modifying the preset register bit in the preset register according to the preset modification rule. The second decoding method is the host's own decoding method. In this way, after first decoding the first instruction using the host's own decoding method, the preset register bit of the preset register will be set once according to the host's own register bit setting algorithm, and thereafter, the preset register bit of the preset register can be modified according to the preset modification rule, so that the preset register bit of the preset register is modified according to a unified rule, effectively avoiding the difference in the setting of the preset register bit of the preset register by different host types.

[0064] In a specific implementation, using the second decoding method to decode the first instruction and modifying the preset register bits in the preset register according to a preset modification rule may include: adding a preset register modification code after the code of the first instruction; and calling the second decoding method to decode the code of the first instruction and the register modification code. Since the preset register modification code is appended after the code of the first instruction, calling the second decoding method (i.e., the host's own decoding method) to decode and execute these two parts of code allows the first instruction to be decoded and executed with high efficiency, while also enabling the preset register bits of the preset register to be set according to a unified rule, thereby effectively improving the usability of the model on different computers.

[0065] Specifically, in another embodiment of the present invention, it is determined that the first instruction is decoded using a first decoding method, and the decoding strategy of the first decoding method is a completely customized strategy; based on this, a customized function can be called to modify the preset register bit (such as various Undefined Flags) of the preset register. Depending on the target instruction, the method for setting the preset register bit of the preset register by the customized function can be different. For example, in one embodiment of the present invention, the method for setting the preset register bit of the preset register by the customized function can adopt any of the following methods: the highest bit of the instruction operation result is XORed with the second highest bit of the result, the carry (CF) bit in the preset register is XORed with the highest bit of the operation result, and the carry (CF) bit in the preset register is assigned to the preset register bit of the preset register.

[0066] The instruction decoding method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0067] like Figure 2 As shown, the instruction decoding method provided by the embodiment of the present invention may include:

[0068] S201, converting a high-level language instruction in the target circuit model into one or more target instructions and storing them in the memory.

[0069] For example, the high-level language may be C language, and the target instruction may be a hexadecimal instruction.

[0070] S202 , fetch a target instruction and perform instruction recognition on the target instruction to identify the instruction type of the target instruction, and store the machine code obtained after instruction recognition into a memory.

[0071] Exemplarily, instruction identification may be performed by identifying an operation code (OPCode) of a target instruction. For example, the instruction type of a target instruction may be identified by an operation code such as MOV or JMP.

[0072] S203: Execute a preset type acquisition instruction to acquire type information of a host running the program.

[0073] For example, the type acquisition instruction may be a cpuid instruction, and the type information of the host may be, for example, information such as the manufacturer and model.

[0074] S204: Determine whether the host belongs to a preset host type according to the host type information. If yes, execute step S205; if not, execute step S206.

[0075] S205 , decode the target instruction using the second decoding method, and execute step S213 .

[0076] S206, determining whether the execution of the target instruction will set the preset register bit in the preset register according to the instruction type of the target instruction, if yes, executing step S207, if not, executing step S205.

[0077] S207, determining a decoding strategy of a first decoding method according to the instruction type of the target instruction; if the instruction type of the target instruction is the first type, executing step S208; if the instruction type of the target instruction is the second type, executing step S211.

[0078] S208: Determine that the decoding strategy of the first decoding mode is a partially customized strategy.

[0079] S209: Add a preset register modification code after the target instruction code.

[0080] Optionally, the register modification code may include various logics for setting, clearing, or maintaining a preset register bit of a preset register. For example, the register modification code may be setting the CF bit in the flag register to 1.

[0081] S210, calling the second decoding mode, decoding the code of the target instruction and the register modification code, and executing step S213.

[0082] S211, determining that the decoding strategy of the first decoding mode is a completely customized strategy;

[0083] S212, decoding the target instruction using a completely customized strategy;

[0084] During the decoding process, the preset register bits of the preset register can be set in a customized manner.

[0085] S213, whether there is a next target instruction, if so, return to S202, process the next target instruction, if not, execute step S214;

[0086] S214 returns to the target circuit model main program and checks whether there is a next high-level language instruction. If so, return to S201; if not, end.

[0087] Correspondingly, in a second aspect, an embodiment of the present invention further provides an instruction decoding device, which can effectively improve the usability of the model on computers from different manufacturers.

[0088] like Figure 3 As shown, the instruction decoding device provided by the embodiment of the present invention may include:

[0089] The first determining unit 31 is configured to determine, when the host running the program does not belong to the preset host type, whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in the preset register;

[0090] a first decoding unit 32, configured to perform a setting operation on the preset register bit in the preset register in response to execution of a first instruction among the target instructions, and decode the first instruction using a first decoding method;

[0091] Alternatively, the second decoding unit 33 is used to decode the first instruction using a second decoding method in response to the execution of the first instruction among the target instructions not performing a setting operation on the preset register bit in the preset register; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

[0092] The instruction decoding device provided by an embodiment of the present invention can, when the host computer running the program does not belong to the preset host type, determine whether the execution of each target instruction in the program will set the preset register bit in the preset register. In response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and the first instruction is decoded using a first decoding method; or, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will not be set, and the first instruction is decoded using a second decoding method. In this way, when the host computer running the program does not belong to the preset host type, that is, when it is uncertain what rules the host computer running the program will follow to set the preset register bit in the preset register, it can determine which decoding method to use for each target instruction based on whether the execution of each target instruction included in the program will set the preset register bit in the preset register. For a first instruction that will set a preset register bit in a preset register, where the first instruction can be any target instruction, a first decoding method can be used for decoding, so that the preset register bit in the preset register can be uniformly set through a custom decoding method, effectively avoiding the problem of inconsistent setting methods of the preset register bit in the preset register for computers of different host types. For a first instruction that will not set a preset register bit in the preset register, a second decoding method can be used for decoding, so that the host's own decoding method can be used for fast decoding, effectively improving decoding efficiency. In this way, with the instruction as the granularity, a more appropriate decoding method of the first decoding method or the second decoding method can be called for decoding for each target instruction, thereby effectively ensuring that different host types of computers have consistent setting methods for the preset register bit in the preset register, while maximizing the decoding efficiency of the program and effectively improving the availability of the model on computers from different manufacturers.

[0093] In one embodiment, the first determining unit 31 may be specifically configured to determine, based on the instruction type of each target instruction in the program, whether execution of each target instruction will perform a setting operation on a preset register bit in a preset register.

[0094] In one embodiment, the first decoding unit 32 may include: a strategy determination module, which determines a decoding strategy of the first decoding method according to the instruction type of the first instruction; and a decoding module, which is used to decode the first instruction using the determined decoding strategy.

[0095] In one embodiment, the strategy determination module can be specifically used to: in response to the instruction type of the first instruction being the first type, determine that the decoding strategy of the first decoding method is a completely customized strategy; in response to the instruction type of the first instruction being the second type, determine that the decoding strategy of the first decoding method is a partially customized strategy.

[0096] In one embodiment, the decoding strategy of the first decoding method is the partially customized strategy; the decoding module can be specifically used to decode the first instruction using the second decoding method, and modify the preset register bit in the preset register according to a preset modification rule.

[0097] In one embodiment, the decoding module includes: an adding submodule for adding a preset register modification code after the code of the first instruction; and a decoding submodule for calling the second decoding method to decode the code of the first instruction and the register modification code.

[0098] In one embodiment, the target instruction includes at least one of the following: a binary instruction, a hexadecimal instruction, and an assembly instruction.

[0099] In one embodiment, the instruction decoding device may further include: a conversion unit for converting the program from a high-level language into a language on which the target instruction is based before determining whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register.

[0100] In one embodiment, the instruction decoding device may further include: a second determination unit, used to determine whether the host running the program belongs to a preset host type before determining whether the execution of each target instruction in the program will perform a setting operation on the preset register bit in the preset register; the second decoding unit is also used to use the second decoding method to decode each target instruction in the program when the second determination unit determines that the host running the program belongs to the preset host type.

[0101] In one embodiment, the second determining unit includes: an acquisition module for executing a preset type acquisition instruction to obtain type information of the host; and a type determination module for determining whether the host belongs to the preset host type based on the host type information.

[0102] Thirdly, as Figure 4As shown, an embodiment of the present invention further provides an electronic device, comprising: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140, wherein the circuit board 130 is placed inside the space enclosed by the housing 100, and the processor 110 and the memory 120 are arranged on the circuit board 130; the power supply circuit 140 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 120 is used to store executable program code; the processor 110 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 120, and is used to execute any one of the instruction decoding methods provided in the aforementioned embodiments. The specific execution process of the above steps by the processor 110 and the steps further performed by the processor 110 by running the executable program code can be referred to the description of the aforementioned embodiment and will not be repeated here.

[0103] In a fourth aspect, embodiments of the present invention further provide a computer-readable storage medium storing one or more programs, wherein the one or more programs can be executed by one or more processors to implement any of the instruction decoding methods provided in the aforementioned embodiments. The specific execution process of the aforementioned steps by the processor and the further steps performed by the processor by running the executable program code can be found in the description of the aforementioned embodiments and are not further described here.

[0104] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0105] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0106] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0107] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0108] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0109] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An instruction decoding method, characterized in that: include: When the host running the program does not belong to a preset host type, determining whether the execution of each target instruction in the program will set a preset register bit in a preset register; wherein the preset host type refers to a host type for which a setting rule for the preset register bit is known; In response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will be set, and the first instruction will be decoded using a first decoding method; or, in response to the execution of the first instruction among the target instructions, the preset register bit in the preset register will not be set, and the first instruction will be decoded using a second decoding method; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

2. The method according to claim 1, characterized in that The determining whether the execution of each target instruction in the program will set the preset register bit in the preset register includes: According to the instruction type of each target instruction in the program, it is determined whether the execution of each target instruction will perform a setting operation on a preset register bit in a preset register.

3. The method according to claim 1, characterized in that In response to the execution of the first instruction among the target instructions, the preset register bit in the preset register is set, and decoding the first instruction using the first decoding mode includes: determining a decoding strategy of the first decoding mode according to an instruction type of the first instruction; The first instruction is decoded using the determined decoding strategy.

4. The method according to claim 3, characterized in that Determining the decoding strategy of the first decoding mode according to the instruction type of the first instruction includes: In response to the instruction type of the first instruction being the first type, determining that the decoding strategy of the first decoding mode is a completely customized strategy; In response to the instruction type of the first instruction being the second type, determining that the decoding strategy of the first decoding mode is a partially customized strategy.

5. The method according to claim 4, characterized in that The decoding strategy of the first decoding mode is the partially customized strategy; Decoding the first instruction using the determined decoding strategy includes: The first instruction is decoded using the second decoding method, and the preset register bit in the preset register is modified according to a preset modification rule.

6. The method according to claim 5, characterized in that The decoding of the first instruction by using the second decoding mode and modifying the preset register bit in the preset register according to a preset modification rule includes: Adding a preset register modification code after the code of the first instruction; The second decoding mode is called to decode the code of the first instruction and the register modification code.

7. The method according to any one of claims 1 to 6, characterized in that The target instruction includes at least one of the following: a binary instruction, a hexadecimal instruction, and an assembly instruction.

8. The method according to claim 7, characterized in that Before determining whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register, the method further includes: The program is converted from a high-level language into a language on which the target instructions are based.

9. The method according to any one of claims 1 to 6, characterized in that Before determining whether the execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register, the method further includes: Determine whether the host running the program belongs to the preset host type; When the host running the program belongs to the preset host type, each target instruction in the program is decoded using the second decoding method.

10. The method according to claim 9, characterized in that Determining whether the host running the program belongs to the preset host type includes: Run a preset type acquisition instruction to obtain type information of the host; Determine whether the host belongs to the preset host type according to the type information of the host.

11. An instruction decoding device, characterized in that: include: a first determining unit for determining, when a host running the program does not belong to a preset host type, whether execution of each target instruction in the program will perform a setting operation on a preset register bit in a preset register; wherein the preset host type refers to a host type for which a setting rule for the preset register bit is known; a first decoding unit, configured to perform a setting operation on the preset register bit in the preset register in response to execution of a first instruction among the target instructions, and decode the first instruction using a first decoding method; or, A second decoding unit is used to decode the first instruction using a second decoding method in response to the fact that the execution of the first instruction among the target instructions will not set the preset register bit in the preset register; wherein the first decoding method is a user-defined decoding method, the second decoding method is the host's own decoding method, and the first instruction is any one of the target instructions.

12. The device according to claim 11, characterized in that The first determining unit is specifically configured to determine, based on the instruction type of each target instruction in the program, whether the execution of each target instruction will perform a setting operation on a preset register bit in a preset register.

13. The device according to claim 11, characterized in that The first decoding unit includes: a strategy determination module, determining a decoding strategy of the first decoding mode according to an instruction type of the first instruction; A decoding module is configured to decode the first instruction using the determined decoding strategy.

14. The device according to claim 13, characterized in that The strategy determination module is specifically used to: In response to the instruction type of the first instruction being the first type, determining that the decoding strategy of the first decoding mode is a completely customized strategy; In response to the instruction type of the first instruction being the second type, determining that the decoding strategy of the first decoding mode is a partially customized strategy.

15. The device according to claim 14, characterized in that The decoding strategy of the first decoding mode is the partially customized strategy; The decoding module is specifically configured to decode the first instruction using the second decoding method, and modify the preset register bit in the preset register according to a preset modification rule.

16. The device according to claim 15, characterized in that The decoding module includes: Adding a submodule, used to add a preset register modification code after the code of the first instruction; The decoding submodule is used to call the second decoding mode to decode the code of the first instruction and the register modification code.

17. The device according to any one of claims 11 to 16, characterized in that The target instruction includes at least one of the following: a binary instruction, a hexadecimal instruction, and an assembly instruction.

18. The device according to claim 17, characterized in that Also includes: The conversion unit is used to convert the program from a high-level language into a language based on the target instruction before determining whether the execution of each target instruction in the program will set the preset register bit in the preset register.

19. The device according to any one of claims 11 to 16, characterized in that Also includes: a second determining unit, configured to determine whether the host running the program belongs to a preset host type before determining whether the execution of each target instruction in the program will set a preset register bit in the preset register; The second decoding unit is further configured to decode each target instruction in the program using the second decoding method when the second determining unit determines that the host running the program belongs to the preset host type.

20. The device according to claim 19, characterized in that The second determining unit includes: An acquisition module, configured to execute a preset type acquisition instruction to acquire the type information of the host; The type determination module is used to determine whether the host belongs to the preset host type according to the type information of the host.

21. An electronic device, characterized in that: include: A housing, at least one processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the instruction decoding method described in any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the instruction decoding method according to any one of claims 1 to 10.

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