Table entry reading method, device and network equipment

Abstract

The present invention provides a table entry reading method, device, and network device. The method includes: after receiving a read command, selecting a target controller, adding the target controller identifier to a corresponding controller identifier cache queue, adding the read command to a corresponding sub-command cache queue, sending the read command to the controller, and adding the corresponding module identifier to the module identifier cache queue; after receiving a table entry, obtaining the module identifier stored first in the module identifier cache queue, adding the table entry to a corresponding sub-table entry cache queue, and sending the table entry in the sub-table entry cache queue to a corresponding interface module according to the order in which the controller identifiers were added in the corresponding controller identifier cache queue. The interface module and the controller can cross-transmit read commands and table entries. If a controller fails, other controllers can be used, thereby improving the reliability of table entry reading; the bandwidth of the interface between the interface module and the controller can be shared, thereby improving bandwidth utilization.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a table entry reading method, device and network equipment. Background Art

[0002] With the development of network technology, router routing table queries face the challenge of high reliability. Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) has the characteristics of large capacity and low cost and is commonly used to store routing tables.

[0003] like Figure 1 The figure shows an architecture diagram of a solution for accessing DDR through table lookup using multiple 100G interfaces in the related art. The solution includes a table entry configuration module 101, a table lookup engine 102, six interface modules 103, six DDR controllers 104, and six DDR SDRAMs 105. Each interface module 103 and each DDR controller 104 are connected via a DDR interface. The specific operation process is as follows: the central processing unit (CPU) calls the table entry configuration module 101 to configure the routing table in each DDR SDRAM 105. After receiving a message, the table lookup engine 102 parses the message to obtain the storage address of the table entry, triggers the interface module 103 corresponding to the storage address, and sends a read command to the DDR controller 104 corresponding to the interface module 103. After receiving the read command, the DDR controller 104 retrieves the table entry from the corresponding DDR SDRAM 105 and returns the table entry to the interface module 103 corresponding to the DDR controller 104.

[0004] In the above solution, the interface modules, DDR controllers, and DDR SDRAMs are mapped one-to-one. If a DDR controller fails, it will be unable to process read commands from the corresponding interface module, thus affecting table lookup access. Furthermore, bandwidth cannot be shared between DDR interfaces. In summary, the existing multi-interface DDR table lookup technology suffers from low reliability and inability to maximize bandwidth utilization. Summary of the Invention

[0005] The embodiments of the present invention provide a table entry reading method, apparatus and network equipment, which are used to solve the problems in the prior art of low reliability and inability to maximize bandwidth during multi-interface DDR table lookup access.

[0006] In a first aspect, an embodiment of the present invention provides a table entry reading method, which is applied to a cross-connect module included in a table entry reading device of a network device, wherein the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller. The method includes:

[0007] After receiving a read command sent by any interface module of the at least two interface modules, determining a target controller according to status information of a sub-command cache queue corresponding to the arbitrary interface module in a command cache queue of each controller and a preset polling rule, adding a controller identifier of the target controller to a controller identifier cache queue corresponding to the arbitrary interface module, and adding the read command to a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the target controller; and

[0008] sending, according to the load balancing principle, the read commands in the sub-command cache queues included in the command cache queues of the controllers to the corresponding controllers, and adding the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the table entry corresponding to the received read command from the corresponding memory; and

[0009] After receiving the table entry returned by any controller among the at least two controllers, obtaining the first stored target module identifier from the module identifier cache queue corresponding to the arbitrary controller, and adding the received table entry to the sub-table entry cache queue corresponding to the arbitrary controller in the table entry cache queue of the interface module corresponding to the target module identifier; and

[0010] According to the order in which the controller identifiers are added in the controller identifier cache queue corresponding to each interface module, entries in the sub-entry cache queue corresponding to each controller in each entry cache queue of each interface module are sent to the corresponding interface module.

[0011] Based on the above solution, since the interface module, controller and memory can cross-transmit read commands and table entries, if a controller fails, other controllers can be used, thereby improving the reliability of table entry reading. In addition, since the interface module, controller and memory are not one-to-one corresponding, the bandwidth of the interface between the interface module and the controller can be shared, thereby improving bandwidth utilization.

[0012] In a possible implementation, determining the target controller according to the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule includes:

[0013] Determine the candidate controller after the last determined target controller according to a preset polling rule;

[0014] Determine status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0015] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0016] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is a non-busy state, the candidate controller is determined as the target controller this time.

[0017] Based on the above scheme, the candidate controller is determined by a preset polling rule, and then the status information of the sub-command cache queue corresponding to any interface module in the command cache queue of the candidate controller is determined. Finally, the target controller is determined based on whether the status information is busy or non-busy, thereby selecting a non-busy controller as the target controller from the candidate controllers, which can improve the efficiency of table entry reading.

[0018] In a possible implementation, determining the status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller specifically includes:

[0019] Obtaining a first number of read commands stored in a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0020] determining whether the first number is less than a first set threshold;

[0021] If it is determined that the first number is less than the first set threshold, determining that the state information of the sub-command cache queue corresponding to the arbitrary interface module is in a non-busy state;

[0022] If it is determined that the first number is not less than the first set threshold, it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state.

[0023] Based on the above scheme, the number of read commands stored in the sub-command cache queue corresponding to any interface module in the command cache queue of the candidate controller is compared with the first set threshold, and the status information of the sub-command cache queue is determined to be a non-busy state or a busy state according to the comparison result. Since the first set threshold is preset, the status information of the sub-command cache queue can be flexibly set.

[0024] In a possible implementation, before determining the candidate controller as the current target controller, the method further includes:

[0025] Determining state information of the candidate controller;

[0026] If it is determined that the state information of the candidate controller is abnormal, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the state information of the candidate controller;

[0027] If it is determined that the state information of the candidate controller is normal, the step of determining the candidate controller as the target controller for this time is performed.

[0028] Based on the above scheme, before determining the candidate controller as the target controller for this time, the target controller is determined based on whether the status information of the candidate controller is abnormal or normal, avoiding using an abnormal alternative controller as the target controller, thereby making the determined target controller more accurate and improving the reliability of table entry reading.

[0029] In a possible implementation, determining the state information of the candidate controller specifically includes:

[0030] Obtain error information sent by the candidate controller resulting from verifying the obtained table entry;

[0031] determining whether a second amount of error information obtained is greater than a second set threshold;

[0032] If it is determined that the second number is greater than the second set threshold, determining that the state information of the candidate controller is abnormal;

[0033] If it is determined that the second number is not greater than the second set threshold, it is determined that the status information of the candidate controller is normal.

[0034] Based on the above scheme, the number of error messages obtained by verifying the obtained table entries sent by the candidate controller is compared with the second set threshold, and the candidate controller is determined to be normal or abnormal based on the comparison result. Since the second set threshold is pre-set, the flexibility of determining the status information of the candidate controller can be improved.

[0035] In one possible implementation, sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules according to the order in which the controller identifiers in the controller identifier cache queues corresponding to the interface modules are added includes:

[0036] Obtain the controller identifier stored first from the controller identifier cache queue corresponding to each interface module;

[0037] The entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in each entry cache queue of each interface module are sent to the corresponding interface module.

[0038] Based on the above solution, the entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in the entry cache queue of the interface module are sent to the corresponding interface module, thereby ensuring the orderly output of the entries and improving the reliability of entry reading.

[0039] In a possible implementation, after adding the entry to the first sub-entry cache queue corresponding to the arbitrary controller in the entry cache queue of the interface module corresponding to the target module identifier, the method further includes:

[0040] Deleting the target module identifier from the module identifier cache queue corresponding to the arbitrary controller;

[0041] After sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules, the method further includes:

[0042] The controller ID stored first is deleted from the controller ID cache queue corresponding to each interface module.

[0043] Based on the above solution, deleting the first stored module identifier and the first stored controller identifier can ensure that the table entries are output in order next time, thereby improving the reliability of the table entry reading.

[0044] In a second aspect, an embodiment of the present invention further provides a table entry reading device, which is applied to a cross-connect module included in a table entry reading device of a network device, wherein the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the table entry reading device includes a command cross-connect unit and a data cross-connect unit;

[0045] The command cross-connect unit is configured to, after receiving a read command sent by any interface module of the at least two interface modules, determine a target controller based on status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule, add the controller identifier of the target controller to the controller identifier cache queue corresponding to the arbitrary interface module, and add the read command to the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the target controller; and, according to a load balancing principle, send the read commands in each sub-command cache queue included in each command cache queue of each controller to the corresponding controller, and add the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the table entry corresponding to the received read command from the corresponding memory;

[0046] The data cross-unit is used to, after receiving the table entry returned by any controller among the at least two controllers, obtain the first stored target module identifier from the module identifier cache queue corresponding to the any controller, and add the received table entry to the sub-table item cache queue corresponding to the any controller in the table item cache queue of the interface module corresponding to the target module identifier; and, according to the order in which each controller identifier is added in the controller identifier cache queue corresponding to each interface module, send the table entries in the sub-table item cache queue corresponding to each controller in each table item cache queue of each interface module to the corresponding interface module.

[0047] In a possible implementation, the command cross-connect unit is specifically configured to:

[0048] Determine the candidate controller after the last determined target controller according to a preset polling rule;

[0049] Determine status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0050] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0051] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is a non-busy state, the candidate controller is determined as the target controller this time.

[0052] In a possible implementation, the command cross-connect unit is specifically configured to:

[0053] Obtaining a first number of read commands stored in a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0054] determining whether the first number is less than a first set threshold;

[0055] If it is determined that the first number is less than the first set threshold, determining that the state information of the sub-command cache queue corresponding to the arbitrary interface module is in a non-busy state;

[0056] If it is determined that the first number is not less than the first set threshold, it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state.

[0057] In a possible implementation, before determining the candidate controller as the current target controller, the command cross-connect unit is further configured to:

[0058] Determining state information of the candidate controller;

[0059] If it is determined that the state information of the candidate controller is abnormal, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the state information of the candidate controller;

[0060] If it is determined that the state information of the candidate controller is normal, the step of determining the candidate controller as the target controller for this time is performed.

[0061] In a possible implementation, the command cross-connect unit is specifically configured to:

[0062] Obtain error information sent by the candidate controller resulting from verifying the obtained table entry;

[0063] determining whether a second amount of error information obtained is greater than a second set threshold;

[0064] If it is determined that the second number is greater than the second set threshold, determining that the state information of the candidate controller is abnormal;

[0065] If it is determined that the second number is not greater than the second set threshold, it is determined that the status information of the candidate controller is normal.

[0066] In a possible implementation, the data cross-link unit is specifically configured to:

[0067] Obtain the controller identifier stored first from the controller identifier cache queue corresponding to each interface module;

[0068] The entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in each entry cache queue of each interface module are sent to the corresponding interface module.

[0069] In a possible implementation, after adding the received entry to the sub-entry cache queue corresponding to the arbitrary controller in the entry cache queue of the interface module corresponding to the target module identifier, the data cross-link unit is further configured to:

[0070] Deleting the target module identifier from the module identifier cache queue corresponding to the arbitrary controller;

[0071] After sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules, the cross-connect module is further configured to:

[0072] The controller ID stored first is deleted from the controller ID cache queue corresponding to each interface module.

[0073] In a third aspect, an embodiment of the present invention further provides a network device, comprising a table entry reading device, wherein the table entry reading device comprises at least two interface modules, at least two controllers, a memory corresponding to each controller, and a table entry reading apparatus as described in any one of the second aspects.

[0074] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, comprising:

[0075] The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer is caused to execute the method according to any one of the first aspects.

[0076] For each of the above-mentioned aspects from the second to the fourth aspects and the technical effects that may be achieved by each of the aspects, please refer to the above-mentioned description of the technical effects that can be achieved by the first aspect or the various possible solutions in the first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0078] Figure 1 This is an architectural diagram of a solution for accessing DDR through table lookup on multiple 100G interfaces in related technologies.

[0079] Figure 2A schematic diagram of an architecture for reading table entries provided by an embodiment of the present invention;

[0080] Figure 3 A flowchart of a method for reading a table entry provided by an embodiment of the present invention;

[0081] Figure 4 A schematic diagram of another architecture for reading table entries provided by an embodiment of the present invention;

[0082] Figure 5 A schematic diagram of the architecture of a DDR cross-connect module provided in an embodiment of the present invention;

[0083] Figure 6 A schematic diagram of another architecture for reading table entries provided by an embodiment of the present invention;

[0084] Figure 7 A schematic diagram of another architecture for reading table entries provided by an embodiment of the present invention;

[0085] Figure 8 A schematic diagram of the format of a table entry provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0086] In order to make the purpose, technical solutions and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0087] In order to improve the reliability of table entry reading and improve the utilization of interface bandwidth, an embodiment of the present invention provides a table entry reading method, which is applied to the cross module 200 included in the table entry reading device of the network device, such as Figure 2 As shown, the table entry reading device further includes at least two interface modules 103, at least two controllers 300 and a memory 400 corresponding to each controller, as shown in FIG. Figure 3 As shown, the method includes:

[0088] S301: After receiving a read command sent by any interface module of at least two interface modules, determine a target controller based on status information of a sub-command cache queue corresponding to any interface module in a command cache queue of each controller and a preset polling rule, add a controller identifier of the target controller to a controller identifier cache queue corresponding to any interface module, and add the read command to a sub-command cache queue corresponding to any interface module in the command cache queue of the target controller;

[0089] S302: Send the read commands in the sub-command cache queues included in the command cache queues of the controllers to the corresponding controllers according to the load balancing principle, and add the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the entry corresponding to the received read command from the corresponding memory;

[0090] S303: After receiving the entry returned by any controller among the at least two controllers, obtain the first stored target module identifier from the module identifier cache queue corresponding to the any controller, and add the received entry to the sub-entry cache queue corresponding to the any controller in the entry cache queue of the interface module corresponding to the target module identifier;

[0091] S304: Send the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules according to the order in which the controller identifiers are added in the controller identifier cache queues corresponding to the interface modules.

[0092] The table entry reading method provided by the embodiment of the present invention can cross-transmit read commands and table entries among the interface module, the controller, and the memory. If a controller fails, other controllers can be used, thereby improving the reliability of table entry reading. In addition, since the interface module, the controller, and the memory are not one-to-one corresponding, the bandwidth of the interface between the interface module and the controller can be shared, thereby improving bandwidth utilization.

[0093] In a specific implementation, the table entry reading device can be a field programmable gate array (FPGA) or other programmable devices; the controller in the embodiment of the present invention can be a DDR controller, the memory can be a DDR SDRAM, the cross module can be a DDR cross module, and the cache queue can be a first-in first-out queue (First Input First Output, FIFO).

[0094] The following describes an embodiment of the present invention by taking a DDR cross module, a DDR controller, a DDR SDRAM and a cache queue as FIFO as an example, and the number of interface modules and controllers is 6. Figure 4 , which is a schematic diagram of an architecture for reading table entries provided by an embodiment of the present invention.

[0095] based on Figure 4In the architecture diagram of table entry reading shown in FIG, after the DDR cross module 402 receives a read command sent by any interface module 103 among the six interface modules 103, it determines the target DDR controller according to the status information of the sub-command cache queue corresponding to any interface 401 in the command cache queue of each DDR controller 104 and the preset polling rule, adds the controller identifier of the target DDR controller 104 to the controller identifier cache queue corresponding to any interface module 103, and adds the read command to the sub-cache queue corresponding to any interface module 103 in the command cache queue of the target DDR controller 104; and sends the read commands in the sub-command cache queues included in each command cache queue of each DDR controller 104 to the corresponding DDR controller 104 according to the load balancing principle, and adds the module identifier of the interface module 103 corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the DDR controller 104 corresponding to the sent read command, so that each DDR controller receives the read command from the corresponding DDR controller 104. Obtain the table entry corresponding to the received read command from SDRAM105; and after receiving the table entry returned by any DDR controller 104 among the 6 DDR controllers 104, obtain the first stored target module identifier from the module identifier cache queue corresponding to any DDR controller 104, and add the received table entry to the sub-table item cache queue corresponding to any DDR controller 104 in the table item cache queue of the interface module corresponding to the target module identifier; and according to the order in which each controller identifier is added in the controller identifier cache queue corresponding to each interface module 103, send the table entries in the sub-table item cache queue corresponding to each DDR controller 104 in each table item cache queue of each interface module 103 to the corresponding interface module 103.

[0096] like Figure 5 FIG. 1 is a schematic diagram of the architecture of a DDR cross-connect module provided by an embodiment of the present invention, Figure 5 It can be seen that in a specific implementation, the DDR cross module 402 may include a DDR command cross unit 4021 and a DDR data cross unit 4022. In order to ensure that the read command and the returned table entries can be output in the correct sequence, two types of FIFOs for storing identifiers are required, where FIFO1_n' is a controller identifier cache queue, which corresponds one-to-one to the interface module 103 and is used to store the controller identifier; FIFO2_n' is a module identifier cache queue, which corresponds one-to-one to the DDR controller and is used to store the module identifier of the interface module 103, where n'=0~5.

[0097] In an embodiment of the present invention, each interface module corresponds to a module identifier, for example, the module identifier corresponding to interface module 0 is 0, the module identifier corresponding to interface module 1 is 1, etc., and each DDR controller corresponds to a controller identifier, for example, the controller identifier corresponding to DDR controller 0 is 0, the controller identifier corresponding to DDR controller 1 is 1, the controller identifier corresponding to DDR controller 2 is 2, etc.

[0098] like Figure 6 and Figure 7 As shown, in addition to FIFO1 and FIFO2, the embodiment of the present invention also includes FIFO3 and FIFO4.

[0099] Among them, FIFO3 is the command cache queue, and each DDR controller corresponds to a command cache queue FIFO3. For example, the command cache queue corresponding to DDR controller 0 is FIFO30, and the command cache queue corresponding to DDR controller 1 is FIFO31... For each command cache queue, it includes a sub-command cache queue corresponding to the interface module. For example, the command cache queue FIFO30 corresponding to DDR controller 0 includes a sub-command cache queue FIFO30_0 corresponding to interface module 0, a sub-command cache queue FIFO30_1 corresponding to interface module 1, a sub-command cache queue FIFO30_2 corresponding to interface module 2, a sub-command cache queue FIFO30_3 corresponding to interface module 3, a sub-command cache queue FIFO30_4 corresponding to interface module 4, and a sub-command cache queue FIFO30_5 corresponding to interface module 5.

[0100] FIFO4 is an entry cache queue. Each interface module corresponds to an entry cache queue FIFO4. For example, the entry cache queue corresponding to interface module 0 is FIFO40, the entry cache queue corresponding to interface module 1 is FIFO41, and so on. For each entry cache queue, it includes a sub-entry cache queue corresponding to the DDR controller. For example, the entry cache queue FIFO40 corresponding to interface module 0 includes a sub-entry cache queue FIFO40_0 corresponding to DDR controller 0, a sub-entry cache queue FIFO40_1 corresponding to DDR controller 1, a sub-entry cache queue FIFO40_2 corresponding to DDR controller 2, a sub-entry cache queue FIFO40_3 corresponding to DDR controller 3, a sub-entry cache queue FIFO40_4 corresponding to DDR controller 4, and a sub-entry cache queue FIFO40_5 corresponding to DDR controller 5.

[0101] The following combination Figure 6 and Figure 7 , the table entry reading method provided by the embodiment of the present invention is described in detail.

[0102] The DDR command cross unit 4021 receives a read command sent by any interface module 103. The DDR command cross unit 4021 determines the target DDR controller based on the status information of the sub-command cache queue corresponding to any interface module in the command cache queue FIFO3 of each DDR controller 104 and the preset polling rules, adds the controller identifier of the target DDR controller to the controller identifier cache queue FIFO1 corresponding to the arbitrary interface module 103, and adds the read command to the sub-command cache queue corresponding to the arbitrary interface module 103 in the command cache queue FIFO3 of the target DDR controller.

[0103] For example, refer to Figure 6 Interface module 0 sends a read command. After receiving the read command, DDR command cross-connect unit 4021 determines that the target DDR controller is DDR controller 1 based on the status information of sub-command cache queues FIFO30_0, FIFO31_0, FIFO32_0, FIFO33_0, FIFO34_0, and FIFO35_0 and the preset polling rule, adds controller identifier 1 of DDR controller 1 to FIFO1_0, and adds the received read command to FIFO31_0.

[0104] In a specific implementation, the target DDR controller is determined. The candidate DDR controller after the last determined target DDR controller can be determined according to a preset polling rule, and then the status information of the sub-command cache queue corresponding to any interface module in the command cache queue of the candidate DDR controller is determined. If it is determined that the status information of the sub-command cache queue corresponding to any interface module is busy, the candidate DDR controller is updated to the DDR controller after the candidate DDR controller, and the step of determining the status information of the sub-command cache queue corresponding to any interface module in the command cache queue of the candidate DDR controller is executed; if it is determined that the status information of the sub-command cache queue corresponding to any interface is not busy, the candidate DDR controller is determined as the target DDR controller this time.

[0105] For example, the preset polling rule is to poll one by one according to the controller ID of the DDR controller, combined with Figure 6 If the target DDR controller determined last time is DDR controller 0, DDR controller 1 is selected as a candidate DDR controller. If the read command is sent by interface module 0, the status information of sub-command buffer queue FIFO31_0 is determined. If the status information of FIFO31_0 is not busy, DDR controller 1 is selected as the target DDR controller. If the status information of FIFO31_0 is busy, DDR controller 2 is selected as a candidate DDR controller. The above steps are repeated until the target DDR controller is determined.

[0106] Specifically, when determining the status information of the sub-command cache queue, the first number of read commands stored in the sub-command cache queue corresponding to any interface in the command cache queue of the candidate DDR controller can be obtained to determine whether the first number is less than a first set threshold. If it is less than, the status information of the sub-command cache queue corresponding to any interface module is determined to be a non-busy state; if it is not less than, it is determined to be a busy state.

[0107] For example, combined Figure 6 If the interface module sending the read command is interface module 0, the candidate DDR controller is DDR controller 1, and the first set threshold is 5, the number of read commands obtained in FIFO31_0 is 6, which is greater than the first set threshold, and FIFO31_0 is determined to be busy.

[0108] In one embodiment, to determine the target DDR controller, in addition to considering the status information of the sub-command cache queue corresponding to the interface module that sends the read command in the command cache queue of the DDR controller, it is also necessary to determine the status information of the DDR controller itself, that is, abnormal or normal. Only when the status information of the DDR controller is normal can the DDR controller be used as the target DDR controller.

[0109] Specifically, in the process of configuring the table entry, the CRC is calculated according to the content of the table entry, recorded as CRC_WR, and the CRC_WR is placed in the high-order unused bits of the table entry, such as Figure 8 FIG. 4 shows the format of the table entries written into the DDR SDRAM.

[0110] When returning a table entry, the DDR controller obtains the table entry and uses the same algorithm as that used to calculate CRC_WR to calculate the table content in the table entry to obtain CRC_RD. The DDR controller obtains CRC_WR from the table entry and compares CRC_WR with CRC_RD. If they are the same, it is determined that the table entry returned this time is correct. Otherwise, it is determined that the returned table entry is incorrect. If it is determined that the returned table entry is incorrect, a count is performed and the count value can be sent to the DDR cross-connect module.

[0111] The DDR cross-connect module monitors the received count value, and if the count value is greater than a second set threshold, determines that the state information of the DDR controller is abnormal; if the count value is not greater than the second set threshold, determines that the state information of the DDR controller is normal.

[0112] In a specific implementation, if the status information of the candidate DDR controller is normal, and the status information of the sub-command cache queue corresponding to the interface module that sends the read command in the command cache queue is in a non-busy state, the candidate DDR controller is used as the target DDR controller; if the status information of the candidate DDR controller is abnormal, and the status information of the sub-command cache queue corresponding to the interface module that sends the read command in the command cache queue is in a non-busy state, the candidate DDR controller is updated to the DDR controller after the candidate DDR controller, and the step of determining the status information of the sub-command cache queue corresponding to the interface module that sends the read command in the command cache queue of the candidate DDR controller is executed.

[0113] For example, combined Figure 6 The candidate DDR controller is DDR controller 1, and the sub-command cache queue corresponding to the interface module sending the read command in the command cache queue is FIFO31_0. If the DDR command cross-connect unit 4021 determines that the status information of DDR controller 1 is abnormal and the status information of FIFO31_0 is non-busy, DDR controller 2 is selected as the candidate DDR controller. Then, the status information of DDR controller 2 and the status information of FIFO32_0 are determined. If the status information of DDR controller 2 is normal and the status information of FIFO32_0 is non-busy, DDR controller 2 is selected as the target DDR controller.

[0114] The DDR command cross-connect unit 4021 determines the target DDR controller, adds the controller identifier of the target DDR controller to the controller identifier cache queue FIFO1 corresponding to the interface module that sends the read command, and adds the read command to the sub-command cache queue corresponding to the interface module that sends the read command in the command cache queue FIFO3 of the target DDR controller. Then, according to the load balancing principle, the read commands in the sub-command cache queues included in the command cache queue FIFO3 corresponding to each DDR controller are sent to the corresponding DDR controller, and the module identifier of the interface module corresponding to the sub-command cache queue where the read command is located is added to the module identifier cache queue FIFO2 of the controller corresponding to the sent read command, so that each DDR controller obtains the table entry corresponding to the received read command from the corresponding DDR SDRAM.

[0115] Combine Figure 6 For example, if the subcommand cache queue FIFO30_4 stores the most read commands, the first read command stored in the subcommand cache queue FIFO30_4 is output to the DDR controller 0, and the module identifier 4 is stored in FIFO2_0. The DDR controller 0 obtains the table entry from the DDR SDRAM0.

[0116] The above is the process of sending a read command, obtaining a table entry, a storage controller identifier, and a storage module identifier. The following describes how to send the table entry to the interface module.

[0117] like Figure 7 As shown, after the DDR data cross-link unit 4022 in the DDR cross-link module receives the table entry sent by any DDR controller, it obtains the first stored target module identifier from the module identifier cache queue FIFO2 corresponding to the DDR controller, and then adds the table entry to the sub-table entry cache queue corresponding to the DDR controller in the table entry cache queue FIFO4 of the interface module corresponding to the target module identifier.

[0118] For example, combined Figure 7 After receiving the entry sent by the DDR controller 0, the DDR data cross-link unit 4022 obtains the first stored module identifier from FIFO2_0 as module identifier 1, and then adds the entry to FIFO40_1.

[0119] After the received table entries are added to the corresponding sub-table entry cache queues through the DDR data cross-link unit 4022, the table entries in the sub-table entry cache queues corresponding to the respective DDR controllers in the table entry storage queues FIFO4 of the respective interface modules are sent to the corresponding interface modules according to the order in which the respective DDR controller identifiers in the controller identifier cache queue FIFO1 corresponding to the respective interface modules are added.

[0120] Specifically, the DDR data cross-connect unit 4022 obtains the first stored controller identifier from the controller identifier cache queue corresponding to each interface module, and then sends the table entries stored in the sub-table entry cache queue corresponding to the first stored controller identifier in each table entry cache queue FIFO4 of each interface module to the corresponding interface module.

[0121] For example, combined Figure 7 The DDR data cross-link unit 4022 obtains the first controller identifier stored in FIFO1_0 as controller identifier 1, and then outputs the first entry stored in FIFO40_1 to interface module 0.

[0122] In one embodiment, after adding a table entry to the sub-table entry cache queue corresponding to any DDR in the table entry cache queue of the interface module corresponding to the target module identifier, the target module identifier is deleted from the module identifier cache queue corresponding to any DDR controller, and after sending the table entries in the sub-table entry cache queue corresponding to each DDR controller in each table entry cache queue of each interface module to the corresponding interface module, the controller identifier stored first is deleted from the controller identifier cache queue corresponding to each interface module.

[0123] For example, combined Figure 7 The DDR data cross-link unit 4022 obtains the first stored interface module identifier from FIFO2_0 as module identifier 1, adds the table entry to FIFO41_0, and then deletes the module identifier 1 from FIFO2_0; the DDR data cross-link unit 4022 obtains the first stored controller identifier from FIFO1_1 as controller identifier 0, outputs the first stored table entry in FIFO41_0 to interface module 1, and then deletes the controller identifier 0 from FIFO1_1.

[0124] The above embodiment can ensure that the next entry can be output in order, thereby improving the accuracy of entry reading.

[0125] In the table entry reading method provided in an embodiment of the present invention, a DDR cross module is used to select a DDR controller from at least two DDR controllers as a target DDR controller. Compared with the one-to-one correspondence between interface modules and DDR controllers in the prior art, this method is more flexible, can improve the reliability of table entry reading, and can dynamically balance the bandwidth shared between various DDR interfaces.

[0126] Based on the same inventive concept, an embodiment of the present invention further provides a table entry reading device, which is applied to a table entry reading device of a network device, wherein the table entry reading device includes a cross module, at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the table entry reading device includes a command cross unit and a data cross unit;

[0127] The command cross-connect unit is configured to, after receiving a read command sent by any interface module of the at least two interface modules, determine a target controller based on status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule, add the controller identifier of the target controller to the controller identifier cache queue corresponding to the arbitrary interface module, and add the read command to the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the target controller; and, according to a load balancing principle, send the read commands in each sub-command cache queue included in each command cache queue of each controller to the corresponding controller, and add the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the table entry corresponding to the received read command from the corresponding memory;

[0128] The data cross-unit is used to, after receiving the table entry returned by any controller among the at least two controllers, obtain the first stored target module identifier from the module identifier cache queue corresponding to the any controller, and add the received table entry to the sub-table item cache queue corresponding to the any controller in the table item cache queue of the interface module corresponding to the target module identifier; and, according to the order in which each controller identifier is added in the controller identifier cache queue corresponding to each interface module, send the table entries in the sub-table item cache queue corresponding to each controller in each table item cache queue of each interface module to the corresponding interface module.

[0129] Optionally, the command cross-connect unit is specifically configured to:

[0130] Determine the candidate controller after the last determined target controller according to a preset polling rule;

[0131] Determine status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0132] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0133] If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is a non-busy state, the candidate controller is determined as the target controller this time.

[0134] Optionally, the command cross-connect unit is specifically configured to:

[0135] Obtaining a first number of read commands stored in a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller;

[0136] determining whether the first number is less than a first set threshold;

[0137] If it is determined that the first number is less than the first set threshold, determining that the state information of the sub-command cache queue corresponding to the arbitrary interface module is in a non-busy state;

[0138] If it is determined that the first number is not less than the first set threshold, it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state.

[0139] Optionally, before determining the candidate controller as the current target controller, the command cross-connect unit is further configured to:

[0140] Determining state information of the candidate controller;

[0141] If it is determined that the state information of the candidate controller is abnormal, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the state information of the candidate controller;

[0142] If it is determined that the state information of the candidate controller is normal, the step of determining the candidate controller as the target controller for this time is performed.

[0143] Optionally, the command cross-connect unit is specifically configured to:

[0144] Obtain error information sent by the candidate controller resulting from verifying the obtained table entry;

[0145] determining whether a second amount of error information obtained is greater than a second set threshold;

[0146] If it is determined that the second number is greater than the second set threshold, determining that the state information of the candidate controller is abnormal;

[0147] If it is determined that the second number is not greater than the second set threshold, it is determined that the status information of the candidate controller is normal.

[0148] Optionally, the data cross-connect unit is specifically configured to:

[0149] Obtain the controller identifier stored first from the controller identifier cache queue corresponding to each interface module;

[0150] The entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in each entry cache queue of each interface module are sent to the corresponding interface module.

[0151] Optionally, after adding the received entry to the entry cache queue of the interface module corresponding to the target module identifier and the sub-entry cache queue corresponding to the arbitrary controller, the data cross-link unit is further configured to:

[0152] Deleting the target module identifier from the module identifier cache queue corresponding to the arbitrary controller;

[0153] After sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules, the cross-connect module is further configured to:

[0154] The controller ID stored first is deleted from the controller ID cache queue corresponding to each interface module.

[0155] Based on the same inventive concept, an embodiment of the present invention further provides a network device, including a table entry reading device, wherein the table entry reading device includes at least two interface modules, at least two controllers, a memory corresponding to each controller, and any one of the above-mentioned table entry reading devices.

[0156] Furthermore, an embodiment of the present application also provides a computer-readable storage medium having computer instructions stored thereon. When the computer instructions are executed on a computer, the computer is caused to execute the steps of any of the above methods.

[0157] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0158] Although the specific embodiments of the present application have been described above, it should be understood by those skilled in the art that these are merely examples, and the scope of protection of the present application is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present application, but these changes and modifications all fall within the scope of protection of the present application. Although the preferred embodiments of the present application have been described, once those skilled in the art become aware of the basic creative concepts, additional changes and modifications may be made to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0159] Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include these modifications and variations.

Claims

1. A table entry reading method, characterized in that: In a cross-connect module included in a table entry reading device for a network device, the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller, the method comprising: After receiving a read command sent by any interface module of the at least two interface modules, determining a target controller according to status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule, adding a controller identifier of the target controller to a controller identifier cache queue corresponding to the arbitrary interface module, and adding the read command to a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the target controller; and sending, according to a load balancing principle, read commands in each sub-command cache queue included in each command cache queue of each controller to the corresponding controller, and adding the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the table entry corresponding to the received read command from the corresponding memory; and After receiving the table entry returned by any controller among the at least two controllers, obtaining the first stored target module identifier from the module identifier cache queue corresponding to the arbitrary controller, and adding the received table entry to the sub-table entry cache queue corresponding to the arbitrary controller in the table entry cache queue of the interface module corresponding to the target module identifier; and According to the order in which the controller identifiers are added in the controller identifier cache queue corresponding to each interface module, entries in the sub-entry cache queue corresponding to each controller in each entry cache queue of each interface module are sent to the corresponding interface module.

2. The method according to claim 1, wherein The determining the target controller according to the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule includes: Determine the candidate controller after the last determined target controller according to a preset polling rule; Determine status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is a non-busy state, the candidate controller is determined as the target controller this time.

3. The method according to claim 2, wherein Determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller specifically includes: Obtaining a first number of read commands stored in a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; determining whether the first number is less than a first set threshold; If it is determined that the first number is less than the first set threshold, determining that the state information of the sub-command cache queue corresponding to the arbitrary interface module is in a non-busy state; If it is determined that the first number is not less than the first set threshold, it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state.

4. The method according to claim 2, wherein Before determining the candidate controller as the target controller for this time, the method further includes: Determining state information of the candidate controller; If it is determined that the state information of the candidate controller is abnormal, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the state information of the candidate controller; If it is determined that the state information of the candidate controller is normal, the step of determining the candidate controller as the target controller for this time is performed.

5. The method according to claim 4, wherein The determining of the state information of the candidate controller specifically includes: Obtain error information sent by the candidate controller resulting from verifying the obtained table entry; determining whether a second amount of error information obtained is greater than a second set threshold; If it is determined that the second number is greater than the second set threshold, determining that the state information of the candidate controller is abnormal; If it is determined that the second number is not greater than the second set threshold, it is determined that the status information of the candidate controller is normal.

6. The method according to claim 1, wherein The step of sending entries in sub-entry cache queues corresponding to respective controllers in respective entry cache queues of respective interface modules to the corresponding interface modules according to the order in which respective controller identifiers are added in the controller identifier cache queues corresponding to the respective interface modules comprises: Obtain the controller identifier stored first from the controller identifier cache queue corresponding to each interface module; The entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in each entry cache queue of each interface module are sent to the corresponding interface module.

7. The method according to any one of claims 1 to 6, wherein: After adding the received entry to the entry cache queue of the interface module corresponding to the target module identifier and the sub-entry cache queue corresponding to the arbitrary controller, the method further includes: Deleting the target module identifier from the module identifier cache queue corresponding to the arbitrary controller; After sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules, the method further includes: The controller ID stored first is deleted from the controller ID cache queue corresponding to each interface module.

8. A table entry reading device, characterized in that: A table entry reading device applied to a network device includes a cross module, the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the table entry reading device includes a command cross unit and a data cross unit; The command cross-connect unit is configured to, after receiving a read command sent by any interface module of the at least two interface modules, determine a target controller based on status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of each controller and a preset polling rule, add the controller identifier of the target controller to the controller identifier cache queue corresponding to the arbitrary interface module, and add the read command to the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the target controller; and, according to a load balancing principle, send the read commands in each sub-command cache queue included in each command cache queue of each controller to the corresponding controller, and add the module identifier of the interface module corresponding to the sub-command cache queue where the sent read command is located to the module identifier cache queue of the controller corresponding to the sent read command, so that each controller obtains the table entry corresponding to the received read command from the corresponding memory; The data cross-unit is used to, after receiving the table entry returned by any controller among the at least two controllers, obtain the first stored target module identifier from the module identifier cache queue corresponding to the any controller, and add the received table entry to the sub-table item cache queue corresponding to the any controller in the table item cache queue of the interface module corresponding to the target module identifier; and, according to the order in which each controller identifier is added in the controller identifier cache queue corresponding to each interface module, send the table entries in the sub-table item cache queue corresponding to each controller in each table item cache queue of each interface module to the corresponding interface module.

9. The device according to claim 8, wherein The command cross unit is specifically used for: Determine the candidate controller after the last determined target controller according to a preset polling rule; Determine status information of a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the status information of the sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; If it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is a non-busy state, the candidate controller is determined as the target controller this time.

10. The device according to claim 9, wherein The command cross unit is specifically used for: Obtaining a first number of read commands stored in a sub-command cache queue corresponding to the arbitrary interface module in the command cache queue of the candidate controller; determining whether the first number is less than a first set threshold; If it is determined that the first number is less than the first set threshold, determining that the state information of the sub-command cache queue corresponding to the arbitrary interface module is in a non-busy state; If it is determined that the first number is not less than the first set threshold, it is determined that the status information of the sub-command cache queue corresponding to the arbitrary interface module is in a busy state.

11. The device according to claim 9, wherein Before determining the candidate controller as the current target controller, the command cross-connect unit is further configured to: Determining state information of the candidate controller; If it is determined that the state information of the candidate controller is abnormal, updating the candidate controller to a controller subsequent to the candidate controller, and executing the step of determining the state information of the candidate controller; If it is determined that the state information of the candidate controller is normal, the step of determining the candidate controller as the target controller for this time is performed.

12. The device according to claim 11, wherein The command cross unit is specifically used for: Obtain error information sent by the candidate controller resulting from verifying the obtained table entry; determining whether a second amount of error information obtained is greater than a second set threshold; If it is determined that the second number is greater than the second set threshold, determining that the state information of the candidate controller is abnormal; If it is determined that the second number is not greater than the second set threshold, it is determined that the status information of the candidate controller is normal.

13. The device according to claim 8, wherein The data cross-link unit is specifically used for: Obtain the controller identifier stored first from the controller identifier cache queue corresponding to each interface module; The entries stored in the sub-entry cache queue corresponding to the controller identifier stored first in each entry cache queue of each interface module are sent to the corresponding interface module.

14. The device according to any one of claims 8 to 13, characterized in that: After adding the received entry to the entry cache queue of the interface module corresponding to the target module identifier and the sub-entry cache queue corresponding to the arbitrary controller, the data cross-link unit is further configured to: Deleting the target module identifier from the module identifier cache queue corresponding to the arbitrary controller; After sending the entries in the sub-entry cache queues corresponding to the controllers in the entry cache queues of the interface modules to the corresponding interface modules, the cross-connect module is further configured to: The controller ID stored first is deleted from the controller ID cache queue corresponding to each interface module.

15. A network device, characterized in that: The device comprises a table entry reading device, wherein the table entry reading device comprises at least two interface modules, at least two controllers, a memory corresponding to each controller, and the table entry reading apparatus according to any one of claims 8 to 14.

16. A computer-readable storage medium, characterized in that include: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 7.

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