A layout design method and related device

Abstract

The present application provides a layout design method and related devices, which relate to the field of computer graphics. The method includes: obtaining a range to be designed; filling the interior of the range to be designed based on a predefined plurality of basic tiles to obtain at least one internal layout of the range to be designed, the range to be designed under each internal layout includes one or more regions divided based on a plurality of tiles, the plurality of basic tiles include at least one basic tile with a dividing line, each basic tile with a dividing line includes a dividing line intersecting with a tile boundary, and the boundaries of the one or more regions are obtained by connecting the dividing lines of a plurality of tiles filled in the range to be designed; based on at least one internal layout of the range to be designed and the outer boundary of the range to be designed, a layout diagram of at least one layout of the range to be designed is obtained. Thus, the dependence of the layout design on the constraints can be weakened, and a layout scheme can be provided more flexibly.

Description

Technical Field

[0001] The present application relates to the field of computer graphics, and in particular to a layout design method and related devices. Background Art

[0002] With the improvement of economic level, people's requirements for the quality of living environment are also increasing. Whether it is the design of the interior of their own residence or the design of the community they live in, they have personalized requirements. In order to meet people's needs, it has become very common to automatically generate a large number of layout design drawings through computers to select designs that meet people's needs.

[0003] At present, a method for generating a layout diagram by computer is known as follows: first, manually input constraints, such as the outer boundary of the scope to be designed, the number of rooms inside, the type of each room, the connection method, etc., and then retrieve the layout diagram that matches the input constraints from the database. However, the layout diagrams in the database are limited and may not meet all the constraints, so it may not be possible to obtain a layout diagram that matches the constraints from the database. In some cases, for some scopes to be designed, the user may not be able to give accurate constraints, and thus cannot obtain the corresponding layout diagram from the database. Therefore, the above-mentioned method of automatically generating a layout diagram by computer is greatly limited in application. Summary of the invention

[0004] The present application provides a layout design method and related devices thereof, in order to weaken the dependence of layout design on constraint conditions and provide a more flexible design solution.

[0005] In a first aspect, the present application provides a layout design method, the method comprising: obtaining a range to be designed; filling the interior of the range to be designed based on a predefined plurality of basic tiles to obtain at least one internal layout of the range to be designed, the range to be designed under each internal layout comprising one or more regions divided based on a plurality of tiles, the plurality of tiles being obtained by at least one basic tile of the plurality of basic tiles, the plurality of basic tiles being smaller in size than the range to be designed, the plurality of basic tiles comprising at least one basic tile with a dividing line, each basic tile with a dividing line comprising a dividing line intersecting with a tile boundary, the boundaries of the one or more regions being obtained by connecting the dividing lines of the plurality of tiles filled in the range to be designed; obtaining a layout diagram of at least one layout of the range to be designed based on the at least one internal layout of the range to be designed and the outer boundary of the range to be designed.

[0006] Therefore, the present application fills the design range with a plurality of predefined basic tiles to obtain at least one different internal layout, and then obtains at least one layout of the design range based on the different internal layouts and the outer boundary of the design range. In this way, the design of the layout diagram is no longer strongly dependent on constraints, breaking the conventional layout design concept, and realizing different ways of segmenting the same design range through a plurality of predefined basic tiles, providing a richer layout design, which neither relies on existing layout designs in reality nor requires users to provide accurate constraints, and provides users with more flexible design solutions.

[0007] In combination with the first aspect, in some possible implementations of the first aspect, the multiple tiles include: at least one basic tile among the multiple basic tiles, and / or at least one tile transformed based on at least one basic tile among the multiple basic tiles; the filling of the interior of the range to be designed based on the predefined multiple basic tiles includes: starting from a starting position, based on the multiple tiles, filling the interior of the range to be designed until the range to be designed is completely filled and the dividing lines of adjacent tiles filled in the range to be designed are connected; wherein the starting position is randomly selected or pre-specified.

[0008] In combination with the first aspect, in some possible implementations of the first aspect, the multiple basic tiles have the same size, and in the basic tile with the dividing line, the intersection position of the dividing line and the boundary is the boundary center of the basic tile.

[0009] In combination with the first aspect, in some possible implementations of the first aspect, each basic tile corresponds to a coding value, the number of bits of the coding value is the same as the number of edges of the basic tile, each coding bit in the coding value corresponds to an edge of the basic tile, and is used to indicate whether the corresponding boundary is divided by a dividing line; the coding values ​​corresponding to any two basic tiles are different, and the values ​​of the coding bits corresponding to the overlapping boundaries of adjacent tiles are equal.

[0010] In combination with the first aspect, in some possible implementations of the first aspect, before obtaining a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and the outer boundary of the range to be designed, the method also includes: inputting a picture containing the range to be designed into a pre-trained first neural network, so as to analyze each pixel within the range to be designed through the first neural network to obtain the foreground and background within the range to be designed, and the first neural network is used to determine whether each pixel belongs to the foreground or the background; and obtaining the outer boundary of the range to be designed based on the foreground and background within the range to be designed.

[0011] In combination with the first aspect, in some possible implementations of the first aspect, after obtaining a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed, the method further includes: estimating the semantics of one or more areas within the range to be designed under each layout of at least one layout of the range to be designed; and obtaining at least one design scheme for the range to be designed based on the semantics of each layout of the at least one layout and one or more areas within the range to be designed under each layout.

[0012] In combination with the first aspect, in some possible implementations of the first aspect, obtaining at least one design scheme for the range to be designed based on each of the at least one layout and the semantics of one or more areas within the range to be designed under each layout includes: determining other semantics of one or more areas within the range to be designed under each layout based on predefined correspondence information and the semantics of one or more areas within the range to be designed under each layout estimated by the second neural network; the correspondence information is used to indicate the correspondence between at least one group of areas, each group of areas including two areas with similar functions, and the semantics of the two areas in each group of areas are interchangeable; obtaining multiple design schemes for the range to be designed based on the layout diagram of each of the at least one layout and the multiple semantics of one or more areas within the range to be designed under each layout.

[0013] In combination with the first aspect, in some possible implementations of the first aspect, the semantics of the two areas in each group of areas indicated in the correspondence information are both semantics of indoor scenes; or, the semantics of the two areas in each group of areas indicated in the correspondence information are respectively: the semantics of indoor scenes and the semantics of outdoor scenes.

[0014] In a second aspect, the present application provides a layout design device, comprising: an acquisition module and a processing module, the acquisition module being used to acquire a range to be designed; the processing module being used to fill the interior of the range to be designed based on a predefined plurality of basic tiles to obtain at least one internal layout of the range to be designed, the range to be designed under each internal layout comprising one or more areas divided based on a plurality of tiles, the plurality of tiles being obtained by at least one basic tile of the plurality of basic tiles, the size of the plurality of basic tiles being smaller than the range to be designed, the plurality of basic tiles comprising at least one basic tile with a dividing line, each basic tile with a dividing line comprising a dividing line intersecting with a tile boundary, the boundaries of the one or more areas being obtained by connecting the dividing lines of the plurality of tiles filled in the range to be designed; and being used to obtain a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed.

[0015] In a third aspect, the present application provides a layout design device, comprising a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and execute the computer program so that the device implements the method in the first aspect and any possible implementation manner of the first aspect.

[0016] In a fourth aspect, the present application provides a chip system comprising at least one processor for supporting the implementation of the functions involved in the above-mentioned first aspect and any possible implementation method of the first aspect.

[0017] In one possible design, the chip system also includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the processor.

[0018] The chip system may be composed of a chip, or may include a chip and other discrete devices.

[0019] In a fifth aspect, the present application provides a computer-readable storage medium, in which computer-readable instructions are stored. When the computer-readable instructions are executed by a computer, the computer implements the method in the first aspect and any possible implementation manner of the first aspect.

[0020] In a sixth aspect, the present application provides a computer program product, comprising: a computer program (also referred to as code, or instruction), which, when executed, enables the method in the above-mentioned first aspect and any possible implementation of the first aspect to be executed.

[0021] It should be understood that the second to sixth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 It is a schematic diagram of a scenario of a layout design method provided in an embodiment of the present application;

[0024] Figure 2 is a schematic flow chart of a layout design method provided in an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of an example of multiple basic tiles provided in an embodiment of the present application;

[0026] Figure 4 This is an example diagram of multiple tiles obtained from multiple basic tiles provided in an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of another example of multiple basic tiles provided in an embodiment of the present application;

[0028] Figure 6 is a schematic diagram of a layout diagram obtained using the method provided in an embodiment of the present application;

[0029] Figure 7 is a schematic block diagram of a layout design device provided in an embodiment of the present application;

[0030] Figure 8 It is another schematic block diagram of the layout design device provided in an embodiment of the present application.

[0031] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0032] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0033] The following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0034] Before introducing the embodiments of the present application, a brief explanation of the terms involved in the present application is first given.

[0035] 1. Backtracking: Backtracking is also called trial and error, and is a computer algorithm. Its basic idea is: starting from a certain state of the problem (initial state), search for all "states" that can be reached from this state. When a road reaches the "end" (cannot move forward), take one or several steps back and start from another possible "state", and continue searching until all "paths" (states) have been tried. This method of constantly "moving forward" and "backtracking" to find a solution is called "backtracking".

[0036] 2. RPLAN dataset: It is a large-scale dataset consisting of a large number of floor plans.

[0037] 3. Downsampling: also called downsampling, for a sample value sequence, sampling is performed once every few sample values, so that the new sequence obtained is the downsampling of the original sequence. The main purpose of downsampling is to make the image fit the size of the display area and generate a thumbnail of the corresponding image.

[0038] 4. Upsampling: Upsampling is the reverse process of downsampling, also known as upsampling or image interpolation. Upsampling is based on the number of samples on the side with more data, and generates the same number of samples on the side with less samples as on the side with more samples. The main purpose of upsampling is to enlarge the original image so that it can be displayed on a display device with higher resolution.

[0039] 5. Morphological opening operation: In mathematical morphology, the opening operation is defined as corrosion followed by expansion. That is, the image is corroded first, and then the corrosion result is expanded. Among them, expansion refers to the expansion of the highlight part in the image, the domain is expanded, and the effect image has a larger highlight area than the original image. When operating, it is manifested as the adjacent area is replaced by the maximum value, and the highlight area increases; corrosion refers to the corrosion of the highlight part in the image, the domain is reduced, and the effect image has a smaller highlight area than the original image. When operating, it is manifested as the adjacent area is replaced by the minimum value, and the highlight area decreases. Morphological opening operation can be used for denoising and retaining the original image.

[0040] 6. Morphological closing operation: In mathematical morphology, closing operation is defined as dilation followed by erosion. That is, the image is dilated and then the dilated result is eroded. The effect of morphological closing operation is to merge slightly connected blocks. If there are disconnected objects in the image, this method can be used to repair the connection.

[0041] 7. Douglas–Peucker algorithm: also known as the Larmer-Douglas-Peucker algorithm, iterative adaptive point algorithm, split and merge algorithm. When digitizing, the curve needs to be sampled, that is, a finite number of points are taken on the curve to turn it into a broken line, and the original shape can be maintained to a certain extent.

[0042] Figure 1 Schematic diagram of an application scenario applicable to the layout design method provided in the embodiment of the present application. Figure 1 As shown, the scenario shows a computer device 110. The computer device 110 can obtain a layout diagram based on relevant data of the range to be designed.

[0043] It should be understood that the computer device 110 may be a server, or a server cluster, or may be a device specially developed for designing a layout, and the present application does not impose any limitation on this.

[0044] It should also be understood that Figure 1 The scenario shown is only an example and should not be construed as limiting the scenarios to which the method provided in this application is applicable.

[0045] With the improvement of economic level, people's requirements for the quality of living environment are also increasing. Whether it is the design of the interior of their own residence or the design of the community they live in, they have personalized requirements. In order to meet people's needs, it has become very common to automatically generate a large number of layout design drawings through computers to select designs that meet people's needs.

[0046] The present application provides a layout design method. The present application fills the design range with a plurality of predefined basic tiles to obtain at least one different internal layout, and then obtains at least one layout of the design range based on the different internal layouts and the outer boundary of the design range. In this way, the design of the layout diagram is no longer strongly dependent on constraints, breaking the conventional layout design concept, and realizing different ways of segmenting the same design range through a plurality of predefined basic tiles, providing a richer layout design, which neither relies on existing layout designs in reality nor requires users to provide accurate constraints, and provides users with design solutions more flexibly.

[0047] The layout design method provided by the embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. The layout design method can be performed by a layout design device. The layout design device can include, for example, but is not limited to, Figure 1 A computer device in a computer device, or a component configured in a computer device (e.g., a chip, a chip system, etc.).

[0048] Figure 22 is a schematic flow chart of a layout design method 200 provided in an embodiment of the present application. Figure 2 Detailed description of each step in.

[0049] S210, obtaining a range to be designed.

[0050] The range to be designed is the range that requires layout design.

[0051] As a possible embodiment, the user can input a picture containing the range to be designed into the layout design device, and the layout design device can determine the range to be designed based on the received picture, for example, directly use the range shown in the picture as the range to be designed, or, according to a predetermined size of the range to be designed, determine a range of corresponding size in the picture as the range to be designed.

[0052] The size of the range to be designed can be determined by the user, for example, the user inputs the size of the range to be designed in advance; or, it can be determined by the layout design device itself, for example, the layout design device randomly generates the size of the range to be designed; or, it can be determined by the layout design device based on the value range of the size of the range to be designed input in advance by the user.

[0053] It should be understood that the present application does not limit the determination of the size of the range to be designed and the method of obtaining the range to be designed.

[0054] S220 . Fill the interior of the scope to be designed based on a plurality of predefined basic tiles to obtain at least one internal layout of the scope to be designed.

[0055] A tile can be understood as the smallest unit for dividing the design range. The tile in the embodiment of the present application is a small wireframe block area that meets the layout division characteristics and is generated based on the wave function collapse algorithm. Among them, the wave function collapse algorithm is based on the connection rules of the block small areas, and is combined in a specific range to obtain a pattern that meets the rules and has the same characteristics. Since different scene layouts such as urban layouts, indoor layouts, etc. can be composed of different wireframe block small areas, it is possible to fill the interior of the design range based on tiles to obtain at least one internal layout. The layout obtained based on tile filling can also be called a layout obtained based on the wave function collapse algorithm.

[0056] It is understandable that the size of the basic tile can be less than or equal to the range to be designed. Therefore, there can be one or more tiles used to divide a range to be designed. Generally, the tile can be of a smaller size so that the range to be designed can be filled with multiple tiles. The multiple tiles may be tiles of the same type or tiles of different types. Thus, multiple different layouts for the same range to be designed can be obtained.

[0057] In order to distinguish different tile types, this document defines basic tiles. One basic tile can correspond to one type. A basic tile can be flipped (for example, flipping the basic tile horizontally or vertically), rotated (for example, rotating the basic tile 90°, 180°, or 270°, etc.) and other operations to obtain multiple different tiles. The multiple different tiles are obtained from the same basic tile and therefore correspond to the same basic tile.

[0058] In other words, the plurality of tiles used to fill the range to be designed include: at least one basic tile among multiple basic tiles, and / or at least one tile transformed based on at least one basic tile among multiple basic tiles.

[0059] In the embodiment of the present application, the multiple basic tiles may include at least one basic tile with a dividing line. Optionally, the multiple basic tiles also include a basic tile without a dividing line.

[0060] In basic tiles with dividing lines, the dividing lines of any two basic tiles correspond to the intersection positions of the boundaries, so as to ensure that when any two basic tiles are used, or when multiple tiles transformed from any two basic tiles are used to fill the design range, the dividing lines of adjacent tiles can be connected; and, in the same basic tiles with dividing lines, the dividing lines of any two basic tiles correspond to the intersection positions of multiple boundaries, so as to ensure that when the same basic tiles are used, or when multiple tiles transformed from the same basic tiles are used to fill the design range, the dividing lines of adjacent tiles can be connected.

[0061] Figure 3 An example of various basic tiles is shown.

[0062] like Figure 3 As shown, Figure 3 a) to e) in FIG. 5 show five basic tiles of the same size, wherein: Figure 3 The basic tile shown in a) in FIG. 1 has no dividing line; Figure 3 The basic tile shown in c) has a dividing line. Figure 3 The basic tiles shown in b), d) and e) in FIG. 1 and 2 all have two mutually perpendicular and intersecting dividing lines.

[0063] The dividing lines in the above figure are perpendicular to the boundary where the basic tile intersects, and the intersection point where the dividing line intersects the boundary of the basic tile is the midpoint of the boundary of the basic tile. Figure 3 b) is divided into two parts of different sizes by the dividing line. Figure 3 c) is evenly divided into two parts of equal size by the dividing line. Figure 3 d) is divided into three parts by the dividing line. Figure 3e) is evenly divided into four parts of the same size. It should be understood that the size of the basic tile can be set according to actual needs. At the same time, among multiple basic tiles, the line width of each basic tile is consistent. For example, the size of the above basic tile can be set to 70×70 pixels and the line width can be set to 2 pixels.

[0064] based on Figure 3 The various basic tiles shown can be used to obtain multiple tiles. Figure 4 Shown by Figure 3 Examples of multiple tiles derived from various base tiles are shown.

[0065] It should be understood that the basic tiles are not limited to Figure 3 As shown, for example Figure 5 Another example of multiple basic tiles is shown. Figure 5 The various basic tiles shown can also produce more different tiles, which will not be described in detail with reference to the figures for the sake of brevity.

[0066] By filling the area to be designed with multiple tiles obtained from multiple basic tiles, the area to be designed can be completely covered. Since the area to be designed is filled based on one or more basic tiles with dividing lines, the internal layout obtained divides the same area to be designed into one or more areas. The boundaries between these areas can be obtained by connecting the dividing lines of each tile. In other words, the dividing lines in the basic tiles play the role of boundaries.

[0067] It should be understood that the boundary is only for the convenience of distinguishing different areas, and does not mean that the boundary must be shown as a line in the layout diagram.

[0068] Optionally, based on the above-mentioned predefined multiple basic tiles, the interior of the range to be designed is filled, including: starting from the starting position, based on multiple tiles, the interior of the range to be designed is filled until the range to be designed is completely filled, and the dividing lines of adjacent tiles filled in the range to be designed are connected. The starting position can be randomly selected or pre-specified. In other words, the first tile placed at the starting position can also be randomly selected or pre-specified.

[0069] In one example, in a picture containing a range to be designed, based on a starting position, the first tile is placed on the picture from the starting position, and illustratively, the upper left corner of the picture is used as the starting position. Use multiple tiles to fill the inside of the picture. If when placing a certain tile, no matter how the tile is flipped or rotated, it cannot be connected to the dividing line of other tiles around it, then it is necessary to trace back to the previous tile before filling in the tile and re-place it until the picture is completely covered by multiple tiles. If the number of backtracking exceeds the preset number or traces back to the starting position, it means that the layout design has failed, and the starting position needs to be reselected. It should be understood that the preset number can be set according to actual needs, for example, it can be 1000 times. As mentioned above, when using tiles to fill the inside of the range to be designed, the dividing lines between any two adjacent tiles are connected among the multiple tiles filled therein, so that the boundary of the area can be obtained.

[0070] In a possible implementation, each basic tile can be encoded into a coded value, and the number of bits of the coded value is the same as the number of sides of the basic tile. Exemplarily, if the number of sides of the basic tile is 4, the number of bits of the coded value is also 4. Each coded bit in the coded value corresponds to an edge of the basic tile, and is used to indicate the situation in which the edge corresponding to each coded bit in the basic tile is divided. For example, it indicates whether it is divided by a dividing line, or it can also indicate the position of the division. It should be understood that the dividing line divides any two basic tiles differently, and the coded values ​​corresponding to any two basic tiles are also different.

[0071] For example, if the intersection of the dividing line and the edge of the tile is the midpoint, the coding bits with different values ​​can be used to indicate whether each edge of the tile is divided. For example, when the value of a certain coding bit is 0, it means that the edge corresponding to the coding bit in the basic tile is not divided by the dividing line; when the coding bit is 1, it means that the edge corresponding to the coding bit in the basic tile is divided by the dividing line.

[0072] As an example, Figure 3 Each of the five basic tiles shown is encoded as a code value, and the following code values ​​can be obtained: Figure 3 The encoding value corresponding to the basic tile shown in a) is (0, 0, 0, 0). Figure 3 The encoding value corresponding to the basic tile shown in b) is (1, 0, 0, 1). Figure 3 The encoding value corresponding to the basic tile shown in c) is (1, 0, 1, 0). Figure 3 The encoding value corresponding to the basic tile shown in d) is (1, 1, 0, 1). Figure 3 The encoding value corresponding to the basic tile shown in e) in FIG. Figure 3Taking b) in the figure as an example, the edge corresponding to the coded bit with value 1 is divided by the dividing line.

[0073] It should also be understood that the values ​​of the coding bits and the meanings they express in the above examples are only examples and should not constitute any limitation to this application. For example, it can also be defined that when the value of the coding bit is 0, the edge corresponding to the coding bit in the basic tile is divided by the dividing line, and when the value of the coding bit is 1, the edge corresponding to the coding bit in the basic tile is not divided by the dividing line.

[0074] In this way, as long as the values ​​of the coding bits corresponding to the overlapping edges of adjacent tiles are equal in the multiple tiles filled in the design range, it means that the dividing lines of the two adjacent tiles are connected. For example, when the values ​​of the coding bits corresponding to the overlapping edges of two adjacent tiles are all 1, it means that the dividing lines of the two adjacent tiles are connected; when the values ​​of the coding bits corresponding to the overlapping edges of the two adjacent tiles are all 0, it means that the overlapping edges of the two adjacent tiles are not divided, that is, the two adjacent tiles are combined into a larger area by splicing. Therefore, when the values ​​of the coding bits corresponding to the overlapping edges of two adjacent tiles are equal, such filling is allowed. For another example, when the coding bits corresponding to the overlapping edges of two adjacent tiles are different, such as one is 0 and the other is 1, it means that the overlapping edges of the two adjacent tiles are not divided in one tile, but divided in another tile, that is, the dividing lines of the two adjacent tiles are not connected, and such filling is not allowed.

[0075] For another example, if the intersection of the dividing line and the edge of the tile is not the midpoint, then different coding bits with different values ​​can be used to indicate whether each edge of the tile is divided, as well as the intersection position of the dividing line and the edge. For example, when the value of a certain coding bit is 00, it means that the edge corresponding to the coding bit in the basic tile is not divided by the dividing line; when the value of the coding bit is 01, 10 or 11, it means that the edge corresponding to the coding bit in the basic tile is divided by the dividing line, and the values ​​of the three coding bits correspond to three different intersection positions. The intersection position can be represented by the distance from a predefined reference point, for example. As long as the values ​​of the coding bits corresponding to the overlapping edges of adjacent tiles are equal in multiple tiles filled in the design range, it means that the dividing lines of the two adjacent tiles are connected. For the sake of brevity, no further examples will be given here.

[0076] It should be understood that determining whether the dividing line between two adjacent tiles is connected by the code values ​​corresponding to the two adjacent tiles is only one possible implementation manner, and the present application includes but is not limited to this.

[0077] In another possible implementation, whether the dividing lines of two adjacent tiles are connected can be judged by the position of the intersection of the dividing lines of two adjacent tiles with the tile boundary. Specifically, if the dividing lines of two adjacent tiles are connected, the intersection of the dividing lines with the overlapping edges on the two tiles should be the same intersection. Therefore, whether the dividing lines of two adjacent tiles are connected can be judged by whether the distances between the intersections of the two dividing lines with the overlapping edges on the two tiles and a certain reference point are the same. If the distances between the intersections of the two dividing lines with the overlapping edges on the two tiles and a certain reference point are equal and in the same direction, it means that the dividing lines of the two adjacent tiles are connected; if they are not equal, it means that the dividing lines of the two adjacent tiles are not connected.

[0078] Based on the same concept described above, those skilled in the art can also make simple changes to obtain more methods for determining whether the dividing lines of two adjacent tiles are connected. The present application includes but is not limited to the above.

[0079] S230: Obtain a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed.

[0080] By executing S220, the computer device can obtain at least one internal layout of the scope to be designed. In order to further obtain a layout diagram of at least one layout of the scope to be designed, it is also necessary to obtain an outer boundary of the scope to be designed.

[0081] Optionally, the method also includes: inputting a picture containing the range to be designed into a pre-trained first neural network, so as to analyze each pixel within the range to be designed through the first neural network to obtain the foreground and background within the range to be designed, and the first neural network is used to determine whether each pixel belongs to the foreground or the background.

[0082] The image containing the range to be designed may be a plurality of different internal layout images of the same range to be designed obtained by S220. In other words, the plurality of different internal layout images obtained by S220 may be input into the first neural network to obtain the foreground and background of the range to be designed respectively. The first neural network may be obtained by training the neural network based on a historical image set with the foreground and background marked.

[0083] Optionally, the first neural network may be an image segmentation network.

[0084] As an example but not limitation, the image segmentation network includes, but is not limited to, Unet network, Deeplab v3 network, and image cascade network (ICnet). Among them, Unet network is a U-shaped symmetrical structure, the first half of the structure is used for feature extraction, and the second half of the structure is used for upsampling. The training speed of this network is fast; Deeplabv3 network refers to the third version of Deeplab network, which is upgraded on the basis of Deeplab v1 and Deeplab v2. The segmentation effect of this network is good, and the segmentation edge is smoother.

[0085] The image segmentation network can divide the image into several specific regions with unique properties according to different segmentation methods. For example, the image segmentation network can learn from the foreground and background in the input historical image set, and then distinguish the foreground and background in the image containing the range to be designed.

[0086] Exemplarily, in an embodiment of the present application, after the picture containing the range to be designed is input into the picture segmentation network, the picture segmentation network analyzes each pixel within the range to be designed. It should be understood that the picture containing the range to be designed includes multiple pixels, wherein each pixel can correspond to the foreground or the background, respectively. For each pixel in the picture containing the range to be designed, the picture segmentation network will output the probability that the pixel belongs to the foreground or the background, thereby determining whether each pixel belongs to the foreground or the background, and then distinguishing the foreground and the background within the range to be designed. It should be understood that the boundary that distinguishes the foreground and the background within the range to be designed is called the outer boundary of the range to be designed.

[0087] The following is an example of two implementation methods of the image segmentation network outputting that each pixel belongs to the foreground or background.

[0088] In a possible implementation, the image segmentation network can output two values ​​for each pixel, which are the probability that the pixel belongs to the foreground and the probability that the pixel belongs to the background. When the probability of the foreground is greater than or equal to the probability of the background, it can be determined that the pixel belongs to the foreground; when the probability of the foreground is less than the probability of the background, it can be determined that the pixel belongs to the background.

[0089] In another possible implementation, the image segmentation network may output the probability that each pixel belongs to the foreground or the probability that the pixel belongs to the background for each pixel. For example, the probability output by the image segmentation network for each pixel is the probability that the pixel belongs to the foreground, and whether the pixel belongs to the foreground may be further determined based on the relationship between the probability and the preset threshold.

[0090] For example, assuming that the preset threshold is 50%, when the probability of the image segmentation network outputting a certain pixel is 70%, that is, 70% is the probability that the pixel belongs to the foreground. Since 70% is greater than 50%, it is determined that the pixel belongs to the foreground; if the probability of the image segmentation network outputting a certain pixel is 50% or less than 50%, since the probability is not greater than the preset threshold of 50%, it is determined that the pixel does not belong to the foreground, that is, the pixel belongs to the background.

[0091] It should be understood that the above-listed methods for determining whether each pixel belongs to the foreground or the background are only examples, and the present application includes but is not limited to the above. The specific process of S230 is described below using the Unet network as an example of an image segmentation network.

[0092] First, each image in the RPLAN image set can be converted into a data set of one or more regions divided by a segmentation line, and each pixel in the data set is marked as foreground or background to obtain a processed data set. The processed data set is input into the Unet network, and the Unet network can learn based on the processed data set.

[0093] Afterwards, at least one internal layout of the design range obtained in S220 can be input into the trained Unet network. The Unet network obtains each pixel in the input layout map by downsampling and upsampling, segments each pixel, and determines whether each pixel belongs to the foreground or the background. Finally, a layout map is outputted in which the foreground and the background are distinguished by a boundary, wherein the boundary that distinguishes the foreground and the background is the outer boundary.

[0094] Combining the design of the internal layout and the determination of the outer boundary of the design range in the previous article, it can be seen that the present application combines the wave function collapse algorithm with the neural network. On the one hand, the internal layout is determined by the wave function collapse algorithm, and on the other hand, the outer boundary is determined by the neural network, thereby obtaining a variety of different layout diagrams, providing a rich layout design.

[0095] Based on the above process, a layout diagram of at least one layout of the range to be designed can be obtained. It can be understood that in the layout diagram output based on the above process, the outer boundary may be an irregularly shaped boundary, and there may be noise points or disconnected areas, so before outputting the layout diagram, the irregularly shaped outer boundary can be optimized.

[0096] Exemplarily, the optimization process includes one or more operations of removing noise, repairing connections, and generating polygon boundaries.

[0097] The noise removal can be achieved by a morphological opening operation. For example, a morphological opening operation is performed on the above layout diagram to remove the noise in the layout diagram.

[0098] If there are disconnected parts in the layout graph, the disconnected parts can be repaired. Repairing the connection can be achieved by morphological closing operation. For example, a morphological closing operation is performed on a layout graph, such as a layout graph with noise removed, so as to repair the layout graph.

[0099] The above-mentioned process of removing noise points and repairing connections may be referred to as thinning. The image after thinning may be further processed to fit the outer boundary into a polygon, that is, to generate a polygonal boundary.

[0100] The generation of polygonal boundaries can be achieved using the Douglas-Peucker algorithm.

[0101] Generating polygonal boundaries based on the refined layout graph may cause the layout graph before the refinement to be over-modified. Therefore, the intersection-and-union ratio of the layout graph before the refinement and the layout graph after the polygonal boundaries are generated can be calculated, and the solutions with the intersection-and-union ratio lower than the preset ratio can be filtered out. For example, if the preset ratio is 70%, the solutions after the polygonal boundaries are generated with the intersection-and-union ratio lower than 70% are filtered out.

[0102] Based on the above process, an optimized layout diagram is obtained.

[0103] In the embodiments of the present application, the layout diagram may have different presentation forms.

[0104] In one example, the layout diagram may be a wireframe diagram, for example, a wireframe diagram generated by a wave function collapse algorithm; or, the wireframe diagram may be generated by other algorithms, for example, a wireframe diagram obtained by directly randomly generating some vertical lines on a white rectangle.

[0105] As another example, the layout diagram may also be a color block diagram, where each area is distinguished by blocks of different colors.

[0106] It should be understood that the presentation forms of the layout diagram are not limited to those listed above and are not listed one by one here.

[0107] Based on the above technical content, the range to be designed is filled with a plurality of predefined basic tiles to obtain at least one different internal layout, and then at least one layout of the range to be designed is obtained based on the different internal layouts and the outer boundary of the range to be designed. In this way, the design of the layout diagram is no longer strongly dependent on constraints, breaking the conventional layout design concept, and using a plurality of predefined basic tiles to achieve different ways of segmenting the same range to be designed, providing a richer layout design, which neither relies on existing layout designs in reality nor requires users to provide accurate constraints, and provides users with more flexible design solutions.

[0108] Alternatively, if Figure 2As shown, the method further includes S240, estimating the semantics of one or more regions within the to-be-designed range under each layout in at least one layout of the to-be-designed range.

[0109] The estimation of the semantics of each region can be achieved through a pre-trained neural network (referred to as the second neural network for ease of distinction and explanation) or through reasoning based on simple rules.

[0110] The semantic estimation can be based on the layout diagram, which can be an optimized layout diagram or an unoptimized layout diagram; the semantic estimation can also be based on a connectivity graph after processing the layout diagram (including the optimized or unoptimized layout diagram). This application does not limit this.

[0111] Among them, the connectivity graph can be obtained by processing the layout graph in the following way: each area of ​​the layout graph is regarded as a node, the connection relationship between the areas in the layout graph is represented by connecting lines, and finally a connectivity graph is obtained by connecting the nodes with connecting lines.

[0112] In one possible implementation, the semantics of one or more regions are estimated by a second neural network.

[0113] The second neural network can be trained based on the historical region semantic set. The historical region semantic set can be, for example, a connected graph obtained by converting the RPLAN image set. Based on the learning of each region in the historical region semantic set and the semantics corresponding to each region, the semantics of each region in the layout map can be estimated.

[0114] The second neural network may be a graph convolutional network or other graph networks. The present application includes but is not limited to this.

[0115] Exemplarily, taking the second neural network as a graph convolution network as an example, the layout diagram of each layout in at least one layout of the design range is input into the graph convolution network, and the graph convolution network performs semantic estimation on each area in the layout diagram. For each area in the layout diagram, the graph convolution network will select the semantics with the highest probability among all semantics when estimating the semantics of the area as the semantic output of the area. For example, after the graph convolution network is learned based on the semantics corresponding to each area in the historical regional semantic set, it contains 12 kinds of semantics. Then, after the layout diagram is input into the graph convolution network, the graph convolution network will estimate each of the 12 semantics for each area of ​​the layout diagram, and accordingly, after estimating each semantic, there is a probability that the area corresponds to the semantics. Finally, for each area, the semantics with the highest probability among all semantics corresponding to the area is output as the semantics of the area. It should be understood that the above 12 kinds of semantics are only an example, and this application does not limit the types and quantities of semantics on which the second neural network performs semantic estimation.

[0116] Combined with the previous design of the internal layout of the design range, the determination of the outer boundary and the semantic estimation of the region, it can be seen that by combining the wave function collapse algorithm with the neural network, on the one hand, the internal layout is determined by the wave function collapse algorithm, and on the other hand, the outer boundary is determined and the semantics is estimated by the neural network, so that a variety of different layout diagrams and semantic estimates of each region in each layout diagram can be obtained, providing rich layout design solutions.

[0117] In another possible implementation, semantic estimation of one or more regions is achieved by reasoning on simple rules.

[0118] For example, semantics are set according to the size of the area. For example, the area with the largest area among all areas is set as the living room, and the area with an area just smaller than the largest area is set as the bedroom. The above rules can be pre-set by the user, and it should be understood that the present application includes but is not limited to this.

[0119] Furthermore, the method also includes: determining other semantics of one or more areas within the scope to be designed under each layout based on predefined correspondence information and the semantics of one or more areas within the scope to be designed under each layout estimated by the second neural network.

[0120] The correspondence information is used to indicate the correspondence of at least one group of regions. A group of regions with a correspondence includes, for example, but is not limited to, two regions with similarity, and the semantics of the two regions can be interchanged.

[0121] Exemplarily, the semantics of two similar areas in each group of areas are both the semantics of indoor scenes, and when designing indoor scenes, the semantics of these two areas can be interchanged; or, the semantics of two similar areas in each group of areas are respectively the semantics of indoor scenes and the semantics of outdoor scenes, and when designing outdoor scenes, the semantics of the indoor area in the group of areas can be replaced with the semantics of the outdoor area in the group of areas.

[0122] In one example, the functions of two regions in each group of regions are similar.

[0123] For example, in interior scene design, the master bedroom and the second bedroom are both used for sleeping, so the functions of the master bedroom and the second bedroom are similar, and the semantics of the master bedroom and the second bedroom can be interchanged. That is, the area with the semantics of the master bedroom can also be replaced with the area with the semantics of the second bedroom, and correspondingly, the area with the semantics of the second bedroom can be replaced with the area with the semantics of the master bedroom.

[0124] For another example, the area sizes of two regions in each group of regions have similar proportions in the layout diagram.

[0125] For example, if the living room is the largest area in the indoor scene and the square is the largest area in the outdoor scene, then the proportion of the living room in the indoor scene is similar to the proportion of the square in the outdoor scene. In this way, the semantics of the living room area in the indoor scene design can be replaced with the square in the outdoor scene design.

[0126] Based on the layout diagram of each of the at least one layout and the multiple semantics of one or more areas within the to-be-designed range under each layout, multiple design solutions for the to-be-designed range can be obtained. And through the semantic conversion of indoor scenes and outdoor scenes, the solution can be applied to more scene designs, providing users with more flexible design solutions.

[0127] In order to better understand the method provided in the embodiments of the present application, Figure 6 The process of obtaining a layout diagram using the method provided by this application is shown. Figure 6 As shown, by filling the scope to be designed based on a variety of basic tiles, at least one internal layout of the scope to be designed can be obtained. Figure 6 a) in the figure shows an internal layout within the scope to be designed. After the scope to be designed including the internal layout is input into the first neural network, the outer boundary of the scope to be designed is estimated by the first neural network. Figure 6 b) in the figure shows the outer boundary estimated by the first neural network. Thus, a layout diagram of the range to be designed can be obtained. The layout diagram is input into the second neural network to perform semantic estimation of the region through the second neural network, and a semantic estimation of each region can be obtained. Figure 6c) in the figure shows the semantics of each region estimated by the second neural network.

[0128] It should be understood that the internal layout obtained by filling the design range with basic tiles is not limited to the one shown in the figure, and there may be many other possible internal layouts. The design range containing other internal layouts can be input into the first neural network to estimate the outer boundary.

[0129] It should also be understood that the layout diagram input to the second neural network is not limited to the one shown in the figure. After the range to be designed containing other internal layouts is input to the first neural network, other layout diagrams of the range to be designed can be obtained. After these layout diagrams are input to the second neural network, semantic estimation of the region can be performed, thereby obtaining semantic estimation of different regions under different layout diagrams. In this way, multiple layout design solutions can be obtained.

[0130] Based on the above scheme, by pre-defining the correspondence information, when designing the layout of the indoor scene, the semantics of two indoor areas with a corresponding relationship can be interchanged, so that more abundant design schemes can be obtained for users to choose; in addition, the semantic replacement between the areas with a corresponding relationship in different scenes can be used to apply the same layout design to different scenes, thereby improving the applicability of the design scheme. In general, the design scheme can be provided more flexibly.

[0131] The following will be combined Figure 7 and Figure 8 The layout design device provided in the embodiment of the present application is described in detail.

[0132] Figure 7 700 may correspond to the layout design device in the above method embodiment, and may be a chip system, or may be a chip system configured to implement the functions of the layout design device in the above method embodiment. In the embodiment of the present application, the chip system may be composed of chips, or may include chips and other discrete devices.

[0133] like Figure 7 As shown, the device 700 includes an acquisition module 710 and a processing module 720. The device 700 can be used to implement the above Figure 2Functions of the layout design device of the embodiment shown. Among them, the acquisition module 710 is used to acquire the range to be designed; the processing module 720 is used to fill the interior of the range to be designed based on a predefined plurality of basic tiles to obtain at least one internal layout of the range to be designed, the range to be designed under each internal layout includes one or more areas divided based on a plurality of tiles, the size of a plurality of basic tiles obtained by at least one basic tile among a plurality of basic tiles is smaller than the range to be designed, the plurality of basic tiles include at least one basic tile with a dividing line, each basic tile with a dividing line includes a dividing line intersecting with a tile boundary, and the boundaries of one or more areas are obtained by connecting the dividing lines of a plurality of tiles filled in the range to be designed; and is used to obtain a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and the outer boundary of the range to be designed.

[0134] Optionally, the multiple tiles include: at least one basic tile from a plurality of basic tiles, and / or, at least one tile obtained by transforming at least one basic tile from a plurality of basic tiles; the processing module 720 is specifically used to: starting from a starting position, based on a plurality of tiles, fill the interior of the range to be designed until the range to be designed is completely filled and the dividing lines of adjacent tiles filled in the range to be designed are connected; wherein the starting position is randomly selected or pre-specified.

[0135] Optionally, the sizes of the multiple basic tiles are the same, and in the basic tile with the dividing line, the intersection position of the dividing line and the border is the border center of the basic tile.

[0136] Optionally, each basic tile corresponds to a coding value, the number of bits of the coding value is the same as the number of edges of the basic tile, each coding bit in the coding value corresponds to an edge of the basic tile, used to indicate whether the corresponding boundary is divided by a dividing line; the coding values ​​corresponding to any two basic tiles are different, and the values ​​of the coding bits corresponding to the overlapping boundaries of adjacent tiles are equal.

[0137] Optionally, the processing module 720 is also used to: input a picture containing the range to be designed into a pre-trained first neural network, so as to analyze each pixel within the range to be designed through the first neural network to obtain the foreground and background within the range to be designed, and the first neural network is used to determine whether each pixel belongs to the foreground or the background; based on the foreground and background within the range to be designed, obtain the outer boundary of the range to be designed.

[0138] Optionally, the processing module 720 is also used to: estimate the semantics of one or more areas within the range to be designed under each layout in at least one layout of the range to be designed; and obtain at least one design scheme for the range to be designed based on the semantics of one or more areas within the range to be designed under each layout in at least one layout and each layout.

[0139] Optionally, the processing module 720 is specifically used to: determine other semantics of one or more areas within the scope to be designed under each layout based on predefined correspondence information and the semantics of one or more areas within the scope to be designed under each layout estimated by the second neural network; the correspondence information is used to indicate the correspondence of at least one group of areas, each group of areas includes two areas with similar functions, and the semantics of the two areas in each group of areas are interchangeable; based on the layout diagram of each layout in at least one layout, and the multiple semantics of one or more areas within the scope to be designed under each layout, obtain multiple design schemes for the scope to be designed.

[0140] Optionally, the semantics of the two areas in each group of areas indicated in the correspondence information are both semantics of indoor scenes; or, the semantics of the two areas in each group of areas indicated in the correspondence information are respectively: semantics of indoor scenes and semantics of outdoor scenes.

[0141] It should be understood that Figure 7 The module division of the device is only exemplary. In actual applications, different functional modules can be divided according to different functional requirements. This application does not impose any limitation on the division form and number of functional modules in actual applications, and Figure 7 This is not intended to limit the application in any way.

[0142] Figure 8 It is another schematic block diagram of the layout design device provided in an embodiment of the present application.

[0143] The layout design device 800 may be a chip system, or may be a device configured with a chip system to implement the layout design function in the above method embodiment. In the embodiment of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices.

[0144] like Figure 8 As shown, the device 800 may include at least one processor 810, which is used to implement the functions of the layout design device in the method provided in the embodiment of the present application.

[0145] Exemplarily, when the layout design device 800 is used to implement the function of the layout design device provided in the embodiment of the present application, the processor 810 can be used to obtain a range to be designed; based on a predefined plurality of basic tiles, the interior of the range to be designed is filled to obtain at least one internal layout of the range to be designed, the range to be designed under each internal layout includes one or more regions obtained based on a plurality of tiles, the plurality of tiles are obtained from at least one basic tile of the plurality of basic tiles, the size of the plurality of basic tiles is smaller than the range to be designed, the plurality of basic tiles include at least one basic tile with a dividing line, each basic tile with a dividing line includes a dividing line intersecting with a tile boundary, and the boundaries of one or more regions are obtained by connecting the dividing lines of the plurality of tiles filled in the range to be designed; based on at least one internal layout of the range to be designed and the outer boundary of the range to be designed, a layout diagram of at least one layout of the range to be designed is obtained. For details, please refer to the detailed description in the method example, which will not be repeated here.

[0146] The layout design device 800 may also include at least one memory 820, which may be used to store program instructions and data, etc. The processor 810 is coupled to the memory 820. The coupling in the embodiment of the present application is an indirect coupling or communication connection between devices, units or modules, which may be electrical, mechanical or other forms, and is used for information exchange between devices, units or modules. The processor 810 may operate in conjunction with the memory 820. The processor 810 may execute program instructions stored in the memory 820. At least one of the at least one memory may be included in the processor.

[0147] The layout design device 800 may also include a communication interface 830 for communicating with other devices via a transmission medium, so that the layout design device 800 can communicate with other devices. The communication interface 830 may be, for example, a transceiver, an interface, a bus, a circuit, or a device capable of implementing a transceiver function. The processor 810 may use the communication interface 830 to send and receive data and / or information, and is used to implement the method performed by the computer device in the embodiment of the present application.

[0148] The specific connection medium between the processor 810, the memory 820 and the communication interface 830 is not limited in the embodiment of the present application. Figure 8 In the embodiment, the processor 810, the memory 820 and the communication interface 830 are connected via a bus 840. The bus 840 is Figure 8 The connections between the other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0149] The present application also provides a computer program product, the computer program product comprising: a computer program (also referred to as code, or instruction), when the computer program is executed, causes the computer to execute the following Figure 2 The method of the illustrated embodiment.

[0150] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program (also referred to as code or instruction). When the computer program is executed, the computer executes the following Figure 2 The method of the illustrated embodiment.

[0151] It should be understood that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined to perform. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0152] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0153] The terms "unit", "module" and the like used in this specification may be used to represent a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution.

[0154] It will be appreciated by those skilled in the art that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in combination with computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. In the several embodiments provided in this application, it should be understood that the disclosed devices, equipment and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0155] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0156] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0157] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0158] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0159] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A layout design method, characterized in that: include: Get the scope to be designed; The user inputs a picture containing the range to be designed into the layout design device, and the layout design device determines the range to be designed based on the received picture; Based on a plurality of predefined basic tiles, the interior of the range to be designed is filled to obtain at least one internal layout of the range to be designed, wherein the range to be designed under each internal layout includes one or more regions divided based on a plurality of tiles, the plurality of tiles are obtained from at least one basic tile among the plurality of basic tiles, the size of the plurality of basic tiles is smaller than the range to be designed, the plurality of basic tiles include at least one basic tile with a dividing line, each basic tile with a dividing line includes a dividing line intersecting with a tile boundary, and the boundaries of the one or more regions are obtained by connecting the dividing lines of the plurality of tiles filled in the range to be designed; Based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed, obtaining a layout diagram of at least one layout of the range to be designed; Before obtaining a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed, the method further includes: Inputting a picture including the range to be designed into a pre-trained first neural network, so as to analyze each pixel in the range to be designed by the first neural network to obtain a foreground and a background in the range to be designed, wherein the first neural network is used to determine whether each pixel belongs to the foreground or the background; Based on the foreground and background within the to-be-designed range, an outer boundary of the to-be-designed range is obtained; After obtaining a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed, the method further includes: estimating the semantics of one or more regions within the scope to be designed in each layout of at least one layout of the scope to be designed by a pre-trained second neural network; Based on each of the at least one layout and the semantics of one or more regions within the to-be-designed range under each layout, obtaining at least one design scheme for the to-be-designed range; The obtaining, based on each of the at least one layout and the semantics of one or more regions within the to-be-designed range under each layout, at least one design scheme for the to-be-designed range comprises: Based on the predefined correspondence information and the semantics of the one or more regions within the to-be-designed range under each layout estimated by the second neural network, determine other semantics of the one or more regions within the to-be-designed range under each layout; the correspondence information is used to indicate the correspondence of at least one group of regions, each group of regions includes two regions with similar functions, and the semantics of the two regions in each group of regions are interchangeable; Based on the layout diagram of each of the at least one layout and the multiple semantics of one or more areas within the to-be-designed range under each layout, multiple design schemes for the to-be-designed range are obtained; The semantics of the two areas in each group of areas indicated in the correspondence information are both the semantics of the indoor scene; or, the semantics of the two areas in each group of areas indicated in the correspondence information are respectively: the semantics of the indoor scene and the semantics of the outdoor scene.

2. The method according to claim 1, characterized in that The plurality of tiles include: at least one basic tile among the plurality of basic tiles, and / or at least one tile transformed based on at least one basic tile among the plurality of basic tiles; The filling of the interior of the to-be-designed range based on the predefined multiple basic tiles includes: Starting from a starting position, based on the multiple tiles, the interior of the range to be designed is filled until the range to be designed is completely filled and the dividing lines of adjacent tiles filled in the range to be designed are connected; wherein the starting position is randomly selected or pre-specified.

3. The method according to claim 2, characterized in that The multiple basic tiles have the same size, and in the basic tile with the dividing line, the intersection position of the dividing line and the boundary is the boundary center of the basic tile.

4. The method according to claim 3, characterized in that Each basic tile corresponds to a coding value, the number of bits of the coding value is the same as the number of edges of the basic tile, each coding bit in the coding value corresponds to an edge of the basic tile, and is used to indicate whether the corresponding boundary is divided by a dividing line; the coding values ​​corresponding to any two basic tiles are different, and the values ​​of the coding bits corresponding to the overlapping boundaries of adjacent tiles are equal.

5. A layout design device, characterized in that: include: An acquisition module is used to acquire the scope to be designed; The user inputs a picture containing the range to be designed into the layout design device, and the layout design device determines the range to be designed based on the received picture; A processing module, configured to fill the interior of the to-be-designed range based on a plurality of predefined basic tiles to obtain at least one internal layout of the to-be-designed range, wherein the to-be-designed range under each internal layout includes one or more regions divided based on a plurality of tiles, wherein the plurality of tiles are obtained from at least one basic tile among the plurality of basic tiles, wherein the size of the plurality of basic tiles is smaller than the to-be-designed range, wherein the plurality of basic tiles include at least one basic tile with a dividing line, wherein each basic tile with a dividing line includes a dividing line intersecting with a tile boundary, and wherein the boundaries of the one or more regions are obtained by connecting the dividing lines of the plurality of tiles filled in the to-be-designed range; and used to obtain a layout diagram of at least one layout of the range to be designed based on at least one internal layout of the range to be designed and an outer boundary of the range to be designed; The processing module is further used to input the picture containing the range to be designed into a pre-trained first neural network, so as to analyze each pixel in the range to be designed through the first neural network to obtain the foreground and background in the range to be designed, and the first neural network is used to determine whether each pixel belongs to the foreground or the background; Based on the foreground and background within the to-be-designed range, an outer boundary of the to-be-designed range is obtained; The processing module is further used to estimate the semantics of one or more regions within the to-be-designed range under each layout of at least one layout of the to-be-designed range through a pre-trained second neural network; Based on each of the at least one layout and the semantics of one or more regions within the to-be-designed range under each layout, obtaining at least one design scheme for the to-be-designed range; The processing module is specifically used to determine other semantics of one or more areas within the scope to be designed under each layout based on predefined correspondence information and the semantics of one or more areas within the scope to be designed under each layout estimated by the second neural network; the correspondence information is used to indicate the correspondence of at least one group of areas, each group of areas includes two areas with similar functions, and the semantics of the two areas in each group of areas are interchangeable; based on the layout diagram of each layout in the at least one layout and the multiple semantics of one or more areas within the scope to be designed under each layout, multiple design schemes for the scope to be designed are obtained; the semantics of the two areas in each group of areas indicated in the correspondence information are both semantics of indoor scenes; or, the semantics of the two areas in each group of areas indicated in the correspondence information are respectively: semantics of indoor scenes and semantics of outdoor scenes.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 4.

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