Semiconductor device and method of manufacturing the same

Abstract

Aims at obtaining semiconductor device capable of inhibiting fluctuation of saturation current and manufacturing method thereof. The semiconductor device related to the invention has: substrate; drift layer of the first conductive type, disposed on the upper surface side of the substrate; base layer of the second conductive type, disposed on the upper surface side of the drift layer; upper semiconductor layer of the first conductive type, disposed on the upper surface side of the base layer; the first electrode, disposed on the upper surface of the substrate, electrically connected with the upper semiconductor layer; the second electrode, disposed on the back surface of the substrate; groove, extending from the upper surface of the substrate to the drift layer, penetrating the upper semiconductor layer and the base layer; and gate electrode, disposed in the groove, the inner side of the groove has the first surface and the second surface disposed at the lower position than the first surface, the second surface is inclined to the inner side of the groove relative to the first surface, and the intersection of the first surface and the second surface is disposed at the lower position than the base layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In Patent Document 1, a trench type longitudinal MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is disclosed. In the MOSFET, the shape of the trench that becomes a gate is a convex shape that faces the inside of the trench like a γ letter. As a result, the surface area of the trench is reduced, the capacitance between the gate and the source and the capacitance between the gate and the drain can be reduced, and the on-off time can be shortened.

[0003] Patent Document 1: Japanese Patent Application Laid-Open (JP-A) No. 11-111983

[0004] In the semiconductor device of Patent Document 1, the trench shape is a γ letter shape, and therefore, an inclination is generated at a portion having a channel. Therefore, the fluctuation of the saturation current can become large. SUMMARY

[0005] The present application has been made to solve the above problems, and has an object to provide a semiconductor device and a manufacturing method thereof that can suppress the fluctuation of the saturation current.

[0006] The semiconductor device according to the present application has a substrate having an upper surface and a back surface on the opposite side of the upper surface; a drift layer of a first conductive type provided on the upper surface side of the substrate; a base layer of a second conductive type different from the first conductive type provided on the upper surface side of the drift layer; an upper semiconductor layer of the first conductive type provided on the upper surface side of the base layer; a first electrode provided on the upper surface of the substrate and electrically connected to the upper semiconductor layer; a second electrode provided on the back surface of the substrate; a trench extending from the upper surface of the substrate to the drift layer so as to pass through the upper semiconductor layer and the base layer; and a gate electrode provided inside the trench, the inner side surface of the trench having a first surface and a second surface provided at a position lower than the first surface, the second surface being inclined toward the inner side of the trench with respect to the first surface, and the intersection of the first surface and the second surface being provided at a position lower than the base layer.

[0007] In a method of manufacturing a semiconductor device according to the present application, a drift layer of a first conductivity type is formed on the upper surface side of a substrate having an upper surface and a back surface opposite to the upper surface, a base layer of a second conductivity type different from the first conductivity type is formed on the upper surface side of the drift layer, an upper semiconductor layer of the first conductivity type is formed on the upper surface side of the base layer, a first trench extending from the upper surface of the substrate to a depth below the base layer is formed by etching, at least one of a condition in which the pressure of an etching gas is increased compared to when the first trench is formed, a condition in which the acceleration voltage of ions used for etching is decreased compared to when the first trench is formed, or a condition in which a byproduct generated by etching is more likely to deposit compared to when the first trench is formed is implemented, etching is performed from the bottom of the first trench, a second trench is formed, a first electrode electrically connected to the upper semiconductor layer is formed on the upper surface of the substrate, a second electrode is formed on the back surface of the substrate, and a gate electrode is formed inside the trench formed by the first trench and the second trench.

[0008] Effects of the Invention

[0009] In the semiconductor device and the method of manufacturing the same according to the present application, the intersection between the first surface and the second surface inclined toward the inside of the trench with respect to the first surface is provided at a position below the base layer. Thus, fluctuation in saturation current can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a plan view of the semiconductor device according to Embodiment 1.

[0011] Figure 2 is a cross-sectional view obtained by cutting along the A-A line. Figure 1

[0012] Figure 3 is an enlarged view of Figure 2

[0013] Figure 4 is an enlarged view of the trench periphery according to Embodiment 1.

[0014] Figure 5 is a view showing a state after a drift layer, a base layer, and an emitter layer are formed on a substrate.

[0015] Figure 6 is a view showing a state after a substrate is etched.

[0016] Figure 7 is a view showing a state after a second trench is formed by etching from the bottom of a first trench.

[0017] Figure 8 is a cross-sectional view of the semiconductor device according to Comparative Example 1. ​​

[0018] Figure 9 is a sectional view of a semiconductor device involved in Comparative Example 2.

[0019] Figure 10 is a sectional view of a semiconductor device involved in Embodiment 1.

[0020] Figure 11 is a characteristic diagram showing dependence of collector current on gate voltage.

[0021] Figure 12 is a depth T C of intersection with respect to the depth T B of the base layer.

[0022] Figure 13 is T C / T B of intersection with respect to the depth of the trench.

[0023] Figure 14 is a diagram for explaining a configuration of a semiconductor device involved in Embodiment 1.

[0024] Figure 15 is a sectional view of a semiconductor device involved in Embodiment 2.

[0025] Figure 16 is a sectional view of a semiconductor device involved in Embodiment 3.

[0026] Figure 17 is a sectional view of a semiconductor device involved in Embodiment 4.

[0027] Figure 18 is a sectional view of a semiconductor device involved in Embodiment 5.

[0028] Figure 19 is a sectional view of a semiconductor device involved in Embodiment 6.

[0029] Figure 20 is a sectional view of a semiconductor device involved in Embodiment 7. DETAILED DESCRIPTION

[0030] With reference to the drawings, a semiconductor device and a manufacturing method thereof involved in each of the present embodiments will be explained. The same reference numerals are assigned to the same or corresponding structural elements, and sometimes repeated explanation is omitted.

[0031] Embodiment 1

[0032] Figure 1 is a plan view of a semiconductor device 100 involved in Embodiment 1. Figure 2 is a sectional view of Figure 1A cross-sectional view taken along the straight line A-A. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 is used as, for example, a power semiconductor device.

[0033] The semiconductor device 100 has a substrate 50 having an upper surface 50a and a back surface 50b on the opposite side from the upper surface 50a. The substrate 50 is of n-type, for example, formed of Si. The n-type corresponds to the first conductivity type, and the p-type corresponds to the second conductivity type. The conductivity types of the layers can also be reversed.

[0034] A drift layer 20 of n-type is provided on the upper surface 50a side of the substrate 50. A base layer 24 of p-type is provided on the upper surface 50a side of the drift layer 20. An emitter layer 23 of n-type is provided on the upper surface 50a side of the base layer 24. The emitter layer 23 corresponds to an upper semiconductor layer. A contact layer 25 of p-type is provided on the upper surface 50a side of the base layer 24. The emitter layer 23 and the contact layer 25 are each formed on a portion of the upper surface 50a side of the base layer 24.

[0035] A buffer layer 21 of n-type is formed on the back surface 50b side of the substrate 50. A collector layer 22 of p-type is formed on the back surface 50b side of the buffer layer 21.

[0036] A trench 12 is formed in the substrate 50. The trench 12 extends through the emitter layer 23 and the base layer 24 to the drift layer 20 from the upper surface 50a of the substrate 50. An inner side surface of the trench 12 is covered with a gate insulating film 13. A gate electrode 14 is embedded in the inside of the trench 12 with the gate insulating film 13 interposed therebetween. An interlayer insulating film 15 covers the upper surface of the gate electrode 14. The gate electrode 14 is electrically connected to a gate pad 19 shown in the drawing. Figure 1

[0037] A plurality of unit regions 40 are formed in the substrate 50. Each unit region 40 has the emitter layer 23, the base layer 24, the contact layer 25, the gate electrode 14, and the interlayer insulating film 15. An emitter electrode 10 electrically connected to the emitter layer 23 is provided on the upper surface 50a of the substrate 50. The emitter electrode 10 corresponds to the first electrode. The emitter electrode 10 is formed on the plurality of unit regions 40. The emitter electrode 10 is connected to the emitter layer 23, the base layer 24, and the contact layer 25. The gate electrode 14 is insulated from the emitter electrode 10 by the interlayer insulating film 15. A collector electrode 11 is formed on the back surface 50b of the substrate 50. The collector electrode 11 corresponds to the second electrode.

[0038] Figure 3 is an enlarged view of Figure 2 Figure 4 ​​is an enlarged view of the periphery of the trench 12 according to Embodiment 1. The narrower the lower, the narrower the width with respect to the trench 12. The inner side surface of the trench 12 has a first surface 16 and a second surface 17 provided at a position lower than the first surface 16. The second surface 17 is inclined toward the inner side of the trench 12 with respect to the first surface 16. In Figure 4 , as one example, the intersection 18 of the first surface 16 and the second surface 17 is disposed at the same depth as the lower end of the base layer 24. That is, the intersection 18 is disposed at the same depth as the lower end of the channel doping. The intersection 18 of the first surface 16 and the second surface 17 can also be provided at a position lower than the base layer 24. In addition, the bottom surface of the trench 12 is formed by a curved surface, in a circular arc shape. The corner portion connecting the bottom surface of the trench 12 and the second surface 17 is chamfered.

[0039] As shown in Figure 4 , the angle θ2 formed by the second surface 17 and the upper surface 50a of the substrate 50 is smaller than the angle θ1 formed by the first surface 16 and the upper surface 50a of the substrate 50. That is, with respect to the trench 12, the reduction amount of the width per unit depth is larger in the lower portion than in the portion above the intersection 18.

[0040] Next, the manufacturing method of the semiconductor device 100 will be described. First, the drift layer 20 is formed on the upper surface 50a side of the substrate 50, the base layer 24 is formed on the upper surface 50a side of the drift layer 20, and the emitter layer 23 is formed on the upper surface 50a side of the base layer 24. Figure 5 is a view showing the state after the drift layer 20, the base layer 24, and the emitter layer 23 are formed on the substrate 50. The base layer 24 and the emitter layer 23 can be formed by ion implantation or the like. The order of formation of the drift layer 20, the base layer 24, and the emitter layer 23 is not limited.

[0041] Next, the mask 56 having the opening 55 is formed on the upper surface of the emitter layer 23. Next, dry etching is performed using the mask 56, and the first trench 12a is formed. Figure 6 is a view showing the state after the substrate 50 is etched. The first trench 12a extends to the lower end of the base layer 24, for example. The depth of the first trench 12a differs depending on the depth of the final trench 12. For example, in the case where the depth of the final trench 12 is 5.0 μm, the depth of the first trench 12a becomes the depth until the lower end of the base layer 24. In addition, the first trench 12a can be formed in such a manner that the first trench 12a extends from the upper surface 50a of the substrate 50 to a depth lower than the base layer 24 by etching.

[0042] The side surface of the first trench 12a is substantially perpendicular to the upper surface 50a of the substrate 50. The angle Θ1 formed by the inner side surface of the first trench 12a and the upper surface 50a of the substrate 50 is, for example, greater than or equal to 89°. The angle Θ1 can be controlled by adjusting the pressure of the etching gas in dry etching or the acceleration voltage of the ions used for etching. In addition, the angle Θ1 can be controlled by adjusting the deposition conditions of the by-products generated along with etching. For example, if the carbon ratio in the gas is increased, the by-products become more likely to deposit. Specifically, the lower the pressure of the etching gas or the higher the acceleration voltage of the ions, the larger the angle Θ1 can be made. In addition, the smaller the amount of by-products generated along with etching, the larger the angle Θ1 can be made.

[0043] Next, dry etching is performed from the bottom of the first trench 12a to form a second trench 12b. Figure 7 is a view showing the state after the second trench 12b is formed by etching from the bottom of the first trench 12a. The inner side surface of the second trench 12b is greatly inclined with respect to the upper surface 50a of the substrate 50 compared to the inner side surface of the first trench 12a. The angle Θ2 formed by the inner side surface of the second trench 12b and the upper surface 50a of the substrate 50 is, for example, less than or equal to 88°.

[0044] The etching conditions for forming the second trench 12b are performed under conditions in which the angle Θ2 can be controlled to be small compared to the etching conditions when the first trench 12a is formed. The etching for forming the second trench 12b is performed, for example, by increasing the pressure of the etching gas compared to when the first trench 12a is formed. In addition, the etching for forming the second trench 12b can be performed by lowering the acceleration voltage of the ions used for etching compared to when the first trench 12a is formed. In addition, the etching for forming the second trench 12b can be performed under conditions in which the by-products generated along with etching are likely to deposit compared to when the first trench 12a is formed. The etching conditions for forming the second trench 12b can be performed as long as at least one of these three conditions is implemented.

[0045] Thus, the first trench 12a and the second trench 12b of the present embodiment are formed by different etching conditions. The trench 12 can be formed after at least the step of forming the base layer 24 of the substrate 50. Then, an oxide film is formed as the gate insulating film 13 on the inner wall of the trench 12. Next, a gate polysilicon is formed as the gate electrode 14 on the gate insulating film 13 inside the trench 12. Thus, the gate electrode 14 is formed inside the trench 12. In addition, the emitter electrode 10 is formed on the upper surface 50a of the substrate 50, and the collector electrode 11 is formed on the back surface 50b of the substrate 50.

[0046] Next, the effects of the present embodiment will be described while being compared with comparative examples.Figure 8 is a sectional view of the semiconductor device 101 involved in the 1st Comparative Example. Figure 9 is a sectional view of the semiconductor device 102 involved in the 2nd Comparative Example. Figure 10 is a sectional view of the semiconductor device 100 involved in the 1st Embodiment. In the case of the semiconductor device 101 involved in the 1st Comparative Example, the inner side surface of the trench 121 is inclined at a certain angle as a whole. In addition, in the case of the semiconductor device 102 involved in the 2nd Comparative Example, the intersection 18 at the inner side surface of the trench 122 is provided at a shallower position than in the present embodiment. The intersection 18 at the trench 122 is provided, for example, at the same depth as the lower end of the emitter layer 23. The depth of the trench 121 and the trench 12 of the present embodiment is, for example, 5.8 μm, and the depth of the trench 122 is 3.8 μm.

[0047] Figure 11 is a characteristic diagram showing the dependence of the collector current on the gate voltage. In Figure 11 , the ICE up to Vg = 15 V is compared for the semiconductor devices 100, 101, 102. In Figure 11 , the gate voltage VG indicates the forward bias to the gate electrode 14. In addition, the collector current ICE indicates the current flowing from the collector electrode 11 to the emitter electrode 10.

[0048] In the case of the semiconductor device 101 involved in the 1st Comparative Example, the smaller the angle θ3 between the upper surface 50a of the substrate 50 and the inner side surface of the trench 121, the smaller the saturation current. In the range of 86° to 89° for the angle θ3, the fluctuation of the saturation current is approximately 30%. In contrast, in the case of the semiconductor device 100 of the present embodiment, a larger collector current is obtained than in the case of the U-shaped trench with θ3 = 90° and the semiconductor devices 101, 102.

[0049] Generally, in the case of the U-shaped trench with θ3 = 90°, as the trench becomes deeper, the feedback capacitance increases. Also, sometimes the deeper the trench, the more difficult it is to maintain the U-shaped form. In addition, in the case where the trench 121 involved in the 1st Comparative Example has a certain or greater inclination, there is a tendency for the channel length to become longer. In addition, the inclination angle of the trench 121 can fluctuate. As Figure 11 indicated in

[0050] In the case of an IGBT, if a forward bias is applied to the collector electrode 11 and the gate electrode 14, an inversion layer is generated at the base layer 24 in contact with the gate insulating film 13, forming a channel. This initiates current flow from the collector electrode 11 to the emitter electrode 10, and the IGBT becomes on. If the channel length is unstable, the current-carrying capacity will fluctuate even with a high forward bias applied to the gate electrode 14. This can potentially lead to an increase in the turn-on voltage, an increase in the on-off characteristics, and a decrease in short-circuit withstand capability. In particular, when multiple chips are used in parallel, the current during power-on may fluctuate. This can potentially reduce the SOA (Safety Operating Area) withstand capability.

[0051] In contrast, in the semiconductor device 100 of this embodiment, the first surface 16 in the trench 12 that contacts the base layer 24 is substantially perpendicular to the upper surface 50a of the substrate 50. Therefore, the channel length can be suppressed. Furthermore, fluctuations in the tilt angle of the first surface 16 can be suppressed. Thus, fluctuations in the channel length can be suppressed. Therefore, fluctuations in the current-carrying capacity when the gate electrode 14 is highly forward biased can be suppressed. That is, fluctuations in the saturation current can be suppressed. Furthermore, fluctuations in the threshold voltage can be suppressed. Thus, the turn-on voltage can be suppressed, and short-circuit withstand capability is improved. Moreover, even when multiple semiconductor devices 100 are connected in parallel, current fluctuations can be suppressed. Therefore, in the SOA, current concentration towards the chip through which current easily flows can be suppressed, and withstand capability can be increased.

[0052] In trench 12, the angle θ1 formed by the first surface 16 and the upper surface 50a of the substrate 50 only needs to be greater than 89° and less than or equal to 90°. For example... Figure 11 As shown, if the angle is within this range, the variation in collector current dependent on angle θ1 becomes smaller, and fluctuations in collector current can be suppressed. Furthermore, the angle θ2 formed by the second surface 17 and the upper surface 50a of the substrate 50 only needs to be greater than 86° and less than or equal to 88°. Therefore, particularly in trenches 12 with a depth of 6 μm or similar, the shape of the bottom of the trench 12 can be maintained as circular. This suppresses electric field concentration during voltage application and reduces voltage drop.

[0053] Figure 12 The depth T of intersection point 18 C relative to the depth T of the base layer 24 B A graph showing the correlation between the ratio and the fluctuation of the collector current. Depth T B This represents the depth from the upper surface 50a of the substrate 50 to the lower end of the portion of the base layer 24 adjacent to the trench 12. That is, the depth T. BThe width of the emitter layer 23 facing the side wall of the trench 12 is added to the length of the channel formed in the base layer 24. Depth T C represents the depth from the upper surface 50a of the substrate 50 to the intersection 18.

[0054] In Figure 12 , T C is shown for the case where the depth of the trench 12 is 5.8 μm, 4.8 μm, and 3.8 μm. B The shallower the trench 12, the greater the fluctuation in the saturation current. However, in the configuration where the depth of the trench 12 is 3.8 μm, likewise, by configuring the intersection 18 of the first face 16 and the second face 17 to be deeper than the base layer 24, it is possible to suppress the fluctuation in the saturation current even when the trench 12 is shallow. C B For example, greater than 1, so that it is possible to suppress the fluctuation in the saturation current. That is, by configuring the intersection 18 of the first face 16 and the second face 17 to be deeper than the base layer 24, it is possible to suppress the fluctuation in the saturation current even when the trench 12 is shallow.

[0055] Figure 13 is T C B with respect to the depth of the trench 12. In Figure 13 , the depth T D of the trench 12 to the bottom is shown for the case where the fluctuation in the saturation current is 2%. The relationship between T C and T B is shown. From the approximate curve of the data shown in Figure 13 , it is understood that the depth T C of the intersection 18, the depth T B of the base layer 24, and the depth T D of the trench 12 satisfy the following formula (1) as long as they satisfy the following formula (1).

[0056]

Formula 1

[0057] T C B ≥ 20.563 x exp(T D 0.973 ) + 1 … (1)

[0058] Thus, it is possible to suppress the fluctuation in the saturation current to be less than or equal to 2%. In addition, from Figure 13 , it is understood that if the trench 12 is made deeper, the ratio of T C B approaches 1.

[0059] Figure 14 is a diagram illustrating the configuration of the semiconductor device 100 according to Embodiment 1. As Figure 14 ​​​​As shown, in the present embodiment, as one example, the intersection 18 of the first face 16 and the second face 17 is disposed at a position lower than the base layer 24. Thereby, as shown in FIG. 6, the fluctuation of the saturation current can be suppressed even when the depth of the trench 12 is shallow. In addition, as shown in FIG. 7, the fluctuation of the saturation current can be suppressed even when the intersection 18 is disposed at the same depth as the lower end of the base layer 24. Figure 12 As shown, in the present embodiment, as one example, the intersection 18 of the first face 16 and the second face 17 is disposed at a position lower than the base layer 24. Thereby, as shown in FIG. 6, the fluctuation of the saturation current can be suppressed even when the depth of the trench 12 is shallow. In addition, as shown in FIG. 7, the fluctuation of the saturation current can be suppressed even when the intersection 18 is disposed at the same depth as the lower end of the base layer 24. Figure 13 As shown, in the present embodiment, as one example, the intersection 18 of the first face 16 and the second face 17 is disposed at a position lower than the base layer 24. Thereby, as shown in FIG. 6, the fluctuation of the saturation current can be suppressed even when the depth of the trench 12 is shallow. In addition, as shown in FIG. 7, the fluctuation of the saturation current can be suppressed even when the intersection 18 is disposed at the same depth as the lower end of the base layer 24.

[0060] In addition, the feedback capacitance C res can be expressed by the following equation (2).

[0061]

Equation 2

[0062]

[0063] Here, W T is the width of the trench 12, C OX is the electrostatic capacitance of the gate insulating film 13 provided inside the trench 12, and C M is the electrostatic capacitance of the depletion layer. W T is the width of the portion where the width of the upper face 50a of the substrate 50 in the trench 12 is the widest. In the present embodiment, compared to the U-shaped trench, the feedback capacitance C D can be suppressed by the amount of the term 2(T B ) / tanθ2 in equation (2). Therefore, in the present embodiment, the reduction of the feedback capacitance C res can be achieved. In this way, in the present embodiment, the fluctuation of the saturation current can be suppressed while suppressing the feedback capacitance. res

[0064] In the present embodiment, the example in which the semiconductor device 100 is an IGBT is described, but the semiconductor device 100 can also be a MOSFET.

[0065] In addition, the semiconductor device 100 can also be formed of a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. For the semiconductor device 100 formed of a wide bandgap semiconductor, in the case where a high current flows, according to the present embodiment, the drop in the withstand voltage caused by the fluctuation of the saturation current can also be suppressed. Therefore, the performance of the semiconductor device 100 can be effectively utilized.

[0066] These modifications can be appropriately applied to the semiconductor device and the manufacturing method thereof according to the following embodiments. Furthermore, regarding the semiconductor device and the manufacturing method thereof according to the following embodiments, since there are many commonalities with Embodiment 1, the description is centered on the differences from Embodiment 1.

[0067] ​Embodiment 2

[0068] Figure 15 is a sectional view of a semiconductor device 200 to which Embodiment 2 is applied. The semiconductor device 200 has a carrier storage layer 26 of n-type with a higher concentration than the drift layer 20. The carrier storage layer 26 is provided to a position deeper than the base layer 24 on the side of the upper surface 50a of the drift layer 20. The other structures are the same as those of the semiconductor device 100.

[0069] In this embodiment, holes supplied from the collector layer 22 at the time of energization are accumulated in the carrier storage layer 26. Thereby, the conductivity can be reduced, and the on-resistance can be reduced.

[0070] Embodiment 3

[0071] Figure 16 is a sectional view of a semiconductor device 300 to which Embodiment 3 is applied. The semiconductor device 300 has a bottom layer 28 of p-type provided under the trench 12. The other structures are the same as those of the semiconductor device 100. By the bottom layer 28, concentration of an electric field at the bottom of the trench gate at the time of turning on and off can be suppressed. Therefore, the SOA tolerance can be further improved.

[0072] Embodiment 4

[0073] Figure 17 is a sectional view of a semiconductor device 400 to which Embodiment 4 is applied. In the case of the semiconductor device 400, the emitter electrode 10 has a trench contact 29. The trench contact 29 penetrates the emitter layer 23 from the upper surface 50a of the substrate 50 between a pair of trenches 12 adjacent to each other, and protrudes to the inside of the base layer 24. The contact layer 25 is provided in the inside of the base layer 24 in a manner to contact the bottom of the trench contact 29. The other structures are the same as those of the semiconductor device 100.

[0074] In the case of the semiconductor device 400, the collector current does not flow just under the emitter layer 23 at the time of turning on and off of the IGBT, but flows through the trench contact 29, for example, as indicated by an arrow 80. That is, the collector current flows through the trench contact 29 before reaching just under the emitter layer 23. Thereby, improvement of the latch-up tolerance can be achieved.

[0075] Embodiment 5

[0076] Figure 18is a sectional view of the semiconductor device 500 according to Embodiment 5. In the semiconductor device 500, the gate electrode has the first gate electrode 14a and the second gate electrode 14b provided below the first gate electrode 14a with the gate insulating film 13 interposed therebetween. The first gate electrode 14a is provided at a position higher than the intersection 18, and the second gate electrode 14b is provided at a position lower than the intersection 18. The other structures are the same as those of the semiconductor device 100. By applying the two-layer gate structure, the thickness of the gate insulating film 13 can be ensured, and the feedback capacitance can be reduced.

[0077] Embodiment 6

[0078] Figure 19 is a sectional view of the semiconductor device 600 according to Embodiment 6. The semiconductor device 600 has a plurality of trenches 12. The plurality of trenches 12 includes a pair of trenches 12 adjacent to each other without the base layer 24 and the emitter layer 23 interposed therebetween. The carrier accumulation layer 27 of the p-type is provided between the pair of trenches 12. The other structures are the same as those of the semiconductor device 100.

[0079] In the present embodiment, the unit region 40 is thinned compared to Embodiment 1. According to this structure, the holes supplied from the collector layer 22 at the time of energization can be accumulated in the carrier accumulation layer 27. Thus, the conductivity can be reduced, and the on-resistance can be reduced.

[0080] In the present embodiment, the unit region 40 is thinned compared to Embodiment 1. According to this structure, the holes supplied from the collector layer 22 at the time of energization can be accumulated in the carrier accumulation layer 27. Thus, the conductivity can be reduced, and the on-resistance can be reduced. Figure 19 In the present embodiment, the unit region 40 is thinned compared to Embodiment 1. According to this structure, the holes supplied from the collector layer 22 at the time of energization can be accumulated in the carrier accumulation layer 27. Thus, the conductivity can be reduced, and the on-resistance can be reduced.

[0081] Embodiment 7

[0082] Figure 20 is a sectional view of the semiconductor device 700 according to Embodiment 7. The semiconductor device 700 is an RC (Reverse-Conducting)-IGBT. In the semiconductor device 700, the diode and the IGBT are formed on the same substrate 50. In the diode region, the collector layer 22 is replaced with the cathode layer 32 of the n-type. In addition, the emitter layer 23 and the contact layer 25 are not provided in the diode region. In the semiconductor device 700, the same effects as those of Embodiment 1 can be obtained.

[0083] Furthermore, the technical features described in each of the embodiments can be appropriately combined.

[0084] Explanation of Reference Numerals

[0085] 10 emitter electrode, 11 collector electrode, 12 trench, 12a first trench, 12b second trench, 13 gate insulating film, 14 gate electrode, 14a first gate electrode, 14b second gate electrode, 15 interlayer insulating film, 16 first surface, 17 second surface, 18 intersection, 19 gate pad, 20 drift layer, 21 buffer layer, 22 collector layer, 23 emitter layer, 24 base layer, 25 contact layer, 26 carrier storage layer, 27 carrier accumulation layer, 28 bottom layer, 29 trench contact, 32 cathode layer, 40 cell region, 50 substrate, 50a upper surface, 50b back surface, 55 opening, 56 mask, 100, 101, 102 semiconductor device, 121, 122 trench, 200, 300, 400, 500, 600, 700 semiconductor device.

Claims

1. A semiconductor device, characterized by comprising: Having: a substrate having an upper surface and a back surface opposite to the upper surface; a drift layer of a first conductive type provided on the upper surface side of the substrate; a base layer of a second conductive type different from the first conductive type provided on the upper surface side of the drift layer; an upper semiconductor layer of the first conductive type provided on the upper surface side of the base layer; a first electrode provided on the upper surface of the substrate and electrically connected to the upper semiconductor layer; a second electrode provided on the back surface of the substrate; a trench extending from the upper surface of the substrate through the upper semiconductor layer and the base layer to the drift layer; and a gate electrode provided inside the trench, an inner side surface of the trench has a first surface and a second surface provided at a lower position than the first surface, the second surface is inclined toward the inner side of the trench with respect to the first surface, an intersection of the first surface and the second surface is provided at a lower position than the base layer, [Formula 1] a depth T from the upper surface of the substrate to the intersection C a depth T from the upper surface of the substrate to the lower end of the portion of the base layer adjacent to the trench B and a depth T to the bottom of the trench D satisfies 2. The semiconductor device according to claim 1, characterized in that, in relation to, T D The units are pm. an angle formed by the first surface and the upper surface of the substrate is greater than 89 degrees and less than or equal to 90 degrees, an angle formed by the second surface and the upper surface of the substrate is greater than 86 degrees and less than or equal to 88 degrees.

3. The semiconductor device according to claim 1 or 2, characterized in that, a carrier storage layer of the first conductive type and having a higher concentration than the drift layer is provided at a deeper position than the base layer on the upper surface side of the drift layer.

4. The semiconductor device according to claim 1 or 2, characterized in that, a bottom layer of the second conductive type is provided below the trench.

5. The semiconductor device according to claim 1 or 2, characterized in that, the first electrode has a trench contact that protrudes from the upper surface of the substrate through the upper semiconductor layer to the inside of the base layer between a pair of trenches adjacent to each other.

6. The semiconductor device according to claim 1 or 2, characterized in that, the gate electrode has a first gate electrode and a second gate electrode provided below the first gate electrode with a gate insulating film interposed therebetween, the first gate electrode is provided at a higher position than the intersection, the second gate electrode is provided at a lower position than the intersection.

7. The semiconductor device according to claim 1 or 2, characterized in that, a plurality of trenches are provided, the plurality of trenches include a pair of trenches adjacent to each other without the base layer and the upper semiconductor layer interposed therebetween, a carrier accumulation layer of the second conductive type is provided between the pair of trenches.

8. The semiconductor device according to claim 1 or 2, characterized in that, the semiconductor device is an RC-IGBT.

9. The semiconductor device according to claim 1 or 2, characterized in that, the substrate is formed of a wide bandgap semiconductor.

10. The semiconductor device according to claim 9, characterized in that, the wide bandgap semiconductor is silicon carbide, gallium nitride, or diamond. ​ 11. A method for manufacturing a semiconductor device, characterized by: forming a drift layer of a first conductive type on the upper surface side of a substrate having an upper surface and a back surface on the opposite side from the upper surface, forming a base layer of a second conductive type different from the first conductive type on the upper surface side of the drift layer, forming an upper semiconductor layer of the first conductive type on the upper surface side of the base layer, forming a first trench extending from the upper surface of the substrate to a depth below the base layer by etching, performing etching from the bottom of the first trench by at least one of increasing the pressure of an etching gas compared to when the first trench is formed, lowering the acceleration voltage of ions used for etching compared to when the first trench is formed, or setting conditions under which byproducts generated along with etching are more likely to deposit compared to when the first trench is formed, forming a first electrode electrically connected to the upper semiconductor layer on the upper surface of the substrate, forming a second electrode on the back surface of the substrate, forming a gate electrode inside a trench formed by the first trench and the second trench, the inner side surface of the trench has a first surface and a second surface disposed below the first surface, the second surface is inclined toward the inner side of the trench with respect to the first surface, the intersection of the first surface and the second surface is disposed below the base layer, a depth T from the upper surface of the substrate to the intersection C a depth T from the upper surface of the substrate to the lower end of the portion of the base layer adjacent to the trench B and a depth T to the bottom of the trench D satisfies 【Formula 1】 in relation to, T D The units are pm.

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