Three-dimensional integrated circuit and fabrication thereof

Abstract

The present disclosure relates to three-dimensional integrated circuits and fabrication thereof. An IC structure includes a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Description

Technical Field

[0001] This disclosure generally relates to three-dimensional integrated circuits and their manufacturing. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, namely transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integration density comes from the reduction in the repetition of the smallest feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of this disclosure, an integrated circuit (IC) structure is provided, comprising: a first transistor formed on a substrate; a first interconnect structure above the first transistor; a dielectric layer above the first interconnect structure; a plurality of 2D semiconductor islands on the dielectric layer; and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

[0004] According to one aspect of this disclosure, an IC structure is provided, comprising: an interconnect structure above a substrate and including a conductive via extending vertically above the substrate and a wire extending laterally above the conductive via; a dielectric layer above the interconnect structure; a plurality of 2D semiconductor seeds arranged in rows and columns on the dielectric layer; a plurality of 2D semiconductor films laterally surrounding the plurality of 2D semiconductor seeds; and a plurality of transistors above the plurality of 2D semiconductor films.

[0005] According to one aspect of this disclosure, a method for manufacturing an integrated circuit is provided, comprising: forming a plurality of first transistors on a substrate; forming an interconnect structure on the plurality of first transistors; forming a dielectric layer on the interconnect structure; forming a plurality of 2D semiconductor seeds on the dielectric layer; annealing the plurality of 2D semiconductor seeds; performing an epitaxial process after annealing the plurality of 2D semiconductor seeds to laterally grow a plurality of 2D semiconductor films from the plurality of 2D semiconductor seeds; and forming a plurality of second transistors on the plurality of 2D semiconductor films. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figures 1A-11 Perspective views and cross-sectional views of intermediate stages in the fabrication of 3D integrated circuit (IC) structures according to some embodiments are shown.

[0008] Figures 12A-14 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some embodiments of the present disclosure are shown.

[0009] Figures 15A-17 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some embodiments of the present disclosure are shown.

[0010] Figures 18-22 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some embodiments of the present disclosure are shown.

[0011] Figures 23-25A , Figures 26A-27A and Figure 28 Exemplary perspective views and cross-sectional views of various stages for manufacturing a 3DIC structure according to some embodiments of the present disclosure are shown.

[0012] Figure 25B The use of some embodiments according to this disclosure is illustrated. Figures 23-25A The Raman spectrum of the WS2 seeds formed by the steps.

[0013] Figure 27B The photoluminescence (PL) spectrum of a 2D semiconductor seed according to some embodiments of the present disclosure is shown.

[0014] Figures 29-31A and Figures 32-34 Exemplary cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of the present disclosure are shown.

[0015] Figure 31B The use of some embodiments according to this disclosure is illustrated. Figures 29-31A Raman spectra of WS2 seeds formed by the steps. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) may be used herein to facilitate the description of the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly. As used herein, “approximately,” “about,” “approximately,” or “substantially” generally likely refers to within twenty percent, or ten percent, or five percent of a given value or range. The numerical values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise.

[0018] Semiconductor devices are essentially scaled down in two dimensions (2D) because the volume occupied by integrated components is essentially located on the surface of a semiconductor wafer. Although improvements in photolithography have significantly improved the fabrication of 2D integrated circuits (ICs), there are physical limitations to the density achievable in two dimensions. One of these limitations is the minimum size that allows these components to be manufactured.

[0019] Therefore, this disclosure provides, in various embodiments, one or more semiconductor islands formed on the amorphous surface of an interconnect structure. Semiconductor islands can be used as active regions for transistors, which in turn allows the formation of three-dimensional (3D) ICs having lower-level transistors (e.g., below the interconnect structure) and higher-level transistors (e.g., above the interconnect structure), which in turn facilitates the placement of more transistors in a given area. Furthermore, in various embodiments, this disclosure forms semiconductor islands by first annealing defective 2D semiconductor seeds to substantially defect-free (or low-defect) 2D semiconductor seeds, and then laterally growing 2D semiconductor islands from the substantially defect-free 2D semiconductor seeds, which in turn allows the resulting semiconductor islands to be free of crystal defects or have negligible crystal defects.

[0020] Figures 1A-11 Perspective views and cross-sectional views of intermediate stages in the fabrication of 3D integrated circuit (IC) structures according to some embodiments are shown. It should be understood that... Figures 1A-11 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchanged.

[0021] Figure 1A A perspective view of the intermediate structure of wafer W1 in the IC manufacturing process is shown, and Figure 1B yes Figure 1A A cross-sectional view. In Figure 1A and Figure 1B In this embodiment, semiconductor wafer W1 is an intermediate structure in an IC manufacturing process in which transistors and interconnect structures have already been formed. In some embodiments, semiconductor wafer W1 may include substrate 102. Substrate 102 may include, for example, an active layer of doped or undoped bulk silicon or a semiconductor-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate (e.g., a silicon substrate or a glass substrate). Alternatively, substrate 102 may include another basic semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0022] In some embodiments, one or more active and / or passive devices 104 are formed on the substrate 102. Figure 1B(Seen as a single transistor). One or more active and / or passive devices 104 may include various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc. Those skilled in the art will understand that the examples provided above are for illustrative purposes only and are not intended to limit this disclosure in any way. Other circuits may also be appropriately formed for a given application.

[0023] In some embodiments, an interconnect structure 106 is formed over one or more active and / or passive devices 104 and a substrate 102. The interconnect structure 106 electrically interconnects one or more active and / or passive devices 104 to form functional circuitry within a semiconductor structure 100. The interconnect structure 106 may include one or more metallization layers 1081 to 1082. M M is one or more metallization layers 1081 to 108 M The number of metallization layers 1081 to 1081. In some embodiments, the value of M may vary according to the design specifications of the semiconductor structure 100. Hereinafter, one or more metallization layers 1081 to 1081... M These can also be collectively referred to as one or more metallization layers 108. Metallization layers 1081 to 108 M Each includes dielectric layers 1101 to 110. M and dielectric layer 1111 to 111 M Dielectric layer 1111 to 111 M Formed in the corresponding dielectric layers 1101 to 110 M Above. Metallization layers 1081 to 108 M Includes one or more horizontal interconnects, for example, on dielectric layers 1111 to 111 respectively. M Medium horizontal or lateral extension of conductors 1141 to 114 M ; and vertical interconnects, for example, in dielectric layers 1101 to 110 respectively. M Vertically extending conductive vias 1161 to 116 M The formation of the interconnect structure 106 can be referred to as the back-end process (BEOL) process.

[0024] Contact plug 1120 electrically couples the overlying interconnect structure 106 to the underlying device 104. In the depicted embodiment, device 104 is a fin field-effect transistor (FinFET), which is a three-dimensional MOSFET structure formed in fin-shaped strips 103 of semiconductor protrusions referred to as fins. Figure 1B The cross-section shown is in the source / drain region 104 SDThe direction parallel to the current flow direction is cut along the longitudinal axis of the fin. The fin 103 can be formed by patterning the substrate 102 using photolithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed on the substrate using suitable photolithography and etching processes, and the sacrificial layer is patterned to form a mandrel. The spacers are formed along the mandrel using a self-aligned process. The sacrificial layer is then removed by a suitable selective etching process. Each remaining spacer can then be used as a hard mask to pattern the corresponding fin 103 by etching trenches into the substrate 102 using, for example, reactive ion etching (RIE). Figure 1A and Figure 1B A single fin 103 is shown, but the substrate 102 may include any number of fins. In some other embodiments, the device 104 is a planar transistor or a gate-all-around (GAA) transistor.

[0025] Shallow groove isolation (STI) regions 105 formed on the opposite sidewalls of fin 103 Figure 1B As shown in the diagram, the STI region 105 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin, and then recessing the top surface of the dielectric material. The dielectric material of the STI region 105 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), subatmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin, etc., or combinations thereof. After deposition, an annealing process or a curing process can be performed. In some cases, the STI region 105 may include a liner, for example, a thermal oxide liner grown through a silicon oxide surface. The recessing process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)), followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof) that can recess the top surface of the dielectric material in the STI region 105 so that the upper part of the fin 103 protrudes relative to the surrounding insulating STI region 105. In some cases, the patterned hard mask used to form fin 103 can also be removed by a planarization process.

[0026] In some embodiments, Figure 1B The gate structure 104 of the FinFET device 104 shown GThis is a high-k metal gate (HKMG) gate structure, which can be formed using a post-gate process. In the post-gate process, a sacrificial dummy gate structure (not shown) is formed after the STI region 105 is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, etc.) can be deposited on the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) can be formed on the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fins and extend between the fins above the surface of the STI region 105. As described in more detail below, the dummy gate structure can be an HKMG gate structure 104. G Replacement, such as Figure 1B As shown in the figure. The material used to form the dummy gate structure and hard mask can be deposited using any suitable method (e.g., CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), etc.), or by thermal oxidation of the semiconductor surface, or a combination thereof.

[0027] exist Figure 1B In, for example, the source / drain regions 104 of transistor 104 are formed in self-alignment with the dummy gate structure. SD and spacer 104 SP The spacer 104 can be formed by deposition and anisotropic etching of the spacer dielectric layer performed after the dummy gate patterning is completed. SP The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof. An anisotropic etching process removes the spacer dielectric layer from above the dummy gate structure, leaving spacer 104. SP It extends laterally along the sidewall of the dummy gate structure to a portion of the surface of fin 103.

[0028] Source / drain region 104 SD This is the semiconductor region that is in direct contact with the semiconductor fin 103. In some embodiments, the source / drain region 104 SD This can include heavily doped regions and relatively lightly doped drain extension regions, or LDD regions. Typically, heavily doped regions use spacers 104. SP Separated from the dummy gate structure, the LDD region can be formed in spacer 104. SPPreviously formed, and therefore in spacer 104 SP The LDD region extends downwards, and in some embodiments, further extends into the portion of the semiconductor fin 103 located below the dummy gate structure. The LDD region can be formed, for example, by implanting dopants (e.g., As, P, B, In, etc.) using an ion implantation process.

[0029] Source / drain region 104 SD This may include epitaxially grown regions. For example, after forming the LDD region, spacer 104 may be formed. SP And subsequently, it can be formed with spacer 104 in the following manner. SP Self-aligned heavily doped source and drain regions: First, the fin is etched to form a recess, then a crystalline semiconductor material is deposited in the recess using a selective epitaxial growth (SEG) process (which can fill the recess). The heavily doped source and drain regions can further extend beyond the original surface of the fin 103 to form a raised source / drain epitaxial structure. The crystalline semiconductor material can be an element (e.g., Si or Ge) or an alloy (e.g., Si...). 1-x C x or Si 1-x Ge x (etc.). SEG processes can utilize any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE), metal-organic CVD (MOCVD), or molecular beam epitaxy (MBE), etc. High doses (e.g., from approximately 10...) 14 cm -2 Up to 10 16 cm -2 The dopants can be introduced into the heavily doped source and drain regions in situ during SEG or by an ion implantation process performed after SEG, or a combination thereof. SD middle.

[0030] Once the source / drain region is formed, 104 SD In the source / drain region 104 SD A first ILD layer (e.g., the lower portion of ILD layer 1100) is deposited on top. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or combinations thereof) may be deposited prior to depositing the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard mask material from above the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first ILD layer. Figure 1B The HKMG gate structure 104 shown GThe dummy gate structure can then be removed by first using one or more etching techniques, thereby creating the corresponding spacer 104. SP The recesses are formed between the elements. Next, a replacement gate dielectric layer 104 comprising one or more dielectrics is deposited. GD Next, a replacement gate metal layer 104 comprising one or more metals is deposited. GM To completely fill the recess. The gate structure layer 104 can be removed from the top surface of the first ILD using, for example, a CMP process. GD and 104 GM The redundant part. For example... Figure 1B As shown, the resulting structure may include the spacer 104 embedded in the spacer. SP HKMG gate layer 104 GD and 104 GM The remaining part.

[0031] Gate dielectric layer 104 GD This includes, for example, high-k dielectric materials, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, etc., combinations thereof, or multiple layers thereof. In some embodiments, the gate metal layer 104 GM It can be a multilayer metal gate stack, including those sequentially formed on the gate dielectric layer 104 GD The gate structure consists of a barrier layer, a work function layer, and a gate fill layer on top. Example materials for the barrier layer include TiN, TaN, Ti, Ta, etc., or multiple combinations thereof. For p-type FETs, the work function layer may include TiN, TaN, Ru, Mo, Al, and for n-type FETs, the work function layer may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr. Other suitable work function materials, or combinations thereof, or multiple layers thereof, may be used. The gate fill layer, filling the remaining portion of the recess, may include metals such as Cu, Al, W, Co, Ru, etc., or combinations thereof, or multiple layers thereof. The materials used in forming the gate structure can be deposited using any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), chemical plating, etc.

[0032] In the formation of HKMG structure 104 G Subsequently, a second ILD layer is deposited on top of the first ILD layer, and the combination of these ILD layers is referred to as ILD layer 1100, as shown below. Figure 1BAs shown. In some embodiments, the insulating material used to form the first ILD layer and the second ILD layer may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low dielectric constant (low k) dielectric, such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), a flowable oxide, or a porous oxide (e.g., a dry gel / aerogel), or combinations thereof. The dielectric material used to form the first ILD layer and the second ILD layer can be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof.

[0033] like Figure 1B As shown, the electrodes of the electronic devices formed in the substrate 102 can be electrically connected to wires 1141 to 114 using contacts 1120 formed through the intermediate dielectric layer. M and conductive vias 1161 to 116 M .exist Figure 1B In the example shown, contact 1120 is connected to the gate structure 104 of FinFET 104. G and source / drain region 104 SD Electrical connection. Contact 1120 can be formed using photolithography, etching, and deposition techniques.

[0034] For example, a patterned mask can be formed on the ILD layer 1100 and used to etch openings extending through the ILD layer 1100 to expose the gate structure 104. G and source / drain region 104 SD Subsequently, a conductive liner can be formed in the openings in the ILD layer 1100. The openings are then filled with a conductive filler material. The liner includes a barrier metal to reduce the diffusion of conductive material from the contact 1120 outwards into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal is connected to the source / drain region 104. SD The semiconductor material in the middle contacts, and can then contact the source / drain region 104. SD In this process, heavily doped semiconductors undergo chemical reactions to form low-resistance ohmic contacts, after which unreacted metal may be removed. For example, if the source / drain region is 104... SD If the heavily doped semiconductor is silicon or a silicon-germanium alloy semiconductor, then the first blocking metal may include Ti, Ni, Pt, Co, other suitable metals or their alloys, and may be associated with the source / drain region 104. SDA silicide is formed. The second barrier metal layer of the conductive liner may additionally include other metals (e.g., TiN, TaN, Ta, or other suitable metals, or alloys thereof). A conductive filler material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, or combinations thereof) can be deposited on the conductive liner layer to fill the contact openings using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination thereof)). Next, all excess conductive material can be removed from the surface of the ILD 1100 using a planarization process (e.g., CMP). The resulting conductive plug extends into the ILD layer 1100 and forms a contact 1120 that contacts electronic devices (e.g., Figure 1B The electrodes of the tri-gate FinFET 104 shown are physically and electrically connected.

[0035] After the contact 1120 is formed, according to the back-end process (BEOL) scheme used in the integrated circuit design, an interconnect structure 106 including multiple interconnect layers can be formed, which is vertically stacked on the contact plug 1120 formed in the ILD layer 1100. Figure 1B In the illustrated BEOL scheme, the various interconnect layers have similar characteristics. However, it should be understood that other embodiments may utilize alternative integration schemes in which the various interconnect layers can use different features. For example, the source / drain contact 1120 shown as a vertical connector can extend to form a conductor for lateral current transmission.

[0036] Multiple interconnect layers include, for example, those formed on the corresponding IMD layers 1101 to 110 using any suitable method (e.g., single damascene process, dual damascene process, etc.). M and 1111 to 111 M Wires 1141 to 114 M and conductive vias 1161 to 116 M In some embodiments, IMD layers 1101 to 110 M and 1111 to 111 M This may include a low-k dielectric material having a k value, for example, below about 4.0 or even 2.0, disposed between such conductive features. In some embodiments, the IMD layer may be made of, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, combinations thereof, etc., formed by any suitable method (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc.). Conductors 1141 to 114 M and conductive vias 1161 to 116M Conductive materials such as copper, aluminum, tungsten, or combinations thereof may be included. In some embodiments, wires 1141 to 114... M and conductive vias 1161 to 116 M It may further include one or more barrier / adhesive layers (not shown) to protect the respective IMD layers 1101 to 110. M and 1111 to 111 M It is protected from metal diffusion (e.g., copper diffusion) and metal poisoning. One or more barrier / adhesive layers may include titanium, titanium nitride, tantalum, tantalum nitride, etc., and can be formed using physical vapor deposition (PVD), CVD, ALD, etc.

[0037] Using methods such as PVD, CVD, ALD, etc., in the metallization layer 108 of the interconnect structure 106 M An additional ILD layer 120 is formed on top of this. The ILD layer 120 serves as a substrate supporting the 2D semiconductor material, which will be discussed in more detail below. Therefore, the ILD layer 120 acts in conjunction with the underlying IMD layers 1101 to 1102. M and 1111 to 111 M And it has a different function from ILD layer 1100, and therefore can have a different function from IMD layers 1101 to 110. M and 1111 to 111 M And different thicknesses and / or materials for ILD layer 1100. For example, ILD layer 120 can be different from IMD layer 1101 to 110. M and 1111 to 111 M And one or more of the ILD layers 1100 may be thinner or thicker. Alternatively, the ILD layer 120 may have the same thickness as the IMD layers 1101 to 110. M and 1111 to 111 M And one or more of the same thickness and / or material in ILD layer 1100.

[0038] In some embodiments, the ILD layer 120 may comprise a low-k dielectric material having a k value, for example, less than about 4.0 or even 2.0. For example, the ILD layer 120 may be made of, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, combinations thereof, etc., and formed by any suitable method (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc.).

[0039] Figure 2AA perspective view of an intermediate stage in the formation of a 2D semiconductor layer 202 according to some embodiments of the present disclosure is shown. 2D semiconductor materials are typically only a few layers thick and exist as a stack of strongly bonded layers with weak interlayer van der Waals attraction, allowing these layers to be mechanically or chemically peeled off into individual atomic thin layers. 2D semiconductor materials are promising candidates for channel, source, and drain materials of transistors. Examples of 2D semiconductor materials include transition metal dichalcogenides (TMD), graphene, layered III-VI chalcogenides, hexagonal boron nitride (h-BN), black phosphorus, etc. In some embodiments, the 2D semiconductor may comprise one or more layers and may have a thickness in the range of about 0.5-100 nm. An advantageous feature of 2D semiconductors with fewer layers is a high electron mobility value, which is about 50-1000 cm⁻¹. 2 / V-sec or even higher. It is understandable that when bulk silicon is cut to a low thickness (e.g., about 2nm) comparable to the thickness of a 2D material film, its mobility may drop sharply.

[0040] exist Figure 2A In this embodiment, a 2D semiconductor layer 202 is grown on a crystal substrate 200 for crystal orientation control. In some embodiments, the crystal substrate 200 may include an active layer, such as a doped or undoped bulk silicon or semiconductor-on-insulator (SOI) substrate. In some embodiments, the crystal substrate 200 may include a sapphire substrate. The sapphire substrate 200 may be a c-plane sapphire substrate (sometimes referred to as c-sapphire). According to alternative embodiments, substrates having other planes (e.g., M-plane, R-plane, or A-plane) may be employed. The substrate 200 may be in the form of a wafer and may have a circular top-view shape or a rectangular top-view shape. The diameter of the substrate 200 may be 3 inches, 12 inches, or larger. In some embodiments, the crystal substrate 200 is a single-crystal substrate, such that the resulting 2D semiconductor layer 202 may be a single-crystal structure having a controlled crystal orientation attributable to the crystal substrate 200.

[0041] In some embodiments, the 2D semiconductor layer 202 is a transition metal dichalcogenide (TMD) material having the chemical formula MX2, where M is a transition metal element, such as titanium, vanadium, cobalt, nickel, zirconium, molybdenum, technetium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, platinum, and X is a chalcogenide element, such as sulfur, selenium, or tellurium. Examples of dichalcogenide materials suitable for the 2D semiconductor layer 202 include MoS2, WS2, WSe2, MoSe2, MoTe2, WTe2, and combinations thereof. However, any suitable transition metal dichalcogenide material may be used alternatively. Once formed, the transition metal dichalcogenide material is in a layered structure of multiple two-dimensional layers of the general form XMX, wherein the chalcogenide atoms are in two planes separated by the planes of the metal atoms.

[0042] The 2D semiconductor layer 202 can be a single layer or can include several single layers. Figure 2B A schematic diagram of a single layer 204 of an example TMD according to some example embodiments is shown. Figure 2B In this process, a one-molecule-thick TMD material layer comprises transition metal atoms 204M and chalcogenide atoms 204X. The transition metal atoms 204M can form a layer in the middle region of the one-molecule-thick TMD material layer, and the chalcogenide atoms 204X can form a first layer above the layer of transition metal atoms 204M, and a second layer below the layer of transition metal atoms 204M. The transition metal atoms 204M can be W atoms or Mo atoms, while the chalcogenide atoms 204X can be S atoms, Se atoms, or Te atoms. Figure 2B In the example, each transition metal atom 204M (e.g., via covalent bonds) is bonded to six chalcogenide atoms 204X, and each chalcogenide atom 204X (e.g., via covalent bonds) is bonded to three transition metal atoms 204M. Throughout the description, the cross-bonded layer shown, comprising a combination of one layer of transition metal atoms 204M and two layers of chalcogenide atoms 204X, is referred to as a monolayer 204 of TMD.

[0043] In some embodiments, a 2D semiconductor layer 202 is grown on a crystal substrate 200 using a suitable deposition technique. For example, in some embodiments where the 2D semiconductor layer 202 is a TMD, the TMD layer 202 can be formed using CVD, where MoO3 and a sulfur-containing gas (e.g., sulfur vapor or H2S) are used as process gases and N2 is used as a carrier gas. According to some exemplary embodiments, the formation temperature can be between about 600°C and about 700°C, and higher or lower temperatures can be used. Process conditions are controlled to achieve the desired total number of monolayers 204. According to alternative embodiments, plasma-enhanced CVD or other suitable methods are used. In some embodiments, growing the 2D semiconductor layer 202 on the substrate 200 may include crystal defects such as vacancy defects, interstitial defects, and / or other defects, and therefore, in some embodiments of this disclosure, the 2D semiconductor layer 202 may be referred to as a defective 2D semiconductor layer. Although the defective 2D semiconductor layer 202 includes crystal defects, it still includes a desired or controlled crystal orientation depending on the crystal orientation of the underlying crystal substrate 200. In some embodiments, the defective 2D semiconductor layer 202 may be grown in the form of a defective 2D semiconductor wafer or a continuous defective 2D semiconductor film.

[0044] The defective 2D semiconductor layer 202 is then transferred onto the ILD layer 120 of wafer W1 and used to form transistors. Figure 2A Preparations for transferring a defective 2D semiconductor layer 202 onto the ILD layer 120 of wafer W1 are also shown. Figure 2A In this process, a protective film 206 is formed on the defective 2D semiconductor layer 202. The protective film 206 functions to protect the defective 2D semiconductor layer 202 from damage during the transfer process. In some embodiments, the protective film 206 comprises a photoresist material such as polymethyl methacrylate (PMMA) or other suitable material, which is in a flowable form and is applied to the defective 2D semiconductor layer 202, for example, using spin coating. The applied protective film 206 is cured and solidified. According to alternative embodiments, other types of flowable and curable materials or dry films that can provide protection may also be used. A heat-release tape 208 is then applied over the PMMA film 206. The heat-release tape 208 may be formed from a material that may lose its adhesiveness under thermal or other conditions (e.g., radiation).

[0045] After the defective 2D semiconductor layer 202 is covered by the protective film 206 and the heat-release tape 208, the defective 2D semiconductor layer 202 is mechanically or chemically peeled off from the underlying crystal substrate 200. Then, as... Figures 3A-3BAs shown, the defective 2D semiconductor layer 202, the overlying protective film 206, and the heat-release tape 208 are transferred onto the ILD layer 120 of wafer W1. Next, the heat-release tape 208 and the protective layer 206 are removed from the defective 2D semiconductor layer 202. According to some embodiments of this disclosure, the heat-release tape 208 is removed by, for example, baking at a temperature in the range of about 120°C to about 250°C. Figure 3B The structure shown causes the heat-release tape 208 to lose its stickiness, and therefore it can be removed from the protective layer 206. Baking can be achieved by applying a heat-release tape 208 to the protective layer 206. Figure 3B The structure shown is placed on a hot plate (not shown) for this process. Next, the protective film 206 is removed, for example, by etching or dissolution. According to some embodiments where the protective film 206 is formed of a photoresist material (e.g., PMMA), the protective film 206 is removed by immersing the structure in hot acetone for a period of time, for example, between about 20 minutes and about 70 minutes. The temperature of the hot acetone can be in the range between about 35°C and about 90°C.

[0046] After removing the protective film 206, the defective 2D semiconductor layer 202 remains on the ILD layer 120. It should be understood that the defective 2D semiconductor layer 202 is a single-crystal film, regardless of the material and lattice structure of the underlying material, such as the amorphous material of the ILD layer 120 (e.g., silicon oxide or silicon nitride). This is superior to growing a 2D material on the amorphous material of the ILD layer 120, as growing a single-crystal 2D semiconductor film from an amorphous material is challenging.

[0047] exist Figures 4A-4B In this process, a defective 2D semiconductor layer 202 is patterned into a plurality of defective 2D semiconductor seeds 210 using appropriate photolithography and etching techniques. In some embodiments, the defective 2D semiconductor seeds 210 are arranged substantially equidistantly in rows and columns when viewed from a top view, and each seed 210 has a diameter of less than about 0.05 μm. 3 Small volume (e.g., with 10 μm) 2 (Surface area and thickness of 0.005 μm). For example, a mask layer is first formed on the defective 2D semiconductor layer 202, then patterned to form a pattern of seed 210, and then an etching process is performed on the defective 2D semiconductor layer 202 by using the patterned mask layer as an etching mask, thereby patterning the defective 2D semiconductor layer 202 into a defective 2D semiconductor seed 210.

[0048] In some embodiments, the patterned mask layer for forming the defective 2D semiconductor seed 210 may comprise an organic material, such as a photoresist material, and the photoresist material may be formed using a spin coating process, and then patterned to have the pattern of the seed 210 using a suitable photolithography technique. For example, the photoresist material may be irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam provided by a radiation source such as an ultraviolet (UV) source, a deep UV (DUV) source, an extreme UV (EUV) source, and an X-ray source. For example, the radiation source could be a mercury lamp with a wavelength of about 436 nm (G-line) or about 365 nm (I-line); a krypton fluoride (KrF) excimer laser with a wavelength of about 248 nm; an argon fluoride (ArF) excimer laser with a wavelength of about 193 nm; a fluoride (F2) excimer laser with a wavelength of about 157 nm; or other light sources with a suitable wavelength (e.g., below about 100 nm). In another example, the light source is an EUV source with a wavelength of about 13.5 nm or less.

[0049] Once a patterned mask is formed on the defective 2D semiconductor layer 202, the defective 2D semiconductor layer 202 is patterned into a defective 2D semiconductor seed 210 by using the patterned mask as an etching mask. The patterning process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic, thus allowing the defective 2D semiconductor seed 210 to have substantially straight sidewalls. Although Figure 4B The defective 2D semiconductor seed 210 shown has vertical sidewalls, but according to some other embodiments, the etching process may produce tapered sidewalls, as shown by the dashed line DL1.

[0050] exist Figures 5A-5B In the process, prior to subsequent lateral growth from the 2D semiconductor seed, a dielectric mesh 212 is formed on the ILD layer 120 of wafer W1 (e.g., as shown in the figure). Figures 7A-7B(As shown). The dielectric grid 212 is located at the desired grain boundary to be formed in the subsequent lateral epitaxial growth process, which in turn prevents the formation of grain boundaries in the subsequent lateral epitaxial growth. In other words, the pattern of the dielectric grid 212 and the pattern of the 2D semiconductor seed 210 are co-designed and coordinated. Furthermore, the pattern of the dielectric grid 212 and the subsequently formed IC device (e.g., transistor) are also co-designed and coordinated. The dielectric grid 212 has grid cells 212o corresponding to defective 2D semiconductor seeds 210 in a one-to-one manner. In some embodiments, the center of the defective 2D semiconductor seed 210 is substantially aligned with the center of the grid cell 212o. In some embodiments, the dielectric grid 212 includes a plurality of first grid lines 2122 extending along a first direction D1 and a plurality of second grid lines 2124 extending along a second direction D2 perpendicular to the first direction D1 and intersecting the plurality of first grid lines 2122. Each grid cell 210o is defined by two corresponding first grid lines 2122 and two corresponding second grid lines 2124, and thus has a rectangular or square top view profile. In some embodiments, the defective 2D semiconductor seed 210 has a circular or elliptical top view profile, and thus has a different top view profile from the grid cell 210o.

[0051] In some embodiments, the dielectric grid 212 may include a suitable dielectric material, such as a low-k dielectric material having a k value of, for example, less than about 4.0 or even 2.0. For example, the ILD layer 120 may be made of, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, combinations thereof, etc. The dielectric grid 212 is formed, for example, by depositing a dielectric layer on a defective 2D semiconductor seed 210, and then patterning the dielectric layer into a dielectric grid using suitable photolithography and etching techniques.

[0052] exist Figures 6A-6B In this process, an annealing process AL1 is performed to transform the defective 2D semiconductor seed 210 into a substantially defect-free (or less defective) 2D semiconductor seed 214. For example, performing the annealing process AL1 causes crystal defects (e.g., vacancies and / or gaps) in each 2D semiconductor seed to diffuse to the edge of the 2D semiconductor seed and disappear, thereby reducing the number of crystal defects in each 2D semiconductor seed to below a threshold suitable for transistor channels, sources, and / or drains. Since 2D semiconductor materials have no dangling bonds and therefore have no or negligible bonding with the amorphous material beneath the ILD layer 120, crystal defects in 2D semiconductor materials diffuse more easily than in 3D semiconductor materials (e.g., silicon, silicon germanium, etc.). Furthermore, because of the presence of a blanket 2D semiconductor layer 202 (such as... Figure 3B Compared to the example shown, the 2D semiconductor seed has a smaller size, so it is easier to diffuse crystal defects to the edge of the 2D semiconductor seed 210 than to diffuse crystal defects to the edge of the 2D semiconductor layer 202.

[0053] In some embodiments, depending on the annealing ambient gas, the annealing process AL1 is performed at a temperature ranging from about 400 degrees Celsius to about 1000 degrees Celsius. In some embodiments, because the annealing process AL1 is performed on small 2D semiconductor seeds, it can be performed at a temperature ranging from about 300 degrees Celsius to about 600 degrees Celsius to prevent seed size shrinkage. If the annealing temperature is too high (e.g., above about 1000 degrees Celsius), the excessive temperature may cause the 2D semiconductor material to melt or vaporize, or cause a chemical reaction with the process gas, resulting in an increase in defects in the 2D semiconductor seed. If the annealing temperature is too low (e.g., below about 300 degrees Celsius), the excessive temperature may provide insufficient crystallization activation energy, or may lead to unwanted deposition phenomena. In some specific embodiments, the annealing process AL1 for forming defect-free 2D semiconductor seeds 214 is performed at a temperature of about 500 degrees Celsius to about 600 degrees Celsius for a duration of about 1 minute to about 90 minutes, and H2S or H2Se is used as the ambient gas.

[0054] In the depicted embodiment, annealing process AL1 is performed after the formation of the dielectric mesh 212, which in turn prevents the defect-free 2D semiconductor seed 214 from being affected by any potential damage that may be caused by the deposition and etching processes that form the dielectric mesh 212. However, in some other embodiments, annealing process AL1 may be performed before the formation of the dielectric mesh 212. In that case, the defect-free 2D semiconductor seed 214 is formed before the formation of the dielectric mesh 212.

[0055] exist Figures 7A-7BIn this process, an epitaxial growth process EPI1 is performed using a defect-free 2D semiconductor seed 214 as a seed to laterally grow a 2D semiconductor film 216, such that the 2D semiconductor film 216 laterally surrounds the defect-free 2D semiconductor seed 214. The 2D semiconductor film 216 has a larger surface area (e.g., top surface area) than the defect-free 2D semiconductor seed 214, and a substantially the same thickness as the defect-free 2D semiconductor seed 214. The defect-free 2D semiconductor seed 214 and the corresponding 2D semiconductor film 216 laterally grown from the defect-free 2D semiconductor seed 214 can be collectively referred to as 2D semiconductor islands 218, which are confined within grid cells in a dielectric grid 212. The 2D semiconductor islands 218 are arranged substantially equidistantly in rows and columns when viewed from a top view. Since 2D semiconductor materials have no or negligible dangling bonds on their top surface, the epitaxial growth process EPI1 has no or negligible vertical growth rate, which in turn produces a 2D semiconductor film 216 with a substantially flat top surface and no angled facets.

[0056] In some embodiments, the 2D semiconductor film 216 comprises transition metal dichalcogenides (TMDs), graphene, layered III-VI chalcogenides, hexagonal boron nitride (h-BN), black phosphorus, etc. In some embodiments, the 2D semiconductor film 216 has the same 2D material as the defect-free 2D semiconductor seed 214 or other 2D materials with a lattice constant similar to that of the seed 214. For example, because MoS2, WS2, WSe2, and MoSe2 have comparable lattice parameters (e.g., in the range from about 0.30 nm to about 0.35 nm), when the defect-free 2D semiconductor seed 214 is formed of MoS2, WS2, WSe2, or MoSe2, the 2D semiconductor film 216 is also formed of MoS2, WS2, WSe2, or MoSe2. In that case, each of the 2D semiconductor films 216 can be a monolayer 204 of one or more TMDs, including, for example... Figure 2B The transition metal atoms 204M and chalcogenide atoms 204X are shown. In some embodiments, a 2D semiconductor film 216 is epitaxially grown using deposition methods such as CVD, low-pressure CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), etc.

[0057] In the epitaxial growth EPI1, the 2D semiconductor material from the 2D semiconductor seed 214 has a higher growth rate than the 2D semiconductor material from the dielectric grid 212. More specifically, the dielectric grid 212 is formed of a dielectric material (e.g., silicon nitride) such that the 2D semiconductor material from the dielectric grid 212 has no growth rate or a negligible growth rate. In this way, growth selectively allows the 2D semiconductor film 216 to be grown only from the defect-free 2D semiconductor seed 214. In some embodiments, because the defect-free 2D semiconductor seed 214 is a defect-free single-crystal seed, the 2D semiconductor film 216 grown from the seed 214 is a defect-free single-crystal film. If the dielectric grid 212 is omitted, as the epitaxial growth EPI1 continues, the 2D semiconductor films 216 grown from different seeds 214 may eventually meet to form grain boundaries, which may be unsuitable for use as transistor channels, source and / or drain regions. However, since the dielectric mesh 212 has been formed on the expected grain boundary before the epitaxial growth process EPI1, the dielectric mesh 212 can prevent 2D semiconductor films 216 grown from different seeds 214 from meeting and forming grain boundaries.

[0058] exist Figure 8 Once the 2D semiconductor island 218 is formed, the dummy gate structure 160 and the gate spacer 170 are formed. SP and source / drain region 170 SD In some embodiments, the dummy gate structure 160 may include a dummy gate dielectric 160. GD 160 dummy gate material GP and hard mask 160 HM First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, etc.) can be deposited on the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) can be formed on the dummy gate material and patterned as a hard mask. HM Then, by using a hard mask 160... HM The dummy gate structure 160 is formed by patterning the dummy gate dielectric and dummy gate material as an etching mask. The material used to form the dummy gate structure 160 can be deposited using any suitable method such as CVD, PECVD, ALD, PEALD, etc., or by thermal oxidation of the semiconductor surface, or a combination thereof. The resulting dummy gate structure 160 can extend across one or more 2D semiconductor islands 218.

[0059] Figure 8 The source / drain region shown is 170. SD and spacer 170SP Formed, for example, as a self-aligned dummy gate structure 160. Spacer 170 SP The spacer dielectric layer can be formed by performing deposition and anisotropic etching after the dummy gate patterning is completed. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof. The anisotropic etching process removes the spacer dielectric layer from the top of the dummy gate structure, leaving spacer 170 extending laterally along the sidewalls of the dummy gate structure 160 to the surface of the 2D semiconductor island 218. SP .

[0060] Source / drain region 170 SD It is a doped semiconductor region in the 2D semiconductor island 218. In some embodiments, the source / drain region 170 SD This can include heavily doped regions and relatively lightly doped drain extension regions, or LDD regions. Typically, heavily doped regions use spacers of 170°. SP The LDD region is spaced apart from the dummy gate structure 160, while the LDD region can be formed with spacers 170. SP Previously formed, and therefore in spacer 170 SP Extending downwards, and in some embodiments further extending into the portion of the 2D semiconductor island 218 located below the dummy gate structure 160. For example, these doped regions can be formed by implanting n-type or p-type dopants (e.g., As, p, B, In, etc.) into the source / drain regions of the 2D semiconductor island 218 (excluding the channel region of the 2D semiconductor island 218 located directly below the dummy gate structure 160) using an ion implantation process; or by first depositing a doped source layer over the source / drain regions of the 2D semiconductor island 218, and then annealing to allow the dopant to diffuse from the doped source layer into the 2D semiconductor island 218.

[0061] exist Figure 9 In the process, an additional ILD layer 182 is formed on wafer W1. Once the source / drain regions 170 are formed... SD ILD layer 182 was deposited in the source / drain region 170. SD Above. A planarization process (e.g., CMP) can be performed to remove the dummy gate material 160 GP Remove excess ILD material and hard mask 160 above HM A top surface is formed, wherein the top surface of the dummy gate material is exposed and can be substantially coplanar with the top surface of the ILD layer 182. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or a combination thereof) may be deposited prior to the deposition of the ILD material.

[0062] The dummy gate structure 160 can then be removed by first using one or more etching techniques, thereby creating a spacer 170. SP To form a concave space Figure 10 The HKMG gate structure 170 shown G Next, a replacement gate dielectric layer 170 comprising one or more dielectrics is deposited. GD Next, a replacement gate metal layer 170 comprising one or more metals is deposited. GM To completely fill the recess. A process such as CMP can be used to remove the gate structure layer 170 from the top surface of the ILD layer 182. GD and 170 GM The excess portion. The resulting HKMG gate structure 170 G It may include being embedded in the corresponding spacer 170 SP HKMG gate layer 170 GD and 170 GM The remaining part.

[0063] Gate dielectric layer 170 GD Including the gate dielectric layer 104 in the transistor 104 located below the interconnect structure 106 GD Similar materials. For example, gate dielectric layer 170 GD This includes high-k dielectric materials, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, etc., or combinations thereof, or multiples thereof. In some embodiments, the gate metal layer 170 GM Including the gate metal layer 104 in the transistor 104 located below the interconnect structure 106 GM Similar materials. For example, gate metal layer 104. GM It may include continuous formation on the gate dielectric layer 170 GD The gate structure consists of a barrier layer, a work function layer, and a gate fill layer on top. Example materials for the barrier layer include TiN, TaN, Ti, Ta, etc., or multiple combinations thereof. For p-type FETs, the work function layer may include TiN, TaN, Ru, Mo, Al, and for n-type FETs, the work function layer may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr. The gate fill layer, filling the remaining portion of the recess, may include metals such as Cu, Al, W, Co, Ru, etc., or combinations thereof, or multiples thereof. The material used to form the gate structure can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, ECP, chemical plating, etc.

[0064] In the formation of HKMG structure 170 G Subsequently, another ILD layer 184 is deposited on top of ILD layer 182. In some embodiments, the materials of ILD layers 182 and 184 may be the same as those of ILD layer 1100 and IMD layers 1101 to 110. M and 1111 to 111 M The materials used in one or more of the ILD layers are similar and will therefore not be repeated for the sake of brevity. The dielectric materials used to form the ILD layers 182 and 184 can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. Once the ILD layer 184 is formed, contacts 186 are formed in the ILD layers 182 and 184 to form a gate structure 170 resting on the 2D semiconductor island 218. G The source / drain regions 170 in the 2D semiconductor island 218 SD Above. Contact 186 is formed using photolithography, etching and deposition techniques, as previously discussed with respect to contact 1120, and has a similar material to contact 1120, and therefore the manufacturing steps and materials of contact 186 will not be repeated for the sake of brevity.

[0065] exist Figure 11 In this process, after forming the contact 186, another interconnect structure 190 is formed on the ILD layer 184 using a similar process and materials as previously discussed with respect to the interconnect structure 106. For example, the interconnect structure 190 electrically interconnects one or more transistors 170 formed on a 2D semiconductor island 218, and may further interconnect one or more transistors formed on the substrate 102 by using, for example, one or more deep vias extending from the upper interconnect structure 190 to the lower interconnect structure 106 through the dielectric mesh 212 and / or the 2D semiconductor island 218. The interconnect structure 190 may include one or more metallization layers 192, each metallization layer 192 including a dielectric layer 194, horizontal interconnects 196 (e.g., metal lines) and vertical interconnects 198 (e.g., metal vias) extending in the dielectric layer 194, respectively.

[0066] HKMG structure 170 G Located in HKMG structure 170 G Source / drain regions on opposite sides 170 SDTogether with the portion below the 2D semiconductor island 218, they serve as transistors 170 formed on the 2D semiconductor island 218. The transistors 170 located above the interconnect structure 106 and the transistors 104 located below the interconnect structure 106 can form an integrated circuit (IC). Because an IC includes transistors at different levels (e.g., transistor 170 at a higher level than transistor 104), it can be referred to as a three-dimensional (3D) IC structure. Although in Figure 11 In the illustrated embodiment, transistor 170 is a planar transistor formed on 2D semiconductor island 218, but in some other embodiments, transistor 170 may be a non-planar transistor, such as a FinFET or GAA transistor formed on 2D semiconductor island 218.

[0067] Figures 12A-14 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of this disclosure are shown. It should be understood that... Figures 12A-14 Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated in additional embodiments of the method. The order of operations / processes can be interchanged. In the embodiments below, [the following can be used with...] Figures 1A-11 The same or similar configurations, materials, processes and / or operations are described, and detailed descriptions may be omitted.

[0068] exist Figures 12A-12B In the patterning process of forming defective 2D semiconductor seeds 210 (such as...) Figures 4A-4B After the steps shown are completed, annealing process AL2 is performed to transform the defective 2D semiconductor seed into a defect-free 2D semiconductor seed 214, without forming a dielectric mesh on the ILD layer 120. In other words, the dielectric mesh formation step is skipped. Annealing process AL2 is similar to the previous steps regarding... Figures 6A-6B The annealing process AL1 is described, and therefore will not be repeated for the sake of brevity.

[0069] exist Figures 13A-13B In this process, an epitaxial growth process EPI2 is performed using a defect-free 2D semiconductor seed 214 as a seed to laterally grow a 2D semiconductor film 216. The defect-free 2D semiconductor seed 214 and the corresponding 2D semiconductor film 216 laterally grown from the defect-free 2D semiconductor seed 214 can be collectively referred to as 2D semiconductor islands 218. The epitaxial conditions of the EPI2 process (e.g., duration, temperature, etc.) are selected such that the 2D semiconductor islands 218 are spaced apart from each other after the EPI2 process is completed. For example, the epitaxial duration is controlled such that the lateral growth of the 2D semiconductor films 216 stops before the 2D semiconductor films 216 meet to form a grain boundary. The material of the 2D semiconductor film 216 is similar to that of... Figures 7A-7B The description is omitted for brevity.

[0070] Then, in Figure 14 In the process, transistors 170 are formed on 2D semiconductor islands 218, and each transistor 170 includes a gate structure 170. G and gate structure 170 G Source / drain regions on opposite sides 170 SD Then, in gate structure 170... G and source / drain region 170 SD Contact element 186 is formed on the upper surface. Then, an upper interconnect structure 190 is formed on the contact element 186. The resulting structure... Figure 14 As shown in the diagram. The formation of transistor 170, contact 186, and interconnect structure 190 is similar to that shown in the diagram. Figures 8-11 The description is omitted for brevity.

[0071] Figures 15A-17 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of this disclosure are shown. It should be understood that... Figures 15A-17 Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of these operations / processes can be interchanged. This can be employed in the following embodiments with... Figures 1A-11 The same or similar configurations, materials, processes and / or operations are described, and detailed descriptions may be omitted.

[0072] exist Figures 15A-15B In the patterning process of forming defective 2D semiconductor seeds 210 (such as...) Figures 4A-4B After the steps shown are completed, annealing process AL3 is performed to transform the defective 2D semiconductor seed into a defect-free 2D semiconductor seed 214, without the need to form a dielectric mesh on the ILD layer 120. Annealing process AL3 is similar to the previously described... Figures 6A-6B The annealing process AL1 is described, and therefore will not be repeated for the sake of brevity.

[0073] exist Figures 16A-16BIn this process, an epitaxial growth process EPI3 is performed using a defect-free 2D semiconductor seed 214 as a seed to laterally grow a 2D semiconductor film 216. The defect-free 2D semiconductor seed 214 and the corresponding 2D semiconductor film 216 laterally grown from the defect-free 2D semiconductor seed 214 can be collectively referred to as 2D semiconductor islands 218. The epitaxial conditions of the epitaxial growth process EPI3 (e.g., duration, temperature, etc.) are selected such that the 2D semiconductor islands 218 meet to form grain boundaries GB1 and GB2 (collectively referred to as grain boundaries GB). Because the 2D semiconductor film 216 is laterally grown from a predetermined position of the 2D semiconductor seed 214, the positions of grain boundaries GB1 and GB2 are predictable and controllable. In this way, by designing the pattern of the 2D semiconductor seed 214, grain boundaries GB1 and GB2 can be formed at the expected positions. For example, the 2D semiconductor seeds 214 arranged in rows and columns allow grain boundaries GB1 and GB2 to jointly form a grid pattern, wherein grain boundary GB1 extends along a first direction D1, and grain boundary GB2 extends along a second direction D2 perpendicular to the first direction D1 and intersects with grain boundary GB1. Because the patterning of grain boundaries GB1 and GB2 is predictable and controllable by using the patterning of the 2D semiconductor seeds 214, transistor layout and interconnect layout can be co-designed and coordinated with the patterning of the 2D semiconductor seeds 214, thereby preventing the formation of transistors on grain boundaries GB1 and GB2. In that case, no transistors or metal interconnects will be formed on grain boundaries GB1 and GB2. The material of the 2D semiconductor film 216 is similar to that of the… Figures 7A-7B The description is omitted for brevity.

[0074] Then, in Figure 17 In the process, transistors 170 are formed on 2D semiconductor islands 218, and each transistor 170 includes a gate structure 170. G and gate structure 170 G Source / drain regions on opposite sides 170 SD Then, in gate structure 170... G and source / drain region 170 SD Contact element 186 is formed on the upper surface. Then, an upper interconnect structure 190 is formed on the contact element 186. The resulting structure... Figure 17 As shown in the diagram. The formation of transistor 170, contact 186, and interconnect structure 190 is similar to that shown in the diagram. Figures 8-11 The description is omitted for brevity.

[0075] Figures 18-22 Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of this disclosure are shown. It should be understood that... Figures 18-22Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of these operations / processes can be interchanged. This can be employed in the following embodiments with... Figures 1A-11 The same or similar configurations, materials, processes and / or operations are described, and detailed descriptions may be omitted.

[0076] exist Figure 18 In the formation of ILD layer 120 (e.g. Figures 1A-1B Following the steps shown, a transition metal layer 302 is deposited on the ILD layer 120 using CVD, ALD, PVD, or other suitable deposition techniques. In some embodiments, the transition metal layer 302 is formed of a transition metal oxide comprising, for example, MoO. X WO X Alternatively, other suitable transition metal oxide materials may be used to form a TMD. In some other embodiments, the transition metal layer 302 is formed of a transition metal including, for example, Mo, W, Pt, or other suitable transition metals that may be used to form a TMD.

[0077] exist Figure 19A and Figure 19B In this process, the transition metal layer 302 is patterned into a plurality of transition metal sheets 310 using appropriate photolithography and etching techniques. In some embodiments, each of the transition metal sheets 310 has a diameter of less than about 0.05 μm. 3 Small volume (e.g., 10 μm) 2 (×0.005μm). For example, a mask layer is first formed on the transition metal layer 302, then patterned to form a pattern of a transition metal sheet, and then an etching process is performed on the transition metal layer 302 by using the patterned mask layer as an etching mask, thereby patterning the transition metal layer 302 into a transition metal sheet 310.

[0078] In some embodiments, the patterned mask layer used to form the transition metal layer 302 may comprise an organic material, such as a photoresist material, and the photoresist material may be formed using a spin coating process, and then patterned into a pattern of the sheet 310 using a suitable photolithography technique. For example, the photoresist material may be irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam provided by a radiation source such as an ultraviolet (UV) source, a deep UV (DUV) source, an extreme UV (EUV) source, and an X-ray source. For example, the radiation source could be a mercury lamp with a wavelength of about 436 nm (G-line) or about 365 nm (I-line); a krypton fluoride (KrF) excimer laser with a wavelength of about 248 nm; an argon fluoride (ArF) excimer laser with a wavelength of about 193 nm; a fluoride (F2) excimer laser with a wavelength of about 157 nm; or other light sources with a suitable wavelength (e.g., below about 100 nm). In another example, the light source is an EUV source with a wavelength of about 13.5 nm or less.

[0079] Once a patterned mask is formed on the transition metal layer 302, the transition metal layer 302 is patterned into a transition metal sheet 310 by using the patterned mask as an etching mask. The patterning process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic, thus allowing the transition metal sheet 310 to have substantially straight sidewalls. Although Figure 19B The transition metal sheet 310 shown has vertical sidewalls, but according to some other embodiments, the etching process may produce tapered sidewalls, as shown by the dashed line DL2.

[0080] exist Figures 20A-20BIn this process, prior to subsequent lateral epitaxial growth from a 2D semiconductor seed formed from a transition metal sheet 310, a dielectric grid 212 is formed on the ILD layer 120 of wafer W1. The dielectric grid 212 is located at the desired grain boundaries to be formed in the subsequent lateral epitaxial growth process, which in turn prevents the formation of grain boundaries in the subsequent lateral epitaxial growth. In other words, the pattern of the dielectric grid 212 and the pattern of the transition metal sheet 310 are co-designed and coordinated. The dielectric grid 212 has grid cells 212o corresponding to the transition metal sheet 310 in a one-to-one manner. In some embodiments, the center of the transition metal sheet 310 is substantially aligned with the center of the grid cell 212o. In some embodiments, the dielectric grid 212 includes a plurality of first grid lines 2122 extending along a first direction D1 and a plurality of second grid lines 2124 extending along a second direction D2 perpendicular to the first direction D1 and intersecting the plurality of first grid lines 2122. Each grid cell 210o is defined by two corresponding first grid lines 2122 and two corresponding second grid lines 2124, and therefore has a rectangular or square top view profile. In some embodiments, the transition metal sheet 310 has a circular or elliptical top view profile, and therefore has a different top view profile from the grid cell 210o. The materials and forming processes related to the dielectric grid 212 are related to... Figures 5A-5B The description is similar, and therefore will not be repeated for the sake of brevity.

[0081] exist Figures 21A-21B In this process, an annealing process AL4 is performed to transform the transition metal sheet 310 into a defect-free 2D semiconductor seed (i.e., a TMD seed) 314. For example, a sulfur-containing gas (e.g., H₂S) or a selenium-containing gas (H₂Se) is used as the ambient gas to perform the annealing process AL4, thereby sulfiding or selenizing the transition metal sheet 310 into a transition metal dichalcogenide (TMD) seed 314. For example, when the transition metal sheet 310 is WO₂... x In some embodiments, the annealing process AL4 performed using H2S results in a reaction with WO x The sulfidation reaction forms WS2, which is used as a TMD seed 314. In the transition metal sheet 310, WO3 is... x In some embodiments, the annealing process AL4 performed using H2Se results in a reaction with WO4. x The selenization reaction forms WSe2, which is used as a TMD seed 314. Furthermore, an annealing process AL4 is performed to cause crystal defects (e.g., vacancies and / or gaps) in each TMD seed to diffuse to the edge of the TMD seed and disappear, thereby reducing the number of crystal defects in each TMD seed to below a threshold suitable for transistor channels, sources, and / or drains.

[0082] In some embodiments, depending on the annealing ambient gas, the annealing process AL4 is performed at a temperature ranging from about 400 degrees Celsius to about 1000 degrees Celsius. In some embodiments, because the annealing process AL4 is performed on small transition metal sheets, it can be performed at a temperature ranging from about 300 degrees Celsius to about 600 degrees Celsius to prevent seed size shrinkage. If the annealing temperature is too high (e.g., above about 1000 degrees Celsius), the excessive temperature may cause the transition metal sheet to melt or vaporize. If the annealing temperature is too low (e.g., below about 300 degrees Celsius), the excessive temperature may provide insufficient crystallization activation energy or may lead to unwanted deposition. In some specific embodiments, the annealing process AL4 for forming defect-free TMD seeds 314 is performed at a temperature ranging from about 500 degrees Celsius to about 600 degrees Celsius for a duration ranging from about 1 minute to about 90 minutes, and H2S or H2Se is used as the ambient gas.

[0083] exist Figure 22 In this process, an epitaxial growth process EPI4 is performed to laterally grow a 2D semiconductor film 316 using a defect-free TMD seed 314 as a seed. The defect-free 2D semiconductor seed 314 and the corresponding 2D semiconductor film 316 laterally grown from the defect-free TMD seed 314 can be collectively referred to as a 2D semiconductor island 318, which is confined within grid cells in a dielectric grid 212. In some embodiments, the 2D semiconductor film 316 has the same TMD material as the defect-free TMD seed 314 or other TMD materials with a lattice constant similar to that of the seed 314. For example, when the defect-free TMD seed 314 is formed by WS2, the 2D semiconductor film 316 can be formed by WS2 using CVD or ALD with WF6 and H2S as precursors. In that case, the WS2 film 316 can be laterally grown from the edge of the WS2 seed 314. When a defect-free TMD seed 314 is formed from WSe2, a 2D semiconductor film 316 can be formed from MoS2 using CVD with MoO3 and sulfur vapor as precursors. In that case, the MoS2 film 316 can grow laterally from the edge of the WSe2 seed 314.

[0084] After forming the 2D semiconductor island 318, transistors can be formed on the 2D semiconductor island 318, and interconnect structures can be formed on the transistors, thereby obtaining... Figure 11 The 3D IC structure shown is illustrated. Details regarding the formation of transistors and interconnect structures on 2D semiconductor islands are similar to those regarding... Figures 8-11 The description is omitted for brevity.

[0085] Figures 23-25A , Figures 26A-27A and Figure 28Exemplary perspective views and cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of this disclosure are shown. It should be understood that... Figures 23-28 Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated in additional embodiments of the method. The order of operations / processes can be interchanged. In the embodiments below, [the following can be used with...] Figures 1A-11 The same or similar configurations, materials, processes and / or operations are described, and detailed descriptions may be omitted.

[0086] exist Figure 23 In this process, a mask layer 400 is formed on the ILD layer 120 and patterned to form openings 400h extending through the mask layer 400 to expose portions of the ILD layer 120. In some embodiments, the patterned mask layer 400 may be a photoresist material formed using a spin coating process, and then patterned using a suitable photolithography technique. For example, the photoresist material 400 is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam provided by a radiation source such as an ultraviolet (UV) source, a deep UV (DUV) source, an extreme UV (EUV) source, and an X-ray source. For example, the radiation source could be a mercury lamp with a wavelength of about 436 nm (G-line) or about 365 nm (I-line); a krypton fluoride (KrF) excimer laser with a wavelength of about 248 nm; an argon fluoride (ArF) excimer laser with a wavelength of about 193 nm; a fluoride (F2) excimer laser with a wavelength of about 157 nm; or other light sources with a suitable wavelength (e.g., below about 100 nm). In another example, the light source is an EUV source with a wavelength of about 13.5 nm or less.

[0087] After forming the patterned mask layer 400, a surface treatment is performed on the exposed portions of the ILD layer 120 exposed in the openings 400h of the patterned mask layer 400 to form treated regions 120t in the ILD layer 120. The surface treatment causes bonds to break along, for example, the ILD surface exposed in the mask openings 400h, to enhance the adsorption capacity for materials in subsequent deposition processes. In some embodiments, the surface treatment includes plasma treatment using oxygen or fluorine plasma, or wet surface modification processes, or combinations thereof. The extent to which the surface treatment is performed (e.g., the extent to which bonds are broken along the surface) affects the number of nucleation sites and, therefore, at least the initial deposition rate of the subsequently deposited 2D semiconductor material, as described later. Generally, the more bonds broken and the more dangling bonds generated, the more nucleation sites are available for the adsorption and nucleation of the 2D semiconductor material to improve the deposition rate, at least in the early stages of deposition. As a result, the processed region 120t of the ILD layer 120 has more nucleation sites for 2D semiconductor materials than the unprocessed region 120u of the ILD layer 120, which in turn allows for selective growth in subsequent 2D semiconductor material deposition processes.

[0088] exist Figure 24 In some embodiments, plasma ashing is used to remove the patterned mask layer 400 from the ILD layer 120. In these embodiments, the plasma ashing process is performed by increasing the temperature of the photoresist mask 400 until it undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, can be used. The removal of the patterned mask layer 400 has no or negligible effect on dangling and / or broken bonds in the treated region 120t, which in turn has no or negligible effect on the deposition selectivity between the treated region 120t and the untreated region 120u in the ILD layer 120.

[0089] exist Figure 25A In this process, a selective deposition process is performed to selectively form multiple defective 2D semiconductor seeds 410 on the processing region 120t of the ILD layer 120. Regarding... Figure 24 The described surface treatment increases the number of nucleation sites on the processed region 120t of the ILD layer 120, and thus allows for the deposition of 2D semiconductor material on the processed region 120t of the ILD layer 120 at a faster deposition rate than on the unprocessed region 120u of the ILD layer 120. In some embodiments, the deposition duration is controlled to occur before 2D semiconductor nucleation begins on the unprocessed region 120u. In this manner, the unprocessed region 120u contains no 2D semiconductor material.

[0090] In some embodiments, the defective 2D semiconductor seed 410 is TMD, graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN), black phosphorus, etc. In some specific embodiments, the defective 2D seed 410 is a WS2 seed having a diameter of about 150 nm to about 250 nm (e.g., about 200 nm), which is deposited using a sulfur-containing gas (e.g., H2S gas) and a plasma generated from a tungsten-containing gas (e.g., WF6). Figure 25B It shows the use of Figures 23-25A The Raman spectrum of the WS2 seeds formed by the steps is shown. As an example, Figure 25B The Raman spectra shown can be obtained by performing Raman spectroscopy on the WS2 seed after the selective deposition process is completed. Figure 25B As shown, the first characteristic peak E of WS2 2g Second characteristic peak A 1g The presence of WS2 in the seed was confirmed, where E 2g and A 1g The prominent peak at that point corresponds to the vibrations of atoms both inside and outside the plane. Figure 25B In the Raman spectrum shown, the first characteristic peak E 2g Located at approximately 340cm -1 up to about 360cm -1 Within the range, and the second characteristic peak A 1g Located at approximately 410cm -1 up to approximately 430cm -1 Within the range. It should be noted that the first characteristic peak E of WS2... 2g Second characteristic peak A 1g The location can vary slightly within the above range, depending on the process parameters of the selective deposition process, such as the flow rates of sulfur-containing and tungsten-containing gases, the temperature at which the selective deposition process is performed, and the duration of the selective deposition process.

[0091] exist Figures 26A-26B In this process, prior to subsequent lateral epitaxial growth from the 2D semiconductor seed 410, a dielectric mesh 212 is formed on the ILD layer 120 of wafer W1. The dielectric mesh 212 is located at the desired grain boundaries to be formed in the subsequent lateral epitaxial growth process, which in turn prevents the formation of grain boundaries in the subsequent lateral epitaxial growth. In other words, the pattern of the dielectric mesh 212 and the pattern of the 2D semiconductor seed 410 are co-designed and coordinated. Furthermore, because the 2D semiconductor seed 410 is selectively grown from the processing region 120t of the ILD layer 120, and the processing region 120t is grown using a patterned mask layer 400 (… Figure 23Since it is formed as a mask, the pattern of the dielectric grid 212 can be designed and coordinated with the pattern of the patterned mask layer 400.

[0092] The dielectric mesh 212 has mesh cells 212o corresponding to the processing region 120t in a one-to-one manner. In some embodiments, the center of the processing region 120t is substantially aligned with the center of the mesh cell 212o. Each mesh cell 210o is defined by two corresponding first mesh lines 2122 and two corresponding second mesh lines 2124, and thus has a rectangular or square top view profile. In some embodiments, the processing region 120t and the overlying defective 2D semiconductor seed 410 have a circular or elliptical top view profile, and thus have a different top view profile than the mesh cell 210o. The materials and formation processes associated with the dielectric mesh 212 are similar to those described above. Figures 5A-5B The description is omitted for brevity.

[0093] exist Figure 27A In this process, annealing process AL5 is performed to transform the defective 2D semiconductor seed 410 into a defect-free 2D semiconductor seed 414. Annealing process AL5 is similar to previously described... Figures 6A-6B The annealing process AL1 is described, and therefore will not be repeated for the sake of brevity. Figure 27B The photoluminescence (PL) spectra of 2D semiconductor seeds (e.g., WS2 seeds) measured before and after H2S annealing are shown. Figure 27B As shown, 2D semiconductor seeds annealed with H2S have higher and sharper peaks than unannealed 2D semiconductor seeds, indicating that H2S annealing leads to increased optical properties and reduced defects in 2D semiconductor seeds.

[0094] exist Figure 28In this process, an epitaxial growth process EPI5 is performed to laterally grow a 2D semiconductor film 416 using a defect-free TMD seed 414 as a seed. The defect-free 2D semiconductor seed 414 and the corresponding 2D semiconductor film 416 laterally grown from the defect-free TMD seed 414 can be collectively referred to as a 2D semiconductor island 418, which is confined within grid cells in a dielectric grid 212. In some embodiments, the 2D semiconductor film 416 has the same TMD material as the defect-free TMD seed 414 or other TMD materials with a lattice constant similar to that of the seed 414. For example, when the defect-free TMD seed 414 is formed by WS2, the 2D semiconductor film 416 can be formed by WS2 using CVD or ALD with WF6 and H2S as precursors. In that case, the WS2 film 416 can be laterally grown from the edge of the WS2 seed 414 in a uniform lateral growth manner. When the defect-free TMD seed 414 is formed from WSe2, the 2D semiconductor film 416 can be formed from MoS2 using CVD with MoO3 and sulfur vapor as precursors. In that case, the MoS2 film 416 can be laterally grown from the edge of the WSe2 seed 414 in a heterogeneous lateral growth manner.

[0095] Figures 29-31A and Figures 32-34 Exemplary cross-sectional views of various stages for fabricating 3D IC structures according to some other embodiments of this disclosure are shown. It should be understood that... Figures 29-34 Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated in additional embodiments of the method. The order of operations / processes can be interchanged. In the embodiments below, [the following can be used with...] Figures 1A-11 The same or similar configurations, materials, processes and / or operations are described, and detailed descriptions may be omitted.

[0096] exist Figure 29In this process, a mask layer 500 is formed on the ILD layer 120 and patterned to form openings 500h extending through the mask layer 500 to expose portions of the ILD layer 120. In some embodiments, the patterned mask layer 500 may be a photoresist material formed using a spin coating process, and then patterned using a suitable photolithography technique. For example, the photoresist material 500 is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam provided by a radiation source such as an ultraviolet (UV) source, a deep UV (DUV) source, an extreme UV (EUV) source, and an X-ray source. For example, the radiation source could be a mercury lamp with a wavelength of about 436 nm (G-line) or about 365 nm (I-line); a krypton fluoride (KrF) excimer laser with a wavelength of about 248 nm; an argon fluoride (ArF) excimer laser with a wavelength of about 193 nm; a fluoride (F2) excimer laser with a wavelength of about 157 nm; or other light sources with a suitable wavelength (e.g., below about 100 nm). In another example, the light source is an EUV source with a wavelength of about 13.5 nm or less.

[0097] After forming the patterned mask layer 500, a transition metal oxide layer 502 is blanket-deposited on the patterned mask layer 500 using CVD, ALD, PVD, or other suitable deposition techniques, and thus a portion of the transition metal oxide layer 502 is formed to line the bottom surface and sidewalls of the mask opening 500h. In some embodiments, the transition metal oxide layer 502 comprises MoO. x WO x Alternatively, other suitable transition metal oxide materials can be used to form TMDs.

[0098] exist Figure 30 In this process, the patterned mask layer 500 is removed using, for example, a stripping process. Stripping the patterned mask layer 500 also removes any overlying portions of the transition metal oxide layer 502, leaving portions of the transition metal oxide layer 502 located in a portion of the ILD layer 120. In some embodiments of this disclosure, the remaining portion of the transition metal oxide layer 502 may be referred to as a transition metal oxide sheet 510. In some embodiments, each of the transition metal sheets 510 has a diameter of about 450 nm to about 550 nm (e.g., about 500 nm).

[0099] exist Figure 31A In this process, a sulfidation or selenization process is performed to sulfidate or selenize the transition metal oxide sheet 510 into a transition metal dichalcogenide (TMD) seed 512. For example, in a transition metal sheet 510 containing WO3... xIn some embodiments, the transition metal sheet 510 can be sulfurized using H2S gas to form WS2 for use as TMD seed 512; or the transition metal sheet 510 can be selenized using H2Se gas to form WSe2 for use as TMD seed 512. Figure 31B It shows the use of Figures 29-31A The Raman spectrum of the WS2 seeds formed by the steps. As an example, Figure 31B The Raman spectra shown can be obtained by performing Raman spectroscopy analysis on the WS2 seeds after the sulfurization process is completed. Figure 31B As shown, the first characteristic peak E of WS2 2g Second characteristic peak A 1g The presence of WS2 in the seed was confirmed, where E 2g and A 1g The prominent peak at that point corresponds to the vibrations of atoms both inside and outside the plane. Figure 31B In the Raman spectrum shown, the first characteristic peak E 2g Located at approximately 340cm -1 up to about 360cm -1 Within the range, and the second characteristic peak A 1g Located at approximately 410cm -1 up to approximately 430cm -1 Within the range. It should be noted that the first characteristic peak E of WS2... 2g Second characteristic peak A 1g The position can vary slightly within the above range, depending on the process parameters of the vulcanization process, such as the flow rate of the sulfur-containing gas, the temperature at which vulcanization is performed, and the duration of vulcanization.

[0100] exist Figure 32 In this process, a dielectric mesh 212 is formed on top of the ILD layer 120 before lateral epitaxial growth from the TMD seed 512. Details relating to the dielectric mesh 212 are similar to those regarding... Figures 5A-5B The description is omitted for brevity.

[0101] exist Figure 33 In this process, annealing process AL6 is performed to transform TMD seed 512 into defect-free TMD seed 514. More specifically, annealing process AL6 causes crystal defects (e.g., vacancies and / or gaps) in each TMD seed to diffuse to the edge of the TMD seed and disappear, thereby reducing the number of crystal defects in each TMD seed to below a suitable threshold for transistor channels, sources, and / or drains. Annealing process AL6 is similar to previous processes... Figures 6A-6B The annealing process AL1 is described, and therefore will not be repeated for the sake of brevity.

[0102] exist Figure 34 In this process, an epitaxial growth process EPI6 is performed to laterally grow a 2D semiconductor film 516 using a defect-free TMD seed 514 as a seed. The defect-free TMD seed 514 and the corresponding 2D semiconductor film 516 laterally grown from the defect-free TMD seed 514 can be collectively referred to as a 2D semiconductor island 518, which is confined within a grid cell in a dielectric grid 212. In some embodiments, the 2D semiconductor film 516 has the same TMD material as the defect-free TMD seed 514 or other TMD materials with a lattice constant similar to that of the seed 514. For example, when the defect-free TMD seed 514 is formed by WS2, the 2D semiconductor film 516 can be formed by WS2 using CVD or ALD with WF6 and H2S as precursors. In that case, the WS2 film 516 can be laterally grown from the edge of the WS2 seed 514 in a uniform lateral growth manner. When a defect-free TMD seed 514 is formed from WSe2, a 2D semiconductor film 516 can be formed from MoS2 using CVD with MoO3 and sulfur vapor as precursors. In that case, the MoS2 film 516 can be laterally grown from the edge of the WSe2 seed 514 in a heterogeneous lateral growth manner.

[0103] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are any specific advantages required for any embodiment. One advantage is that “IC-preferred” (i.e., 2D semiconductor islands with no or negligible crystal defects) can be formed on the amorphous surface of the interlayer dielectric or intermetallic dielectric. Another advantage is that IC-preferred 2D semiconductor islands formed on the ILD or IMD can be used as active regions for transistors, thereby forming 3D ICs with lower-level (e.g., below the interconnect structure) lower transistors and higher-level (e.g., above the interconnect structure) higher transistors.

[0104] In some embodiments, an IC structure includes: a first transistor formed on a substrate, a first interconnect structure above the first transistor, a dielectric layer above the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands. In some embodiments, each 2D semiconductor island includes a 2D semiconductor seed and a 2D semiconductor film laterally surrounding the 2D semiconductor seed. In some embodiments, the 2D semiconductor film is formed of the same material as the 2D semiconductor seed. In some embodiments, the 2D semiconductor film is formed of a different material than the 2D semiconductor seed. In some embodiments, the surface area of ​​the 2D semiconductor film is larger than the surface area of ​​the 2D semiconductor seed. In some embodiments, the thickness of the 2D semiconductor film is substantially the same as the thickness of the 2D semiconductor seed. In some embodiments, from a top view, the 2D semiconductor islands are arranged in rows and columns. In some embodiments, the 2D semiconductor islands are spaced apart from each other. In some embodiments, the IC structure also includes a dielectric grid above the dielectric layer, and the 2D semiconductor islands are disposed in a plurality of grid cells of the dielectric grid in a one-to-one manner. In some embodiments, two adjacent 2D semiconductor islands form a grain boundary. In some embodiments, the IC structure also includes a second interconnect structure above the plurality of second transistors.

[0105] In some embodiments, an IC structure includes: an interconnect structure, a dielectric layer, a plurality of 2D semiconductor seeds, a plurality of 2D semiconductor films, and a plurality of transistors. The interconnect structure is above a substrate and includes conductive vias extending vertically above the substrate and wires extending laterally above the conductive vias. The dielectric layer is above the interconnect structure. 2D semiconductor seeds are arranged in rows and columns on the dielectric layer. 2D semiconductor films laterally surround the 2D semiconductor seeds, respectively. Transistors are above the 2D semiconductor films. In some embodiments, the 2D semiconductor seeds are made of transition metal dichalcogenide (TMD), graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN), or black phosphorus. In some embodiments, the 2D semiconductor films are made of TMD, graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN), or black phosphorus. In some embodiments, the 2D semiconductor seeds and 2D semiconductor films are formed of the same TMD material. In some embodiments, the 2D semiconductor seeds are formed of a first TMD material, and the 2D semiconductor films are formed of a second TMD material different from the first TMD material.

[0106] In some embodiments, a method includes: forming a plurality of first transistors on a substrate; forming an interconnect structure on the plurality of first transistors; forming a dielectric layer on the interconnect structure; forming a plurality of 2D semiconductor seeds on the dielectric layer; annealing the plurality of 2D semiconductor seeds; performing an epitaxial process after annealing the plurality of 2D semiconductor seeds to laterally grow a plurality of 2D semiconductor films from the plurality of 2D semiconductor seeds; and forming a plurality of second transistors on the plurality of 2D semiconductor films. In some embodiments, forming 2D semiconductor seeds includes: depositing a 2D semiconductor layer on a crystal substrate; transferring the 2D semiconductor layer from the crystal substrate to the dielectric layer; and patterning the 2D semiconductor layer into a plurality of 2D semiconductor seeds. In some embodiments, forming 2D semiconductor seeds includes: depositing a transition metal layer on the dielectric layer; patterning the transition metal layer into a plurality of transition metal sheets; and sulfiding or selenizing the plurality of transition metal sheets to form a plurality of 2D semiconductor seeds. In some embodiments, forming a 2D semiconductor seed includes: performing a surface treatment to treat a plurality of regions of a dielectric layer while leaving another region of the dielectric layer untreated; and selectively depositing a plurality of 2D semiconductor seeds on the plurality of treated regions of the dielectric layer rather than on the untreated regions of the dielectric layer.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0108] Example 1. An integrated circuit (IC) structure, comprising:

[0109] The first transistor formed on the substrate;

[0110] The first interconnect structure above the first transistor;

[0111] The dielectric layer above the first interconnect structure;

[0112] The plurality of 2D semiconductor islands on the dielectric layer; and

[0113] Multiple second transistors are formed on the multiple 2D semiconductor islands.

[0114] Example 2. The IC structure according to Example 1, wherein each of the plurality of 2D semiconductor islands includes a 2D semiconductor seed and a 2D semiconductor film laterally surrounding the 2D semiconductor seed.

[0115] Example 3. The IC structure according to Example 2, wherein the 2D semiconductor film is formed of the same material as the 2D semiconductor seed.

[0116] Example 4. The IC structure according to Example 2, wherein the 2D semiconductor film is formed of a material different from the 2D semiconductor seed.

[0117] Example 5. The IC structure according to Example 2, wherein the surface area of ​​the 2D semiconductor film is greater than the surface area of ​​the 2D semiconductor seed.

[0118] Example 6. The IC structure according to Example 2, wherein the thickness of the 2D semiconductor film is substantially the same as the thickness of the 2D semiconductor seed.

[0119] Example 7. An IC structure according to Example 1, wherein, viewed from a top view, the plurality of 2D semiconductor islands are arranged in rows and columns.

[0120] Example 8. The IC structure according to Example 1, wherein the plurality of 2D semiconductor islands are spaced apart from each other.

[0121] Example 9. The IC structure described in Example 1 further includes:

[0122] The dielectric grid above the dielectric layer, wherein the plurality of 2D semiconductor islands are arranged in a one-to-one manner in the plurality of grid cells of the dielectric grid.

[0123] Example 10. The IC structure according to Example 1, wherein two adjacent islands of the plurality of 2D semiconductor islands form a grain boundary.

[0124] Example 11. The IC structure according to Example 1 further includes:

[0125] The second interconnect structure is built upon the plurality of second transistors.

[0126] Example 12. An IC structure, comprising:

[0127] An interconnect structure is located above a substrate and includes a conductive via extending vertically above the substrate and a wire extending laterally above the conductive via.

[0128] A dielectric layer is placed on top of the interconnect structure;

[0129] Multiple 2D semiconductor seeds are arranged in rows and columns on the dielectric layer;

[0130] Multiple 2D semiconductor films are respectively arranged laterally around the multiple 2D semiconductor seeds; and

[0131] Multiple transistors are disposed on the multiple 2D semiconductor films.

[0132] Example 13. The IC structure according to Example 12, wherein the plurality of 2D semiconductor seeds are made of transition metal dichalcogenide (TMD), graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN) or black phosphorus.

[0133] Example 14. The IC structure according to Example 12, wherein the plurality of 2D semiconductor films are made of TMD, graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN) or black phosphorus.

[0134] Example 15. The IC structure according to Example 12, wherein the plurality of 2D semiconductor seeds and the plurality of 2D semiconductor films are formed of the same TMD material.

[0135] Example 16. The IC structure according to Example 12, wherein the plurality of 2D semiconductor seeds are formed of a first TMD material, and the plurality of 2D semiconductor films are formed of a second TMD material different from the first TMD material.

[0136] Example 17. A method for manufacturing an integrated circuit, comprising:

[0137] Multiple first transistors are formed on the substrate;

[0138] An interconnect structure is formed over the plurality of first transistors;

[0139] A dielectric layer is formed on the interconnect structure;

[0140] Multiple 2D semiconductor seeds are formed on the dielectric layer;

[0141] Anneal the plurality of 2D semiconductor seeds;

[0142] After annealing the plurality of 2D semiconductor seeds, an epitaxial process is performed to laterally grow a plurality of 2D semiconductor films from the plurality of 2D semiconductor seeds; and

[0143] Multiple second transistors are formed on the plurality of 2D semiconductor films.

[0144] Example 18. The method according to Example 17, wherein forming the plurality of 2D semiconductor seeds includes:

[0145] Depositing a 2D semiconductor layer on a crystal substrate;

[0146] Transferring the 2D semiconductor layer from the crystal substrate to the dielectric layer; and

[0147] The 2D semiconductor layer is patterned into the plurality of 2D semiconductor seeds.

[0148] Example 19. The method according to Example 17, wherein forming the plurality of 2D semiconductor seeds includes:

[0149] A transition metal layer is deposited on the dielectric layer;

[0150] The transition metal layer is patterned into multiple transition metal sheets; and

[0151] The plurality of transition metal sheets are sulfided or selenized to form the plurality of 2D semiconductor seeds.

[0152] Example 20. The method according to Example 17, wherein forming the plurality of 2D semiconductor seeds includes:

[0153] Perform surface treatment to process multiple regions of the dielectric layer while leaving another region of the dielectric layer unprocessed; and

[0154] The plurality of 2D semiconductor seeds are selectively deposited on a plurality of processed regions of the dielectric layer rather than on unprocessed regions of the dielectric layer.

Claims

1. An integrated circuit (IC) structure, comprising: The first transistor formed on the substrate; The first interconnect structure above the first transistor; The dielectric layer above the first interconnect structure; A plurality of 2D semiconductor islands on the dielectric layer, wherein each of the plurality of 2D semiconductor islands includes a 2D semiconductor seed and a 2D semiconductor film laterally surrounding the 2D semiconductor seed, wherein the 2D semiconductor seed of each of the plurality of 2D semiconductor islands includes a transition metal dichalcogenide (TMD); and Multiple second transistors are formed on the multiple 2D semiconductor islands.

2. The IC structure according to claim 1, wherein, The 2D semiconductor film is formed from the same material as the 2D semiconductor seed.

3. The IC structure according to claim 1, wherein, The 2D semiconductor film is formed from a material different from the 2D semiconductor seed.

4. The IC structure according to claim 1, wherein, The surface area of ​​the 2D semiconductor film is greater than the surface area of ​​the 2D semiconductor seed.

5. The IC structure according to claim 1, wherein, The thickness of the 2D semiconductor film is substantially the same as the thickness of the 2D semiconductor seed.

6. The IC structure according to claim 1, wherein, From a top view, the plurality of 2D semiconductor islands are arranged in rows and columns.

7. The IC structure according to claim 1, wherein, The plurality of 2D semiconductor islands are spaced apart from each other.

8. The IC structure according to claim 1, further comprising: The dielectric grid above the dielectric layer, wherein the plurality of 2D semiconductor islands are arranged in a one-to-one manner in the plurality of grid cells of the dielectric grid.

9. The IC structure according to claim 1, wherein, Two adjacent 2D semiconductor islands form a grain boundary.

10. The IC structure according to claim 1, further comprising: The second interconnect structure is built upon the plurality of second transistors.

11. An IC structure, comprising: An interconnect structure is located above a substrate and includes a conductive via extending vertically above the substrate and a wire extending laterally above the conductive via. A dielectric layer is placed on top of the interconnect structure; Multiple 2D semiconductor seeds are arranged in rows and columns on the dielectric layer; Multiple 2D semiconductor films are laterally surrounded by multiple 2D semiconductor seeds, wherein the multiple 2D semiconductor films and the multiple 2D semiconductor seeds have the same material; as well as Multiple transistors are disposed on the multiple 2D semiconductor films.

12. The IC structure according to claim 11, wherein, The plurality of 2D semiconductor seeds are made of transition metal dichalcogenide (TMD), graphene, layered III-VI chalcogenide, hexagonal boron nitride (h-BN) or black phosphorus.

13. The IC structure according to claim 11, wherein, The plurality of 2D semiconductor films are made of TMD, graphene, layered III-VI chalcogenides, hexagonal boron nitride (h-BN) or black phosphorus.

14. The IC structure according to claim 11, wherein, The plurality of 2D semiconductor seeds and the plurality of 2D semiconductor films are formed from the same TMD material.

15. The IC structure according to claim 11, wherein, The plurality of 2D semiconductor seeds are formed from a first TMD material, and the plurality of 2D semiconductor films are formed from a second TMD material different from the first TMD material.

16. A method for manufacturing an integrated circuit, comprising: Multiple first transistors are formed on the substrate; An interconnect structure is formed over the plurality of first transistors; A dielectric layer is formed on the interconnect structure; Multiple 2D semiconductor seeds are formed on the dielectric layer; Anneal the plurality of 2D semiconductor seeds; After annealing the plurality of 2D semiconductor seeds, an epitaxial process is performed to grow a plurality of 2D semiconductor films laterally from the plurality of 2D semiconductor seeds, wherein the plurality of 2D semiconductor films and the plurality of 2D semiconductor seeds have the same material; as well as Multiple second transistors are formed on the plurality of 2D semiconductor films.

17. The method according to claim 16, wherein, Forming the plurality of 2D semiconductor seeds includes: Depositing a 2D semiconductor layer on a crystal substrate; Transferring the 2D semiconductor layer from the crystal substrate to the dielectric layer; and The 2D semiconductor layer is patterned into the plurality of 2D semiconductor seeds.

18. The method according to claim 16, wherein, Forming the plurality of 2D semiconductor seeds includes: A transition metal layer is deposited on the dielectric layer; The transition metal layer is patterned into multiple transition metal sheets; and The plurality of transition metal sheets are sulfided or selenized to form the plurality of 2D semiconductor seeds.

19. The method of claim 16, wherein, Forming the plurality of 2D semiconductor seeds includes: Perform surface treatment to process multiple regions of the dielectric layer while leaving another region of the dielectric layer unprocessed; and The plurality of 2D semiconductor seeds are selectively deposited on a plurality of processed regions of the dielectric layer rather than on unprocessed regions of the dielectric layer.

Images