Fabrication method of TSV structure in three-dimensional integrated circuit packaging

Abstract

This invention provides a method for fabricating a TSV structure in a three-dimensional integrated circuit package. By employing an insulating film layer that can be patterned using photolithography and blocks the diffusion of copper particles during the formation of the TSV holes, this insulating film layer serves both as a mask layer for etching the TSV holes and as an insulating dielectric layer for the TSV structure. This dual-function insulating film layer allows for the etching of TSV holes using only this single insulating film layer, effectively reducing process steps and manufacturing costs. Furthermore, the insulating film layer's ability to block copper particle diffusion significantly reduces the risk of Cu particles generated during CMP polishing of the Cu-filled layer / blocking adhesion layer composite interface diffusing into the insulating film layer, thereby improving the electrical properties and reliability of the package.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for preparing a TSV structure in a three-dimensional integrated circuit package. Background Technology

[0002] As the demands for high performance, small size, high reliability, and ultra-low power consumption in chips and electronic products increase, advanced packaging technologies are constantly breaking through and developing, leading to a growing demand for 3D integrated circuits (3DIC). 3D integrated circuits are a chip stacking technology used for semiconductor packaging, bringing new advantages in efficiency, power, performance, and form factor to the semiconductor industry.

[0003] 3D IC circuits are formed by stacking chips and wafers (C2W) or wafers stacking one another (W2W), with interconnections between layers achieved through through-silicon vias (TSVs). TSV technology is a technique for interconnecting stacked chips in 3D IC circuits. It achieves electrical interconnection between different chips by fabricating vertically interconnected TSV structures on silicon wafers. TSV technology allows for maximum chip stacking density in three dimensions, the shortest interconnect lines between chips, and the smallest overall size. It also significantly improves chip speed and low-power performance, making it one of the most promising technologies in electronic packaging today.

[0004] Currently, the fabrication methods of TSV structures in 3DIC circuit packaging, such as Figures 1 to 9 As shown, it includes the following steps:

[0005] like Figure 1 As shown, a silicon (Si) wafer is thinned to 200 mm.

[0006] like Figure 2 As shown, a silicon oxide (SiO2) mask layer 201 and a photoresist layer 202 are formed on a silicon wafer 100;

[0007] like Figure 3 As shown, the photoresist layer 202 is patterned to obtain a patterned photoresist layer 203;

[0008] like Figure 4 As shown, the patterned photoresist layer 203 is used to etch the mask layer 201 to obtain the patterned mask layer 204;

[0009] like Figure 5 As shown, based on the patterned mask layer 204, the silicon wafer 200 and the composite film layer 210 are etched to form TSV holes 205 that expose the metal wiring 211.

[0010] like Figures 6 to 8As shown, an insulating pad layer 206, a barrier adhesion layer 207, and a Cu filling layer 208 are formed sequentially.

[0011] like Figure 9 As shown, the barrier adhesion layer 207 and Cu filling layer 208 are finally CMP ground to obtain a TSV structure with a flat surface.

[0012] Among them, such as Figure 9 As shown, during the CMP polishing of the composite interface of Cu filling layer 208 / barrier adhesion layer 207, Cu particles 212 are at risk of diffusing into the patterned mask layer 204. Cu particles with a large diffusion coefficient will diffuse into the patterned mask layer 204, affecting electrical properties and reliability. At the same time, the TSV structure fabrication process requires both photoresist layer 202 and silicon dioxide mask layer 201 to be used as masks, which complicates the process steps and increases costs. Summary of the Invention

[0013] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating TSV structures in three-dimensional integrated circuit packaging, which solves the problems in the existing three-dimensional integrated circuit packaging TSV structure fabrication process, where the composite interface process of CMP grinding Cu filling layer / barrier adhesion layer easily generates Cu grinding particles that diffuse into the mask layer, affecting electrical properties and reliability, and the fabrication process of TSV structures is complex.

[0014] To achieve the above and other related objectives, the present invention provides a method for fabricating a TSV structure in a three-dimensional integrated circuit package, the method comprising the following steps:

[0015] A semiconductor substrate is provided, the semiconductor substrate comprising a redistribution layer, a composite film layer and a silicon substrate stacked sequentially;

[0016] An insulating film layer is deposited on the surface of the silicon substrate. The insulating film layer can be patterned using photolithography and can block the diffusion of copper particles.

[0017] The insulating film layer is exposed and developed to obtain a patterned insulating film layer;

[0018] Based on the patterned insulating film layer, the silicon substrate and the composite film layer are sequentially etched to form TSV holes, which expose the metal wiring in the redistribution layer.

[0019] Optionally, the material of the insulating film layer includes one or more combinations of PI, BCB and PBO.

[0020] Optionally, the thickness of the insulating film layer is 1 μm to 5 μm.

[0021] Optionally, the insulating film layer may be formed by spin coating or by semi-cured film lamination.

[0022] Optionally, the process may further include a step of thinning the silicon substrate before depositing an insulating film layer on the surface of the silicon substrate.

[0023] Furthermore, the method for thinning the silicon substrate includes a CMP polishing process, and the thickness of the silicon substrate after thinning is 5μm to 15μm.

[0024] Optionally, after forming the TSV hole, the following steps are further included:

[0025] An insulating liner is formed on the sidewall of the TSV hole;

[0026] A barrier adhesion layer and a Cu filling layer are deposited on the surface of the obtained structure, wherein the Cu filling layer at least fills the TSV pores;

[0027] The Cu filling layer and the barrier adhesion layer were ground using CMP grinding technology to obtain a TSV structure with a flat surface.

[0028] Furthermore, the insulating liner layer is formed using an ALD process, the barrier adhesion layer is formed using a PVD process, and the Cu filler layer is formed using an ECP process.

[0029] Optionally, the insulating dielectric layer in the composite film layer includes one or a combination of silicon oxide and silicon nitride layers.

[0030] Optionally, the metal wiring in the composite film layer has a damascus structure, and the metal wiring in the rewiring layer has a damascus structure.

[0031] As described above, the method for fabricating the TSV structure in the three-dimensional integrated circuit package of the present invention employs an insulating film layer that can be patterned by photolithography and can block the diffusion of copper particles during the formation of TSV holes. This insulating film layer serves as both a mask layer for etching the TSV holes and an insulating dielectric layer for the TSV structure. This dual-function insulating film layer allows the etching of TSV holes to be achieved with only this one insulating film layer, effectively reducing process steps and manufacturing costs. In addition, the ability of this insulating film layer to block the diffusion of copper particles can greatly reduce the risk of Cu particles generated during CMP polishing of the Cu filling layer / blocking adhesion layer composite interface diffusing into the insulating film layer, thereby improving the electrical properties and reliability of the package. Attached Figure Description

[0032] Figures 1 to 9 The diagram shows the cross-sectional structure of each step in the fabrication process of the TSV structure in the three-dimensional integrated circuit packaging of the prior art.

[0033] Figures 10 to 21 The diagram shows cross-sectional structural schematics of each step in the fabrication process of the TSV structure in the three-dimensional integrated circuit packaging of this invention.

[0034] Component designation explanation

[0035] 200 silicon wafers

[0036] 201 Mask layer

[0037] 202 Photoresist layer

[0038] 203 Patterned photoresist layer

[0039] 204 Graphical mask layers

[0040] 205 TSV holes

[0041] 206 Insulating Pad Layer

[0042] 207 Barrier Adhesion Layer

[0043] 208 Cu filled layer

[0044] 209 TSV Structure

[0045] 210 composite film layer

[0046] 211 Metal wiring

[0047] 212 Cu particles

[0048] 10 Semiconductor substrate

[0049] 100 Rerouting Layer

[0050] 101 Metal Wiring

[0051] 102 Wiring Media Layer

[0052] 103 Composite film layer

[0053] 104 silicon substrate

[0054] 105 chip

[0055] 106 Supporting substrate

[0056] 11 Insulating film layer

[0057] 110 Graphical insulating film layer

[0058] 12 TSV holes

[0059] 13 Insulating Pad Layer

[0060] 14. Barrier Adhesion Layer

[0061] 140 barrier layer

[0062] 141 Adhesion layer

[0063] 15 Cu-filled layer

[0064] 16 TSV Structure Detailed Implementation

[0065] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0067] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0068] Please see Figures 10 to 21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] This embodiment provides a method for fabricating a TSV structure in a three-dimensional integrated circuit package, the method comprising the following steps:

[0070] S1, providing a semiconductor substrate, the semiconductor substrate comprising a redistribution layer, a composite film layer and a silicon substrate stacked sequentially;

[0071] S2, depositing an insulating film layer on the surface of the silicon substrate, wherein the insulating film layer can be patterned using photolithography and can block the diffusion of copper particles;

[0072] S3, the insulating film layer is exposed and developed to obtain a patterned insulating film layer;

[0073] S4, based on the patterned insulating film layer, the silicon substrate and the composite film layer are sequentially etched to form TSV holes, and the TSV holes expose the metal wiring in the redistribution layer.

[0074] The method for fabricating the TSV structure in the three-dimensional integrated circuit packaging of this embodiment employs an insulating film layer that can be patterned by photolithography and can block the diffusion of copper particles during the formation of TSV holes. This insulating film layer serves as both a mask layer for etching the TSV holes and an insulating dielectric layer for the TSV structure. This dual-function insulating film layer allows the etching of TSV holes to be achieved with only this one insulating film layer, effectively reducing process steps and manufacturing costs. In addition, the ability of this insulating film layer to block the diffusion of copper particles can greatly reduce the risk of Cu particles generated during CMP grinding of the Cu filling layer / blocking adhesion layer composite interface diffusing into the insulating film layer, thereby improving the electrical properties and reliability of the package.

[0075] The fabrication method of the TSV structure in the three-dimensional integrated circuit package of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0076] like Figure 10 and Figure 11 As shown, where Figure 11 for Figure 10 An enlarged schematic diagram at point A is shown. Since the main purpose of this embodiment is to form a TSV structure, the following figures only show the schematic for ease of understanding. Figure 10 The process of forming a TSV structure at point A (the area where the TSV structure needs to be formed) first involves step S1, which provides a semiconductor substrate 10, which includes a redistribution layer 100, a composite film layer 103, and a silicon substrate 104 stacked sequentially.

[0077] It should be noted that TSV structures may need to be formed in multiple different regions on the semiconductor substrate 10. Furthermore, the height of the TSV structures formed in different regions may also differ, but the fabrication method of this embodiment can be used to prepare the TSV structures. For ease of description, the accompanying drawings of this embodiment only illustrate a certain region, for example... Figure 10 The process of forming a TSV structure in region A.

[0078] The size of the silicon substrate 104 is set as needed, such as the common 6-inch, 8-inch, 12-inch, etc.; in addition, the thickness of the silicon substrate 104 is also set as needed.

[0079] As an example, stacked chips 105 are formed along the thickness direction in the semiconductor substrate 10. The chips 105 are electrically connected in the stacking direction via metal wiring 101. For example, the metal wiring 101 in the redistribution layer 100 and the metal wiring 101 in the composite film layer 103 are electrically connected by bonding. Currently, the commonly used metal wiring 101 often employs a damask structure. Furthermore, the type of chips 105 stacked along the thickness direction in the semiconductor substrate 10 can be selected according to design requirements, and no excessive restrictions are imposed here. For example… Figure 10 The chip 105 located on the lower layer of the semiconductor substrate 10 is a SoC chip, and the chip 105 located on the upper layer of the semiconductor substrate 10 is a MOS chip.

[0080] As an example, the redistribution layer 100 includes a routing dielectric layer 102 and the metal wiring 101. The number of layers, distribution, and material of the metal wiring 101, as well as the material of the routing dielectric layer 102, are not excessively restricted here; they can be set according to actual needs. Generally, the routing dielectric layer 102 is a single-layer structure of silicon oxide or silicon nitride, or it can be a stack of silicon oxide and silicon nitride layers.

[0081] As an example, the composite film layer 103 also includes the wiring dielectric layer 102 and the metal wiring 101. The number of layers, distribution, and material of the metal wiring 101, as well as the material of the wiring dielectric layer 102, are not excessively restricted here; they can be set according to actual needs. Generally, the wiring dielectric layer 102 is a single-layer structure of silicon oxide or silicon nitride, or it can be a stack of silicon oxide and silicon nitride layers.

[0082] As an example, a support substrate 106 is formed on the side of the semiconductor substrate 10 away from the silicon substrate 104 before the fabrication of the TSV structure.

[0083] like Figure 12 As shown, step S2 is then performed to deposit an insulating film layer 11 on the surface of the silicon substrate 104. The insulating film layer 11 can be patterned using photolithography and can block the diffusion of copper particles.

[0084] As a preferred example, the material of the insulating film layer 11 includes one or more of PI (polyimide), BCB (benzocyclobutene resin), and PBO (poly(p-phenylenebenzodioxazole)). That is, the material of the insulating film layer 11 can be only PI, BCB, or PBO, or a mixture of any two of PI, BCB, and PBO, or a mixture of PI, BCB, and PBO. In addition, the insulating film layer 11 may also contain unintentionally doped materials. This doping is due to precision control during the manufacturing process and will not significantly alter the performance of the insulating film layer 11; therefore, it should fall within the scope of protection of this embodiment.

[0085] As an example, the thickness of the insulating film layer 11 is selected to be 1μm to 5μm, such as 1μm, 2μm, 3μm, 4μm, 5μm.

[0086] Depending on the material of the insulating film layer 11, a spin coating process or a semi-cured film lamination process can be used to form the insulating film layer 11 on the silicon substrate 104. However, it is not limited to these methods, and other suitable processes can also be used.

[0087] As an example, to reduce the final packaged device size, the silicon substrate 104 can be thinned before proceeding with the next step. The thinning process can include, but is not limited to, CMP polishing, and may also include mechanical polishing. In this embodiment, to improve the flatness of the silicon substrate 104 after polishing, CMP polishing is preferred for thinning. As an example, the thickness of the thinned silicon substrate 104 can be selected from 5μm to 15μm, for example, 5μm, 10μm, 15μm, etc., and can be set as needed; no excessive limitation is imposed here.

[0088] like Figure 13 As shown, step S3 is then performed to expose and develop the insulating film layer 11 to obtain a patterned insulating film layer 110. Based on the characteristic that the insulating film layer 11 can be patterned by photolithography, the insulating film layer 11 can be directly exposed and developed to obtain a patterned insulating film layer 110, which exposes the surface of the subsequent TSV hole formation area.

[0089] like Figure 14As shown, in step S4, the silicon substrate 104 and the composite film layer 103 are sequentially etched based on the patterned insulating film layer 110 to form TSV holes 12. The TSV holes 12 expose the metal wiring 101 in the redistribution layer 100. This completes the formation of the TSV holes 12 required for the TSV structure. The formation of the TSV holes 12 only requires one layer of the insulating film layer 110 as a mask to complete the etching of the TSV holes 12, effectively reducing process steps and lowering manufacturing costs.

[0090] like Figures 15 to 21 As shown, after forming the TSV hole 12, a series of steps including hole filling are also included, specifically:

[0091] S51, such as Figure 16 As shown, an insulating liner layer 13 is formed on the sidewall of the TSV hole 12; specifically: as shown in the figure. Figure 15 As shown, the insulating liner layer 13 is formed by depositing any suitable deposition process, such as ALD. The material of the insulating liner layer 13 can be any suitable insulating material, such as silicon oxide or silicon nitride. Figure 16 As shown, the insulating pad layer 13 on the bottom wall of the TSV hole 12 is then removed by a dry etching process. During this process, the insulating pad layer 13 on the surface of the silicon substrate 104 is also removed, resulting in the insulating pad layer 13 formed only on the side wall of the TSV hole 12.

[0092] S52, such as Figures 17 to 19 As shown, where Figure 18 for Figure 17 A partially enlarged view of the barrier adhesion layer 14 formed in the process, showing that the barrier adhesion layer 14 and the Cu filling layer 15 are deposited on the surface of the resulting structure, wherein the Cu filling layer 15 at least completely fills the TSV holes 12; specifically: as shown in the figure. Figure 17 and Figure 18 As shown, the barrier adhesion layer 14 is formed by depositing any suitable deposition process, such as PVD. The barrier adhesion layer 14 is selected as a stacked structure of a lower barrier layer 140 and an upper adhesion layer 141. Figure 19 As shown, any suitable deposition process, such as the ECP process with strong pore-filling capability, is used to fill the TSV pores 12.

[0093] S53, such as Figure 20 and Figure 21 As shown, where Figure 20 for Figure 21The enlarged schematic diagram at point A shows that the Cu filling layer 15 and the barrier adhesion layer 14 are polished using CMP polishing technology to obtain a flat TSV structure 16. During the CMP polishing process, since the insulating film layer 11 has strong anti-copper particle diffusion performance, the risk of Cu particles generated during polishing diffusing into the insulating film layer 11 during the CMP polishing of the composite interface of Cu filling layer 15 / barrier adhesion layer 14 can be effectively reduced, thereby improving the electrical properties and reliability of the package.

[0094] In summary, this invention provides a method for fabricating a TSV structure in a three-dimensional integrated circuit package. By employing an insulating film layer that can be patterned using photolithography and blocks the diffusion of copper particles during the formation of the TSV holes, this insulating film layer serves both as a mask layer for etching the TSV holes and as an insulating dielectric layer for the TSV structure. This dual-function insulating film layer allows for the etching of the TSV holes using only this single insulating film layer, effectively reducing process steps and manufacturing costs. Furthermore, the insulating film layer's ability to block copper particle diffusion significantly reduces the risk of Cu particles generated during CMP polishing of the Cu-filled layer / blocking adhesion layer composite interface diffusing into the insulating film layer, improving the electrical properties and reliability of the package. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a TSV structure in a three-dimensional integrated circuit package, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, the semiconductor substrate comprising a redistribution layer, a composite film layer and a silicon substrate stacked sequentially; An insulating film layer is deposited on the surface of the silicon substrate. The insulating film layer can be patterned using photolithography and can block the diffusion of copper particles. The insulating film layer is exposed and developed to obtain a patterned insulating film layer; Based on the patterned insulating film layer, the silicon substrate and the composite film layer are sequentially etched to form TSV holes, which expose the metal wiring in the redistribution layer.

2. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The insulating film layer is made of one or more of PI, BCB and PBO.

3. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The thickness of the insulating film layer is 1μm to 5μm.

4. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The insulating film layer is formed by spin coating or by semi-curing film lamination.

5. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The process further includes a step of thinning the silicon substrate before depositing an insulating film layer on the surface of the silicon substrate.

6. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 5, characterized in that: The method for thinning the silicon substrate includes a CMP polishing process, and the thickness of the silicon substrate after thinning is 5 μm to 15 μm.

7. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that, After forming the TSV hole, the following steps are also included: An insulating liner is formed on the sidewall of the TSV hole; A barrier adhesion layer and a Cu filling layer are deposited on the surface of the obtained structure, wherein the Cu filling layer at least fills the TSV pores; The Cu filling layer and the barrier adhesion layer were ground using CMP grinding technology to obtain a TSV structure with a flat surface.

8. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 7, characterized in that: The insulating liner layer is formed using the ALD process, the barrier adhesion layer is formed using the PVD process, and the Cu filler layer is formed using the ECP process.

9. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The insulating dielectric layer in the composite film layer includes one or a combination of silicon oxide layer and silicon nitride layer.

10. The method for fabricating a TSV structure in a three-dimensional integrated circuit package according to claim 1, characterized in that: The metal wiring in the composite film layer has a damascus structure, and the metal wiring in the rewiring layer has a damascus structure.

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