Driving backplane and manufacturing method thereof, and display panel

Abstract

The present application provides a driving backplane and its preparation method, as well as a display panel. In this application, multiple auxiliary signal lines are provided on a side of multiple signal lines away from a substrate to reduce the impedance of the multiple signal lines, thereby allowing the provision of signal lines with smaller widths, thereby reducing the space occupied by the signal lines on the driving backplane. The orthographic projections of the multiple auxiliary signal lines on the substrate fall within the orthographic projection range of the signal lines on the substrate, so that the auxiliary signal lines do not occupy additional space on the driving backplane, thereby improving the transparency of the driving backplane. At the same time, by providing a light-shielding layer, reflections from the signal lines and the auxiliary signal lines can be avoided. Moreover, the orthographic projection of the light-shielding layer on the substrate coincides with the orthographic projection of the auxiliary signal lines on the substrate, so that the light-shielding layer satisfies the light-shielding function while not reducing the transparency of the driving backplane, thereby solving the problem of low transparency of existing transparent displays.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a preparation method thereof, and a display panel. Background Art

[0002] With the advancement of display technology, transparent displays have become widely used. Besides displaying images for users to see, transparent displays also allow users to see scenery on the other side of the display, greatly enhancing the applicability of display technology. However, the numerous metal traces within transparent displays severely restrict their transparency. Furthermore, to reduce glare from these metal traces, an additional BM process is added. The BM line width is typically approximately 2μm larger than the width of a single metal trace, further reducing the transparency of the transparent display area. Summary of the Invention

[0003] The present application provides a driving backplane and a preparation method thereof, and a display panel to alleviate the technical problem of low transparency of existing transparent displays.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The embodiment of the present application provides a driving backplane, which includes:

[0006] substrate;

[0007] A plurality of signal lines are arranged on one side of the substrate;

[0008] a plurality of auxiliary signal lines, arranged on a side of the signal line away from the substrate, each of the auxiliary signal lines being electrically connected to a corresponding one of the signal lines; and

[0009] a light shielding layer, arranged on a side of the auxiliary signal line away from the signal line;

[0010] The orthographic projection of the auxiliary signal line on the substrate falls within the orthographic projection range of the signal line electrically connected thereto on the substrate, and the orthographic projection of the light shielding layer on the substrate coincides with the orthographic projection of the auxiliary signal line on the substrate.

[0011] In the driving backplane provided in the embodiment of the present application, the plurality of signal lines include a plurality of data lines arranged at intervals along a first direction and a plurality of gate scan lines arranged at intervals along a second direction, and the plurality of auxiliary signal lines include auxiliary data lines electrically connected to the data lines and first auxiliary gate scan lines electrically connected to the gate scan lines; wherein the data lines and the gate scan lines are insulated and cross-define a plurality of sub-pixels.

[0012] In the driving backplane provided in the embodiment of the present application, the plurality of signal lines further include a plurality of first power lines extending along the first direction and a plurality of second power lines extending along the second direction, and the plurality of auxiliary signal lines include a first auxiliary power line electrically connected to the first power line and a second auxiliary power line electrically connected to the second power line; wherein each of the sub-pixels includes a first electrode and a second electrode, the first power line is electrically connected to the first electrode, and the second power line is electrically connected to the second electrode.

[0013] In the driving backplane provided in the embodiment of the present application, each of the sub-pixels also includes multiple thin film transistors, and the first power line is electrically connected to the first electrode through the multiple thin film transistors; wherein each of the thin film transistors includes a gate, a source and a drain, the gate scanning line and the first power line are arranged on the same layer as the gate, and the data line and the second power line are arranged on the same layer as the source and the drain.

[0014] In the driving backplane provided in the embodiment of the present application, a dielectric layer is provided between the auxiliary signal line and the light shielding layer, and the orthographic projection of the dielectric layer on the substrate coincides with the orthographic projection of the light shielding layer on the substrate.

[0015] The present invention also provides a method for preparing a driver backplane, which includes:

[0016] providing a substrate;

[0017] preparing a plurality of signal lines on the substrate;

[0018] A plurality of auxiliary signal lines and a light-shielding layer are prepared on a side of the signal line away from the substrate, the light-shielding layer being located on a side of the auxiliary signal line away from the signal line, so that each of the auxiliary signal lines is electrically connected to a corresponding signal line, and the orthographic projection of the auxiliary signal line on the substrate falls within the range of the orthographic projection of the signal line electrically connected thereto on the substrate, and the orthographic projection of the light-shielding layer on the substrate coincides with the orthographic projection of the auxiliary signal line on the substrate.

[0019] In the method for preparing a driving backplane provided in an embodiment of the present application, the step of preparing a plurality of signal lines on the substrate includes:

[0020] A first metal layer and a second metal layer are deposited on the substrate, and the first metal layer and the second metal layer are patterned to form a plurality of signal lines.

[0021] In the method for preparing a driving backplane provided in an embodiment of the present application, the step of preparing a plurality of auxiliary signal lines and a light shielding layer on a side of the signal line away from the substrate includes:

[0022] depositing a third metal layer, an inorganic thin film, and a light-shielding thin film in sequence on the plurality of signal lines and the substrate;

[0023] The light shielding film, the inorganic film, and the third metal layer are patterned respectively to form the light shielding layer, the dielectric layer, and the plurality of auxiliary signal lines.

[0024] In the method for preparing a driving backplane provided in an embodiment of the present application, the step of separately patterning the light-shielding film, the inorganic film, and the third metal layer to form the light-shielding layer, the dielectric layer, and the plurality of auxiliary signal lines includes:

[0025] Etching the light-shielding film using a yellow light process to form the light-shielding layer;

[0026] Using the light shielding layer as a mask, dry etching is performed on the inorganic thin film to expose the third metal layer and simultaneously form the dielectric layer;

[0027] The third metal layer is etched by wet etching using the light shielding layer as a mask to form the auxiliary signal line.

[0028] An embodiment of the present application further provides a display panel, which includes the driving backplane of one of the aforementioned embodiments.

[0029] The beneficial effects of the present application are as follows: in the driving backplane and its preparation method, and the display panel provided by the present application, multiple auxiliary signal lines are set on the side of the multiple signal lines away from the substrate to reduce the impedance of the multiple signal lines, so that signal lines with smaller widths can be set, thereby reducing the space occupied by the signal lines on the driving backplane, and the positive projections of the multiple auxiliary signal lines on the substrate fall within the positive projection range of the signal lines on the substrate, so that the auxiliary signal lines do not occupy additional space on the driving backplane, thereby improving the transparency of the driving backplane. At the same time, by setting a shading layer, the reflection of the signal lines and the auxiliary signal lines can be avoided, and the positive projection of the shading layer on the substrate coincides with the positive projection of the auxiliary signal lines on the substrate, so that the shading layer does not reduce the transparency of the driving backplane while satisfying the shading effect, thereby solving the problem of low transparency of existing transparent displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic top view of the drive backplane provided in an embodiment of the present application.

[0032] Figure 2 for Figure 1 A detailed structural diagram of a sub-pixel in FIG.

[0033] Figure 3 for Figure 2 Schematic diagram of the circuit structure of the neutron pixel.

[0034] Figure 4 A schematic diagram of a partial cross-sectional structure of a driver backplane provided in an embodiment of the present application.

[0035] Figure 5 A schematic diagram of the detailed structure of the first metal layer provided in an embodiment of the present application.

[0036] Figure 6 A schematic diagram of the detailed structure of the buffer layer opening positions provided in an embodiment of the present application.

[0037] Figure 7 A schematic diagram of the detailed structure of the second metal layer provided in an embodiment of the present application.

[0038] Figure 8 A schematic diagram of the detailed structure of the openings on the interlayer insulating layer provided in an embodiment of the present application.

[0039] Figure 9 A schematic diagram of the detailed structure of the third metal layer provided in an embodiment of the present application.

[0040] Figure 10 A schematic flow chart of a method for preparing a driver backplane according to an embodiment of the present application.

[0041] Figure 11 A schematic cross-sectional view of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0043] Please refer to Figures 1 to 4 , Figure 1 A schematic diagram of a top view of the drive backplane provided in an embodiment of the present application is shown. Figure 2for Figure 1 A detailed structural diagram of a sub-pixel in Figure 3 for Figure 2 Schematic diagram of the circuit structure of the neutron pixel, Figure 4 This is a schematic diagram of a partial cross-section of the driving backplane provided in an embodiment of the present application. The driving backplane 100 includes a substrate 10 and a plurality of signal lines arranged in an array on one side of the substrate 10. The plurality of signal lines include a plurality of data lines DL spaced apart along a first direction X and a plurality of gate scan lines SL spaced apart along a second direction Y. The data lines DL and the gate scan lines SL are insulated and intersected to define a plurality of sub-pixels SP. The first direction X is perpendicular to the second direction Y. For example, the first direction X is horizontal and the second direction Y is vertical, but the present application is not limited thereto.

[0044] Furthermore, if Figure 2 As shown, the plurality of signal lines further include a plurality of first power lines 20 extending along the first direction X and a plurality of second power lines 30 extending along the second direction Y. The first power lines 20 and the second power lines 30 are used to provide driving signals to each of the sub-pixels SP. Optionally, the first power lines 20 are VDD signal lines, and the second power lines 30 are VSS signal lines.

[0045] Each sub-pixel SP includes a first electrode 41 and a second electrode 42. The first power line 20 is electrically connected to the first electrode 41, and the second power line 30 is electrically connected to the second electrode 42. Specifically, each sub-pixel SP also includes multiple thin-film transistors and at least one storage capacitor. The first power line 20 is electrically connected to the first electrode 41 via the multiple thin-film transistors. The following embodiments of the present application are described using an example in which each sub-pixel SP includes two thin-film transistors and one storage capacitor. For example, the sub-pixel SP includes a first thin-film transistor T1, a second thin-film transistor T2, and a first storage capacitor C1, but the present application is not limited thereto.

[0046] Specifically, if Figure 3 As shown, the gate of the first thin-film transistor T1 is electrically connected to the gate scan line SL, the source of the first thin-film transistor T1 is electrically connected to the data line DL, and the drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2 and the first plate of the first storage capacitor C1. The source of the second thin-film transistor T2 is electrically connected to the first power line 20, and the drain of the second thin-film transistor T2 is electrically connected to the second plate of the first storage capacitor C1 and the first electrode 41. The second power line 30 is electrically connected to the second electrode 42.

[0047] The specific film layer structure of each thin film transistor will be described below by taking the second thin film transistor T2 as an example. Figure 4 As shown, the second thin-film transistor T2 includes an active layer 51, a gate 52, a source electrode 53, and a drain electrode 54, and the second thin-film transistor T2 is disposed on the substrate 10. Specifically, the driving backplane 100 further includes a gate insulating layer 11, a buffer layer 12, and an interlayer insulating layer 13 stacked on the substrate 10. The active layer 51 is disposed on the substrate 10, the gate insulating layer 11 covers the active layer 51 and the substrate 10, the gate 52 is disposed on the gate insulating layer 11 and is disposed corresponding to the active layer 51, the buffer layer 12 covers the gate 52 and the substrate 10, the source electrode 53 and the drain electrode 54 are disposed on the buffer layer 12, and the interlayer insulating layer 13 covers the source electrode 53, the drain electrode 54, and the buffer layer 12.

[0048] The structure of the thin film transistor will be further described below in conjunction with the schematic diagram of the top view of each film layer on the driving backplane 100:

[0049] Specifically, please refer to Figure 4 and Figure 5 , Figure 5 The active layer 51 is provided on the substrate 10 , the gate insulating layer 11 covers the active layer 51 and the substrate 10 , and the gate 52 is provided on the gate insulating layer 11 .

[0050] Specifically, an inorganic thin film and a first metal layer are stacked and deposited on the active layer 51 and the substrate 10. The first metal layer is located on the side of the inorganic thin film away from the active layer 51. The first metal layer and the inorganic thin film are patterned. The inorganic thin film forms the gate insulating layer 11, and the first metal layer forms the gate 52 of the second thin-film transistor T2, the gate scan line SL, the first power line 20, and the first electrode C11 of the first storage capacitor C1. The gate insulating layer 11 overlies the active layer 51 and is positioned corresponding to the channel region of the active layer 51. The gate 52 of the second thin-film transistor T2 is positioned on the gate insulating layer 11 and is also positioned corresponding to the channel region of the active layer 51. The active layer 51 located on both sides of the channel region serves as the source and drain regions of the active layer 51.

[0051] Please refer to Figure 4 and Figure 6 , Figure 6A schematic diagram illustrating the detailed structure of the buffer layer opening locations provided in an embodiment of the present application. The buffer layer 12 overlies the gate 52 and the substrate 10. The buffer layer 12 is patterned to form multiple vias, such as a first via 121 and a second via 122 located on either side of the gate 52 of the second thin-film transistor T2, as well as a third via 123 for partially exposing the first power line 20. The buffer layer 12 is made of inorganic materials such as silicon oxide and silicon nitride to block water and oxygen.

[0052] Please refer to Figure 4 and Figure 7 , Figure 7 Detailed structural diagram of the second metal layer provided in an embodiment of the present application. The source electrode 53 and the drain electrode 54 are disposed on the buffer layer 12. The source electrode 53 is electrically connected to the source region of the active layer 51 through the first via 121, and the drain electrode 54 is electrically connected to the drain region of the active layer 51 through the second via 122.

[0053] Specifically, a second metal layer is deposited on the buffer layer 12 and patterned to form the source 53 and drain 54 of the second thin-film transistor T2. Simultaneously, the data line DL, the second power line 30, the second plate C12 of the first storage capacitor C1, a first signal transfer line 61, and a second signal transfer line 62 are formed. The first signal transfer line 61 is electrically connected to the first power line 20 through the third via 123 of the interlayer insulating layer 13, and the second signal transfer line 62 is electrically connected to the gate scan line SL through a via in the interlayer insulating layer 13. Both the first signal transfer line 61 and the second signal transfer line 62 are located between the data line DL and the second power line 30.

[0054] It should be noted that the first power line 20 and the second power line 30 of the present application are not limited to being arranged in different layers and extending in different directions. For example, the first power line 20 and the second power line 30 can also be arranged in the same layer and extend in the same direction.

[0055] Furthermore, in order to reduce the impedance of the plurality of signal lines, the driving backplane 100 further includes a plurality of auxiliary signal lines located on a side of the signal lines away from the substrate 10 , and each of the auxiliary signal lines is electrically connected to a corresponding one of the signal lines.

[0056] Specifically, please refer to Figures 4 to 9 , Figure 8 This is a schematic diagram of the detailed structure of the opening on the interlayer insulating layer provided in the embodiment of the present application. Figure 9Detailed structural diagram of the third metal layer provided in an embodiment of the present application. The interlayer insulating layer 13 overlies the source 53, the drain 54, and the buffer layer 12, and the auxiliary signal line is disposed on the interlayer insulating layer 13. The interlayer insulating layer 13 is patterned to form a plurality of vias, such as a fourth via 131 exposing a portion of the first signal transfer line 61 and a fifth via 132 exposing a portion of the second power line 30. Furthermore, the vias also expose the second signal transfer line 62, the data line DL, and the first plate C11.

[0057] In addition, the interlayer insulating layer 13 is provided with a via at a position corresponding to a portion of the drain electrode 54 of the second thin film transistor T2 and a portion of the second power line 30, and the first electrode 41 and the second electrode 42 are arranged in the via hole of the interlayer insulating layer 13, wherein the first electrode 41 is electrically connected to the drain electrode 54 of the second thin film transistor T2, and the second electrode 42 is electrically connected to the second power line 30.

[0058] A third metal layer is deposited on the interlayer insulating layer 13 and patterned to form a plurality of auxiliary signal lines. Specifically, the patterned third metal layer includes a first auxiliary power line 21, a second auxiliary power line 31, an auxiliary data line DDL, an auxiliary gate scan line DSL, and an auxiliary first electrode plate DC11. The first auxiliary power line 21 is electrically connected to the first signal adapter line 61 through the fourth via 131, thereby electrically connecting the first auxiliary power line 21 to the first power line 20. The second auxiliary power line 31 is electrically connected to the second power line 30 through the fifth via 132. The auxiliary data line DDL is electrically connected to the data line DL through a via in the interlayer insulating layer 13. The auxiliary gate scan line DSL is electrically connected to the second signal adapter line 62 through a via in the interlayer insulating layer 13, thereby electrically connecting the auxiliary gate scan line DSL to the gate scan line SL. The auxiliary first electrode plate DC11 is electrically connected to the first electrode plate C11 through a via in the interlayer insulating layer 13. The orthographic projection of each auxiliary signal line on the substrate 10 falls within the orthographic projection range of the signal line electrically connected thereto on the substrate 10 .

[0059] By setting multiple auxiliary signal lines on the side of the multiple signal lines away from the substrate 10 to reduce the impedance of the multiple signal lines, signal lines with smaller widths can be set, thereby reducing the space occupied by the signal lines on the driving backplane 100. The orthographic projections of the multiple auxiliary signal lines on the substrate 10 fall within the orthographic projection range of the signal lines on the substrate 10, so that the auxiliary signal lines will not occupy additional space on the driving backplane 100, thereby improving the transparency of the driving backplane 100.

[0060] Furthermore, in order to avoid reflections from each of the signal lines and each of the auxiliary signal lines, the driving backplane 100 further includes a light-shielding layer 70, which is arranged on the side of the auxiliary signal line away from the signal line. Moreover, the orthographic projection of the light-shielding layer 70 on the substrate 10 coincides with the orthographic projection of the auxiliary signal line on the substrate 10. Specifically, a dielectric layer 14 is provided between the auxiliary signal line and the light-shielding layer 70, and the orthographic projection of the dielectric layer 14 on the substrate 10 coincides with the orthographic projection of the light-shielding layer 70 on the substrate 10. In this way, by providing the light-shielding layer 70, reflections from the signal lines and the auxiliary signal lines can be avoided, and the orthographic projection of the light-shielding layer 70 on the substrate 10 coincides with the orthographic projection of the auxiliary signal line on the substrate 10, so that the light-shielding layer 70 does not reduce the transparency of the driving backplane 100 while satisfying the light-shielding effect, thereby solving the problem of low transparency of existing transparent displays.

[0061] In one embodiment, please refer to Figures 1 to 10 , Figure 10 The process diagram of the driver backplane manufacturing method provided in the embodiment of the present application is as follows:

[0062] S301: Provide substrate;

[0063] Optionally, the substrate 10 may be a rigid substrate 10 or a flexible substrate 10. When the substrate 10 is a rigid substrate 10, it may include a rigid transparent substrate 10 such as a glass substrate 10. When the substrate 10 is a flexible substrate 10, it may include a flexible transparent substrate 10 such as a polyimide (PI) film or an ultra-thin glass film. This embodiment uses a glass substrate 10 as an example for description.

[0064] S302: preparing a plurality of signal lines on the substrate;

[0065] Specifically, a first metal layer and a second metal layer are deposited on the substrate 10, and the first metal layer and the second metal layer are patterned to form a plurality of signal lines. Specifically, the patterned first metal layer is formed with the gate scan line SL, the first power line 20 and other signal lines, such as Figure 5 The second metal layer is patterned to form the data line DL, the second power line 30 and other signal lines, as shown Figure 7 shown.

[0066] S303: Prepare multiple auxiliary signal lines and a shading layer 70 on the side of the signal line away from the substrate 10, the shading layer 70 is located on the side of the auxiliary signal line away from the signal line, so that each of the auxiliary signal lines is electrically connected to a corresponding signal line, and the orthographic projection of the auxiliary signal line on the substrate 10 falls within the orthographic projection range of the signal line electrically connected to it on the substrate 10, and the orthographic projection of the shading layer 70 on the substrate 10 coincides with the orthographic projection of the auxiliary signal line on the substrate 10.

[0067] Specifically, a third metal layer, an inorganic thin film, and a light shielding film are sequentially deposited on the plurality of signal lines and the substrate 10. The light shielding film, the inorganic thin film, and the third metal layer are patterned to form the light shielding layer 70, the dielectric layer 14, and the plurality of auxiliary signal lines.

[0068] Specifically, the light-shielding film is etched by a yellow light process to form the light-shielding layer 70; the inorganic film is etched by dry etching using the light-shielding layer 70 as a mask to expose the third metal layer and simultaneously form the dielectric layer 14; the third metal layer is etched by wet etching using the light-shielding layer 70 as a mask to form the auxiliary signal line.

[0069] The auxiliary signal lines include a first auxiliary power line 21, a second auxiliary power line 31, an auxiliary data line DDL, an auxiliary gate scan line DSL, etc. Figure 9 As shown. The first auxiliary power line 21 is electrically connected to the first power line 20. The second auxiliary power line 31 is electrically connected to the second power line 30. The auxiliary data line DDL is electrically connected to the data line DL. The auxiliary gate scan line DSL is electrically connected to the gate scan line SL. The orthographic projection of each auxiliary signal line on the substrate 10 falls within the orthographic projection of the signal line electrically connected to it on the substrate 10, and the orthographic projection of the light shielding layer 70 on the substrate 10 coincides with the orthographic projection of the auxiliary signal line on the substrate 10.

[0070] In this embodiment, the auxiliary signal lines are formed by self-alignment using the light shielding layer 70 as a mask, allowing the light shielding layer 70 and the auxiliary signal lines to be formed in the same process, thereby saving one mask, reducing production tact time, and lowering production costs. Furthermore, the driver backplane manufacturing method of the present application, by simultaneously forming the light shielding layer 70 and the auxiliary signal lines, avoids the problem of reduced transparency caused by the need to provide a wider light shielding layer 70 due to misalignment between the light shielding layer 70 and the auxiliary signal lines when using two processes.

[0071] Based on the same inventive concept, the present application also provides a display panel. Figures 1 to 11 , Figure 11 A schematic cross-sectional view of a display panel provided in an embodiment of the present application. The display panel 1000 includes a driver backplane 100 according to one of the aforementioned embodiments. Optionally, the display panel 1000 also includes a light-emitting device 200, which is attached to the driver backplane 100 and includes, for example, an LED chip.

[0072] According to the above embodiments, it can be seen that:

[0073] The present application provides a driving backplane and its preparation method, as well as a display panel. In this application, multiple auxiliary signal lines are provided on a side of multiple signal lines away from a substrate to reduce the impedance of the multiple signal lines, thereby allowing the provision of signal lines with smaller widths, thereby reducing the space occupied by the signal lines on the driving backplane. The orthographic projections of the multiple auxiliary signal lines on the substrate fall within the orthographic projection range of the signal lines on the substrate, so that the auxiliary signal lines do not occupy additional space on the driving backplane, thereby improving the transparency of the driving backplane. At the same time, by providing a light-shielding layer, reflections from the signal lines and the auxiliary signal lines can be avoided. Moreover, the orthographic projection of the light-shielding layer on the substrate coincides with the orthographic projection of the auxiliary signal lines on the substrate, so that the light-shielding layer satisfies the light-shielding function while not reducing the transparency of the driving backplane, thereby solving the problem of low transparency of existing transparent displays.

[0074] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving backplane, characterized in that: include: substrate; A plurality of signal lines are arranged on one side of the substrate; a plurality of auxiliary signal lines, arranged on a side of the signal line away from the substrate, each of the auxiliary signal lines being electrically connected to a corresponding one of the signal lines; as well as a light shielding layer, arranged on a side of the auxiliary signal line away from the signal line; In which, the orthographic projection of the auxiliary signal line on the substrate falls within the orthographic projection range of the signal line electrically connected to it on the substrate, the orthographic projection of the shading layer on the substrate coincides with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the shading layer on the substrate falls within the orthographic projection range of the corresponding signal line on the substrate.

2. The driving backplane according to claim 1, characterized in that: The plurality of signal lines include a plurality of data lines arranged at intervals along a first direction and a plurality of gate scan lines arranged at intervals along a second direction, and the plurality of auxiliary signal lines include auxiliary data lines electrically connected to the data lines and first auxiliary gate scan lines electrically connected to the gate scan lines; wherein the data lines and the gate scan lines are insulated and crossed to define a plurality of sub-pixels.

3. The driving backplane according to claim 2, characterized in that: The plurality of signal lines further include a plurality of first power lines extending along the first direction and a plurality of second power lines extending along the second direction, and the plurality of auxiliary signal lines include a first auxiliary power line electrically connected to the first power line and a second auxiliary power line electrically connected to the second power line; wherein each of the sub-pixels includes a first electrode and a second electrode, the first power line is electrically connected to the first electrode, and the second power line is electrically connected to the second electrode.

4. The driving backplane according to claim 3, characterized in that: Each of the sub-pixels also includes multiple thin film transistors, and the first power line is electrically connected to the first electrode through the multiple thin film transistors; each of the thin film transistors includes a gate, a source and a drain, the gate scan line and the first power line are arranged on the same layer as the gate, and the data line and the second power line are arranged on the same layer as the source and the drain.

5. The driving backplane according to claim 1, characterized in that: A dielectric layer is provided between the auxiliary signal line and the light shielding layer, and an orthographic projection of the dielectric layer on the substrate coincides with an orthographic projection of the light shielding layer on the substrate.

6. A method for preparing a driving backplane, characterized in that: include: providing a substrate; preparing a plurality of signal lines on the substrate; A plurality of auxiliary signal lines and a light-shielding layer are prepared on a side of the signal line away from the substrate, the light-shielding layer is located on a side of the auxiliary signal line away from the signal line, each of the auxiliary signal lines is electrically connected to a corresponding signal line, and the orthographic projection of the auxiliary signal line on the substrate falls within the orthographic projection range of the signal line electrically connected thereto on the substrate, the orthographic projection of the light-shielding layer on the substrate coincides with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the light-shielding layer on the substrate falls within the orthographic projection range of the corresponding signal line on the substrate.

7. The method for preparing a driving backplane according to claim 6, wherein: The step of preparing a plurality of signal lines on the substrate comprises: A first metal layer and a second metal layer are deposited on the substrate, and the first metal layer and the second metal layer are patterned to form a plurality of signal lines.

8. The method for preparing a driving backplane according to claim 7, wherein: The step of preparing a plurality of auxiliary signal lines and a light shielding layer on a side of the signal line away from the substrate comprises: depositing a third metal layer, an inorganic thin film, and a light-shielding thin film in sequence on the plurality of signal lines and the substrate; The light shielding film, the inorganic film, and the third metal layer are patterned respectively to form the light shielding layer, the dielectric layer, and the plurality of auxiliary signal lines.

9. The method for preparing a driving backplane according to claim 8, wherein: The step of patterning the light shielding film, the inorganic film, and the third metal layer to form the light shielding layer, the dielectric layer, and the plurality of auxiliary signal lines comprises: Etching the light-shielding film using a yellow light process to form the light-shielding layer; Using the light shielding layer as a mask, dry etching is performed on the inorganic thin film to expose the third metal layer and simultaneously form the dielectric layer; The third metal layer is etched by wet etching using the light shielding layer as a mask to form the auxiliary signal line.

10. A display panel, characterized in that: The drive back plate comprises the drive back plate according to any one of claims 1 to 5.

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