Integrated circuit chip and method of forming the same

Abstract

Various embodiments of the present disclosure are directed to ferroelectric random access memory cells or some other suitable type of memory cells that include a bottom electrode interface structure. The memory cells also include a bottom electrode, a switching layer above the bottom electrode, and a top electrode above the switching layer. The bottom electrode interface structure separates the bottom electrode and the switching layer from one another. Moreover, the interface structure is dielectric and is configured to block or otherwise resist diffusion of metal atoms and / or impurities in the bottom electrode to the switching layer. By blocking or otherwise resisting such diffusion, leakage current can be reduced. Moreover, the durability of the memory cells can be increased. Various embodiments of the present disclosure are also directed to integrated circuit chips and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit chips and methods for forming the same. Background Technology

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data even when power is off. Some promising candidates for next-generation non-volatile memory include ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Summary of the Invention

[0003] According to one aspect of the present invention, an integrated circuit chip including a memory cell is provided, wherein the memory cell includes: a bottom electrode; a switching layer located above the bottom electrode; a top electrode located above the switching layer; and an interface structure separating the bottom electrode and the switching layer from each other, wherein the interface structure is a dielectric and is configured to prevent metal atoms and / or impurities in the bottom electrode from diffusing to the switching layer.

[0004] According to another aspect of the present invention, an integrated circuit chip is provided, including a ferroelectric random access memory cell, wherein the ferroelectric random access memory cell includes: a bottom electrode; a ferroelectric switching layer located above the bottom electrode; a top electrode located above the ferroelectric switching layer; and an interface structure separating the bottom electrode from the ferroelectric switching layer, wherein the interface structure is a dielectric and includes metallic and non-metallic elements, wherein the metallic elements are shared by the interface structure and the bottom electrode, and wherein the concentration of the non-metallic elements decreases from the top to the bottom of the interface structure.

[0005] According to another aspect of the present invention, a method for forming an integrated circuit chip is provided, comprising: depositing a bottom electrode layer covering and electrically coupled to wires; plasma treating the top surface of the bottom electrode layer to form an interface layer covering the bottom electrode layer; depositing a switching layer over the interface layer using a precursor gas, wherein the interface layer is configured to block the precursor gas from diffusing to the bottom electrode layer and interacting with the bottom electrode layer; depositing a top electrode layer over the switching layer; and patterning the bottom electrode layer, the top electrode layer, the switching layer, and the interface layer to form a memory cell. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of a memory cell including a bottom electrode interface structure are shown.

[0008] Figures 2A-2C Show Figure 1 Cross-sectional views of some alternative embodiments of the memory cell.

[0009] Figure 3 Show Figure 1 Enlarged cross-sectional views of some embodiments of memory cells, wherein the memory cells are in the interconnect structure of an integrated circuit (IC) chip.

[0010] Figures 4A-4E Show Figure 3 Cross-sectional views of some alternative embodiments of the memory cell.

[0011] Figure 5A and Figure 5B Cross-sectional views of some embodiments of an IC chip are shown, in which memory cells are integrated with separate transistor-resistor (IT1R) cells and include separate bottom electrode interface structures.

[0012] Figure 6 Show Figure 5A and Figure 5B The top layout of some embodiments of the IC chip.

[0013] Figure 7 Show Figure 5A Cross-sectional views of some alternative embodiments of the IC chip, wherein the memory cells have different layouts.

[0014] Figures 8-19 The illustration shows a series of cross-sectional views of some embodiments of a method for forming a memory cell integrated with a 1T1R cell and including a bottom electrode interface structure.

[0015] Figure 20 Show Figures 8-19 Block diagrams of some embodiments of the method. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0018] Ferroelectric random access memory (FeRAM) cells can be overlaid on wires in the interconnect structure of an integrated circuit (IC) chip. A FeRAM cell may include a bottom electrode, a ferroelectric switching layer above the bottom electrode, and a top electrode layer covering the ferroelectric switching layer. The bottom electrode extends toward and is electrically coupled to the wires via a barrier layer. The barrier layer separates the bottom electrode from the wires and prevents material migration from the wires to the bottom electrode.

[0019] The challenge of FeRAM cells is that active metal atoms from the barrier layer can diffuse to the bottom electrode. Furthermore, active metal atoms and / or impurities in the bottom electrode can diffuse from the bottom electrode to the ferroelectric switching layer. Active metal atoms have high diffusion coefficients and can include, for example, copper atoms, tantalum atoms, other suitable metal atoms, or any combination thereof. Impurities can diffuse into the bottom electrode during the deposition of the ferroelectric switching layer and can include, for example, chloride ions and / or other suitable ions from precursors used during the deposition of the ferroelectric switching layer. Active metal atoms and / or impurities can increase leakage current and therefore may cause data degradation.

[0020] Various embodiments of this disclosure pertain to FeRAM cells or some other suitable type of memory cell, including a bottom electrode interface structure. The memory cell covers wires in the interconnect structure of an IC chip and also includes a bottom electrode and a switching layer. Where the memory cell is an FeRAM cell, the switching layer may be a ferroelectric switching layer. The bottom electrode extends toward and is electrically coupled to the wires via a barrier layer. The barrier layer separates the bottom electrode from the wires and is configured to block or otherwise reduce the diffusion of active metal atoms from the wires to the bottom electrode. The switching layer covers the bottom electrode and is separated from it via a bottom electrode interface structure. The bottom electrode interface structure is dielectric and is configured to block or otherwise reduce the diffusion of active metal atoms and / or impurities from the bottom electrode to the switching layer. For example, such active metal atoms may migrate from the barrier layer to the bottom electrode or may be otherwise created at the bottom electrode.

[0021] By blocking or otherwise reducing the diffusion of active metal atoms and / or impurities from the barrier layer and / or bottom electrode to the switching layer, the bottom electrode interface structure can reduce leakage current at the switching layer. By reducing leakage current in the switching layer, the bottom electrode interface structure can enhance data retention in the memory cell, thereby improving memory cell reliability. Furthermore, the bottom electrode interface structure can also be configured to block or otherwise reduce the diffusion of active metal atoms from the wires to the switching layer, thus eliminating the need for a barrier layer. Eliminating the barrier layer reduces material and processing costs.

[0022] refer to Figure 1 A cross-sectional view 100 is provided for some embodiments of a memory cell 102 including a bottom electrode interface structure 104. As described above, the bottom electrode interface structure 104 is configured to block or otherwise reduce the diffusion of impurities and / or active metal atoms from the bottom electrode 106 to the switching layer 108. This can reduce leakage current and thus improve durability.

[0023] Memory cell 102 is overlaid on bottom metal structure 110 and can be, for example, a FeRAM cell, a resistive random access memory (RRAM) cell, or some other suitable type of memory cell. Bottom metal structure 110 can be, for example, a wire, a via, a contact, or some other suitable structure. Memory cell 102 includes a bottom electrode barrier layer 112, a bottom electrode 106, a bottom electrode interface structure 104, a switching layer 108, and a top electrode 114 stacked on top of bottom metal structure 110.

[0024] The bottom electrode 106, bottom electrode barrier layer 112, top electrode 114, and bottom metal structure 110 are conductive, and the bottom electrode barrier layer 112 is dielectric. Furthermore, with respect to the memory cell 102 being an FeRAM cell, the switch layer 108 is ferroelectric. The bottom electrode barrier layer 112 covers the bottom metal structure 110, and the bottom electrode 106 covers the bottom electrode barrier layer 112, such that the bottom electrode barrier layer 112 separates the bottom electrode 106 from the bottom metal structure 110. The bottom electrode interface structure 104 covers the bottom electrode 106, and the switch layer 108 covers the bottom electrode interface structure 104, such that the bottom electrode interface structure 104 separates the bottom electrode 106 from the switch layer 108. The top electrode 114 covers the switch layer 108.

[0025] The bottom electrode interface structure 104 is a dielectric and is a different material from the bottom electrode 106 and the switching layer 108. The bottom electrode interface structure 104 is configured to block or otherwise resist the diffusion or migration of material used during the formation of the switching layer 108 into the bottom electrode 106 and the resulting impurities in the bottom electrode 106. For example, the switching layer 108 can be formed by atomic layer deposition (ALD) or some other suitable deposition process using gaseous precursors. The bottom electrode interface structure 104 can block or otherwise prevent the diffusion of gaseous precursors into the bottom electrode 106 during the deposition process.

[0026] Without the bottom electrode interface structure 104, materials used during the formation of the switching layer 108 might diffuse into the bottom electrode 106 and could result in impurities in the bottom electrode 106. For example, chloride and / or oxide precursors might diffuse into the bottom electrode 106. The bottom electrode 106 might generate substances including chloride ions (e.g., Cl-). - ) and / or oxygen ions (O - Impurities in the bottom electrode 106 can diffuse into the switching layer 108 after the switching layer 108 is formed, without the bottom electrode interface structure 104. This could lead to increased leakage current, which could cause data retention degradation and thus reduce the reliability of the memory cell 102. Therefore, the bottom electrode interface structure 104 reduces leakage current by preventing impurities in the bottom electrode 106. This enhances data retention and thus the reliability of the memory cell 102. Furthermore, by reducing leakage current, the breakdown voltage of the memory cell 102 can be increased.

[0027] In some embodiments, the bottom electrode interface structure 104 is inert to the materials used during the formation of the switching layer 108. Inertness means that the bottom electrode interface structure 104 does not react with the materials and / or relies on more energy to react with the materials than the bottom electrode 106. In embodiments where the switching layer 108 is deposited by ALD, inertness allows precursors to react fully or more completely with each other. This, in turn, reduces the likelihood of non-reactive precursors contaminating the switching layer 108 and thus increasing leakage current. Therefore, the bottom electrode interface structure 104 can further reduce leakage current at the switching layer 108, which can enhance data retention and thus enhance the reliability of the memory cell 102.

[0028] In some embodiments, impurities enter the bottom electrode 106 during the formation of the bottom electrode 106 and / or between the formation of the bottom electrode 106 and the switching layer 108. The bottom electrode interface structure 104 is also configured to block or otherwise prevent these impurities from diffusing from the bottom electrode 106 to the switching layer 108 to further reduce leakage current. As described above, by reducing leakage current, data retention and thus the reliability of the memory cell 102 can be enhanced.

[0029] In some embodiments, the bottom electrode barrier layer 112 comprises active metal atoms, and the bottom electrode 106 and / or the bottom electrode interface structure 104 are configured to block or otherwise prevent the diffusion of active metal atoms to the switching layer 108. As used herein, the active metal atoms are metal atoms having a high diffusion coefficient. A high diffusion coefficient can be, for example, greater than about 10. -13 square centimeters per second (cm) 2 s -1 ), 10 -12 cm 2 s -1 10 -11 cm 2 s -1 Or some other suitable amount of diffusion coefficient. Non-limiting examples of active metal atoms include, for example, copper atoms, tantalum atoms, etc. By blocking or otherwise preventing the diffusion of active metal atoms from the bottom electrode barrier layer 112 to the switch layer 108, the bottom electrode 106 and / or the bottom electrode interface structure 104 can reduce leakage current. By reducing leakage current, data retention and thus the reliability of the memory cell 102 can be enhanced.

[0030] In some embodiments, the bottom electrode 106 includes active metal atoms, and the bottom electrode interface structure 104 is configured to block or otherwise prevent the diffusion of active metal atoms into the switching layer 108. By blocking or otherwise preventing active metal atoms from the bottom electrode 106, the bottom electrode interface structure 104 can reduce leakage current. By reducing leakage current, data retention in the memory cell 102 can be enhanced, and thus the reliability of the memory cell 102 can be improved.

[0031] In some embodiments, the bottom electrode 106 blocks or otherwise prevents the diffusion of active metal atoms from the bottom electrode barrier layer 112 by: 1) being more amorphous and / or less crystalline than the bottom electrode barrier layer 112; 2) having an average grain size larger or smaller than the average grain size of the bottom electrode barrier layer 112; 3) having a different lattice constant than the bottom electrode barrier layer 112; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms; or 5) any combination of the foregoing. For example, the bottom electrode 106 may be or comprise titanium nitride having a nitrogen atom percentage of about 50% or some other suitable percentage, while the bottom electrode barrier layer 112 may be or comprise tantalum and / or tantalum nitride. However, other suitable materials are also feasible.

[0032] The amorphous state and crystallinity cited throughout this disclosure can be quantified, for example, by X-ray diffraction (XRD), electron backscatter diffraction (EBSD), differential scanning calorimetry (DSC), or any other suitable technique. Furthermore, such quantification can be used, for example, for relative comparisons between amorphous states and crystallinity, as described throughout this disclosure.

[0033] In some embodiments, the bottom electrode interface structure 104 blocks or otherwise prevents the diffusion of active metal atoms and / or impurities from or into the bottom electrode 106 by: 1) being more amorphous and / or less crystalline than the bottom electrode 106; 2) having an average grain size larger or smaller than the average grain size of the bottom electrode 106; 3) having a different lattice constant than the bottom electrode 106; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms and / or impurities; or 5) any combination of the foregoing. In some embodiments, the bottom electrode interface structure 104 is amorphous, while the bottom electrode 106 is crystalline.

[0034] The bottom metal structure 110 is an active metal atom or comprises active metal atoms, and the bottom electrode barrier layer 112 is configured to block or otherwise prevent the diffusion of active metal atoms from the bottom metal structure 110 to the bottom electrode 106. In some embodiments, the bottom electrode barrier layer 112 achieves this by: 1) being more amorphous and / or less crystalline than the bottom metal structure 110; 2) having an average grain size that is larger or smaller than the average grain size of the bottom metal structure 110; 3) having a different lattice constant than the bottom metal structure 110; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms; or 5) any combination of the foregoing.

[0035] In at least some embodiments where the bottom electrode barrier layer 112 includes active metal atoms, the active metal atoms of the bottom metal structure 110 correspond to a different metal element 112 than the active metal atoms of the bottom electrode barrier layer. For example, the active metal atoms of the bottom metal structure 110 may correspond to copper, while the active metal atoms of the bottom electrode barrier layer 112 may correspond to tantalum. However, other suitable elements are acceptable. In some embodiments, the active metal atoms of the bottom electrode barrier layer 112 have a first diffusion coefficient, and the active metal atoms of the bottom metal structure 110 have a larger second diffusion coefficient.

[0036] The switching layer 108 has properties for representing data bits and is configured to reversibly switch between a first state and a second state. For example, the first state can represent a binary "1", while the second state can represent a binary "0", and vice versa. For example, this property can correspond to resistance, residual polarization, some other suitable property, or any combination thereof.

[0037] In an embodiment where memory cell 102 is a FeRAM cell, switching layer 108 has residual polarization. A first state of residual polarization represents binary "1", and a second state of residual polarization represents binary "0", and vice versa. The residual polarization can be set to the first state by applying a first voltage exceeding the coercive voltage from top electrode 114 to bottom electrode 106. Furthermore, the residual polarization can be set to the second state by applying a second voltage exceeding the coercive voltage and having the opposite polarity to the first voltage from top electrode 114 to bottom electrode 106. The state of the residual polarization can be electrically determined by setting it to the first state. If the residual polarization is in the second state, a current pulse is generated. Otherwise, no current pulse is generated.

[0038] In some embodiments, the bottom electrode 106 is or includes tantalum nitride, molybdenum, titanium nitride, tungsten nitride, iridium, ruthenium, etc. In some embodiments, the thickness T of the bottom electrode 106 is... beFor approximately 50-500 angstroms, approximately 50-275 angstroms, approximately 275-500 angstroms, or some other suitable value.

[0039] In some embodiments, the bottom electrode 106 is or comprises inactive metal atoms. Furthermore, in some embodiments, within the range of all metal atoms in the bottom electrode 106, the bottom electrode 106 is substantially composed of inactive metal atoms and / or the metal atoms are substantially composed of inactive metal atoms. As used herein, inactive metal atoms are metal atoms having a low diffusion coefficient. A low diffusion coefficient can be, for example, less than about 10. -13 cm 2 s -1 10 -14 cm 2 s -1 Or some other suitable amount of diffusion coefficient.

[0040] In some embodiments, the bottom electrode 106 is or includes active metal atoms. Furthermore, in some embodiments, within the range of all metal atoms in the bottom electrode 106, the bottom electrode 106 is substantially composed of active metal atoms and / or the metal atoms are substantially composed of active metal atoms. Non-limiting examples of materials having active metal atoms include, for example, tantalum, copper, etc.

[0041] In some embodiments, the bottom electrode barrier layer 112 is or includes tantalum, tantalum nitride, some other suitable material, or any combination of the foregoing. In some embodiments, the bottom electrode barrier layer 112 is a single-layer film. In alternative embodiments, the bottom electrode barrier layer 112 is a multilayer film. For example, the bottom electrode barrier layer 112 may be a two-layer film comprising a tantalum nitride layer and a tantalum layer covering the tantalum nitride layer. In some embodiments, the bottom metal structure 110 is or includes copper, aluminum copper, tantalum, some other suitable material, or any combination of the foregoing.

[0042] In some embodiments, the switching layer 108 is a high-k dielectric and / or comprises a metal oxide. In some embodiments, the switching layer 108 is or comprises an orthorhombic hafnium oxide-based film, a zirconium oxide-based film, etc. For example, the switching layer 108 may be or comprises hafnium zirconium oxide (e.g., HfZrO or HZO), hafnium aluminum oxide (e.g., HfAlO), hafnium lanthanum oxide (e.g., HfLaO), hafnium cerium oxide (e.g., HfCeO), hafnium oxide (e.g., HfO), hafnium silicon oxide (e.g., HfSiO), hafnium gadolinium oxide (e.g., HfGdO), etc. In some embodiments, the switching layer 108 is doped with a dopant atomic percentage equal to or less than about 50%, 40%, 25%, or some other suitable percentage. Dopant may be, for example, or include aluminum (e.g., Al), silicon (e.g., Si), lanthanum (e.g., La), scandium (e.g., Sc), calcium (e.g., Ca), barium (e.g., Ba), gadolinium (e.g., Gd), yttrium (e.g., Y), strontium (e.g., Sr), some other suitable elements, or any combination of the above elements. In embodiments where memory cell 102 is an FeRAM cell and therefore switch layer 108 is ferroelectric, the ratio of orthorhombic, tetragonal, and cubic phases to orthorhombic, tetragonal, cubic, and monoclinic phases in switch layer 108 is greater than about 0.5 or some other suitable value.

[0043] In some embodiments, the thickness T of the switching layer 108 sl For approximately 20-500 angstroms, approximately 20-260 angstroms, approximately 260-500 angstroms, or some other suitable value. If the thickness T... sl If the thickness is too small (e.g., less than about 20 angstroms), the crystallinity of the switching layer 108 may be poor, resulting in a low breakdown voltage. On the other hand, if the thickness T... sl If the voltage is too high (e.g., greater than about 500 angstroms), the operating voltage of memory cell 102 may be high.

[0044] In some embodiments, the bottom electrode interface structure 104 is or includes a metal oxide, a metal nitride, a metal oxide oxynitride, etc. For example, the bottom electrode interface structure 104 may be or includes titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, etc. In at least some embodiments where the bottom electrode 106 is or includes titanium nitride, the bottom electrode interface structure 104 is or includes titanium oxynitride, etc. In at least some embodiments where the bottom electrode 106 is or includes tantalum nitride, the bottom electrode interface structure 104 is or includes tantalum oxynitride, etc.

[0045] In some embodiments, the bottom electrode interface structure 104 is or includes an oxide or oxynitride of an active metal atom. In other embodiments, the bottom electrode interface structure 104 is or includes inactive metal atoms. Furthermore, in some embodiments, the bottom electrode interface structure 104 is substantially composed of inactive metal atoms and / or the metal atoms are substantially composed of inactive metal atoms within the range of all metal atoms in the bottom electrode interface structure 104. In some embodiments, the bottom electrode interface structure 104 and the bottom electrode 106 share a common metal, which may be active or inactive. In some embodiments, the concentration of non-metallic elements (e.g., nitrogen, oxygen, etc.) in the bottom electrode interface structure 104 decreases from the top to the bottom of the bottom electrode interface structure 104. The concentration may decrease continuously or discretely from top to bottom.

[0046] In some embodiments, the bottom electrode interface structure 104 comprises or is substantially composed of a metallic element and a first non-metallic element. In some embodiments, the bottom electrode 106 shares the metallic element, and the bottom electrode 106 does not contain the first non-metallic element. Furthermore, in some embodiments, the bottom electrode interface structure 104 also includes a second non-metallic element different from the first non-metallic element. In some embodiments, the metallic element and the second non-metallic element are shared by the bottom electrode 106, and the bottom electrode 106 does not contain the first non-metallic element. For example, the first non-metallic element and the second non-metallic element may be oxygen, nitrogen, or some other suitable element, respectively.

[0047] In some embodiments, the interface at the bottom surface of the switching layer 108 has a smaller arithmetic mean roughness than would exist without the bottom electrode interface structure 104. A bottom electrode interface structure 104 is present, with the interface between the bottom electrode interface structure 104 and the switching layer 108. Without the bottom electrode interface structure 104, the interface is between the bottom electrode 106 and the switching layer 108. In some embodiments, the smaller arithmetic mean roughness is about 3 angstroms, less than about 3 angstroms, about 2-3 angstroms, or some other suitable value. The arithmetic mean roughness can be measured, for example, by atomic force microscopy (AFM). A smaller arithmetic mean roughness can enhance the electric field uniformity across the switching layer 108 and thus enhance durability.

[0048] In some embodiments, the thickness T of the bottom electrode interface structure 104 ifs For approximately 20-200 angstroms, approximately 20-110 angstroms, approximately 110-200 angstroms, or some other suitable value. If the thickness T... ifs If the thickness is too small (e.g., less than about 20 angstroms), the bottom electrode interface structure 104 may not be able to block the diffusion of active metal atoms and / or impurities through it. Therefore, the bottom electrode interface structure 104 may not be able to reduce leakage current. If the thickness T...ifs If it is too large (e.g., more than about 200 angstroms), it may present process challenges.

[0049] In some embodiments, the top electrode 114 is or includes tantalum nitride, molybdenum, titanium nitride, tungsten nitride, iridium, ruthenium, etc. In some embodiments, the top electrode 114 is or includes the same material as the bottom electrode 106. In other embodiments, the top electrode 114 is a different material from the bottom electrode 106. In some embodiments, the top electrode 114 is or includes inactive metal atoms. Furthermore, in some embodiments, within the range of all metal atoms in the top electrode 114, the top electrode 114 is substantially composed of inactive metal atoms and / or the metal atoms are substantially composed of inactive metal atoms. In some embodiments, the top electrode 114 is or includes a nitride of active metal atoms. In some embodiments, the thickness of the top electrode 114 is about 50-500 angstroms, about 50-275 angstroms, about 275-500 angstroms, or some other suitable value.

[0050] refer to Figures 2A-2C Provided Figure 1 Cross-sectional views 200A-200C show some alternative embodiments of the memory cell 102.

[0051] exist Figure 2A In this configuration, the bottom electrode blocking layer 112 is omitted, and the bottom electrode 106 directly contacts the bottom metal structure 110. Thus, the bottom electrode 106 and / or the bottom electrode interface structure 104 are configured to block or otherwise prevent the diffusion of active metal atoms from the bottom metal structure 110 to the switching layer 108. By blocking or otherwise preventing the diffusion of active metal atoms to the switching layer 108, the bottom electrode 106, and / or the bottom electrode interface structure 104, leakage current can be reduced. Reducing leakage current enhances data retention in the memory cell 102 and thus improves reliability. However, the breakdown voltage may increase.

[0052] In some embodiments, the bottom electrode 106 blocks or otherwise resists the diffusion of active metal atoms by: 1) being more amorphous and / or less crystalline than the bottom metal structure 110; 2) having an average grain size larger or smaller than the average grain size of the bottom metal structure 110; 3) having a different lattice constant than the bottom metal structure 110; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms; or 5) any combination of the foregoing. For example, the bottom electrode 106 may be or comprise titanium nitride having a nitrogen atom percentage of about 50% or some other suitable percentage, while the bottom metal structure 110 may be or comprise copper and / or aluminum copper. However, other suitable materials are also feasible. In some embodiments, the bottom electrode interface structure 104 blocks or otherwise resists the diffusion of active metal atoms from the bottom metal structure 110 by: 1) being more amorphous and / or less crystalline than the bottom electrode 106; 2) having an average grain size that is larger or smaller than the average grain size of the bottom electrode 106; 3) having a different lattice constant than the bottom electrode 106; 4) being composed of atoms with atomic radii greater than and / or smaller than those of active metal atoms and / or impurities; or 5) any combination of the foregoing.

[0053] exist Figure 2B In this embodiment, the bottom electrode interface structure 104 includes multiple interface layers 104a-104c stacked between the bottom electrode 106 and the switching layer 108. In an alternative embodiment, the bottom electrode interface structure 104 includes additional interface layers. Furthermore, in an alternative embodiment, one or more interface layers 104a-104c are omitted. Each interface layer 104a-104c is independent, as per [the relevant context]. Figure 1 The bottom electrode interface structure 104 is described.

[0054] In some embodiments, interface layers 104a-104c are, include, or are substantially composed of a group of common elements, including one or more metallic elements and one or more non-metallic elements. The one or more non-metallic elements may, for example, include oxygen, nitrogen, or any combination thereof. In at least some such embodiments, interface layers 104a-104c have different atomic percentages of non-metallic elements and further have different atomic percentages of metallic elements. For example, a first interface layer 104a may have a first atomic percentage of non-metallic elements, a second interface layer 104b may have a second atomic percentage of non-metallic elements, and a third interface layer 104c may have a third atomic percentage of non-metallic elements, wherein the first, second, and third atomic percentages are different. In some embodiments, the atomic percentage of non-metallic elements decreases discretely from the switching layer 108 to the bottom electrode 106. For example, continuing with the previous example, the first atomic percentage may be less than the second atomic percentage, and the second atomic percentage may be less than the third atomic percentage.

[0055] In some embodiments, interface layers 104a-104c are or comprise titanium oxide or nitride, and have an individual atomic percentage of oxygen or nitride that decreases discretely from switch layer 108 to bottom electrode 106. In some embodiments, interface layers 104a-104c are or comprise titanium oxynitride and have an individual atomic percentage of oxynitride that decreases discretely from switch layer 108 to bottom electrode 106.

[0056] exist Figure 2C In this configuration, the top electrode interface structure 202 separates the switching layer 108 from the top electrode 114. Furthermore, a top metal structure 204 and a top electrode barrier layer 206 are stacked above the top electrode 114, with the top electrode barrier layer 206 separating the top metal structure 204 from the top electrode 114. In an alternative embodiment, the top electrode barrier layer 206 is omitted, and the top metal structure 204 directly contacts the top electrode 114.

[0057] Top electrode interface structure 202 as about Figure 1 The described bottom electrode interface structure 104, in addition to the top electrode interface structure 202 blocking or resisting the diffusion of impurities and / or active metal atoms from above the top electrode interface structure 202 to the switching layer 108. For example, such impurities and / or active metal atoms may originate from the top electrode 114, the top metal structure 204, the top electrode blocking layer 206, or any combination thereof. In an alternative embodiment, the bottom electrode interface structure 104 includes as described above. Figure 2B The described plurality of interface layers 104a-104c and / or top electrode interface structure 202 include, as per [reference to...] Figure 2B Multiple interface layers are described for the bottom electrode interface structure 104.

[0058] For example, the top electrode 114 can be as described in relation to Figure 1 The bottom electrode 106 is described. For example, the top metal structure 204 can be as described regarding... Figure 1 The bottom metal structure 110 is described. For example, the top electrode blocking layer 206 can be as described regarding... Figure 1 The bottom electrode barrier layer 112 is described.

[0059] although Figure 2A Described Figure 1 A variant in which the bottom electrode blocking layer 112 is omitted, but the variant can be applied to Figure 2B and Figure 2C Any one of them. Therefore, for example, it can be from... Figure 2B and / or Figure 2C The bottom electrode barrier layer 112 is omitted. Although Figure 2B Described Figure 1A variant in which the bottom electrode interface structure 104 includes multiple interface layers 104a-104c, but the variant can be applied to Figure 2A and Figure 2C Any one of them. Therefore, the bottom electrode blocking layer 112 may include, for example, one of the following: Figure 2A and / or Figure 2B Multiple interface layers 104a-104c in the model. Although Figure 2C Described Figure 1 A variant in which the top electrode interface structure 202 separates the top electrode 114 from the switching layer 108, but the variant can be applied to Figure 2A and Figure 2B Any one of them. Therefore, the top electrode interface structure 202 can connect the top electrode 114 with... Figure 2A and / or Figure 2B The switch layer 108 is separated. Although Figure 2C The top metal structure 204 and the top electrode barrier layer 206 are described as being stacked on top of the top electrode 114, but in Figure 1 , Figure 2A and Figure 2B In some embodiments, the top metal structure 204 and the top electrode barrier layer 206 may be stacked on top of the top electrode 114.

[0060] refer to Figure 3 Provided Figure 1 Cross-sectional view 300 of some embodiments of memory cell 102, wherein memory cell 102 is located in interconnect structure 302 of IC chip, vertically positioned between bottom electrode wire 304b and top electrode wire 304t. Note that bottom electrode wire 304b may, for example, correspond to... Figure 1 and Figures 2A-2C The bottom metal structure 110 is described.

[0061] A top electrode via 306t extends downward from the top electrode wire 304t to the top electrode 114, and a top electrode blocking layer 206 surrounds the bottom of the top electrode via 306t to separate the top electrode via 306t from the top electrode 114. Note that the top electrode via 306t may correspond, for example, to... Figure 2C The described top metal structure 204 and / or top electrode blocking layer 206 may, for example, correspond to the following regarding Figure 2C The described counterpart. Furthermore, the top electrode via 306t and the top electrode barrier layer 206 extend through the hard mask 308 on top of the top electrode 114. In an alternative embodiment, the hard mask 308 is omitted.

[0062] In some embodiments, the hard mask 308 is or includes silicon nitride and / or some other suitable dielectric. In some embodiments, the top electrode conductor 304t, the bottom electrode conductor 304b, and the top electrode via 306t are or include, for example, copper, aluminum copper, some other suitable metal, or any combination thereof.

[0063] The bottom electrode 106 has a T-shaped profile and protrudes downward toward the bottom electrode lead 304b, thereby forming a bottom electrode via 310. Furthermore, a bottom electrode barrier layer 112 surrounds the bottom electrode via 310 to separate the bottom electrode via 310 and thus separate the bottom electrode 106 from the bottom electrode lead 304b. In an alternative embodiment, the bottom electrode barrier layer 112 is omitted, allowing the bottom electrode via 310 to directly contact the bottom electrode lead 304b.

[0064] Bottom electrode 106, bottom electrode interface structure 104, switching layer 108, top electrode 114, and hard mask 308 share a common width. In alternative embodiments, the width varies. Bottom electrode 106, bottom electrode interface structure 104, switching layer 108, top electrode 114, and hard mask 308 each form a common sidewall on opposite sides of memory cell 102. The common sidewall has a planar profile, but may also have a curved or other suitable profile in alternative embodiments. Furthermore, the common sidewall is padded by sidewall spacer structure 312. Sidewall spacer structure 312 has a plurality of spacer segments that are independent of the common sidewall from top to bottom and padded separately to the common sidewall. In some embodiments, sidewall spacer structure 312 is or includes silicon nitride and / or some other suitable dielectric. Furthermore, in some embodiments, sidewall spacer structure 312 is the same material as hard mask 308.

[0065] Multiple intermetallic dielectric (IMD) layers 314 surround the bottom electrode conductor 304b and the top electrode conductor 304t, respectively, and a via dielectric layer 316 separates the IMD layers 314 and surrounds the bottom electrode via 310. Furthermore, an etch stop layer 318 covers the via dielectric layer 316 and the memory cell 102, separating the upper layer of the IMD layer 314 from the via dielectric layer 316 and the memory cell 102.

[0066] In some embodiments, the IMD layer 314 is or includes an extremely low-k dielectric and / or some other suitable dielectric. In some embodiments, the via dielectric layer 316 is or includes silicon carbide and / or some other suitable dielectric. In some embodiments, the etch stop layer 318 is or includes silicon carbide, tetraethyl orthosilicate (TEOS) oxide, some other suitable dielectric, or any combination thereof.

[0067] refer to Figures 4A-4E Provided Figure 3 Cross-sectional views 400A-400F show some alternative embodiments of the memory cell 102.

[0068] exist Figure 4A In this embodiment, the sidewall spacer structure 312 is omitted. Furthermore, the bottom electrode 106 and the bottom electrode interface structure 104 share a first width, while the top electrode 114 and the hard mask 308 share a second width smaller than the first width. In an alternative embodiment, the width varies between the bottom electrode 106 and the bottom electrode interface structure 104 and / or between the top electrode 114 and the hard mask 308.

[0069] Bottom electrode 106 and bottom electrode interface structure 104 form first common sidewalls on opposite sides of memory cell 102, while top electrode 114 and hard mask 308 form second common sidewalls on opposite sides. The first and second common sidewalls have planar profiles, but curved or other suitable profiles are acceptable. Switching layer 108 has sidewalls that arc inwardly towards each other from the first to the second common sidewalls on opposite sides of memory cell 102. Therefore, the width of switching layer 108 decreases from bottom electrode interface structure 104 to top electrode 114.

[0070] exist Figure 4B In the original embodiment, the bottom electrode 106 and the bottom electrode interface structure 104 share a first width, while the switch layer 108, the top electrode 114, and the hard mask 308 share a smaller second width. In an alternative embodiment, the width varies between the bottom electrode 106 and the bottom electrode interface structure 104 and / or between the switch layer 108, the top electrode 114, and the hard mask 308. Furthermore, the bottom electrode 106 and the bottom electrode interface structure 104 form first common sidewalls on opposite sides of the memory cell 102, while the switch layer 108, the top electrode 114, and the hard mask 308 form second common sidewalls on opposite sides. The first and second common sidewalls have planar profiles, but curved or other suitable profiles are acceptable.

[0071] The sidewall spacer structure 312 covers the bottom electrode interface structure 104 and is laterally located between the first common sidewalls. Furthermore, the sidewall spacer structure 312 cushions the second common sidewall. Specifically, the spacer segments are independent of and cushion the second common sidewall from top to bottom.

[0072] exist Figure 4C In the middle, the bottom electrode blocking layer 112, the bottom electrode 106, the bottom electrode interface structure 104, the switching layer 108, the top electrode 114 and the hard mask 308 are recessed at the bottom electrode through hole 310.

[0073] The bottom electrode barrier layer 112, bottom electrode 106, bottom electrode interface structure 104, and switching layer 108 share a first width, while the top electrode 114 and hard mask 308 share a smaller second width. In an alternative embodiment, the width varies between the bottom electrode barrier layer 112, bottom electrode 106, bottom electrode interface structure 104, and switching layer 108 and / or between the top electrode 114 and hard mask 308. The electrode barrier layer 112, bottom electrode 106, bottom electrode interface structure 104, and switching layer 108 each form a first common sidewall on opposite sides of the memory cell 102, while the top electrode 114 and hard mask 308 each form a second common sidewall on opposite sides. The first and second common sidewalls have planar profiles, but curved or other suitable profiles are applicable.

[0074] The sidewall spacer structure 312 covers the switch layer 108 and is laterally located between the first common sidewalls. Furthermore, the sidewall spacer structure 312 pads the second common sidewall. Specifically, the spacer segments are independent of and pad the second common sidewall from top to bottom.

[0075] exist Figure 4D In the middle, memory unit 102 as Figure 4C In addition to the memory cell 102 being more linear and having a different proportion in its composition, the top electrode via 306t is offset to one side of the memory cell 102 instead of being located at the center in the width direction of the memory cell 102.

[0076] exist Figure 4E In this design, the bottom electrode via 310, hard mask 308, and sidewall spacer structure 312 are omitted, while the bottom electrode barrier layer 112, bottom electrode 106, bottom electrode interface structure 104, and switch layer 108 have a U-shaped profile surrounding the bottom of the top electrode 114. Furthermore, the bottom electrode barrier layer 112, bottom electrode 106, bottom electrode interface structure 104, switch layer 108, and top electrode 114 are covered by an etch stop layer 318 and have separate top surfaces flush with each other.

[0077] Although Figure 3 and Figures 4A-4E Is using Figure 1 The embodiment of memory cell 102 will be used for illustration, but Figure 3 and Figures 4A-4E The embodiments can be used alternatively Figures 2A-2C Any embodiment thereof. For example, the bottom electrode barrier layer 112 can be drawn from... Figure 3 and Figures 4A-4E Omitted in any of them, such as regarding Figure 2A As shown and described.

[0078] refer to Figure 5A A cross-sectional view 500A is provided for some embodiments of memory cell 102, wherein memory cell 102 includes a separate bottom electrode interface structure 104 and is integrated into a separate transistor-resistor (ITIR) cell 502 in an IC chip. Figure 5A Each of the memory cells 102, such as Figure 4D The memory cell 102 is shown and described. The 1T1R cell 502 includes a separate drain region 504 and a separate drain-side conductive path 506.

[0079] Drain regions 504 are doped regions of substrate 508, and each has a doping type opposite to that of adjacent regions of substrate 508. Furthermore, drain regions 504 are electrically isolated from each other by trench isolation structure 510 and partially define access transistors 512 (partially shown) for individually selecting memory cells 102. Trench isolation structure 510 extends to the top of substrate 508 and comprises silicon oxide and / or some other suitable dielectric material. For example, trench isolation structure 510 may be a shallow trench isolation (STI) structure or some other suitable trench isolation structure. For example, substrate 508 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate.

[0080] A drain-side conductive path 506 electrically connects the drain region 504 to the memory cell 102. Furthermore, the drain-side conductive path 506 is formed by an interconnect structure 302, which includes a plurality of conductors 304 and a plurality of vias 306. The plurality of conductors 304 include a top electrode conductor 304t and a bottom electrode conductor 304b. In some embodiments, the top electrode conductor 304t corresponds to a bit line BL. The plurality of vias 306 includes a top electrode via 306t. The layer level of the via 306 closest to the substrate 508 is located in the interlayer dielectric (ILD) layer 514, while the remaining layers of the vias 306 and conductors 304 are located in the IMD layer 314. The conductors 304 and vias 306 may be, for example, copper, some other suitable conductive material, or any combination of the foregoing materials.

[0081] A peripheral region 516 on one side of the 1T1R cell 502 accommodates a peripheral device 518 (shown only partially). The peripheral device 518 can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (finFET), a gate-all-around field-effect transistor (GAAFET), or some other suitable type of semiconductor device. Each peripheral device 518 includes a pair of source / drain regions 520 (only one shown) located in the substrate 508 and a gate structure (not shown) between the source / drain regions 520. The source / drain regions 520 are doped regions of the substrate 508, and each has a doping type opposite to that of the adjacent region of the substrate 508.

[0082] refer to Figure 5B Along with interception Figure 5A The cross-sectional view of 500A provides an orthogonal axis. Figure 5A A cross-sectional view 500B of some embodiments of the IC chip. The 1T1R unit 502 includes a separate memory unit 102, a separate drain-side conductive path 506, a separate access transistor 512, and a separate source-side conductive path 522. Figure 5B The memory cells 102 are all like Figure 4D The memory cell 102 shown and described.

[0083] Access transistor 512 is located on substrate 508, between substrate 508 and interconnect structure 302, and electrically isolated by trench isolation structure 510. Access transistor 512 includes a separate drain region 504, a separate source region 524, a separate gate dielectric layer 526, and a separate gate electrode 528. Gate electrode 528 covers gate dielectric layer 526 and, in some embodiments, forms word line WL. Drain and source regions 504 and 524 are doped regions of substrate 508, and each has a doping type opposite to that of adjacent regions of substrate 508. Drain region 504 is connected to the drain side of gate electrode 528, and source region 524 is connected to the source side of gate electrode 528. Access transistor 512 may be, for example, a MOSFET, a FinFET, a GAAFET, or some other suitable type of semiconductor device.

[0084] The drain-side conductive path 506 electrically couples the drain region 504 to the memory cell 102, and the source-side conductive path 522 electrically couples the source region 524 to the source line SL. The drain-side conductive path and the source-side conductive paths 506 and 522 are formed by a plurality of wires 304 and a plurality of vias 306 in the interconnect structure 302.

[0085] refer to Figure 6 Provided Figure 5A and Figure 5B The top layout 600 of some embodiments of the IC chip. Figure 5A and Figure 5B Cross-sectional views 500A and 500B can be taken, for example, along lines A and B or other suitable locations. The IC chip includes multiple IT1R cells 502 arranged in multiple rows and columns, thereby forming a memory array 602. Peripheral devices 518 surround the memory array 602 in a peripheral region 516 of the IC chip. The peripheral devices 518 can, for example, implement read / write circuitry and / or other suitable circuitry to operate the IT1R cells 502.

[0086] In some embodiments, memory array 602 has a NOR (or non-) memory architecture. Therefore, 1T1R cells 502 in any given column share a common bit line (see, for example...). Figure 5A and Figure 5B Bit line (BL) and common source line (see, for example) Figure 5B The source line (SL) is connected in parallel with the common bit line to the common source line, and electrically coupled in parallel. For example, Figure 5A and Figure 5B This can correspond to such a memory architecture. In an alternative embodiment, memory array 602 has a NAND (NAND) memory architecture. Therefore, 1T1R cells 502 in any given column share a common bit line (see, for example...). Figure 5A and Figure 5B Bit line (BL) and common source line (see, for example) Figure 5B The source line (SL) is connected in series with the common bit line to the common source line. Figure 5A and Figure 5B The layout of wires 304 and vias 306 may differ in memory architectures, for example.

[0087] Although Figure 5A and Figure 5B Is using Figure 4D The memory cell embodiment in the text is shown, but alternatives can be used. Figure 1 , Figures 2A-2C , Figure 3 , Figures 4A-4C and Figure 4E any one or combination of them is used for Figure 5A and Figure 5B In the middle. For example, Figure 4E The memory cell embodiments in the text can be alternatively used for Figure 5A and Figure 5B In the middle. As another example, it can be used alternatively. Figure 2A The memory cell embodiment in the example makes it possible to... Figure 5A and Figure 5B The bottom electrode blocking layer 112 is omitted. As yet another example, Figure 5A One of the memory cells 102 in the memory cell can be as follows Figure 4D ,and Figure 5A Another one in memory cell 102 can be as follows Figure 3 .

[0088] refer to Figure 7 Provided Figure 5A Cross-sectional view 700 of some alternative embodiments of the IC chip, wherein memory cells 102 have different layouts. The first memory cell 102a is as follows: Figure 3 Configuration, and the second memory unit 102b as Figure 4DConfiguration. In an alternative embodiment, the first memory unit 102a is configured as follows: Figure 1 , Figures 2A-2C , Figures 4A-4C and Figure 4E Any one or combination thereof, and / or the second memory unit 102b is configured as follows Figure 1 , Figures 2A-2C , Figures 4A-4C and Figure 4E Any one or a combination thereof.

[0089] Reference Figures 8-19 A series of cross-sectional views 800-1900 provide some embodiments of methods for forming memory cells, wherein the memory cells include separate bottom electrode interface structures and are integrated into an IC chip's IT1R cell. Cross-sectional views 800-1900 may, for example, correspond to... Figure 5A And therefore it can be shown, for example Figure 5A and Figure 5B The formation of IC chips. Furthermore, cross-sectional views 800-1900 can, for example, be along... Figure 6 Cut off line A in the middle.

[0090] like Figure 8 As shown in cross-sectional view 800, the trench isolation structure 510 is formed to extend to the top of the substrate 508. The trench isolation structure 510 separately surrounds and defines the area of ​​the substrate 508 where the 1T1R cell 502 is formed, and further surrounds and defines the peripheral area 516 of the IC chip.

[0091] Also by Figure 8 As shown in cross-sectional view 800, a plurality of semiconductor devices are formed on substrate 508. The plurality of semiconductor devices include access transistors 512, each access transistor 512 being individually located at and corresponding to the formation of 1T1R cell 502. Furthermore, the plurality of semiconductor devices include peripheral devices 518 at a peripheral region 516 of the IC chip. Access transistor 512 includes a separate drain region 504 and a separate source region (not shown) in substrate 508. Furthermore, access transistor 512 includes a separate gate structure (not shown). The gate structure has a separate drain side respectively bordered to drain region 504, and also has a separate source side respectively bordered to source region. Peripheral device 518 includes pairs of separate source / drain regions 520 in substrate 508 (only one of each pair is shown) and also includes a separate gate structure (not shown) between and bordering the source / drain regions 520.

[0092] Also by Figure 8Cross-sectional view 800 shows that an interconnect structure 302 is partially formed above and electrically coupled to a semiconductor device (e.g., access transistor 512 and peripheral device 518). The interconnect structure 302 includes a dielectric structure and further includes a plurality of wires 304 and a plurality of vias 306 stacked within the dielectric structure. The dielectric structure includes an ILD layer 514 and a plurality of IMD layers 314 above the ILD layer 514. The plurality of wires 304 includes a plurality of bottom electrode wires 304b along the top surface of the interconnect structure 302. The bottom electrode wires 304b are formed separately from and correspondingly at the IT1R cell 502. Furthermore, the bottom electrode wires 304b are electrically coupled to the drain region 504 of the access transistor 512 via the underlying wires and vias, respectively.

[0093] The wire 304 (including the bottom electrode wire 304b) comprises active metal atoms. As used herein, the active metal atoms are metal atoms with a high diffusion coefficient. For example, a high diffusion coefficient can be greater than about 10. -13 cm 2 s -1 10 -12 cm 2 s -1 10 -11 cm 2 s -1 Or some other suitable amount of diffusion coefficient. Non-limiting examples of active metal atoms include copper atoms, tantalum atoms, etc.

[0094] like Figure 9 As shown in cross-sectional view 900, a via dielectric layer 316 is deposited or otherwise formed on the interconnect structure 302. Note that for the sake of drawing compactness, the lower portion of the interconnect structure 302 is omitted here and in the following figures. The via dielectric layer 316 may be, for example, or include silicon carbide, silicon-rich oxide, some other suitable dielectric, or any combination thereof.

[0095] like Figure 10 As shown in cross-sectional view 1000, the via dielectric layer 316 is patterned to form via openings 1002, which are separate from and correspondingly formed at the 1T1R unit 502. The via openings 1002 extend through the via dielectric layer 316 and expose the bottom electrode wires 304b. For example, the patterning can be performed by photolithography / etching processes or some other suitable patterning process.

[0096] like Figure 11As shown in cross-sectional view 1100, a bottom electrode barrier layer 112 and a bottom electrode layer 1102 are deposited, covering the via dielectric layer 316 and lining the via opening 1002. In an alternative embodiment, the bottom electrode barrier layer 112 is omitted. A portion of the bottom electrode barrier layer 112 and the bottom electrode layer 1102 in the via opening 1002 at least partially forms the bottom electrode via 310.

[0097] The bottom electrode barrier layer 112 is configured to block or otherwise prevent the diffusion of active metal atoms from the bottom electrode wire 304b to the bottom electrode layer 1102. In some embodiments, the bottom electrode barrier layer 112 blocks or otherwise resists diffusion by: 1) being more amorphous and / or less crystalline than the bottom electrode wire 304b; 2) having an average grain size that is larger or smaller than the average grain size of the bottom electrode wire 304b; 3) having a different lattice constant than the bottom electrode wire 304b; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms; or 5) any combination of the foregoing.

[0098] In some embodiments, the bottom electrode barrier layer 112 is or comprises inactive metal atoms. Furthermore, in some embodiments, the bottom electrode barrier layer 112 is substantially composed of inactive metal atoms and / or the metal atoms are substantially composed of inactive metal atoms across all the metal atoms in the bottom electrode barrier layer 112. As used herein, inactive metal atoms are metal atoms having a low diffusion coefficient. A low diffusion coefficient can be, for example, less than about 10. -13 cm 2 s -1 10 - 14 cm 2 s -1 10 -15 cm 2 s -1 Or some other suitable amount of diffusion coefficient.

[0099] In some embodiments, the bottom electrode barrier layer 112 is or includes active metal atoms. Furthermore, in some embodiments, the bottom electrode barrier layer 112 is substantially composed of active metal atoms and / or the metal atoms are substantially composed of active metal atoms across all the metal atoms in the bottom electrode barrier layer 112. The active metal atoms are metal atoms with a high diffusion coefficient. For example, the high diffusion coefficient can be greater than about 10. -13 cm 2 s -1 Or some other suitable amount of diffusion coefficient.

[0100] In some embodiments where the bottom electrode barrier layer 112 includes active metal atoms, the active metal atoms of the bottom electrode wire 304b correspond to a different metal element 112 than the active metal atoms of the bottom electrode barrier layer. For example, the active metal atoms of the bottom electrode wire 304b may correspond to copper, while the active metal atoms of the bottom electrode barrier layer 112 may correspond to tantalum. However, other suitable metal elements are also acceptable. In some embodiments, the active metal atoms of the bottom electrode barrier layer 112 have a first diffusion coefficient, while the active metal atoms of the bottom electrode wire 304b have a second diffusion coefficient greater than or different from the first diffusion coefficient.

[0101] In some embodiments where the bottom electrode barrier layer 112 comprises active metal atoms, the bottom electrode layer 1102 blocks or otherwise resists the diffusion of active metal atoms. In some embodiments, the bottom electrode layer 1102 blocks or otherwise resists diffusion by: 1) being more amorphous and / or less crystalline than the bottom electrode barrier layer 112; 2) having an average grain size that is larger or smaller than the average grain size of the bottom electrode barrier layer 112; 3) having a different lattice constant than the bottom electrode barrier layer 112; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms; or 5) any combination of the foregoing.

[0102] In some embodiments, the bottom electrode layer 1102 is or includes tantalum nitride, molybdenum, titanium nitride, tungsten nitride, iridium, ruthenium, etc. It has been recognized that such materials block or otherwise resist the diffusion of active metal atoms, including copper, tantalum, etc. In some embodiments, the bottom electrode layer 1102 is or includes titanium nitride having a nitrogen atom percentage of about 50% or some other suitable percentage, while the bottom electrode barrier layer 112 is or includes tantalum and / or tantalum nitride. However, other suitable materials are also feasible.

[0103] In terms of the degree to which the bottom electrode layer 1102 blocks or otherwise prevents the diffusion of active metal atoms, the bottom electrode layer 1102 can prevent active metal atoms from diffusing to and contaminating the switching layer subsequently deposited on the bottom electrode layer 1102. Contamination of the switching layer by active metal atoms can lead to increased leakage current, which negatively impacts the reliability, breakdown voltage, and other suitable characteristics of the forming memory cell. Therefore, by blocking or otherwise resisting diffusion, the bottom electrode layer 1102 can reduce leakage current and improve the performance of the forming memory cell.

[0104] In some embodiments where the bottom electrode barrier layer 112 includes active metal atoms, the bottom electrode layer 1102 allows the active metal atoms to diffuse through the active metal atoms or otherwise, thus not blocking or otherwise impeding the diffusion of the active metal atoms. In some embodiments, the bottom electrode barrier layer 112 is or includes inactive metal atoms. Furthermore, in some embodiments, the bottom electrode barrier layer 112 is substantially composed of inactive metal atoms and / or the metal atoms are substantially composed of inactive metal atoms across all the metal atoms. In some embodiments, the bottom electrode layer 1102 is or includes active metal atoms. In some embodiments, the bottom electrode layer 1102 is substantially composed of active metal atoms and / or the metal atoms are substantially composed of active metal atoms across all the metal atoms.

[0105] like Figure 12 As shown in cross-sectional view 1200, a bottom electrode interface layer 1202 is formed above the bottom electrode layer 1102 and liner the via opening 1002. The bottom electrode interface layer 1202 is dielectric and is a different material from the bottom electrode layer 1102. The bottom electrode interface layer 1202 is configured to block or otherwise prevent the diffusion of active metal atoms and / or impurities through the bottom electrode interface layer 1202. In some embodiments, the bottom electrode interface layer 1202 blocks or otherwise resists diffusion by: 1) being more amorphous and / or less crystalline than the bottom electrode layer 1102; 2) having an average grain size that is larger or smaller than the average grain size of the bottom electrode layer 1102; 3) having a different lattice constant than the bottom electrode layer 1102; 4) being composed of atoms with atomic radii greater than and / or smaller than those of the active metal atoms and / or impurities; or 5) any combination of the foregoing.

[0106] As seen below, a switching layer is subsequently formed on the bottom electrode interface layer 1202. By blocking or otherwise resisting diffusion, the bottom electrode interface layer 1202 prevents active metal atoms and / or impurities from diffusing into the switching layer. As active metal atoms and / or impurities diffuse into the switching layer, leakage current may increase, and thus durability may decrease. Therefore, by blocking or otherwise resisting diffusion, the bottom electrode interface layer 1202 can reduce leakage current. Reducing leakage current, in turn, improves reliability and increases the breakdown voltage of the forming memory cell.

[0107] In some embodiments, the bottom electrode interface layer 1202 is or includes a metal oxide, a metal nitride, a metal oxynitride, etc. For example, the bottom electrode interface layer 1202 may be or includes titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, etc. In at least some embodiments where the bottom electrode layer 1102 is or includes titanium nitride, the bottom electrode interface layer 1202 is or includes titanium oxynitride, etc. In at least some embodiments where the bottom electrode layer 1102 is or includes tantalum nitride, the bottom electrode interface layer 1202 is or includes tantalum oxynitride, etc.

[0108] In some embodiments, the bottom electrode interface layer 1202 comprises inactive metal atoms and / or is substantially composed of inactive metal atoms across all metal atoms. In some embodiments, the bottom electrode interface layer 1202 comprises active metal atoms and / or is substantially composed of active metal atoms across all metal atoms. In some embodiments, the bottom electrode interface layer 1202 shares a common metal element with the bottom electrode layer 1102. In some embodiments, the bottom electrode interface layer 1202 has no remanent polarization and is therefore not ferroelectric. Such embodiments can occur at least when the formed memory cells are FeRAM cells and RRAM cells.

[0109] In some embodiments, the process for forming the bottom electrode interface layer 1202 is or includes plasma treatment of the bottom electrode layer 1102. For example, plasma treatment may be performed to oxidize and / or introduce nitrogen into portions of the top bottom electrode layer 1102, thereby forming the bottom electrode interface layer 1202 from the top. In some embodiments, plasma treatment reduces crystallinity and / or increases amorphousness at the top and thus at the bottom electrode interface layer 1202. Plasma treatment includes generating plasma from a process gas and exposing the bottom electrode layer 1102 to the plasma. In some embodiments, plasma treatment is performed at: 1) a processing power greater than about 600 watts or some other suitable value; 2) a process temperature of about 200-500 degrees Celsius (°C), about 200-350°C, about 350-500°C or some other suitable value; 3) a process gas that is or contains ammonia (e.g., NH3), nitrogen (e.g., N2), nitrous oxide (e.g., N2O), oxygen (e.g., O2), some other suitable gas, or any combination thereof; 4) a process temperature of about 1-10 Torr, about 1-5.5 Torr, about 5.5-10 Torr or some other suitable value; or 5) or any combination thereof.

[0110] like Figure 13As shown in cross-sectional view 1300, a switching layer 108 is deposited or otherwise formed over the bottom electrode interface layer 1202. The switching layer 108 has features for representing data bits and is configured to reversibly switch between a first state and a second state. For example, the switching layer 108 may be ferroelectric, whereby the remanent polarization of the switching layer 108 can be used to represent data bits. The first state of the remanent polarization represents binary "1", while the second state of the remanent polarization represents binary "0", and vice versa.

[0111] In some embodiments, the switching layer 108 is or includes a hafnium oxide-based film, a zirconium oxide-based film, etc., in an orthorhombic phase. For example, the switching layer 108 may be or includes hafnium zirconium oxide (e.g., HfZrO or HZO), hafnium aluminum oxide (e.g., HfAlO), hafnium lanthanum oxide (e.g., HfLaO), hafnium cerium oxide (e.g., HfCeO), hafnium oxide (e.g., HfO), hafnium silicon oxide (e.g., HfSiO), hafnium gadolinium oxide (e.g., HfGdO), etc. In some embodiments, the switching layer 108 is doped with a dopant atomic percentage equal to or less than about 50%, 40%, 25%, or some other suitable percentage. Dopant may be, for example, or include aluminum (e.g., Al), silicon (e.g., Si), lanthanum (e.g., La), scandium (e.g., Sc), calcium (e.g., Ca), barium (e.g., Ba), gadolinium (e.g., Gd), yttrium (e.g., Y), strontium (e.g., Sr), some other suitable elements, or any combination of the above elements. In some embodiments, the switching layer 108 is a high-k dielectric and / or a metal oxide. In embodiments where the memory cell being formed is an FeRAM cell and therefore the switching layer 108 is ferroelectric, the ratio of the orthorhombic, tetragonal, and cubic phases of the switching layer 108 to the orthorhombic, tetragonal, cubic, and monoclinic phases is greater than about 0.5 or some other suitable value.

[0112] The switch layer 108 can be deposited by ALD, chemical vapor deposition (CVD), or some other suitable deposition process. In at least some embodiments of ALD deposition of the switch layer 108, the bottom electrode interface layer 1202 is exposed to a gaseous precursor. The gaseous precursor may be, for example, or include a chlorine precursor, an oxide precursor, other suitable gaseous precursors, or any combination thereof.

[0113] The bottom electrode interface layer 1202 is configured to block or otherwise impede the diffusion of gaseous precursors. Without the bottom electrode interface layer 1202, gaseous precursors could diffuse into the bottom electrode layer 1102 and potentially introduce impurities into it. For example, chloride and / or oxide precursors could diffuse into the bottom electrode layer 1102 and could result in the presence of chloride ions (e.g., Cl-). - ) and / or oxygen ions (O -Impurities. Furthermore, without the bottom electrode interface layer 1202, impurities may diffuse from the bottom electrode layer 1102 to the switching layer 108 after the switching layer 108 is deposited. This can lead to an increase in leakage current, which may reduce data retention and therefore reliability of the forming memory cell. Therefore, by preventing the above-mentioned behavior, the bottom electrode interface layer 1202 can reduce leakage current. This, in turn, can enhance data retention and thus reliability of the forming memory cell.

[0114] In some embodiments, the bottom electrode interface layer 1202 blocks or otherwise resists diffusion by: 1) being more amorphous and / or less crystalline than the bottom electrode layer 1102 and / or the switching layer 108; 2) having an average grain size that is larger or smaller than the average grain size of the bottom electrode layer 1102 and / or the switching layer 108; 3) having a lattice constant that is different from the lattice constant of the bottom electrode layer 1102 and / or the switching layer 108; 4) being composed of atoms with atomic radii greater than and / or smaller than the diffusion atoms to be blocked or otherwise resisted; or 5) being / having any combination of the above.

[0115] In some embodiments, the bottom electrode interface layer 1202 is also inert to the gaseous precursors used during the deposition of the switching layer 108. Inertness means that the bottom electrode interface layer 1202 does not react with the gaseous precursors and / or relies on more energy than the bottom electrode layer 1102 to react with the gaseous precursors. Due to inertness, the gaseous precursors can react more completely with each other, thereby reducing the likelihood of unreacted or partially reacted precursors contaminating the switching layer 108 and increasing leakage current. Therefore, the bottom electrode interface layer 1202 can further reduce leakage current, which can enhance data retention of the forming memory cells and thus improve reliability.

[0116] In some embodiments, the bottom electrode layer 1102 reacts with the gaseous precursor, while the bottom electrode interface layer 1202 is inert and / or does not react with the gaseous precursor. In at least some of these embodiments, the omission of the bottom electrode interface layer 1202 may result in unreacted or partially reacted precursors, which may contaminate the switching layer 108 and thus potentially increase leakage current.

[0117] like Figure 14 As shown in cross-sectional view 1400, the top electrode layer 1402 is deposited above the switch layer 108. The top electrode layer 1402 can be deposited, for example, by physical vapor deposition (PVD), CVD, some other suitable deposition process, or any combination thereof.

[0118] Also by Figure 14Cross-sectional view 1400 shows the formation of a hard mask 308, separate and corresponding to the 1T1R cell 502. As will be seen below, the hard mask 308 has a pattern for the memory cells of the 1T1R cell 502. The hard mask 308 can be formed, for example, by depositing a hard mask layer over the top electrode layer 1402 and subsequently patterning the hard mask layer into the hard mask 308. Patterning can be performed, for example, by a photolithography / etching process or some other suitable patterning process.

[0119] like Figure 15 As shown in cross-sectional view 1500, with the hard mask 308 in place, the top electrode layer 1402 (see, for example, [reference needed]) Figure 14 The first etching is performed. The first etching stops on the switch layer 108 and the pattern of the hard mask 308 is transferred to the top electrode layer 1402 to form the 1T1R unit 502 and the top electrode 114 corresponding to the 1T1R unit 502.

[0120] like Figure 16 As shown in cross-sectional view 1600, a sidewall spacer structure 312 is formed on the switching layer 108 covering the common sidewall through a hard mask 308 and a top electrode 114. The process for forming the sidewall spacer structure 312 may include, for example, 1) depositing a spacer layer covering and lining the switching layer 108 and further lining the common sidewall with a hard mask 308; 2) etching back the spacer layer. However, other suitable methods are also feasible.

[0121] like Figure 17 As shown in cross-sectional view 1700, with the sidewall spacer structure 312 and hard mask 308 in place, a second etching is performed on the switching layer 108, bottom electrode interface layer 1202, bottom electrode layer 1102, and bottom electrode barrier layer 112. The second etching stops on the via dielectric layer 316 and transfers the pattern of the hard mask 308 and sidewall spacer structure 312 to the switching layer 108, bottom electrode interface layer 1202, bottom electrode layer 1102, and bottom electrode barrier layer 112. The second etching divides the switching layer 108, bottom electrode interface layer 1202, bottom electrode layer 1102, and bottom electrode barrier layer 112 into segments that are separate from and correspond to the 1T1R unit 502.

[0122] A portion of the bottom electrode layer 1102 is hereinafter referred to as the bottom electrode 106, and a portion of the bottom electrode interface layer 1202 is hereinafter referred to as the bottom electrode interface structure 104. The bottom electrode 106, the top electrode 114, the bottom electrode interface structure 104, the switching layer 108, and the bottom electrode barrier layer 112 collectively form a memory cell 102 at the 1T1R unit 502. In embodiments where the switching layer 108 is ferroelectric, the memory cell 102 may be an FeRAM cell.

[0123] like Figure 18 and Figure 19 As shown in cross-sectional views 1800 and 1900, the interconnect structure 302 is completed above the memory cell 102. Figure 18 At this location, an etch stop layer 318 is deposited above and pads the memory cell 102. Furthermore, an additional IMD layer 314 is deposited above the etch stop layer 318. Figure 19 At the location, a plurality of additional wirings 304 and a plurality of additional vias 306 are formed above the memory cell 102, recessed into the additional IMD layer 314 above the memory cell 102. The plurality of additional wirings 304 include top electrode conductors 304t that are separate from and correspondingly cover the memory cell 102. The plurality of additional vias 306 include top electrode vias 306t that are separate from and respectively cover the memory cell 102. Furthermore, the top electrode vias 306t extend correspondingly from the top electrode conductors 304t to the memory cell 102.

[0124] Although reference Figures 8-19 The described method will help you understand Figures 8-19 The structure shown is not limited to this method, but can be used independently of it. Although Figures 8-19 It is described as a series of actions, but it should be understood that the order of the actions may be changed in other embodiments. Although Figures 8-19 The illustrations and descriptions are of a specific set of actions, but some actions may be omitted in other embodiments. Furthermore, actions not illustrated and / or described may be included in other embodiments. Although Figures 8-19 use Figure 4D The embodiment of memory cell 102 illustrates the method, but alternative embodiments that can perform the method are used for Figure 1 , Figures 2A-2C , Figure 3 and Figures 4A-4C An embodiment of memory cell 102 in any one or combination of the above.

[0125] refer to Figure 20 Provided Figures 8-19 A block diagram of some embodiments of the method is shown in 2000.

[0126] At position 2002, an interconnect structure is partially formed above the substrate, wherein the interconnect structure includes bottom electrode wires. See, for example, [reference needed]. Figure 8 .

[0127] At 2004, a via dielectric layer is deposited over the interconnect structure. See, for example, [link to example]. Figure 9 .

[0128] At 2006, a via dielectric layer was patterned to form via openings that covered the bottom electrode conductors and exposed them. See, for example, [link to example]. Figure 10 .

[0129] At 2008, a bottom electrode barrier layer and a bottom electrode layer were deposited to cover the via dielectric layer and padded the via opening. See, for example, [link to relevant documentation]. Figure 11 .

[0130] At point 2010, a bottom electrode interface layer is formed covering the bottom electrode layer, wherein the bottom electrode interface layer is configured to block or resist the diffusion of active metal elements and / or impurities. See, for example, [reference needed]. Figure 12 .

[0131] At 2012, a switching layer and a top electrode layer are deposited and stacked above the bottom electrode interface layer, with the switching layer between the top electrode layer and the bottom electrode interface layer. See, for example, [link to relevant documentation]. Figure 13 and Figure 14 In some embodiments, the memory cell being formed is an FeRAM cell, whereby the switching layer is ferroelectric. In other embodiments, the memory cell is some other suitable type of memory cell, whereby the switching layer is some other suitable type of material.

[0132] In 2014, the bottom and top electrode layers, the bottom electrode interface structure, and the FSL were patterned to form a memory cell that overlays the bottom electrode wires and is electrically coupled to them. See, for example, [link to relevant documentation]. Figures 15-17 .

[0133] In 2016, the interconnect structure was completed above and around the memory cells. See, for example, [link to relevant documentation]. Figure 18 and Figure 19 .

[0134] Although Figure 20 The block diagram 2000 is illustrated and described herein as a series of actions or events; however, it should be understood that the order of these actions or events shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all illustrated actions require the implementation of one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0135] In some embodiments, this disclosure provides an IC chip including a memory cell, wherein the memory cell includes: a bottom electrode; a switching layer located above the bottom electrode; a top electrode located above the switching layer; and an interface structure separating the bottom electrode and the switching layer from each other, wherein the interface structure is a dielectric and configured to prevent the diffusion of metal atoms and / or impurities in the bottom electrode to the switching layer. In some embodiments, the interface structure is more amorphous than the bottom electrode. In some embodiments, the switching layer is ferroelectric. In some embodiments, the bottom electrode and the interface structure share a common metal element. In some embodiments, the interface structure is a metal oxide, a metal nitride, or a metal oxynitride. In some embodiments, the bottom electrode is a metal nitride, and wherein the interface structure is a metal oxynitride. In some embodiments, the IC chip further includes: a wire located below the bottom electrode; and a barrier layer separating the wire from the bottom electrode and configured to prevent the diffusion of material from the wire to the bottom electrode; wherein the barrier layer includes active metal atoms having a density greater than about 10. -13 square centimeters per second (cm) 2 s -1 The diffusion coefficient of the bottom electrode is specified, and the bottom electrode is configured to block the diffusion of active metal atoms. In some embodiments, the IC chip further includes: a wire located below the bottom electrode; and a barrier layer separating the wire from the bottom electrode and configured to block the diffusion of material from the wire to the bottom electrode; wherein the barrier layer includes tantalum, and wherein the bottom electrode includes molybdenum, titanium nitride, tungsten nitride, iridium, and ruthenium.

[0136] In some embodiments, this disclosure provides an IC chip including a FeRAM cell, wherein the FeRAM cell includes: a bottom electrode; a ferroelectric switching layer located above the bottom electrode; a top electrode located above the ferroelectric switching layer; and an interface structure separating the bottom electrode from the ferroelectric switching layer, wherein the interface structure is a dielectric and includes a metallic element and a non-metallic element, wherein the metallic element is shared by the interface structure and the bottom electrode, and wherein the concentration of the non-metallic element decreases from the top to the bottom of the interface structure. In some embodiments, the bottom electrode contains no non-metallic element at all. In some embodiments, the interface structure further includes a second non-metallic element shared by the interface structure and the bottom electrode. In some embodiments, the concentration varies discretely from top to bottom. In some embodiments, the non-metallic element includes oxygen or nitrogen. In some embodiments, the IC chip further includes an additional interface structure separating the top electrode and the ferroelectric switching layer from each other, wherein the additional interface structure is a dielectric and configured to block the diffusion of metal atoms and / or impurities in the top electrode to the ferroelectric switching layer. In some embodiments, the IC chip further includes: a wire located below the bottom electrode and in direct contact with the bottom electrode; wherein the wire and the bottom electrode include active metal atoms having a concentration greater than about 10.-13 square centimeters per second (cm) 2 s -1 The diffusion coefficient of ) is given, and the interface structure is configured to block the diffusion of active metal atoms into the ferroelectric switch layer.

[0137] In some embodiments, this disclosure provides a method for forming an integrated circuit chip, comprising: depositing a bottom electrode layer covering and electrically coupled to wires; plasma-treating a top surface of the bottom electrode layer to form an interface layer covering the bottom electrode layer; depositing a switching layer over the interface layer using a precursor gas, wherein the interface layer is configured to block the precursor gas from diffusing to and interacting with the bottom electrode layer; depositing a top electrode layer over the switching layer; and patterning the bottom electrode layer and the top electrode layer, the switching layer, and the interface layer to form a memory cell. In some embodiments, the interface layer relies on more energy than the bottom electrode layer to react with the precursor gas. In some embodiments, the plasma treatment comprises generating plasma from a gas comprising oxygen and / or nitrogen. In some embodiments, the plasma treatment forms the interface layer from the top of the bottom electrode layer and reduces the crystallinity at the top. In some embodiments, the method further comprises: depositing a barrier layer covering the wires and comprising metal atoms; wherein the bottom electrode layer is deposited over the barrier layer, wherein metal atoms diffuse from the barrier layer to the bottom electrode layer, and wherein the interface layer is configured to block the metal atoms from migrating from the bottom electrode layer to the switching layer.

[0138] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. An integrated circuit chip, comprising a memory cell, wherein, The memory unit includes: Bottom electrode; The switching layer is located above the bottom electrode; The top electrode is located above the switching layer; and An interface structure separates the bottom electrode from the switching layer, wherein the interface structure comprises multiple interface layers, each of which has a different atomic percentage of a metal element. The interface structure is dielectric and configured to prevent metal atoms and / or impurities in the bottom electrode from diffusing to the switching layer. The plurality of interface layers include a discretely decreasing percentage of oxygen or nitride atoms from the switch layer to the bottom electrode.

2. The integrated circuit chip according to claim 1, wherein, The interface structure is more amorphous than the bottom electrode.

3. The integrated circuit chip according to claim 1, wherein, The switching layer is made of ferroelectric material.

4. The integrated circuit chip according to claim 1, wherein, The bottom electrode shares the same metal element as the interface structure.

5. The integrated circuit chip according to claim 1, wherein, The interface structure is a metal oxide, a metal nitride, or a metal nitride.

6. The integrated circuit chip according to claim 1, wherein, The bottom electrode is a metal nitride, and the interface structure is a metal nitride.

7. The integrated circuit chip according to claim 1, further comprising: The wire is located below the bottom electrode; as well as A barrier layer separates the wire from the bottom electrode and is configured to prevent the material of the wire from diffusing to the bottom electrode; The barrier layer comprises active metal atoms, wherein the active metal atoms have a density of more than 10. -13 cm 2 s -1 The diffusion coefficient, wherein the bottom electrode is configured to block the diffusion of the active metal atoms.

8. The integrated circuit chip according to claim 1, further comprising: The wire is located below the bottom electrode; as well as A barrier layer separates the wire from the bottom electrode and is configured to prevent the material of the wire from diffusing to the bottom electrode; The barrier layer includes tantalum, and the bottom electrode includes molybdenum, titanium nitride, tungsten nitride, iridium, and ruthenium.

9. An integrated circuit chip, comprising a ferroelectric random access memory (RAM) cell, wherein the ferroelectric RAM cell comprises: Bottom electrode; A ferroelectric switching layer is located above the bottom electrode; The top electrode is located above the ferroelectric switch layer; as well as An interface structure separates the bottom electrode from the ferroelectric switching layer. The interface structure comprises multiple interface layers, which are dielectric and include both metallic and non-metallic elements. Each of the multiple interface layers has a different atomic percentage of a metallic element, which is shared by both the interface structure and the bottom electrode. The concentration of the non-metallic elements decreases from the top to the bottom of the interface structure. The plurality of interface layers include a discretely decreasing percentage of oxygen or nitride atoms from the ferroelectric switch layer to the bottom electrode.

10. The integrated circuit chip according to claim 9, wherein, The bottom electrode does not contain the non-metallic element.

11. The integrated circuit chip according to claim 10, wherein, The interface structure also includes a second non-metallic element, which is shared by the interface structure and the bottom electrode.

12. The integrated circuit chip according to claim 9, wherein, The concentration varies discretely from the top to the bottom.

13. The integrated circuit chip according to claim 9, wherein, The non-metallic elements include oxygen or nitrogen.

14. The integrated circuit chip according to claim 9, further comprising: An additional interface structure separates the top electrode and the ferroelectric switch layer from each other, wherein the additional interface structure is a dielectric and is configured to prevent metal atoms and / or impurities in the top electrode from diffusing into the ferroelectric switch layer.

15. The integrated circuit chip according to claim 9, further comprising: A wire is located below the bottom electrode and in direct contact with the bottom electrode; The wire and the bottom electrode include active metal atoms, and the active metal atoms have a density of more than 10. - 13 cm 2 s -1 The diffusion coefficient, wherein the interface structure is configured to block the diffusion of the active metal atoms to the ferroelectric switch layer.

16. A method for forming an integrated circuit chip, comprising: A bottom electrode layer is deposited, which covers the wire and is electrically coupled to the wire; Plasma treatment is performed on the top surface of the bottom electrode layer to form multiple interface layers covering the bottom electrode layer, each of the multiple interface layers having a different atomic percentage of metal elements; A switching layer is deposited over the interface layer using a precursor gas, wherein the interface layer is configured to prevent the precursor gas from diffusing to and interacting with the bottom electrode layer. A top electrode layer is deposited above the switching layer; and The bottom electrode layer, the top electrode layer, the switch layer, and the interface layer are patterned to form memory cells. The plurality of interface layers include a discretely decreasing percentage of oxygen or nitride atoms from the switch layer to the bottom electrode layer.

17. The method according to claim 16, wherein, The interface layer requires more energy than the bottom electrode layer to react with the precursor gas.

18. The method according to claim 16, wherein, The plasma processing involves generating plasma from a gas including oxygen and / or nitrogen.

19. The method of claim 16, wherein, The plasma treatment forms the interface layer from the top of the bottom electrode layer and reduces the crystallinity at the top.

20. The method of claim 16, further comprising: A barrier layer is deposited, the barrier layer covering the wire and containing metal atoms; The bottom electrode layer is deposited above the barrier layer, the metal atoms diffuse from the barrier layer to the bottom electrode layer, and the interface layer is configured to prevent the metal atoms from migrating from the bottom electrode layer to the switching layer.

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