Silicon controlled electrostatic protection device and method of manufacturing the same
By introducing a high concentration of the third N+ injection region and the third P+ injection region into the thyristor electrostatic discharge device to form a Zener diode structure, the problem of high trigger voltage of traditional thyristors is solved, achieving low trigger voltage and high stability, enhancing ESD current discharge capability, and adapting to integrated circuit protection in CMOS process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JOULWATT TECH INC LTD
- Filing Date
- 2021-12-23
- Publication Date
- 2026-07-21
AI Technical Summary
Traditional silicon controlled rectifier (SCR) electrostatic discharge (ESD) devices have high trigger voltages, which cannot effectively protect the gate oxide layer in integrated circuits. Especially after the feature size of CMOS devices has decreased, the upper limit of the ESD design window has decreased, limiting their application range.
In a silicon controlled rectifier (SCR) electrostatic discharge device, a high concentration of third N+ injection region and third P+ injection region is introduced to form a Zener diode structure. The trigger current discharge path is reduced by Zener breakdown, and the spacing is precisely adjusted by polysilicon gate to achieve stability and robustness.
It effectively reduces the trigger voltage of the thyristor device, improves the stability and robustness of the device, enhances the ability to discharge ESD current, adapts to different operating voltage requirements, and has good application prospects.
Smart Images
Figure CN114883381B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and specifically to a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device and its manufacturing method. Background Technology
[0002] ESD (Electro-Static Discharge) is a natural phenomenon that occurs throughout the entire product lifecycle. From chip manufacturing, packaging, and testing to application, the external environment and internal structure accumulate a certain amount of charge, making them vulnerable to static electricity. Therefore, ESD protection devices are used to connect to the circuit being protected. When the internal circuitry of the protected circuit is functioning normally, the ESD protection device remains off, preventing interference with the circuit's operation. Conversely, when an ESD event occurs, the ESD protection device activates before the internal circuitry is damaged, providing a low-resistance discharge path to prevent ESD current from flowing into the internal circuitry and causing damage.
[0003] As a commonly used ESD protection device, the silicon controlled rectifier (SCR) is widely used for the protection of I / O ports and power domains of integrated circuit chips. SCRs have advantages such as high robustness and simple manufacturing process. However, they also have disadvantages such as high turn-on voltage and low holding voltage, and are not very effective in protecting the gate oxide layer of MOSFETs at the input and output terminals of integrated circuits.
[0004] like Figure 1 The diagram shows a traditional thyristor structure used for ESD protection. Typically, the I / O port of the protected integrated circuit chip is connected to the anode of the thyristor, and the cathode is connected to ground. When the internal circuitry of the protected integrated circuit chip is operating normally, the voltage at the I / O port is insufficient to cause avalanche breakdown of the reverse PN junction formed by the N-well 20 and P-well 30 of the thyristor; therefore, the thyristor is in the off state. When the anode of the thyristor is subjected to forward ESD stress, the voltage increases. When the voltage at the anode rises to the point where avalanche breakdown occurs in the reverse PN junction formed by the N-well 20 and P-well 30, the voltage drop across the well resistance between the N-well 20 and P-well 30 caused by the avalanche breakdown current turns on the parasitic NPN or PNP transistor within the thyristor. Once one parasitic transistor turns on, the voltage drop across its collector immediately turns on the other parasitic transistor. Ultimately, the two parasitic transistors form an open-circuit positive feedback mechanism, which fully turns on the thyristor structure, creating a low-resistance path to discharge ESD current.
[0005] However, with the continuous reduction of feature size in CMOS devices and the continuous improvement of integrated circuit performance, the gate oxide thickness in integrated circuits is becoming thinner and thinner, resulting in a significant decrease in the gate oxide breakdown voltage (BV). This directly leads to a reduction in the upper limit of the ESD design window. Since the trigger voltage of traditional thyristors is mainly determined by the avalanche breakdown voltage of the reverse PN junction formed by the N-well and P-well, the trigger voltage of traditional thyristors is relatively high. This makes it ineffective in protecting the gate oxide layer of the input and output ports of integrated circuits with high process requirements, failing to meet the expected requirements and thus limiting its application range.
[0006] Therefore, it is necessary to provide improved technical solutions to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention
[0007] To address the aforementioned technical problems, this invention provides a thyristor electrostatic discharge (ESD) protection device and its manufacturing method, which can reduce the trigger voltage of the thyristor ESD protection device and can achieve different trigger voltages for the thyristor device, exhibiting high stability and high robustness.
[0008] According to a first aspect of this disclosure, a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is provided, comprising: a substrate;
[0009] An N-type well region and a P-type well region are sequentially disposed on the substrate along the transverse direction;
[0010] A first N+ injection region and a first P+ injection region are sequentially and alternately disposed within the N-type well region, and both the first N+ injection region and the first P+ injection region are connected to the anode of the thyristor electrostatic discharge device.
[0011] A second N+ injection region and a second P+ injection region are sequentially and spaced apart within the P-type well region, and both the second N+ injection region and the second P+ injection region are connected to the cathode of the thyristor electrostatic discharge device.
[0012] A third N+ injection region is disposed across the N-type well region and the P-type well region;
[0013] The third P+ injection region adjacent to the third N+ injection region,
[0014] The doping concentrations of the third N+ implantation region and the third P+ implantation region are higher than those of the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, and the second P+ implantation region.
[0015] Furthermore, when the PN junction structure formed by the third N+ injection region and the third P+ injection region undergoes Zener breakdown, it triggers the formation of a current discharge path in the thyristor.
[0016] Optionally, the smaller the spacing between the third N+ injection region and the third P+ injection region, the lower the Zener breakdown voltage of the PN junction structure formed by the third N+ injection region and the third P+ injection region.
[0017] Optionally, it further includes: a polysilicon gate disposed on the upper surface of the substrate and located between the third N+ implantation region and the third P+ implantation region.
[0018] The spacing between the third N+ implantation region and the third P+ implantation region is defined by the polysilicon gate.
[0019] Optionally, the spacing between the third N+ implantation region and the third P+ implantation region is equal to the width of the polysilicon gate.
[0020] Optionally, the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially in the lateral direction, and the third P+ implantation region is located within the P-type well region.
[0021] Optionally, the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially along the longitudinal direction, and the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are all spanned across the N-type well region and the P-type well region.
[0022] Optionally, the number of at least one of the third N+ injection region and the third P+ injection region is multiple, such that the number of PN junction structures formed by the vertically arranged third N+ injection region and the third P+ injection region is multiple.
[0023] Furthermore, a polysilicon gate is disposed between any two adjacent third N+ injection regions and third P+ injection regions.
[0024] Optionally, the first N+ injection region and the first P+ injection region, the first P+ injection region and the third N+ injection region, the third P+ injection region and the second N+ injection region, and the second N+ injection region and the second P+ injection region are all isolated by a field oxygen structure or a shallow trench isolation structure.
[0025] According to a second aspect of this disclosure, a method for manufacturing a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is provided, comprising: forming a substrate;
[0026] An N-type well region and a P-type well region are sequentially formed on the substrate along the transverse direction;
[0027] Forming an isolation structure;
[0028] A first N+ injection region and a first P+ injection region are formed within the N-type well region;
[0029] A second N+ injection region and a second P+ injection region are formed within the P-type well region;
[0030] A third N+ injection region is formed spanning the N-type well region and the P-type well region, and a third P+ injection region is formed adjacent to the third N+ injection region.
[0031] The doping concentrations of the third N+ implantation region and the third P+ implantation region are both higher than those of the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, and the second P+ implantation region.
[0032] Optionally, forming a third N+ injection region spanning the N-type well region and the P-type well region, and a third P+ injection region adjacent to the third N+ injection region, includes:
[0033] A polycrystalline silicon gate is formed on the upper surface of the substrate;
[0034] The third N+ implantation region and the third P+ implantation region are formed on both sides of the polysilicon gate using a gate self-alignment process.
[0035] The spacing between the third N+ implantation region and the third P+ implantation region is defined by the polysilicon gate.
[0036] Optionally, the spacing between the third N+ implantation region and the third P+ implantation region is equal to the width of the polysilicon gate.
[0037] Optionally, the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially in the lateral direction, and the third P+ implantation region is formed within the P-type well region.
[0038] Optionally, the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially along the longitudinal direction, and the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are all spanned across the N-type well region and the P-type well region.
[0039] Optionally, the number of polysilicon gates formed on the upper surface of the substrate is multiple, and each polysilicon gate has a third N+ implantation region and a third P+ implantation region formed by a gate self-alignment process on both sides.
[0040] Optionally, the isolation structure is a field oxygen structure or a shallow trench isolation structure.
[0041] The beneficial effects of the present invention include at least the following:
[0042] The thyristor electrostatic discharge (ESD) protection device and its manufacturing method of this invention, based on the existing structure of thyristor ESD protection devices (hereinafter referred to as thyristor devices), additionally sets a high-concentration third N+ injection region spanning the N-type well region and the P-type well region, as well as a high-concentration third P+ injection region adjacent to the third N+ injection region. This forms a PN junction structure (i.e., a Zener diode structure) composed of the high-concentration third N+ injection region and the high-concentration third P+ injection region in the thyristor ESD protection device. The current generated during Zener breakdown of the high-concentration third N+ injection region and the third P+ injection region assists in triggering the thyristor to form a current discharge path. During this process, since the breakdown voltage required for Zener breakdown is lower than that required for avalanche breakdown, the trigger voltage of the thyristor device is effectively reduced. Furthermore, the entire device has a simple structure, high stability and robustness, and good application prospects.
[0043] In a further preferred embodiment, after depositing a polysilicon gate, a gate self-alignment process is used to form high-concentration third N+ and third P+ implantation regions on both sides of the polysilicon gate, respectively. This achieves accurate positioning of the spacing between the high-concentration third N+ and third P+ implantation regions, which helps to obtain a more accurate Zener breakdown voltage. Simultaneously, by adjusting the width of the polysilicon gate, the spacing between the high-concentration third N+ and third P+ implantation regions can be precisely and stably adjusted. This results in a thyristor device with high stability, high robustness, and a precisely and stably adjustable trigger voltage (Zener breakdown voltage), which helps to enhance the application scenarios of the thyristor device.
[0044] In a further preferred embodiment, by vertically aligning the third N+ implantation region, the polysilicon gate, and the third P+ implantation region across the N-type well region and the P-type well region, the area of the thyristor device can be further reduced, which helps to achieve device miniaturization.
[0045] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present invention. Attached Figure Description
[0046] Figure 1 A cross-sectional front view of an existing silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is shown.
[0047] Figure 2 A cross-sectional front view of a silicon controlled rectifier electrostatic discharge (SED) device provided according to a first embodiment of the present invention is shown;
[0048] Figure 3 A cross-sectional top view of a silicon controlled rectifier electrostatic discharge (SRC) device provided according to a first embodiment of the present invention is shown.
[0049] Figure 4A cross-sectional top view of a silicon controlled rectifier electrostatic discharge (SED) device provided according to a second embodiment of the present invention is shown.
[0050] Figure 5 Show Figure 4 A cross-sectional front view of the thyristor electrostatic discharge protection device during ion implantation along the AA tangent;
[0051] Figure 6 Show Figure 4 A cross-sectional front view of the thyristor electrostatic discharge protection device along the AA tangent.
[0052] Figure 7 A schematic flowchart illustrating a method for manufacturing a silicon controlled rectifier electrostatic discharge (SCR) device according to an embodiment of the present invention is shown. Detailed Implementation
[0053] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0054] Example 1
[0055] Combination Figure 2 and Figure 3 As shown, the thyristor electrostatic discharge (ESD) protection device provided in the first embodiment of the present invention includes: a substrate 10 and an N-type well region 20 and a P-type well region 30 sequentially disposed on the substrate 10 in a transverse direction.
[0056] Within the N-type well region 20, a first N+ injection region 21 and a first P+ injection region 22 are sequentially spaced along the lateral direction. Both the first N+ injection region 21 and the first P+ injection region 22 are connected to the anode of the SCR (Silicon Controlled Rectifier) device via multiple electrodes 60. Within the P-type well region 30, a second N+ injection region 31 and a second P+ injection region 32 are sequentially spaced along the lateral direction. Both the second N+ injection region 31 and the second P+ injection region 32 are connected to the cathode of the SCR device via multiple electrodes 60. It can be understood that the first N+ injection region 21, the first P+ injection region 22, and the N-type well region 20 together constitute the parasitic NPN bipolar transistor of the SCR device, and the second P+ injection region 32, the second N+ injection region 31, and the P-type well region 30 together constitute the parasitic PNP bipolar transistor of the SCR device. The parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor together constitute an SCR structure for electrostatic discharge protection. When the parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor are turned on at the same time, the SCR structure can form a PNPN or NPNP SCR path and discharge ESD current.
[0057] Furthermore, the thyristor electrostatic discharge protection device in this embodiment of the invention further includes: a third N+ injection region 23 spanning the N-type well region 20 and the P-type well region 30, and a third P+ injection region 33 adjacent to the third N+ injection region 23.
[0058] Among them, the third N+ implantation region 23 and the third P+ implantation region 33 are heavily doped regions, that is, the doping concentration of the third N+ implantation region 23 and the third P+ implantation region 33 is higher than that of the first N+ implantation region 21, the first P+ implantation region 22, the second N+ implantation region 31 and the second P+ implantation region 32, so that the heavily doped third N+ implantation region 23 and the third P+ implantation region 33 can form a PN junction structure with a high doping concentration (i.e., a parasitic Zener diode structure). Furthermore, when the PN junction structure formed by the third N+ injection region 23 and the third P+ injection region 33 undergoes Zener breakdown, a breakdown current parallel to the upper surface of the substrate 10 in the horizontal direction can be formed. The voltage drop generated by this breakdown current on the well resistor can trigger the parasitic NPN bipolar transistor or the parasitic PNP bipolar transistor to turn on. When one parasitic bipolar transistor turns on, the voltage drop caused by the current generated on its collector will immediately trigger the other parasitic bipolar transistor to turn on. Finally, the two parasitic bipolar transistors form an open-circuit positive feedback mechanism, which makes the SCR structure in the silicon controlled rectifier electrostatic discharge device fully open, forming a low-resistance ESD current discharge path, and realizing electrostatic protection for the protected integrated circuit.
[0059] It is understandable that highly doped PN junctions generally undergo Zener breakdown. This means that when the reverse voltage across the PN junction increases to a certain value, a strong electric field can be established within the barrier region of the PN junction. This electric field can directly pull out valence electrons bound in covalent bonds, causing a large number of electron-hole pairs to form in the barrier region of the PN junction, resulting in a large reverse current and breakdown. (Because the space charge region of a highly doped PN junction has a large charge density and a narrow width, even a small reverse voltage applied across the PN junction can establish a strong electric field and cause Zener breakdown.) Therefore, this invention can effectively reduce the trigger voltage of thyristor devices, and the entire device has a simple structure, high stability and robustness, and good application prospects.
[0060] Furthermore, in this embodiment, since the breakdown current formed by the PN junction structure formed by the third N+ injection region 23 and the third P+ injection region 33 during Zener breakdown is parallel to the upper surface of the substrate 10, that is, parallel to the direction of the well resistor, the breakdown current formed by the PN junction during Zener breakdown can act on the well resistor to the maximum extent to form a larger voltage drop. When the parasitic bipolar transistor is triggered to conduct, the conduction degree of the parasitic bipolar transistor can also be further improved, thereby further enhancing the discharge capability of ESD current and optimizing the electrostatic protection capability of the thyristor electrostatic protection device.
[0061] In this embodiment, the smaller the distance 'a' between the third N+ injection region 23 and the third P+ injection region 33, the lower the Zener breakdown voltage of the PN junction structure formed by the third N+ injection region 23 and the third P+ injection region 33. Exemplarily, in one possible embodiment of the present invention, the Zener breakdown voltage of the PN junction structure formed by the third N+ injection region 23 and the third P+ injection region 33 is, for example, directly proportional to the distance 'a' between the third N+ injection region 23 and the third P+ injection region 33. It is understood that the space charge region of a PN junction with a high doping concentration (corresponding to the distance 'a' between the third N+ injection region 23 and the third P+ injection region 33 in this embodiment) has a large charge density, and the narrower its width, the lower the reverse voltage required to cause Zener breakdown.
[0062] Furthermore, the thyristor electrostatic discharge (ESD) device in this embodiment of the invention also includes a polysilicon gate 40 disposed on the upper surface of the substrate 10 and located between the third N+ implantation region 23 and the third P+ implantation region 33. The spacing 'a' between the third N+ implantation region 23 and the third P+ implantation region 33 is defined by the polysilicon gate 40. (See also...) Figure 2 and Figure 3 As can be seen, in the thyristor electrostatic discharge protection device provided in this embodiment, the third N+ injection region 23, the polysilicon gate 40 and the third P+ injection region 33 are arranged sequentially in the lateral direction, and the third P+ injection region 33 is located in the P-type well region 30.
[0063] Since the spacing 'a' in SCR ESD devices is generally small, and the Zener breakdown voltage of the PN junction structure formed by the third N+ implantation region 23 and the third P+ implantation region 33 is sensitive to changes in the spacing 'a', the active region etching and implantation of the third N+ implantation region 23 and the third P+ implantation region 33 can be offset due to process fluctuations, resulting in a large deviation in the Zener breakdown voltage of the final SCR ESD device. To address this issue, exemplarily, in this embodiment, a polysilicon gate 40 of a predetermined width can be deposited on the upper surface of the substrate 10 according to a pre-designed spacing 'a'. Then, a gate self-alignment process is used to implant ions of corresponding concentrations on both sides of the polysilicon gate 40 to form the third N+ implantation region 23 and the third P+ implantation region 33, respectively. It is understood that the spacing 'a' between the third N+ implantation region 23 and the third P+ implantation region 33 formed in this manner is equal to the width of the polysilicon gate 40, thus enabling accurate positioning of the spacing 'a' and contributing to a more accurate Zener breakdown voltage. Meanwhile, by adjusting the width of the deposited polysilicon gate 40, the spacing a can be precisely and stably adjusted. Furthermore, by adjusting the spacing a (which can be as small as 0), different trigger voltages can be achieved to meet the ESD protection requirements of different operating voltages. This enables the formed thyristor electrostatic protection device to have high stability, high robustness, and a precisely and stably adjustable trigger voltage (i.e., Zener breakdown voltage), which helps to enhance the application scenarios of thyristor devices.
[0064] Optionally, such as Figure 2 , Figure 5 and Figure 6 As shown, in this embodiment, the first N+ injection region 21 and the first P+ injection region 22, the first P+ injection region 22 and the third N+ injection region 23, the third P+ injection region 33 and the second N+ injection region 31, and the second N+ injection region 31 and the second P+ injection region 32 are all isolated by the field oxygen structure 50. However, it should be noted that in other embodiments of the present invention, the above-mentioned injection regions can also be isolated by a shallow trench isolation structure, and the present invention does not limit this.
[0065] Example 2
[0066] The structure of the thyristor electrostatic discharge (ESD) protection device provided in the second embodiment of the present invention is as follows: Figure 4 , Figure 5 and Figure 6 As shown.
[0067] In this embodiment, the thyristor electrostatic discharge protection device basically adopts the same structure as in the first embodiment above, and the similarities will not be repeated here.
[0068] The difference lies in that, in this embodiment, the third N+ implantation region 23, the polysilicon gate 40, and the third P+ implantation region 33 are arranged sequentially along the longitudinal direction, and the third N+ implantation region 23, the polysilicon gate 40, and the third P+ implantation region 33 are all spanned across the N-type well region 20 and the P-type well region 30.
[0069] Furthermore, in this embodiment, there are multiple polysilicon gates 40, and multiple implantation regions, including at least one of the third N+ implantation region 23 and the third P+ implantation region 33, such that there are multiple PN junction structures formed by the vertically arranged third N+ implantation region 23 and the third P+ implantation region 33. A polysilicon gate 40 is disposed between any two adjacent third N+ implantation regions 23 and third P+ implantation regions 33.
[0070] In this embodiment, by longitudinally aligning the third N+ injection region 23, the polysilicon gate 40, and the third P+ injection region 33 across the N-type well region 20 and the P-type well region 30, the area of the thyristor device can be further reduced, facilitating device miniaturization. Simultaneously, the multiple PN junction structures formed longitudinally can further enhance the breakdown current during Zener breakdown, thereby further improving the conduction level of the parasitic bipolar transistor when it is triggered, thus further enhancing the ESD current discharge capability and optimizing the electrostatic discharge capability of the thyristor electrostatic discharge device.
[0071] Furthermore, such as Figure 7 As shown, the present invention also discloses a method for manufacturing a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device, which can be used to manufacture the SCR ESD device disclosed in any of the above embodiments. The manufacturing method specifically includes performing the following steps:
[0072] In step S1, a substrate is formed. Exemplarily, substrate 10 is, for example, a P-type silicon substrate.
[0073] In step S2, an N-type well region and a P-type well region are sequentially formed on the substrate along the lateral direction. For example, N-type doping is performed in the corresponding regions on the surface of the substrate 10 along the lateral direction to form an N-type well region 20, and P-type doping is performed to form a P-type well region 30.
[0074] In step S3, an isolation structure is formed.
[0075] Optionally, the isolation structure can be a field oxide structure or a shallow trench isolation structure, and the isolation structure can be formed using conventional processes. Taking the formation of a field oxide structure as an example, for instance, an oxide layer is first deposited on the surface of substrate 10, then a hard mask is deposited, followed by etching using the mask, and finally, field oxide is grown at a high temperature, after which the hard mask is removed. The specific process is not limited in detail.
[0076] In step S4, a first N+ implantation region and a first P+ implantation region are formed within the N-type well region. Exemplarily, corresponding N-type and P-type ion implantations are performed in the N-type well region 20 to form a first N+ implantation region 21 and a first P+ implantation region 22. In this embodiment, the first N+ implantation region 21 and the first P+ implantation region 22 are arranged laterally from left to right along the surface of the substrate 10.
[0077] In step S5, a second N+ implantation region and a second P+ implantation region are formed within the P-type well region. Exemplarily, corresponding N-type and P-type ion implantations are performed in the P-type well region 30 to form a second N+ implantation region 31 and a second P+ implantation region 32. In this embodiment, the second N+ implantation region 31 and the second P+ implantation region 32 are arranged laterally from left to right along the surface of the substrate 10.
[0078] In step S6, a third N+ injection region spanning the N-type well region and the P-type well region, and a third P+ injection region adjacent to the third N+ injection region are formed.
[0079] In this invention, step S6 specifically includes: forming a polysilicon gate 40 on the upper surface of the substrate 10; performing corresponding N-type and P-type ion implantations on both sides of the polysilicon gate 40 using a gate self-alignment process to form a third N+ implantation region 23 and a third P+ implantation region 33, respectively. (Refer to...) Figure 5 The doping concentrations of the third N+ implantation region 23 and the third P+ implantation region 33 are higher than those of the first N+ implantation region 21, the first P+ implantation region 22, the second N+ implantation region 31, and the second P+ implantation region 32, so that the heavily doped third N+ implantation region 23 and the third P+ implantation region 33 can form a highly doped PN junction structure (i.e., a parasitic Zener diode structure). Furthermore, when the PN junction structure formed by the third N+ injection region 23 and the third P+ injection region 33 undergoes Zener breakdown, a breakdown current parallel to the upper surface of the substrate 10 in the horizontal direction can be formed. The voltage drop generated by this breakdown current on the well resistor can trigger the parasitic NPN bipolar transistor or the parasitic PNP bipolar transistor to turn on. When one parasitic bipolar transistor turns on, the voltage drop caused by the current generated on its collector will immediately trigger the other parasitic bipolar transistor to turn on. Finally, the two parasitic bipolar transistors form an open-circuit positive feedback mechanism, which makes the SCR structure in the silicon controlled rectifier electrostatic discharge device fully open, forming a low-resistance ESD current discharge path, and realizing electrostatic protection for the protected integrated circuit.
[0080] Optionally, in the first embodiment of the present invention, the third N+ implantation region 23, the polysilicon gate 40, and the third P+ implantation region 33 are arranged sequentially in the lateral direction, and the third P+ implantation region 33 is formed within the P-type well region 30. See also [specific details]. Figure 2 , Figure 3The foregoing description of Embodiment 1 is sufficient for understanding, and will not be repeated here.
[0081] In the second embodiment of the present invention, the third N+ implantation region 23, the polysilicon gate 40, and the third P+ implantation region 33 are arranged sequentially along the longitudinal direction, and the third N+ implantation region 23, the polysilicon gate 40, and the third P+ implantation region 33 are all disposed across the N-type well region 20 and the P-type well region 40. Furthermore, in this embodiment, multiple polysilicon gates 40 are formed on the upper surface of the substrate 10, and each polysilicon gate 40 has a third N+ implantation region 23 and a third P+ implantation region 33 formed using a gate self-alignment process on both sides. See details for further information. Figure 4 , Figure 5 , Figure 6 The foregoing description of Embodiment 2 is sufficient for understanding, and will not be repeated here.
[0082] Furthermore, the spacing between the third N+ implantation region 23 and the third P+ implantation region 33 is defined by the polysilicon gate 40. The spacing between the third N+ implantation region 23 and the third P+ implantation region 33 is equal to the width of the polysilicon gate 40.
[0083] In summary, the thyristor electrostatic discharge (ESD) protection device and its manufacturing method of this invention, based on the existing structure of thyristor ESD protection devices (hereinafter referred to as thyristor devices), additionally sets a high-concentration third N+ injection region spanning the N-type well region and the P-type well region, as well as a high-concentration third P+ injection region adjacent to the third N+ injection region. This forms a PN junction structure (i.e., a Zener diode structure) composed of the high-concentration third N+ injection region and the high-concentration third P+ injection region in the thyristor ESD protection device. The current generated during Zener breakdown of the high-concentration third N+ injection region and the third P+ injection region assists in triggering the thyristor to form a current discharge path. During this process, since the breakdown voltage required for Zener breakdown is lower than that required for avalanche breakdown, the trigger voltage of the thyristor device is effectively reduced. Furthermore, the entire device has a simple structure, high stability and robustness, and good application prospects.
[0084] In a further preferred embodiment, after depositing a polysilicon gate, a gate self-alignment process is used to form high-concentration third N+ and third P+ implantation regions on both sides of the polysilicon gate, respectively. This achieves accurate positioning of the spacing between the high-concentration third N+ and third P+ implantation regions, which helps to obtain a more accurate Zener breakdown voltage. Simultaneously, by adjusting the width of the polysilicon gate, the spacing between the high-concentration third N+ and third P+ implantation regions can be precisely and stably adjusted. This results in a thyristor device with high stability, high robustness, and a precisely and stably adjustable trigger voltage (Zener breakdown voltage), which helps to enhance the application scenarios of the thyristor device.
[0085] In a further preferred embodiment, by vertically aligning the third N+ implantation region, the polysilicon gate, and the third P+ implantation region across the N-type well region and the P-type well region, the area of the thyristor device can be further reduced, which helps to achieve device miniaturization.
[0086] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. A silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device, wherein, include: Substrate; An N-type well region and a P-type well region are sequentially disposed on the substrate along the transverse direction; A first N+ injection region and a first P+ injection region are sequentially and alternately disposed within the N-type well region, and both the first N+ injection region and the first P+ injection region are connected to the anode of the thyristor electrostatic discharge device. A second N+ injection region and a second P+ injection region are sequentially and spaced apart within the P-type well region, and both the second N+ injection region and the second P+ injection region are connected to the cathode of the thyristor electrostatic discharge device. A third N+ injection region is disposed across the N-type well region and the P-type well region; The third P+ injection region is longitudinally adjacent to the third N+ injection region; A polysilicon gate is disposed on the upper surface of the substrate and located between the third N+ implantation region and the third P+ implantation region, wherein the spacing between the third N+ implantation region and the third P+ implantation region is defined by the polysilicon gate; The doping concentrations of the third N+ implantation region and the third P+ implantation region are higher than those of the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, and the second P+ implantation region. Furthermore, when the PN junction structure formed by the third N+ injection region and the third P+ injection region undergoes Zener breakdown, the resulting breakdown current is parallel to the direction of the well resistor, triggering the thyristor to form a current discharge path. The third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially along the longitudinal direction, and the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are all spanned across the N-type well region and the P-type well region.
2. The thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The smaller the distance between the third N+ injection region and the third P+ injection region, the lower the Zener breakdown voltage of the PN junction structure formed by the third N+ injection region and the third P+ injection region.
3. The thyristor electrostatic discharge (ESD) protection device according to claim 1, wherein, The spacing between the third N+ implantation region and the third P+ implantation region is equal to the width of the polysilicon gate.
4. The thyristor electrostatic discharge protection device according to claim 1, wherein, The number of at least one of the third N+ injection regions and the third P+ injection regions is multiple, such that the number of PN junction structures formed by the vertically arranged third N+ injection regions and the third P+ injection regions is multiple. Furthermore, a polysilicon gate is disposed between any two adjacent third N+ injection regions and third P+ injection regions.
5. The thyristor electrostatic discharge protection device according to claim 1, wherein, The first N+ injection region and the first P+ injection region, the first P+ injection region and the third N+ injection region, the third P+ injection region and the second N+ injection region, and the second N+ injection region and the second P+ injection region are all isolated by field oxygen structures or shallow trench isolation structures.
6. A method for manufacturing a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device, wherein, include: Forming a substrate; An N-type well region and a P-type well region are sequentially formed on the substrate along the transverse direction; Forming an isolation structure; A first N+ injection region and a first P+ injection region are formed within the N-type well region; A second N+ injection region and a second P+ injection region are formed within the P-type well region; A third N+ injection region is formed spanning the N-type well region and the P-type well region, and a third P+ injection region is formed longitudinally adjacent to the third N+ injection region. The doping concentrations of the third N+ implantation region and the third P+ implantation region are higher than those of the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, and the second P+ implantation region. Furthermore, when the PN junction structure formed by the third N+ injection region and the third P+ injection region undergoes Zener breakdown, the resulting breakdown current is parallel to the direction of the well resistor, triggering the thyristor to form a current discharge path. Forming a third N+ injection region spanning the N-type well region and the P-type well region, and a third P+ injection region adjacent to the third N+ injection region, includes: A polycrystalline silicon gate is formed on the upper surface of the substrate; The third N+ implantation region and the third P+ implantation region are formed on both sides of the polysilicon gate using a gate self-alignment process, and the spacing between the third N+ implantation region and the third P+ implantation region is defined by the polysilicon gate. The third N+ implantation region, the polysilicon gate, and the third P+ implantation region are arranged sequentially along the longitudinal direction, and the third N+ implantation region, the polysilicon gate, and the third P+ implantation region are all spanned across the N-type well region and the P-type well region.
7. The method for manufacturing a thyristor electrostatic discharge (ESD) device according to claim 6, wherein, The spacing between the third N+ implantation region and the third P+ implantation region is equal to the width of the polysilicon gate.
8. The method for manufacturing a thyristor electrostatic discharge (ESD) device according to claim 6, wherein, The number of polysilicon gates formed on the upper surface of the substrate is multiple, and each polysilicon gate has a third N+ implantation region and a third P+ implantation region formed by gate self-alignment process on both sides.
9. The method for manufacturing a thyristor electrostatic discharge (ESD) device according to claim 6, wherein, The isolation structure is a field oxygen structure or a shallow trench isolation structure.