A soft start circuit for DC-DC converters

Abstract

The present invention relates to a soft start circuit applied to a DC-DC converter, comprising a bias current generating circuit, a narrow pulse clock generator, a ramp voltage generator, a first comparator and a two-choice circuit. The bias current generating circuit is used to generate a fixed bias current; the narrow pulse clock generator is used to generate a narrow pulse clock signal; the ramp voltage generator is used to generate a ramp voltage; the first comparator is used to compare the ramp voltage with an external reference voltage and output an enable signal; the two-choice circuit selects and outputs a ramp-up reference voltage according to the enable signal. The soft start circuit of the present invention controls the intermittent charging of the capacitor in the ramp voltage generator through a narrow pulse clock signal, controls the rising speed of the ramp voltage, and prolongs the soft start time. Through circuit configuration, the required capacitance value can be reduced, the capacitor size and the circuit size can be reduced, and the full integration of the capacitor in the soft start circuit can be achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a soft start circuit applied to a DC-DC converter. Background Art

[0002] With the rapid development of fields such as communications, computers, and consumer electronics, the demand for power management is also increasing. However, during the startup process, DC-DC converters are prone to generating inrush current and output voltage overshoot, which can damage power transistors, subsequent circuits, and even power supply batteries. To prevent this, the most common method is to use a soft-start circuit, which can control the ramp-up speed of the DC-DC converter output voltage from zero to the target value. Figure 1 As shown in (a), the traditional soft-start circuit uses a current source to charge a capacitor to limit the reference voltage V of the error amplifier. REF The rising speed, V REF Waveform Figure 1 As shown in (b) of Figure 1, the duty cycle signal of the DC-DC converter gradually increases from zero to the nominal value, thereby suppressing inrush current and output voltage overshoot.

[0003] However, since the reference voltage V REF If the voltage needs to rise at a relatively small rate, a larger capacitance value is required to implement this method. Therefore, the capacitor in the traditional soft-start circuit is difficult to integrate inside the chip, which increases the overall cost and circuit size. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a soft start circuit for a DC-DC converter. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a soft start circuit for a DC-DC converter, comprising a bias current generating circuit, a narrow pulse clock generator, a ramp voltage generator, a first comparator and a two-choose-one circuit, wherein:

[0006] The bias current generating circuit is connected to the input end of the narrow pulse clock generator and the input end of the ramp voltage generator respectively, and the bias current generating circuit is used to generate a fixed bias current;

[0007] The narrow pulse clock generator is connected to the clock signal input terminal of the ramp voltage generator and is used to generate a narrow pulse clock signal clk;

[0008] The ramp voltage generator is connected to the non-inverting input terminal of the first comparator and is used to generate a ramp voltage V according to the narrow pulse clock signal clk. SS ;

[0009] The inverting input terminal of the first comparator inputs the external reference voltage V REF The output end is connected to the two-choice circuit, which is used to adjust the ramp voltage V SS and the external reference voltage V REF Perform comparison and output an enable signal EN according to the comparison result;

[0010] The two-select-one circuit is used to select and output the ramp-up reference voltage V according to the enable signal EN. REF_SS .

[0011] In one embodiment of the present invention, the bias current generating circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first resistor, and a second resistor;

[0012] The gate of the first NMOS tube inputs the external reference voltage V REF , the source of the first NMOS tube is respectively connected to the source of the second NMOS tube and the first end of the first resistor, the second end of the first resistor is connected to the ground end, and the drain of the first NMOS tube is respectively connected to the drain and gate of the first PMOS tube;

[0013] The gate of the second NMOS transistor is connected to the source of the third NMOS transistor and the first end of the second resistor respectively, the second end of the second resistor is connected to the ground terminal, the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the second PMOS transistor respectively; the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor;

[0014] The gate of the first PMOS tube is connected to the gate of the second PMOS tube and the gate of the third PMOS tube respectively; the sources of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected to the power supply voltage terminal.

[0015] In one embodiment of the present invention, the narrow pulse clock generator includes a fourth PMOS transistor, a fourth NMOS transistor, an OR gate, a first capacitor, and a second comparator;

[0016] The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage terminal, the drain of the fourth PMOS transistor is respectively connected to the non-inverting input terminal of the second comparator, the upper plate of the first capacitor, and the drain of the fourth NMOS transistor, and the lower plate of the first capacitor is connected to the ground terminal.

[0017] The gate of the fourth NMOS transistor is connected to the output end of the OR gate, and the source of the fourth NMOS transistor is connected to the ground end;

[0018] The inverting input terminal of the second comparator inputs the external reference voltage V REF , the output end of the second comparator is respectively connected to the first input end of the OR gate and the clock signal input end of the ramp voltage generator;

[0019] The second input terminal of the OR gate is connected to the output terminal of the first comparator.

[0020] In one embodiment of the present invention, the ramp voltage generator includes a fifth PMOS transistor, a sixth PMOS transistor, a second capacitor, and a first NOT gate;

[0021] The input end of the first NOT gate is connected to the output end of the second comparator, and the output end of the first NOT gate is connected to the gate of the sixth PMOS transistor;

[0022] The gate of the fifth PMOS transistor is connected to the gate of the fourth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply voltage terminal, and the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor;

[0023] The drain of the sixth PMOS transistor is connected to the upper plate of the second capacitor and the non-inverting input terminal of the first comparator respectively, and the lower plate of the second capacitor is connected to the ground terminal.

[0024] In one embodiment of the present invention, the two-choose-one circuit includes a sixth NMOS transistor, a fifth NMOS transistor, and a second NOT gate;

[0025] The gate of the sixth NMOS transistor is connected to the output of the first comparator and the input of the second NOT gate, and the source of the sixth NMOS transistor inputs the external reference voltage V REF The drain of the sixth NMOS tube is connected to the drain of the fifth NMOS tube, and the drain of the sixth NMOS tube serves as the output end of the two-choose-one circuit to output the ramp-up reference voltage V REF_SS ;

[0026] The gate of the fifth NMOS tube is connected to the output end of the second NOT gate, and the source of the fifth NMOS tube inputs the ramp voltage V SS .

[0027] In one embodiment of the present invention, the first comparator includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and an eleventh PMOS transistor;

[0028] Wherein, the source terminals of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are all connected to the ground terminal;

[0029] The gate of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the drain of the seventh NMOS transistor is respectively connected to the drain and gate of the ninth NMOS transistor and the gate of the eleventh NMOS transistor;

[0030] The gate of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the eighth NMOS transistor is respectively connected to the gate and drain of the tenth NMOS transistor and the gate of the twelfth NMOS transistor;

[0031] The drain of the eleventh NMOS tube is connected to the drain and gate of the ninth PMOS tube respectively; the drain of the twelfth NMOS tube is connected to the drain of the tenth PMOS tube;

[0032] The gate of the seventh PMOS transistor serves as the inverting input terminal of the first comparator, the source of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor and the drain of the eleventh PMOS transistor respectively, and the drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor; the gate of the eighth PMOS transistor is connected as the non-inverting input terminal of the first comparator, and the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor;

[0033] The source of the ninth PMOS tube, the source of the tenth PMOS tube, and the source of the eleventh PMOS tube are all connected to the power supply voltage terminal;

[0034] The gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube; the drain of the tenth PMOS tube serves as the output end of the first comparator; the gate of the eleventh PMOS tube is connected to the external bias voltage V B .

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The soft-start circuit for a DC-DC converter of the present invention employs a narrow-pulse clock generator employing a relaxation oscillator structure to generate a narrow-pulse clock signal, which controls the intermittent charging of a capacitor in a ramp voltage generator, suppressing inrush current and output voltage overshoot, thereby controlling the ramp voltage's rising speed and extending the soft-start time. The circuit configuration reduces the required capacitance, capacitor size, and circuit size, enabling full integration of the capacitor in the soft-start circuit and saving overall cost.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of a traditional soft start circuit. Figure 1 (a) is a schematic diagram of the structure of a traditional soft start circuit. Figure 1 (b) is the external reference voltage V of the error amplifier in the traditional soft-start circuit. REF Waveform diagram;

[0039] Figure 2 A structural block diagram of a soft start circuit applied to a DC-DC converter provided by an embodiment of the present invention;

[0040] Figure 3 A circuit diagram of a soft start circuit applied to a DC-DC converter provided by an embodiment of the present invention;

[0041] Figure 4 A circuit diagram of a comparator provided by an embodiment of the present invention;

[0042] Figure 5 The following are simulation results provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0043] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a soft start circuit for a DC-DC converter proposed in accordance with the present invention in conjunction with the accompanying drawings and specific embodiments.

[0044] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0045] Example 1

[0046] See Figure 2 , Figure 2 The present invention provides a block diagram of a soft start circuit for a DC-DC converter.

[0047] like Figure 2 As shown, the soft start circuit of this embodiment includes a bias current generating circuit 10 , a narrow pulse clock generator 20 , a ramp voltage generator 30 , a first comparator 40 and a two-select-one circuit 50 .

[0048] Specifically, the power supply voltage terminal VDD outputs the power supply voltage to power the circuit, and the bias current generating circuit 10 inputs the reference voltage V REF , outputs a fixed bias current. Specifically, the bias current generating circuit 10 is connected to the input end of the narrow pulse clock generator 20 and the input end of the ramp voltage generator 30 respectively. The bias current generating circuit 10 generates the bias current I required by the narrow pulse clock generator 20 and the ramp voltage generator 30. B1 and bias current I B2 .

[0049] The narrow pulse clock generator 20 is connected to the clock signal input terminal of the ramp voltage generator 30, and the narrow pulse clock generator 20 is used to generate a narrow pulse clock signal clk. The ramp voltage generator 30 is connected to the non-inverting input terminal of the first comparator 40, and the ramp voltage generator 30 is used to generate a ramp voltage V according to the narrow pulse clock signal clk. SS Specifically, the output signal of the first comparator 40 is shaped to output a narrow pulse clock signal clk with a high and low level periodic change.

[0050] The inverting input terminal of the first comparator 40 inputs the external reference voltage V REF The output terminal is connected to the two-choose-one circuit 50, and the first comparator 40 is used to compare the ramp voltage V SS and external reference voltage V REF Compare and output the enable signal EN according to the comparison result; the two-select circuit 50 is used to select and output the ramp-up reference voltage V according to the enable signal EN REF_SS Specifically, when the ramp voltage V SS Greater than the external reference voltage V REF When the output enable signal EN is high, the two-select circuit 50 outputs the external reference voltage V REF Otherwise, the output enable signal EN is low, and the two-select-one circuit 50 outputs the ramp voltage V SS .

[0051] See Figure 3 , Figure 3 The present invention provides a schematic structural diagram of a soft start circuit for a DC-DC converter.

[0052] like Figure 3 As shown, in a specific embodiment, the bias current generating circuit 10 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first resistor R1 and a second resistor R2.

[0053] Specifically, the gate of the first NMOS transistor MN1 inputs the external reference voltage V REF The source of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2 and the first end of the first resistor R1 respectively, the second end of the first resistor R1 is connected to the ground terminal GND, and the drain of the first NMOS transistor MN1 is connected to the drain and gate of the first PMOS transistor MP1 respectively.

[0054] The gate of the second NMOS transistor MN2 is respectively connected to the source of the third NMOS transistor MN3 and the first end of the second resistor R2. The second end of the second resistor R2 is connected to the ground terminal GND. The drain of the second NMOS transistor MN2 is respectively connected to the gate of the third NMOS transistor MN3 and the drain of the second PMOS transistor MP2. The drain of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3.

[0055] Furthermore, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 respectively; the sources of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all connected to the power supply voltage terminal VDD.

[0056] In a specific embodiment, the bias current generating circuit 10 adopts a VI conversion structure, and uses the negative feedback principle to convert the external reference voltage V REF Clamped to the second resistor R2, thus generating a fixed bias current I B , the expression is as follows:

[0057]

[0058] Among them, V REF is the external reference voltage, I B To fix the bias current, R2 is the resistance value of the second resistor.

[0059] Furthermore, the current passes through the current mirror composed of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5, providing bias current I for the narrow pulse clock generator 20 and the ramp voltage generator 30 respectively. B1 and bias current IB2 .

[0060] In a specific embodiment, the narrow pulse clock generator 20 includes a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, an OR gate OR1, a first capacitor C1, and a second comparator 20-1.

[0061] Specifically, the gate of the fourth PMOS transistor MP4 is connected to the gate of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4 is connected to the power supply voltage terminal VDD, the drain of the fourth PMOS transistor MP4 is respectively connected to the non-inverting input terminal of the second comparator 20-1, the upper plate of the first capacitor C1 and the drain of the fourth NMOS transistor MN4, and the lower plate of the first capacitor C1 is connected to the ground terminal GND.

[0062] A gate of the fourth NMOS transistor MN4 is connected to the output end of the OR gate OR1 , and a source of the fourth NMOS transistor MN4 is connected to the ground end GND.

[0063] Furthermore, the inverting input terminal of the second comparator 20-1 inputs the external reference voltage V REF The output terminal of the second comparator 20 - 1 is connected to the first input terminal of the OR gate OR1 and the clock signal input terminal of the ramp voltage generator 30 ; the second input terminal of the OR gate OR1 is connected to the output terminal of the first comparator 40 .

[0064] In a specific embodiment, when the soft start circuit is working, the bias current I B1 The first capacitor C1 is charged. At this time, the second input terminal of the OR gate OR1 is at a low potential. The OR gate OR1 is controlled by the first input terminal, that is, by the first comparator 40 .

[0065] Furthermore, through the bias current I B1 Continuously charging, the voltage V on the first capacitor C1 C1 exceeds the external reference voltage V REF , the second comparator 20-1 outputs a high-level signal, and the fourth NMOS transistor MN4 is turned on. At this time, the level of the first capacitor C1 drops to zero, and the output of the second comparator 20-1 will instantly become a low-level signal. This cycle repeats, and the narrow pulse clock generator 20 can output the narrow pulse clock signal clk.

[0066] Preferably, the narrow pulse clock generator 20 adopts a relaxation oscillator structure.

[0067] In a specific embodiment, the ramp voltage generator 30 includes a fifth PMOS transistor MP5 , a sixth PMOS transistor MP6 , a second capacitor C2 , and a first inverter INV1 .

[0068] The input end of the first NOT gate INV1 is connected to the output end of the second comparator 20 - 1 , and the output end of the first NOT gate INV1 is connected to the gate of the sixth PMOS transistor MP6 .

[0069] The gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth PMOS transistor MP4 , the source of the fifth PMOS transistor MP5 is connected to the power supply voltage terminal VDD, and the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6 .

[0070] The drain of the sixth PMOS transistor MP6 is connected to the upper plate of the second capacitor C2 and the non-inverting input terminal of the first comparator 40 respectively, and the lower plate of the second capacitor C2 is connected to the ground terminal GND.

[0071] In a specific embodiment, the ramp voltage generator 30 inputs a bias current I B2 , and inputs the clock signal clk as the control signal, so that the second capacitor C2 is intermittently charged, and the voltage of the second capacitor C2 slowly rises and outputs the ramp voltage V SS .

[0072] In a specific embodiment, the narrow pulse clock signal clk is shaped by the first inverter INV1 and then input into the gate of the sixth PMOS transistor MP6.

[0073] Specifically, the narrow pulse clock signal clk can control the charging path in the ramp voltage generator 30. When the narrow pulse clock signal clk is at a low level, the sixth PMOS transistor MP6 is turned on, thereby biasing the current I B2 The second capacitor C2 is charged. At this time, the voltage V C2 When the narrow pulse clock signal clk is at a high level, the sixth PMOS tube MP6 is turned off, and the bias current I B2 The second capacitor C2 cannot be charged, so the voltage V on the second capacitor C2 C2 Maintain the charging voltage state of the previous cycle. Intermittently charge the second capacitor C2 to control the ramp voltage V SS The rising speed.

[0074] In a specific embodiment, the two-to-one circuit 50 includes a sixth NMOS transistor MN6 , a fifth NMOS transistor MN5 , and a second inverter INV2 .

[0075] The gate of the sixth NMOS transistor MN6 is connected to the output terminal of the first comparator 40 and the input terminal of the second inverter INV2 respectively, and the source of the sixth NMOS transistor MN6 inputs the external reference voltage V REFThe drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth NMOS transistor MN5. The drain of the sixth NMOS transistor MN6 serves as the output terminal of the two-select-one circuit 50 to output the ramp-up reference voltage V REF_SS .

[0076] The gate of the fifth NMOS transistor MN5 is connected to the output end of the second inverter INV2, and the source of the fifth NMOS transistor MN5 inputs the ramp voltage V SS .

[0077] See Figure 4 , Figure 4 4 is a schematic diagram of the circuit structure of a comparator provided by an embodiment of the present invention.

[0078] like Figure 4 As shown, the first comparator 40 includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10 and an eleventh PMOS transistor MP11.

[0079] The sources of the seventh NMOS transistor MN7 , the eighth NMOS transistor MN8 , the ninth NMOS transistor MN9 , the tenth NMOS transistor MN10 , the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 are all connected to the ground terminal GND.

[0080] Specifically, the gate of the seventh NMOS transistor MN7 is connected to the drain of the eighth NMOS transistor MN8 , and the drain of the seventh NMOS transistor MN7 is respectively connected to the drain and gate of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11 .

[0081] The gate of the eighth NMOS transistor MN8 is connected to the drain of the seventh NMOS transistor MN7 . The drain of the eighth NMOS transistor MN8 is respectively connected to the gate and drain of the tenth NMOS transistor MN10 and the gate of the twelfth NMOS transistor MN12 .

[0082] The drain of the eleventh NMOS transistor MN11 is connected to the drain and gate of the ninth PMOS transistor MP9 ; the drain of the twelfth NMOS transistor MN12 is connected to the drain of the tenth PMOS transistor MP10 .

[0083] In a specific embodiment, the gate of the seventh PMOS transistor MP7 serves as the inverting input terminal of the first comparator 40, the source of the seventh PMOS transistor MP7 is respectively connected to the source of the eighth PMOS transistor MP8 and the drain of the eleventh PMOS transistor MP11, and the drain of the seventh PMOS transistor MP7 is connected to the drain of the seventh NMOS transistor MN7; the gate of the eighth PMOS transistor MP8 is connected as the non-inverting input terminal of the first comparator 40, and the drain of the eighth PMOS transistor MP8 is connected to the drain of the eighth NMOS transistor MN8.

[0084] Specifically, the source of the ninth PMOS transistor MP9, the source of the tenth PMOS transistor MP10, and the source of the eleventh PMOS transistor MP11 are all connected to the power supply voltage terminal VDD; the gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10; the drain of the tenth PMOS transistor MP10 serves as the output terminal of the first comparator 40; and the gate of the eleventh PMOS transistor MP11 is connected to the external bias voltage VB.

[0085] In a specific embodiment, when the ramp voltage V SS Does not exceed the reference voltage V REF When the ramp voltage V SS Exceeds the reference voltage V REF When , the enable signal EN output by the comparator is high.

[0086] Specifically, when the first comparator 40 outputs the enable signal EN at a low level, the second invertor INV2 is converted, the fifth NMOS transistor MN5 is turned on, the sixth NMOS transistor MN6 is turned off, and the two-select-one circuit 50 outputs the ramp voltage V SS .

[0087] Similarly, when the first comparator 40 outputs the enable signal EN as a high level, the sixth NMOS transistor MN6 is turned on. At the same time, after the conversion of the second NOT gate INV2, the fifth NMOS transistor MN5 is turned off, and the two-select circuit 50 outputs the external reference voltage V REF .

[0088] It is worth noting that the second comparator 20 - 1 and the first comparator 40 have the same structure, both using a two-stage open-loop amplifier structure.

[0089] Specifically, taking the first comparator 40 as an example, the first stage of the comparator employs a negative resistance amplifier structure. The seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are of equal size. The output impedance of the first-stage negative resistance amplifier is extremely high, thereby achieving extremely high gain. The second stage of the comparator employs a push-pull current comparator, which accelerates comparison speed.

[0090] Furthermore, the effect of the slope compensation circuit of this embodiment is described through simulation experiments.

[0091] This embodiment is simulated on Cadence Spectre using SMIC's 0.18μm BCD process. Figure 5 It can be seen that the ramp voltage V SS It will be controlled by the narrow pulse clock and rise slowly. At this time, the ramp-up reference voltage V REF_SS is the ramp voltage V SS , when the ramp voltage V SS exceeds the external reference voltage V REF When the soft start output ramps up the reference voltage V REF_SS is the external reference voltage V REF See for example Figure 5 The simulation results shown are consistent with the design of the soft start circuit of this embodiment.

[0092] This embodiment of the soft-start circuit for a DC-DC converter employs a relaxation oscillator structure to generate a narrow-pulse clock signal, which controls the intermittent charging of the capacitor in the ramp voltage generator. This suppresses inrush current and output voltage overshoot, controls the ramp voltage's rise rate, and extends the soft-start time. This circuit configuration reduces the required capacitance, capacitor size, and circuit size, enabling full integration of the capacitor in the soft-start circuit and saving overall cost.

[0093] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0094] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A soft start circuit for a DC-DC converter, characterized in that: The invention comprises a bias current generating circuit (10), a narrow pulse clock generator (20), a ramp voltage generator (30), a first comparator (40) and a two-select-one circuit (50), wherein: The bias current generating circuit (10) is connected to the input end of the narrow pulse clock generator (20) and the input end of the ramp voltage generator (30), respectively, and the bias current generating circuit (10) is used to generate a fixed bias current; the narrow pulse clock generator (20) is connected to the clock signal input end of the ramp voltage generator (30) and is used to generate a narrow pulse clock signal clk; the ramp voltage generator (30) is connected to the non-inverting input end of the first comparator (40) and is used to generate a ramp voltage V according to the narrow pulse clock signal clk SS The first comparator (40) inputs an external reference voltage V to the inverting input terminal; REF The output end is connected to the two-choice circuit (50) for the ramp voltage V SS and the external reference voltage V REF Comparison is performed and an enable signal EN is output according to the comparison result; the two-select-one circuit (50) is used to select and output the ramp-up reference voltage V according to the enable signal EN. REF_SS ; The bias current generating circuit (10) comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a first resistor (R1) and a second resistor (R2); wherein the gate of the first NMOS transistor (MN1) inputs the external reference voltage V REF The source of the first NMOS tube (MN1) is respectively connected to the source of the second NMOS tube (MN2) and the first end of the first resistor (R1); the second end of the first resistor (R1) is connected to the ground (GND); the drain of the first NMOS tube (MN1) is respectively connected to the drain and gate of the first PMOS tube (MP1); the gate of the second NMOS tube (MN2) is respectively connected to the source of the third NMOS tube (MN3) and the first end of the second resistor (R2); the second end of the second resistor (R2) is connected to the ground (GND); the second NMOS The drain of the OS transistor (MN2) is respectively connected to the gate of the third NMOS transistor (MN3) and the drain of the second PMOS transistor (MP2); the drain of the third NMOS transistor (MN3) is connected to the drain of the third PMOS transistor (MP3); the gate of the first PMOS transistor (MP1) is respectively connected to the gate of the second PMOS transistor (MP2) and the gate of the third PMOS transistor (MP3); the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are all connected to the power supply voltage terminal (VDD); The narrow pulse clock generator (20) comprises a fourth PMOS transistor (MP4), a fourth NMOS transistor (MN4), an OR gate (OR1), a first capacitor (C1) and a second comparator (20-1); wherein the gate of the fourth PMOS transistor (MP4) is connected to the gate of the third PMOS transistor (MP3), the source of the fourth PMOS transistor (MP4) is connected to the power supply voltage terminal (VDD), the drain of the fourth PMOS transistor (MP4) is respectively connected to the non-inverting input terminal of the second comparator (20-1), the upper plate of the first capacitor (C1) and the drain of the fourth NMOS transistor (MN4), and the lower plate of the first capacitor (C1) is connected to the ground terminal (GND); the gate of the fourth NMOS transistor (MN4) is connected to the output terminal of the OR gate (OR1), and the source of the fourth NMOS transistor (MN4) is connected to the ground terminal (GND); the inverting input terminal of the second comparator (20-1) inputs the external reference voltage V REF , the output end of the second comparator (20-1) is respectively connected to the first input end of the OR gate (OR1) and the clock signal input end of the ramp voltage generator (30); the second input end of the OR gate (OR1) is connected to the output end of the first comparator (40); The ramp voltage generator (30) comprises a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a second capacitor (C2) and a first NOT gate (INV1); wherein the input end of the first NOT gate (INV1) is connected to the output end of the second comparator (20-1), and the output end of the first NOT gate (INV1) is connected to the gate of the sixth PMOS transistor (MP6); the gate of the fifth PMOS transistor (MP5) is connected to the gate of the fourth PMOS transistor (MP4), the source of the fifth PMOS transistor (MP5) is connected to the power supply voltage end (VDD), and the drain of the fifth PMOS transistor (MP5) is connected to the source of the sixth PMOS transistor (MP6); the drain of the sixth PMOS transistor (MP6) is respectively connected to the upper plate of the second capacitor (C2) and the non-inverting input end of the first comparator (40), and the lower plate of the second capacitor (C2) is connected to the ground end (GND); The fixed bias current generated by the bias current generating circuit (10) passes through a current mirror composed of the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5), and provides bias currents for the narrow pulse clock generator (20) and the ramp voltage generator (30), respectively.

2. The soft start circuit for a DC-DC converter according to claim 1, wherein: The two-choose-one circuit (50) comprises a sixth NMOS transistor (MN6), a fifth NMOS transistor (MN5) and a second NOT gate (INV2); The gate of the sixth NMOS transistor (MN6) is respectively connected to the output end of the first comparator (40) and the input end of the second NOT gate (INV2), and the source of the sixth NMOS transistor (MN6) inputs the external reference voltage V REF The drain of the sixth NMOS transistor (MN6) is connected to the drain of the fifth NMOS transistor (MN5), and the drain of the sixth NMOS transistor (MN6) serves as the output end of the two-select-one circuit (50) to output the ramp-up reference voltage V REF_SS ; The gate of the fifth NMOS transistor (MN5) is connected to the output end of the second NOT gate (INV2), and the source of the fifth NMOS transistor (MN5) inputs the ramp voltage V SS .

3. The soft start circuit for a DC-DC converter according to claim 2, wherein: The first comparator (40) comprises a seventh NMOS tube (MN7), an eighth NMOS tube (MN8), a ninth NMOS tube (MN9), a tenth NMOS tube (MN10), an eleventh NMOS tube (MN11), a twelfth NMOS tube (MN12), a seventh PMOS tube (MP7), an eighth PMOS tube (MP8), a ninth PMOS tube (MP9), a tenth PMOS tube (MP10) and an eleventh PMOS tube (MP11); Wherein, the source electrodes of the seventh NMOS tube (MN7), the eighth NMOS tube (MN8), the ninth NMOS tube (MN9), the tenth NMOS tube (MN10), the eleventh NMOS tube (MN11) and the twelfth NMOS tube (MN12) are all connected to the ground terminal (GND); The gate of the seventh NMOS tube (MN7) is connected to the drain of the eighth NMOS tube (MN8), and the drain of the seventh NMOS tube (MN7) is respectively connected to the drain and gate of the ninth NMOS tube (MN9) and the gate of the eleventh NMOS tube (MN11); The gate of the eighth NMOS tube (MN8) is connected to the drain of the seventh NMOS tube (MN7), and the drain of the eighth NMOS tube (MN8) is respectively connected to the gate and drain of the tenth NMOS tube (MN10) and the gate of the twelfth NMOS tube (MN12); The drain of the eleventh NMOS transistor (MN11) is respectively connected to the drain and gate of the ninth PMOS transistor (MP9); The drain of the twelfth NMOS transistor (MN12) is connected to the drain of the tenth PMOS transistor (MP10); The gate of the seventh PMOS tube (MP7) serves as the inverting input terminal of the first comparator (40), the source of the seventh PMOS tube (MP7) is respectively connected to the source of the eighth PMOS tube (MP8) and the drain of the eleventh PMOS tube (MP11), and the drain of the seventh PMOS tube (MP7) is connected to the drain of the seventh NMOS tube (MN7); The gate of the eighth PMOS transistor (MP8) serves as the non-inverting input terminal of the first comparator (40), and the drain of the eighth PMOS transistor (MP8) is connected to the drain of the eighth NMOS transistor (MN8); The source of the ninth PMOS tube (MP9), the source of the tenth PMOS tube (MP10), and the source of the eleventh PMOS tube (MP11) are all connected to the power supply voltage terminal (VDD); The gate of the ninth PMOS transistor (MP9) is connected to the gate of the tenth PMOS transistor (MP10); The drain of the tenth PMOS tube (MP10) serves as the output end of the first comparator (40); The gate of the eleventh PMOS transistor (MP11) is connected to the external bias voltage V B .

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