Sampling circuit based on multi-channel high-speed SAR ADC

Abstract

The application discloses a sampling circuit based on a multi-channel high-speed SAR ADC, a first sampling switch is composed of a gate voltage self-boosting circuit and a gate voltage transmission control switch, can complete selection of a channel from multiple channels and sampling of an input signal of the channel; a second sampling switch is composed of an NMOS tube, can realize synchronization sampling of the signal of the channel with the first sampling switch, and transmit the result to a high-speed ADC for conversion and output. The application improves the traditional gate voltage self-boosting sampling circuit, uses a multiplexing design concept, adopts the gate voltage transmission control switch, realizes sharing of multiple channels with one ADC, improves the identity of conversion precisions of the channels, introduces the second sampling switch, eliminates the nonlinearity of the sampling voltage caused by the drain current of the MOS tube on one hand, and isolates the output nodes of the multiple channels from the top end of the capacitor array of the ADC on the other hand, solves the problem of the capacitor mismatch of the capacitor array caused by the large parasitic capacitance of the output nodes of the multiple channels, and greatly improves the precision of the whole ADC system.

Description

Technical Field

[0001] This invention belongs to the field of analog signal chain technology, and specifically relates to a sampling circuit based on a multi-channel high-speed SAR ADC. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), many electronic systems in IoT fields such as environmental monitoring, mobile sharing devices, and fire alarms need to acquire and process multiple analog input signals during operation. This can be achieved by using multiple ADCs in the system, but this approach significantly increases system power consumption and chip area. To solve this problem, it is necessary to design a high-speed SAR ADC with multi-channel sampling that meets the above application requirements while achieving high speed, low power consumption, and high integration. The multi-channel sampling circuit, located at the front end of the multi-channel high-speed SAR ADC, discretizes the input continuous analog signal. This is the first step in the ADC's analog-to-digital conversion and plays a crucial role in improving the speed and accuracy of the entire ADC system.

[0003] For multi-channel high-speed SAR ADCs, as the number of channels increases, the traditional method of directly connecting multiple sampling circuits in parallel will face many problems: First, when the number of channels reaches dozens, the number of transistors in the sampling circuit will increase dramatically, greatly increasing the system's power consumption and chip area; Second, in a multi-channel SAR ADC sampling circuit, when one channel is turned on while the others are turned off, the leakage current of the MOSFET prevents the channel from being completely turned off, causing charge leakage at the gate of the sampling transistor of the turned-on channel, resulting in nonlinearity in the output voltage. As the number of channels increases, this nonlinearity will reduce the system's accuracy; Third, as the number of channels increases, the parasitic capacitance of the output node of the multi-channel sampling circuit will become very large. When this node is directly connected to the top end of the capacitor array, it will cause capacitor mismatch in the capacitor array, causing nonlinearity errors in the output and greatly reducing the accuracy of the entire ADC system. Summary of the Invention

[0004] To overcome the problems existing in the above-mentioned technologies, this invention provides a sampling circuit based on a multi-channel high-speed SAR ADC. Utilizing a multiplexing design concept and employing a gate voltage transfer control switch, multiple channels can share a single ADC, improving the consistency of conversion accuracy across all channels. Simultaneously, a second sampling switch is introduced, which eliminates the nonlinearity of the sampling voltage caused by MOSFET leakage current and isolates the multi-channel output nodes from the top terminal of the ADC capacitor array. This solves the problem of capacitor mismatch in the capacitor array caused by the large parasitic capacitance of the multi-channel output nodes, greatly improving the accuracy of the entire ADC system.

[0005] To achieve the above objectives, the present invention provides a sampling circuit based on a multi-channel high-speed SAR ADC, including a first sampling switch and a second sampling switch, wherein,

[0006] The first sampling switch is used to select one input signal from multiple input signals and sample that input signal. Its input terminal is coupled to N external input signals V. i <1:N>, its output is coupled to the input of the second sampling switch, providing the second sampling switch with an input signal V. i <n>;

[0007] The second sampling switch is used to synchronize the sampling of signal V with the first sampling switch. i <n>Sampling is performed, and the result Vout is transmitted to the subsequent high-speed ADC for conversion and output. Its input is coupled to the output of the first sampling switch, and its output Vout is coupled to the Top terminal of the capacitor array of the subsequent high-speed ADC.

[0008] Preferably, the first sampling switch includes a gate voltage bootstrap circuit and N gate voltage transfer control switches S<1:N>, wherein the fo_vi terminal of the gate voltage bootstrap circuit is coupled to the fo_vi terminal of the gate voltage transfer control switch, and the Vg terminal of the gate voltage bootstrap circuit is coupled to the Vg terminal of the gate voltage transfer control switch and the Vg terminal of the second sampling switch, respectively.

[0009] Preferably, the gate voltage bootstrap circuit includes two control signals clk_s and clk_s_n with opposite polarities, and six NMOS transistors: M 202 M 203 M 206 M 207 M 208 and M 210 4 PMOS transistors: M 201 M 204 M 205 and M 209 A capacitor C0, wherein:

[0010] The control signals clk_s are respectively coupled to M 201 M 202 M 209 and M 210 When the gate of the circuit is high, the circuit enters the sampling state; the control signals clk_s_n are coupled to M. 203 M 208 The gate and M 209 M 210 When the drain of the circuit is high, the circuit enters a holding state.

[0011] M 204 The drain of the capacitor is coupled to the power supply AVDD, its gate is coupled to the Vg terminal, and its source is coupled to the upper plate of capacitor C0 and M, respectively. 205 The source of capacitor C0 is connected in this way, which allows the voltage on the upper plate of capacitor C0 to reach a desired large value without being clamped.

[0012] The fo_vi end is respectively connected to M 202 The source, M 203 Drain, M 206 The source of the capacitor C0 is coupled to the lower plate of the capacitor C0. When the circuit is in the sampling state, the voltage at this terminal will change with the voltage of the input signal selected by the gate voltage transfer control switch.

[0013] Vg terminal and M respectively 204 M 206 The gate and M 205 M 207 The drains are coupled together;

[0014] M 201 M 209 The source and M 207 The gates of all are coupled to the power supply AVDD; M 203 M 208 M 210 The source electrodes are all coupled to ground AGND; M 201 M 202 M 206 The drain and M 205 The gates are coupled together; M 207 The source and M 208 The drain is coupled.

[0015] Preferably, the gate voltage transfer control switch S<1:N> is composed of N gate voltage transfer control switches connected in parallel.

[0016] Preferably, the gate voltage transfer control switch includes an enable signal OE1, two enable signals OE2 and OE2_N with opposite polarities, and seven NMOS transistors: M 303 M 304 M 305 M 306 M 307 M 308 and M 310 3 PMOS transistors: M 301 M 302 and M 309 ,in:

[0017] Enable signal OE1 is coupled to M respectively 301 M 302 The gate of the signal, and the enable signal OE2 are respectively coupled to M. 303 M 304 The gates of the two together control the transmission of signals at the Vg port;

[0018] Enable signal OE2 is coupled to M respectively 309 M 310 The gate, and through M 309 M 310 The inverter formed by these components generates an enable signal OE2_N, and OE2_N is coupled to M. 309 M 310 The drain; the enable signal OE2_N is coupled to M. 305 The gate, controlling M 305 The conduction and cutoff of M, when it is high level, 305 Conduction;

[0019] Vg terminals are coupled to M respectively. 301 The source, M 303 The drain, input V i The terminals are respectively coupled to M 307 Drain, M 308 The source, output V o Terminal coupling M 308 The drain electrode;

[0020] fo_vi terminal coupling M 307 The source pole, when M 307 When the gate is high, the voltage at the fo_vi terminal will follow the input signal V. i Voltage changes;

[0021] M 306 gate, M 309 The sources of all are coupled to the power supply AVDD; M 305 M 310 The source electrodes are all coupled to ground AGND; M 301 Drain coupling M 302 The source pole, M 303 Source coupling M 304 The drain, M 305 Drain coupling M 306 The source pole;

[0022] M 307 M 308 The gates of M are respectively 302 M 306 The drain and M 304 The source and the pole are coupled.

[0023] Preferably, the second sampling switch uses only one NMOS transistor M. 401 To achieve, among which,

[0024] M 401 The gate of the device is coupled to the Vg terminal of the second sampling switch, and its source is coupled to the output V of the gate voltage transfer control switch. o The drain of the first sampling switch is coupled to the Vout terminal of the second sampling switch, and the final sampled signal is output.

[0025] The beneficial effects of this invention include at least the following: Compared with the prior art, this invention utilizes a reuse design concept and employs a gate voltage transfer control switch to enable multiple channels to share a single ADC, thereby improving the consistency of conversion accuracy across channels and reducing the chip area occupied by the multi-channel sampling circuit. Furthermore, the introduction of a second sampling switch eliminates the nonlinearity of the sampling voltage caused by MOS transistor leakage current. Additionally, it isolates the multi-channel output nodes from the top of the ADC capacitor array, solving the problem of capacitor mismatch caused by the large parasitic capacitance of the multi-channel output nodes, and significantly improving the accuracy of the entire ADC system. Attached Figure Description

[0026] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:

[0027] Figure 1 This is a block diagram of the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;

[0028] Figure 2 This is a block diagram of the specific structure of the sampling circuit based on the multi-channel high-speed SAR ADC in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;

[0030] Figure 4 This is a circuit diagram of the gate voltage transfer control switch in the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;

[0031] Figure 5 This is a simulation test diagram of the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;

[0032] Figure 6 This is a time-domain simulation diagram of Vout and clk_s of the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;

[0033] Figure 7 The Vout and V of the sampling circuit based on the multi-channel high-speed SAR ADC in this embodiment of the invention are... i <1> Time-domain simulation diagram;

[0034] Figure 8 This is an FFT simulation result diagram of the sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention. Detailed Implementation

[0035] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] See Figure 1-4 The diagram shows a block diagram and circuit schematic of a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention, including a first sampling switch 100 and a second sampling switch 400, wherein...

[0037] The first sampling switch 100 is used to select one input signal from multiple input signals and sample that input signal. Its input terminal is coupled to N external input signals V. i <1:N>, its output terminal is coupled to the input terminal of the second sampling switch 400, providing the second sampling switch 400 with an input signal V. i <n>;

[0038] The second sampling switch 400 is used to synchronize the sampling of signal V with the first sampling switch 100. i <n>Sampling is performed, and the result Vout is transmitted to the subsequent high-speed ADC for conversion and output. Its input terminal is coupled to the output terminal of the first sampling switch 100, and its output terminal Vout is coupled to the Top terminal of the capacitor array of the subsequent high-speed ADC.

[0039] The first sampling switch 100 includes a gate voltage bootstrap circuit 200 and N gate voltage transfer control switches 300S<1:N>, wherein the fo_vi terminal of the gate voltage bootstrap circuit 200 is coupled to the fo_vi terminal of the gate voltage transfer control switch 300, and the Vg terminal of the gate voltage bootstrap circuit 200 is coupled to the Vg terminal of the gate voltage transfer control switch 300 and the Vg terminal of the second sampling switch 400.

[0040] The gate voltage bootstrap circuit 200 includes two control signals clk_s and clk_s_n with opposite polarities, and six NMOS transistors: M 202 M 203 M 206 M 207 M 208 and M 210 4 PMOS transistors: M 201 M 204 M 205 and M 209 A capacitor C0, wherein:

[0041] The control signals clk_s are respectively coupled to M 201 M 202 M 209 and M 210 When the gate of the circuit is high, the circuit enters the sampling state; the control signals clk_s_n are coupled to M. 203 M 208 The gate and M 209 M 210 When the drain of the circuit is high, the circuit enters a holding state.

[0042] M 204 The drain of the capacitor is coupled to the power supply AVDD, its gate is coupled to the Vg terminal, and its source is coupled to the upper plate of capacitor C0 and M, respectively. 205 The source of capacitor C0 is connected in this way, which allows the voltage on the upper plate of capacitor C0 to reach a desired large value without being clamped.

[0043] The fo_vi end is respectively connected to M 202 The source, M 203 Drain, M 206 The source of the capacitor C0 is coupled to the lower plate of the capacitor C0. When the circuit is in the sampling state, the voltage at this terminal will change with the voltage of the input signal selected by the gate voltage transfer control switch 300.

[0044] Vg terminal and M respectively 204 M 206 The gate and M 205 M 207 The drains are coupled together;

[0045] M 201 M 209 The source and M 207 The gates of all are coupled to the power supply AVDD; M 203 M 208 M 210 The source electrodes are all coupled to ground AGND; M 201 M 202 M 206 The drain and M 205 The gates are coupled together; M 207 The source and M 208 The drain is coupled.

[0046] The grid voltage transfer control switch 300S<1:N> is composed of N grid voltage transfer control switches 300 connected in parallel.

[0047] The gate voltage transfer control switch 300 includes one enable signal OE1, two enable signals OE2 and OE2_N with opposite polarities, and seven NMOS transistors: M 303 M 304 M 305 M 306 M 307 M 308 and M 310 3 PMOS transistors: M 301 M 302 and M 309 ,in:

[0048] Enable signal OE1 is coupled to M respectively 301 M 302 The gate of the signal, and the enable signal OE2 are respectively coupled to M. 303 M 304 The gates of the two together control the transmission of signals at the Vg port;

[0049] Enable signal OE2 is coupled to M respectively 309 M 310 The gate, and through M 309 M 310 The inverter formed by these components generates an enable signal OE2_N, and OE2_N is coupled to M. 309 M 310 The drain; the enable signal OE2_N is coupled to M. 305 The gate, controlling M 305 The conduction and cutoff of M, when it is high level, 305 Conduction;

[0050] Vg terminals are coupled to M respectively. 301 The source, M 303 The drain, input V i The terminals are respectively coupled to M 307 Drain, M 308 The source, output V o Terminal coupling M 308 The drain electrode;

[0051] fo_vi terminal coupling M 307 The source pole, when M 307 When the gate is high, the voltage at the fo_vi terminal will follow the input signal V. i Voltage changes;

[0052] M 306 gate, M 309 The sources of all are coupled to the power supply AVDD; M 305 M 310 The source electrodes are all coupled to ground AGND; M 301 Drain coupling M 302 The source pole, M 303 Source coupling M 304 The drain, M 305 Drain coupling M 306 The source pole;

[0053] M 307 M 308 The gates of M are respectively 302 M 306 The drain and M 304 The source and the pole are coupled.

[0054] The second sampling switch 400 uses only one NMOS transistor M. 401 To achieve, among which,

[0055] M 401 Its gate is coupled to the Vg terminal of the second sampling switch 400, and its source is coupled to the output V of the gate voltage transfer control switch 300. o The drain of the sampler is coupled to the Vout terminal of the second sampling switch 400 to output the final sampled signal.

[0056] The following are specific embodiments of the 200-channel 10-bit high-speed SAR ADC sampling circuit designed based on 28nm CMOS process according to the present invention, and the technical solution of the present invention will be further described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0057] like Figures 1 to 4 As shown, the present invention provides a multi-channel high-speed SAR ADC sampling circuit, including a first sampling switch 100 and a second sampling switch 400. The first sampling switch 100 further includes a gate voltage bootstrap circuit 200 and 200 gate voltage transfer control switches 300. (See also...) Figure 2 The gate voltage bootstrap circuit 200 provides the required voltage Vg to the 200-channel gate voltage transfer control switches 300 and the second sampling switch 400. Its fo_vi terminal is coupled to the fo_vi terminal of the 200-channel gate voltage transfer control switches 300, and its Vg terminal is coupled to the Vg terminal of both the 200-channel gate voltage transfer control switches 300 and the second sampling switch 400. The gate voltage transfer control switches receive the required voltage Vg from the 200 input signals Vg. i Select one channel from <1:200> and sample it to generate V. i <n>As the input signal of the second sampling switch 400, its output terminal is coupled to the input terminal of the second sampling switch 400; the second sampling switch 400 and the gate voltage transfer control switch synchronously process the signal V. i <n>The sample is taken and the result Vout is transmitted to the subsequent high-speed ADC for conversion and output.

[0058] The gate voltage bootstrap circuit 200 includes two control signals clk_s and clk_s_n with opposite polarities, and six NMOS transistors: M 202 M 203 M 206 M 207 M 208 and M 210 4 PMOS transistors: M 201 M 204 M 205 and M 209 And a capacitor C0. For example... Figure 3 As shown, the control signal clk_s passes through M 201 and M 202 The inverter structure is converted into a new voltage signal to control M. 205 The circuit is turned on. When the control signal clk_s is low, transistor M in the circuit... 203 M 204 M 207 and M 208 When the circuit is turned on, the upper plate of capacitor C0 is connected to the power supply voltage AVDD, and the lower plate is connected to ground AGND. Capacitor C0 charges to the power supply voltage, while Vg = 0; when the control signal clk_s is high, M 205 When the circuit is turned on, the voltage at port fo_vi is equal to V. i <n>Then Vg = V i <n>+AVDD. M 204 The drain of the transistor is coupled to the power supply AVDD, its gate is coupled to the Vg terminal, and its source is coupled to the upper plate of capacitor C0. This connection method is different from the traditional PMOS transistor connection method. It allows the voltage on the upper plate of capacitor C0 to reach a desired large value without being clamped, ensuring that Vg = V i <n>+AVDD always holds true.

[0059] The 200-channel grid voltage transfer control switch 300 consists of 200 grid voltage transfer control switches connected in parallel. The circuit of each grid voltage transfer control switch is as follows: Figure 4 As shown, it includes one enable signal OE1, two enable signals OE2 and OE2_N with opposite polarities, and 7 NMOS transistors: M 303 M 304 M 305 M 306 M 307 M 308 and M 310 3 PMOS transistors: M 301 M 302 and M 309 Enable signals OE1 and OE2 jointly control the input signals V from 200 channels. i Select one signal from <1:200> for sampling and output. When OE1 <1> Low level, OE2 <1> When the voltage level is high and OE1<2:200> is high and OE2<2:200> is low, the first input signal is selected, and the remaining input signals are turned off. When the first input signal is selected, M of that channel... 301 M 302 M 303 and M 304 M is in the on state. 307 and M 308 The gate voltage is Vg, when Vg = V i <1> When +AVDD, M 308 The gate-source voltage difference remains constant at the supply voltage and is independent of the input signal, which can reduce M. 308 The on-resistance is reduced to decrease the attenuation of the input signal during the sampling process, thereby improving M. 308 The sampling accuracy; when Vg = 0, M 307 and M 308 When the circuit is in the off state, it enters the hold phase. When the other input signals are off, the M values ​​of these paths... 301 M 302 M 303 and M 304 All were shut down, while M 305 and M 306 M is turned on 307 and M 308 The gate voltage is 0, and all are in the off state.

[0060] The second sampling switch 400 consists of only one NMOS transistor M. 401 Composition, such as Figure 3 As shown. When Vg = V i <1> When +AVDD, M 401 The gate-source voltage difference remains constant at the power supply voltage and is independent of the input signal, and will be synchronized with the first gate voltage transfer control switch to control the input signal V. i <1> Sampling is performed to improve the final sampling accuracy; when Vg = 0, M 401 It was shut down and entered the hold phase. Meanwhile, M... 401 On the one hand, it eliminates the nonlinearity of the sampling voltage caused by the leakage current of the MOS transistor; on the other hand, it isolates the output node of the 200-channel gate voltage transfer control switch 300 from the top terminal of the ADC capacitor array, thus solving the problem of capacitor mismatch caused by the large parasitic capacitance of the 200-channel output node.

[0061] All design modules are combined and connected, and then simulated in Cadence software.

[0062] Figure 5 This is a simulation test diagram based on a 200-channel high-speed SAR ADC sampling circuit. The following... Figure 6 , Figure 7 and Figure 8 All are in accordance with Figure 5 The result diagram is obtained from the simulation settings.

[0063] See Figure 6 , Figure 7 The final sampling result Vout( Figure 6 (The dashed line in the middle) is in the control signal clk_s ( Figure 6 Under the action of the solid line, it accurately followed and maintained the input signal V. i <1> ( Figure 7 Information (the solid line in the middle).

[0064] See Figure 8 The final sampling result Vout has an effective number of bits (ENOB) of 10.5 bits, and an SNR of 64.9 dB and an SFDR of 65.7 dBc, which meets the requirements of a 200-channel 10-bit high-speed SAR ADC for the sampling circuit.

[0065] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made to it in form and detail without departing from the scope defined by the claims of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A sampling circuit based on a multi-channel high-speed SAR ADC, characterized in that, Includes a first sampling switch and a second sampling switch, wherein, The first sampling switch is used to select one input signal from multiple input signals and sample that input signal. Its input terminal is coupled to N external input signals. Its output terminal is coupled to the input terminal of the second sampling switch, providing the second sampling switch with one input signal. ; The second sampling switch is used to synchronize the signal with the first sampling switch. Perform sampling and output the results The signal is transmitted to the subsequent high-speed ADC for conversion and output. Its input is coupled to the output of the first sampling switch, and its output, Vout, is coupled to the Top terminal of the capacitor array of the subsequent high-speed ADC. The first sampling switch includes a gate voltage bootstrap circuit and N gate voltage transfer control switches. The gate voltage bootstrap circuit's fo_vi terminal is coupled to the gate voltage transfer control switch's fo_vi terminal, and the gate voltage bootstrap circuit's Vg terminal is coupled to the gate voltage transfer control switch's Vg terminal and the second sampling switch's Vg terminal, respectively. The gate voltage bootstrap circuit includes two control signals clk_s and clk_s_n with opposite polarities, and six NMOS transistors: M 202 M 203 M 206 M 207 M 208 and M 210 4 PMOS transistors: M 201 M 204 M 205 and M 209 A capacitor C0, wherein: The control signals clk_s are respectively coupled to M 201 M 202 M 209 and M 210 When the gate of the circuit is high, the circuit enters the sampling state; the control signals clk_s_n are coupled to M. 203 M 208 The gate and M 209 M 210 When the drain of the circuit is high, the circuit enters a holding state. M 204 The drain of the capacitor is coupled to the power supply AVDD, its gate is coupled to the Vg terminal, and its source is coupled to the upper plate of capacitor C0 and M, respectively. 205 The source of capacitor C0 is connected in this way, which allows the voltage on the upper plate of capacitor C0 to reach a desired large value without being clamped. The fo_vi end is respectively connected to M 202 The source, M 203 Drain, M 206 The source of the capacitor C0 is coupled to the lower plate of the capacitor C0. When the circuit is in the sampling state, the voltage at this terminal will change with the voltage of the input signal selected by the gate voltage transfer control switch. Vg terminal and M respectively 204 M 206 The gate and M 205 M 207 The drains are coupled together; M 201 M 209 The source and M 207 The gates of all are coupled to the power supply AVDD; M 203 M 208 M 210 The source electrodes are all coupled to ground AGND; M 201 M 202 M 206 The drain and M 205 The gates are coupled together; M 207 The source and M 208 The drains are coupled together; The gate voltage transfer control switch It consists of N gate voltage transfer control switches connected in parallel; The gate voltage transfer control switch includes an enable signal OE1, two enable signals OE2 and OE2_N with opposite polarities, and seven NMOS transistors: M 303 M 304 M 305 M 306 M 307 M 308 and M 310 3 PMOS transistors: M 301 M 302 and M 309 ,in: Enable signal OE1 is coupled to M respectively 301 M 302 The gate of the signal, and the enable signal OE2 are respectively coupled to M. 303 M 304 The gates of the two together control the transmission of signals at the Vg port; Enable signal OE2 is coupled to M respectively 309 M 310 The gate, and through M 309 M 310 The inverter formed by these components generates an enable signal OE2_N, and OE2_N is coupled to M. 309 M 310 The drain; the enable signal OE2_N is coupled to M. 305 The gate, controlling M 305 The conduction and cutoff of M, when it is high level, 305 Conduction; Vg terminals are coupled to M respectively. 301 The source, M 303 The drain, input V i The terminals are respectively coupled to M 307 Drain, M 308 The source, output V o Terminal coupling M 308 The drain electrode; fo_vi terminal coupling M 307 The source pole, when M 307 When the gate is high, the voltage at the fo_vi terminal will follow the input signal V. i Voltage changes; M 306 gate, M 309 The sources of all are coupled to the power supply AVDD; M 305 M 310 The source electrodes are all coupled to ground AGND; M 301 Drain coupling M 302 The source pole, M 303 Source coupling M 304 The drain, M 305 Drain coupling M 306 The source pole; M 307 M 308 The gates of M are respectively 302 M 306 The drain and M 304 The source and the pole are coupled.

2. The sampling circuit based on a multi-channel high-speed SAR ADC according to claim 1, characterized in that, The second sampling switch uses only one NMOS transistor M. 401 To achieve, among which, M 401 The gate of the device is coupled to the Vg terminal of the second sampling switch, and its source is coupled to the output V of the gate voltage transfer control switch. o The drain of the first sampling switch is coupled to the Vout terminal of the second sampling switch, and the final sampled signal is output.

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