A Flip-complementary Low-Noise Voltage-Controlled Oscillator for Up-Conversion with Reduced Flicker Noise

Abstract

The present invention discloses a flip complementary low-noise voltage-controlled oscillator that reduces flicker noise up-conversion. In radar technology applications, the voltage / frequency gain of the voltage-controlled oscillator is too large, so that the low-frequency noise affects the phase noise. The present invention uses a flip complementary structure and a tail inductor to enable the voltage-controlled oscillator to obtain a larger transconductance, suppress noise, and achieve the function of reducing flicker noise up-conversion. Compared with the traditional technology using a single mutual coupling pair, the flip complementary structure proposed in the present invention reuses the current, improves the performance while saving overall power consumption, and has a simple structure; compared with the traditional complementary structure, the voltage-controlled oscillator proposed in the present invention reduces flicker noise up-conversion and improves phase noise. Based on the present invention, a circuit that can further generate IQ orthogonal differential signals, as well as a flip complementary low-noise voltage-controlled oscillator in the form of substrate injection and a corresponding circuit that generates IQ orthogonal differential signals.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a flip-complementary low-noise voltage-controlled oscillator capable of reducing flicker noise and frequency up-conversion. Background Art

[0002] With the development of radar technology, millimeter-wave radar technology has gradually become a research hotspot. As a key circuit module in millimeter-wave radar technology, the voltage-controlled oscillator (VCO) has many design challenges: (1) the deterioration of phase noise performance, which is mainly due to the significant decrease in the quality factor (Q value) of passive devices after the operating frequency is increased to the millimeter-wave frequency band; (2) the inherent flicker noise of complementary metal oxide semiconductor (CMOS) devices seriously affects the near-end phase noise of millimeter-wave VCO, that is, the flicker noise performance is poor.

[0003] In addition, since the transistor variable capacitor has a nonlinear CV curve, resulting in inconsistent phase noise over the tuning range, all noise generated by the VCO will pass through the VCO’s K VCO The carrier is modulated and additional phase noise is generated. This part of phase noise can be added to the classic Leeson noise model, which is defined as follows:

[0004]

[0005] where f 0 is the oscillation frequency, f m is the frequency offset, F is the noise figure of the transistor amplifier, k is the Boltzmann constant, T is the temperature, P s is the flicker noise angular frequency, V m Represents the equivalent amplitude of low-frequency noise, in units of In communication applications, due to K VCO is very small, so the latter term can be ignored, and the former term, the Leeson noise, dominates and determines the phase noise of the oscillator. However, for radar applications, especially radars that require a large tuning range, such as FMCW radars, K VCO It will be very large, which means that the VCO has a high voltage / frequency gain. The latter term cannot be ignored, and low-frequency noise such as flicker noise will have a greater impact on the phase noise of the oscillator.

[0006] In millimeter-wave radar technology, the traditional complementary structure VCO circuit has a poor ability to suppress the up-conversion of low-frequency noise such as flicker noise, resulting in poor overall phase noise. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention aims to provide a method for VCO In larger radar technology applications, low-noise millimeter-wave signal output is achieved.

[0008] The present invention proposes a flip complementary low noise voltage controlled oscillator for reducing flicker noise up-conversion. At the same time, based on the flip complementary low noise voltage controlled oscillator proposed by the present invention, a circuit capable of generating IQ orthogonal differential signals, a flip complementary low noise voltage controlled oscillator in substrate injection form and a corresponding circuit for generating IQ orthogonal differential signals are further proposed.

[0009] Furthermore, the low-noise voltage-controlled oscillator includes: an inductor L1, an inductor L2, an inductor L3, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, and a port OUTP and a port OUTN. Inductor L1 is connected in parallel with capacitor array C1 and variable capacitor C2. NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair. The drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then to the a end of inductor L1. The drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the b end of inductor L1. Inductor L3 is connected in parallel with variable capacitor C5 and capacitor array C6. PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair. The drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then to the a end of inductor L3. The drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then to the b end of inductor L3. The source terminals of the OS transistor M1 and the NMOS transistor M2 are connected and then connected to the a terminal of the inductor L2. The source terminals of the PMOS transistors M3 and the PMOS transistors M4 are connected and then connected to the b terminal of the inductor L2. The a terminal of the capacitor C3 is connected to the drain of the NMOS transistor M1. The b terminal of the capacitor C3 is connected to the drain of the PMOS transistor M3. The a terminal of the capacitor C4 is connected to the drain of the NMOS transistor M2. The b terminal of the capacitor C4 is connected to the drain of the PMOS transistor M4. The center tap of the inductor L1 is connected to the power supply. The center tap of the inductor L3 is grounded. The port OUTP is connected to the drain of the NMOS transistor M1. The port OUTN is connected to the drain of the NMOS transistor M2. The differential signal flows out from the port OUTP and the port OUTN.

[0010] The NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

[0011] Further, the variable capacitor includes: transistor variable capacitors C1', C2', capacitors C3', C4', resistors R1, R2, four ports VOP, VON, VCTRL and VIBIAS. Port VOP is connected to the a-end of capacitor C3', and the b-end of capacitor C3' is connected to the b-end of resistor R1 and the a-end of transistor variable capacitor C1'; port VON is connected to the a-end of capacitor C4', and the b-end of capacitor C4' is connected to the b-end of resistor R2 and the a-end of transistor variable capacitor C2'. Port VCTRL is connected to the b-end of transistor variable capacitor C1' and the b-end of transistor variable capacitor C2', and port VIBIAS is connected to the a-end of resistor R1 and the a-end of resistor R2.

[0012] The transistor variable capacitors C1' and C2' are identical, the capacitors C3' and C4' are identical, and the resistors R1 and R2 are identical.

[0013] Furthermore, the flipped complementary low-noise voltage-controlled oscillator circuit for generating IQ differential orthogonal signals includes: an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, a capacitor array C7, a variable capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor C11, a capacitor array C12, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, and ports OUTP_I, port OUTN_I, port OUTP_Q, and port OUTN_Q. Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel, NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then to the a end of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the b end of inductor L1, inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel, PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then to the a end of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then to the b end of inductor L3, NMOS tube M1 The source of the NMOS tube M2 is connected to the a end of the inductor L2, the source of the PMOS tube M3 and the PMOS tube M4 are connected to the b end of the inductor L2, the a end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and I differential signals flow out from the ports OUTP_I and OUTN_I.

[0014] The inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8. The NMOS tube M5 and the NMOS tube M6 form an NMOS mutual coupling pair. The drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then to the a end of the inductor L4. The drain of the NMOS tube M6 is connected to the gate of the NMOS tube M5 and then to the b end of the inductor L4. The inductor L6 is connected in parallel with the variable capacitor C11 and the capacitor array C12. The PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair. The drain of the PMOS tube M7 is connected to the gate of the PMOS tube M8 and then to the a end of the inductor L6. The drain of the PMOS tube M8 is connected to the gate of the PMOS tube M7 and then to the b end of the inductor L6. The NMOS tube M5 The source of the NMOS tube M6 is connected to the a terminal of the inductor L5, the source of the PMOS tube M7 and the PMOS tube M8 are connected to the b terminal of the inductor L5, the a terminal of the capacitor C9 is connected to the drain of the NMOS tube M5, the b terminal of the capacitor C9 is connected to the drain of the PMOS tube M7, the a terminal of the capacitor C10 is connected to the drain of the NMOS tube M6, the b terminal of the capacitor C10 is connected to the drain of the PMOS tube M8, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is grounded, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q differential signal flows out from the port OUTP_Q and the port OUTN_Q. The inductor L2 and the inductor L5 are coupled to each other.

[0015] NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same, capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same, variable capacitor C2, variable capacitor C5, variable capacitor C8, and variable capacitor C11 are the same, capacitor C3, capacitor C4, capacitor C9, and capacitor C10 are the same, and PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.

[0016] Furthermore, the substrate-injected flipped complementary low-noise voltage-controlled oscillator for up-conversion with reduced flicker noise comprises: an inductor L1, an inductor L2, an inductor L3, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, and a port OUTP and a port OUTN. The inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2. The NMOS tube M1 and the NMOS tube M2 form an NMOS mutual coupling pair. The substrate of the NMOS tube M1 is connected to the gate of the NMOS tube M1, the substrate of the NMOS tube M2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a end of the inductor L1, the drain of the NMOS tube M2 is connected to the gate of the NMOS tube M1 and then connected to the b end of the inductor L1, the inductor L3 is connected in parallel with the variable capacitor C5 and the capacitor array C6, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, the substrate of the PMOS tube M4 is connected to the gate of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the gate of the PMOS tube M4 and then connected to the gate of the PMOS tube M4. The a-end of the inductor L3 is connected, the drain of the PMOS tube M4 is connected to the gate of the PMOS tube M3 and then to the b-end of the inductor L3, the source of the NMOS tube M1 and the NMOS tube M2 are connected and then to the a-end of the inductor L2, the source of the PMOS tube M3 and the PMOS tube M4 are connected and then to the b-end of the inductor L2, the a-end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b-end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a-end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b-end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, and the differential signal flows out from the port OUTP and the port OUTN.

[0017] The NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

[0018] Furthermore, the substrate-injected flipped complementary low-noise voltage-controlled oscillator circuit for generating IQ differential orthogonal signals includes: an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, a capacitor array C7, a variable capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor C11, a capacitor array C12, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, and ports OUTP_I, port OUTN_I, port OUTP_Q, and port OUTN_Q. Inductor L1, capacitor array C1 and variable capacitor C2 are connected in parallel, NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair, the substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, the substrate of NMOS tube M2 is connected to the gate of NMOS tube M2, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a end of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b end of inductor L1, inductor L3, variable capacitor C5 and capacitor array C6 are connected in parallel, PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair, the substrate of PMOS tube M3 is connected to the gate of PMOS tube M3, the substrate of PMOS tube M4 is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the inductor L3. The a end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and I differential signals flow out from the ports OUTP_I and OUTN_I.

[0019] The inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8. The NMOS tube M5 and the NMOS tube M6 form an NMOS mutual coupling pair. The substrate of the NMOS tube M5 is connected to the gate of the NMOS tube M5, the substrate of the NMOS tube M6 is connected to the gate of the NMOS tube M6, the drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then connected to the a end of the inductor L4, the drain of the NMOS tube M6 is connected to the gate of the NMOS tube M5 and then connected to the b end of the inductor L4. The inductor L6 and the variable capacitor C11 and the capacitor array C12 are connected in parallel. The PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair. The substrate of the PMOS tube M7 is connected to the gate of the PMOS tube M7, the substrate of the PMOS tube M8 is connected to the gate of the PMOS tube M8, the drain of the PMOS tube M7 is connected to the gate of the PMOS tube M8 and then connected to the inductor L6. The a-end of the capacitor C9 is connected to the drain of the NMOS tube M5, the b-end of the capacitor C9 is connected to the drain of the NMOS tube M5, the b-end of the capacitor C9 is connected to the drain of the PMOS tube M7, the a-end of the capacitor C10 is connected to the drain of the NMOS tube M6, the b-end of the capacitor C10 is connected to the drain of the PMOS tube M8, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is grounded, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q-path differential signal flows out from the port OUTP_Q and the port OUTN_Q. The inductor L2 and the inductor L5 are coupled to each other.

[0020] NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same, capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same, variable capacitor C2, variable capacitor C5, variable capacitor C8, and variable capacitor C11 are the same, capacitor C3, capacitor C4, capacitor C9, and capacitor C10 are the same, and PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.

[0021] The present invention provides a flip complementary structure and a tail inductor to enable the voltage controlled oscillator to obtain a larger transconductance. VCOIn the case of a large noise, the noise is suppressed, the function of reducing flicker noise up-conversion is realized, and the close-frequency phase noise is reduced. Compared with the traditional technology using a single mutual coupling pair, the flip complementary structure proposed in the present invention reuses the current, which improves the performance while saving overall power consumption, and has a simple structure; compared with the traditional complementary structure, the voltage-controlled oscillator proposed in the present invention reduces flicker noise up-conversion and improves phase noise. At the same time, based on the proposed flip complementary low-noise voltage-controlled oscillator, a circuit that can generate IQ orthogonal differential signals is further proposed, by coupling the inductor L2 and the inductor L5 in the middle of the two identical oscillators to form an orthogonal I and Q paths, and output an IQ orthogonal differential signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the circuit schematic diagram of the traditional NMOS VCO circuit;

[0023] Figure 2 It is the circuit schematic diagram of the traditional PMOS VCO circuit;

[0024] Figure 3 It is the circuit schematic diagram of the traditional complementary structure VCO circuit;

[0025] Figure 4 This is a circuit schematic diagram of the flip complementary low noise voltage controlled oscillator proposed by the present invention;

[0026] Figure 5 For the present invention Figure 4 The circuit diagram of the transistor variable capacitor in;

[0027] Figure 6 The schematic diagram of the IQ quadrature circuit of the flip complementary low noise voltage controlled oscillator proposed by the present invention;

[0028] Figure 7 It is a circuit principle diagram of the substrate injection type flip complementary low noise voltage controlled oscillator proposed by the present invention;

[0029] Figure 8 This is a schematic diagram of the IQ orthogonal circuit of the substrate injection type flip complementary low noise voltage controlled oscillator proposed by the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose and effect of the present invention more clear, the present invention is further described in detail below in conjunction with the accompanying drawings. It should be understood that what is described here is only used to explain the present invention and is not used to limit the present invention.

[0031] Figure 1-3 It is a traditional NMOS / PMOS VCO circuit and a complementary structure VCO circuit.

[0032] Figure 4The circuit schematic diagram of the flip complementary low noise voltage controlled oscillator proposed by the present invention includes: inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, and port OUTP and port OUTN. Inductor L1 is connected in parallel with capacitor array C1 and variable capacitor C2. NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair. The drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then to the a end of inductor L1. The drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the b end of inductor L1. Inductor L3 is connected in parallel with variable capacitor C5 and capacitor array C6. PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair. The drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then to the a end of inductor L3. The drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then to the b end of inductor L3. The source terminals of the OS transistor M1 and the NMOS transistor M2 are connected and then connected to the a terminal of the inductor L2. The source terminals of the PMOS transistors M3 and the PMOS transistors M4 are connected and then connected to the b terminal of the inductor L2. The a terminal of the capacitor C3 is connected to the drain of the NMOS transistor M1. The b terminal of the capacitor C3 is connected to the drain of the PMOS transistor M3. The a terminal of the capacitor C4 is connected to the drain of the NMOS transistor M2. The b terminal of the capacitor C4 is connected to the drain of the PMOS transistor M4. The center tap of the inductor L1 is connected to the power supply. The center tap of the inductor L3 is grounded. The port OUTP is connected to the drain of the NMOS transistor M1. The port OUTN is connected to the drain of the NMOS transistor M2. The differential signal flows out from the port OUTP and the port OUTN.

[0033] The NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

[0034] like Figure 5 As shown, Figure 4 The variable capacitors in the circuit include: transistor variable capacitors C1', C2', capacitors C3', C4', resistors R1, R2, and four ports VOP, VON, VCTRL, and VIBIAS. Port VOP is connected to the a-end of capacitor C3', and the b-end of capacitor C3' is connected to the b-end of resistor R1 and the a-end of transistor variable capacitor C1'; port VON is connected to the a-end of capacitor C4', and the b-end of capacitor C4' is connected to the b-end of resistor R2 and the a-end of transistor variable capacitor C2'. Port VCTRL is connected to the b-end of transistor variable capacitor C1' and the b-end of transistor variable capacitor C2', and port VIBIAS is connected to the a-end of resistor R1 and the a-end of resistor R2.

[0035] The transistor variable capacitors C1' and C2' are identical, the capacitors C3' and C4' are identical, and the resistors R1 and R2 are identical.

[0036] As described above, the working principle of the voltage-controlled oscillator is as follows: NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair, and PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair. The mutual coupling pair forms a negative resistance, which compensates for the energy loss of the LC resonant circuit during oscillation and maintains stable oscillation of the circuit. The capacitance of the capacitor array C1 and the capacitor array C6 can change the center frequency of the oscillator. The variable capacitor C2 and the variable capacitor C5 can change the capacitance by changing the voltage of the port VCTRL, thereby changing the center frequency of the oscillator.

[0037] The voltage controlled oscillator is analyzed according to the phase noise model. VCO When the value is large, the latter term is mainly analyzed. According to the noise model of the circuit, a pair of mutual couplings has a significant effect on the V m The noise current is multiplied by the equivalent impedance of the transistor and the equivalent impedance of the inductor in parallel. The two pairs of mutual coupling pairs of the traditional complementary voltage-controlled oscillator are connected in parallel, and their V m is the product of the noise current and the transistor equivalent impedance; and the flip complementary low noise voltage controlled oscillator proposed in the present invention is similar to two resonant cavities coupled, and its V m is twice that of a pair of mutually coupled oscillators. Since the equivalent impedance of the inductor is generally much smaller than the equivalent impedance of the transistor, although the proposed voltage-controlled oscillator V m It is twice that of a mutually coupled pair of oscillators, but still much smaller than the V of a traditional complementary voltage-controlled oscillator. m Therefore, the flip complementary low noise voltage controlled oscillator proposed in the present invention has a smaller phase noise than the traditional complementary voltage controlled oscillator. In addition, the phase noise of the system with N oscillators coupled to each other is reduced compared with a single oscillator, so that the flip complementary low noise voltage controlled oscillator proposed in the present invention has a lower phase noise.

[0038] The flipped complementary structure proposed in the present invention reuses current in the two resonant cavities, which improves transconductance while saving power consumption and optimizes the phase noise performance of the oscillator. The tail inductor filters the second-order component in the oscillator noise, further optimizing the phase noise.

[0039] Figure 6The flip complementary low noise voltage controlled oscillator proposed by the present invention is applied to an IQ quadrature circuit, and includes: an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, a capacitor array C7, a variable capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor C11, a capacitor array C12, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, and ports OUTP_I, port OUTN_I, port OUTP_Q, and port OUTN_Q. Inductor L1, capacitor array C1, and variable capacitor C2 are connected in parallel, NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then to the a end of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then to the b end of inductor L1, inductor L3, variable capacitor C5, and capacitor array C6 are connected in parallel, PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then to the a end of inductor L3, the drain of PMOS tube M4 is connected to the gate of PMOS tube M3 and then to the b end of inductor L3, NMOS tube M1 The source of the NMOS tube M2 is connected to the a end of the inductor L2, the source of the PMOS tube M3 and the PMOS tube M4 are connected to the b end of the inductor L2, the a end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and I differential signals flow out from the ports OUTP_I and OUTN_I.

[0040] The inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8. The NMOS tube M5 and the NMOS tube M6 form an NMOS mutual coupling pair. The drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then to the a end of the inductor L4. The drain of the NMOS tube M6 is connected to the gate of the NMOS tube M5 and then to the b end of the inductor L4. The inductor L6 is connected in parallel with the variable capacitor C11 and the capacitor array C12. The PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair. The drain of the PMOS tube M7 is connected to the gate of the PMOS tube M8 and then to the a end of the inductor L6. The drain of the PMOS tube M8 is connected to the gate of the PMOS tube M7 and then to the b end of the inductor L6. The NMOS tube M5 The source of the NMOS tube M6 is connected to the a terminal of the inductor L5, the source of the PMOS tube M7 and the PMOS tube M8 are connected to the b terminal of the inductor L5, the a terminal of the capacitor C9 is connected to the drain of the NMOS tube M5, the b terminal of the capacitor C9 is connected to the drain of the PMOS tube M7, the a terminal of the capacitor C10 is connected to the drain of the NMOS tube M6, the b terminal of the capacitor C10 is connected to the drain of the PMOS tube M8, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is grounded, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q differential signal flows out from the port OUTP_Q and the port OUTN_Q. The inductor L2 and the inductor L5 are coupled to each other.

[0041] NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same, capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same, variable capacitor C2, variable capacitor C5, variable capacitor C8, and variable capacitor C11 are the same, capacitor C3, capacitor C4, capacitor C9, and capacitor C10 are the same, and PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.

[0042] By coupling the inductor L2 and the inductor L5 between two identical oscillators, the I path and the Q path are orthogonal to output an IQ orthogonal differential signal.

[0043] Figure 7The substrate-injected flip-complementary low-noise voltage-controlled oscillator for up-conversion with reduced flicker noise proposed in the present invention comprises: an inductor L1, an inductor L2, an inductor L3, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, and a port OUTP and a port OUTN. The inductor L1 is connected in parallel with the capacitor array C1 and the variable capacitor C2. The NMOS tube M1 and the NMOS tube M2 form an NMOS mutual coupling pair. The substrate of the NMOS tube M1 is connected to the gate of the NMOS tube M1, the substrate of the NMOS tube M2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a end of the inductor L1, the drain of the NMOS tube M2 is connected to the gate of the NMOS tube M1 and then connected to the b end of the inductor L1, the inductor L3 is connected in parallel with the variable capacitor C5 and the capacitor array C6, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, the substrate of the PMOS tube M4 is connected to the gate of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the gate of the PMOS tube M4 and then connected to the gate of the PMOS tube M4. The a-end of the inductor L3 is connected, the drain of the PMOS tube M4 is connected to the gate of the PMOS tube M3 and then to the b-end of the inductor L3, the source of the NMOS tube M1 and the NMOS tube M2 are connected and then to the a-end of the inductor L2, the source of the PMOS tube M3 and the PMOS tube M4 are connected and then to the b-end of the inductor L2, the a-end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b-end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a-end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b-end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, and the differential signal flows out from the port OUTP and the port OUTN.

[0044] The NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

[0045] Figure 4 The substrates of the NMOS tubes M1 and M2 are connected to a low level, and the substrates of the PMOS tubes M3 and M4 are connected to a high level. Figure 7 The substrates of NMOS tubes M1 and M2 are connected to their respective gates, and the substrates of PMOS tubes M3 and M4 are connected to their respective gates, thereby forming substrate injection. Substrate injection injects signals into the substrate, increasing the g of the transistor.m , so smaller transistors can be used, reducing current and flicker noise. At the same time, it enables the transistor to switch states more quickly, strengthen the degree of opening and closing, improve signal strength, and further reduce phase noise.

[0046] Figure 8 The invention discloses a substrate-injected flipped complementary low-noise voltage-controlled oscillator circuit for generating IQ differential orthogonal signals, comprising: an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, a capacitor array C1, a variable capacitor C2, a capacitor C3, a capacitor C4, a variable capacitor C5, a capacitor array C6, a capacitor array C7, a variable capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor C11, a capacitor array C12, an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, and ports OUTP_I, OUTN_I, OUTP_Q, and OUTN_Q. Inductor L1, capacitor array C1 and variable capacitor C2 are connected in parallel, NMOS tube M1 and NMOS tube M2 form an NMOS mutual coupling pair, the substrate of NMOS tube M1 is connected to the gate of NMOS tube M1, the substrate of NMOS tube M2 is connected to the gate of NMOS tube M2, the drain of NMOS tube M1 is connected to the gate of NMOS tube M2 and then connected to the a end of inductor L1, the drain of NMOS tube M2 is connected to the gate of NMOS tube M1 and then connected to the b end of inductor L1, inductor L3, variable capacitor C5 and capacitor array C6 are connected in parallel, PMOS tube M3 and PMOS tube M4 form a PMOS mutual coupling pair, the substrate of PMOS tube M3 is connected to the gate of PMOS tube M3, the substrate of PMOS tube M4 is connected to the gate of PMOS tube M4, the drain of PMOS tube M3 is connected to the gate of PMOS tube M4 and then connected to the inductor L3. The a end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP_I is connected to the drain of the NMOS tube M1, the port OUTN_I is connected to the drain of the NMOS tube M2, and I differential signals flow out from the ports OUTP_I and OUTN_I.

[0047] The inductor L4 is connected in parallel with the capacitor array C7 and the variable capacitor C8. The NMOS tube M5 and the NMOS tube M6 form an NMOS mutual coupling pair. The substrate of the NMOS tube M5 is connected to the gate of the NMOS tube M5, the substrate of the NMOS tube M6 is connected to the gate of the NMOS tube M6, the drain of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and then connected to the a end of the inductor L4, the drain of the NMOS tube M6 is connected to the gate of the NMOS tube M5 and then connected to the b end of the inductor L4. The inductor L6 and the variable capacitor C11 and the capacitor array C12 are connected in parallel. The PMOS tube M7 and the PMOS tube M8 form a PMOS mutual coupling pair. The substrate of the PMOS tube M7 is connected to the gate of the PMOS tube M7, the substrate of the PMOS tube M8 is connected to the gate of the PMOS tube M8, the drain of the PMOS tube M7 is connected to the gate of the PMOS tube M8 and then connected to the inductor L6. The a-end of the capacitor C9 is connected to the drain of the NMOS tube M5, the b-end of the capacitor C9 is connected to the drain of the NMOS tube M5, the b-end of the capacitor C9 is connected to the drain of the PMOS tube M7, the a-end of the capacitor C10 is connected to the drain of the NMOS tube M6, the b-end of the capacitor C10 is connected to the drain of the PMOS tube M8, the center tap of the inductor L4 is connected to the power supply, the center tap of the inductor L6 is grounded, the port OUTP_Q is connected to the drain of the NMOS tube M5, the port OUTN_Q is connected to the drain of the NMOS tube M6, and the Q-path differential signal flows out from the port OUTP_Q and the port OUTN_Q. The inductor L2 and the inductor L5 are coupled to each other.

[0048] NMOS tube M1, NMOS tube M2, NMOS tube M5, and NMOS tube M6 are the same, capacitor array C1, capacitor array C6, capacitor array C7, and capacitor array C12 are the same, variable capacitor C2, variable capacitor C5, variable capacitor C8, and variable capacitor C11 are the same, capacitor C3, capacitor C4, capacitor C9, and capacitor C10 are the same, and PMOS tube M3, PMOS tube M4, PMOS tube M7, and PMOS tube M8 are the same.

Claims

1. A low-noise voltage-controlled oscillator with upconversion and reduced flicker noise. Features include: Inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, and port OUTP, port OUTN; The inductor L1, the capacitor array C1, and the variable capacitor C2 are connected in parallel, the NMOS tube M1 and the NMOS tube M2 form an NMOS mutual coupling pair, the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a end of the inductor L1, and the drain of the NMOS tube M2 is connected to the gate of the NMOS tube M1 and then connected to the b end of the inductor L1; The inductor L3, the variable capacitor C5, and the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the drain of the PMOS tube M3 is connected to the gate of the PMOS tube M4 and then connected to the a end of the inductor L3, the drain of the PMOS tube M4 is connected to the gate of the PMOS tube M3 and then connected to the b end of the inductor L3; The source terminals of the NMOS tubes M1 and M2 are connected to each other and then connected to the a terminal of the inductor L2. The source terminals of the PMOS tubes M3 and M4 are connected to each other and then connected to the b terminal of the inductor L2. The a terminal of the capacitor C3 is connected to the drain of the NMOS tube M1. The b terminal of the capacitor C3 is connected to the drain of the PMOS tube M3. The a terminal of the capacitor C4 is connected to the drain of the NMOS tube M2. The b terminal of the capacitor C4 is connected to the drain of the PMOS tube M4. The center tap of the inductor L1 is connected to the power supply. The center tap of the inductor L3 is grounded. The port OUTP is connected to the drain of the NMOS tube M1. The port OUTN is connected to the drain of the NMOS tube M2. The differential signal flows out from the port OUTP and the port OUTN. Among them, the NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

2. The inverted complementary low noise voltage controlled oscillator for up-conversion with reduced flicker noise according to claim 1, It is characterized in that The variable capacitor includes: transistor variable capacitors C1', C2', capacitors C3', C4', resistors R1, R2, four ports VOP, VON, VCTRL and VIBIAS; The port VOP is connected to the a-end of the capacitor C3', the b-end of the capacitor C3' is connected to the b-end of the resistor R1 and the a-end of the transistor variable capacitor C1'; the port VON is connected to the a-end of the capacitor C4', the b-end of the capacitor C4' is connected to the b-end of the resistor R2 and the a-end of the transistor variable capacitor C2'; the port VCTRL is connected to the b-end of the transistor variable capacitor C1' and the b-end of the transistor variable capacitor C2', and the port VIBIAS is connected to the a-end of the resistor R1 and the a-end of the resistor R2; The transistor variable capacitors C1' and C2' are identical, the capacitors C3' and C4' are identical, and the resistors R1 and R2 are identical.

3. A flip-complementary low-noise voltage-controlled oscillator circuit that generates IQ differential orthogonal signals. It is characterized in that It comprises a pair of flip complementary low noise voltage controlled oscillators as claimed in claim 1, characterized in that: a coupling relationship is generated between the inductors connected to the source stage of the MOS tube in the pair of flip complementary low noise voltage controlled oscillators, thereby forming an orthogonal I path and a Q path, and outputting an IQ orthogonal differential signal.

4. A low noise voltage controlled oscillator with upconversion and reduced flicker noise. Features include: Inductor L1, inductor L2, inductor L3, capacitor array C1, variable capacitor C2, capacitor C3, capacitor C4, variable capacitor C5, capacitor array C6, NMOS tube M1, NMOS tube M2, PMOS tube M3, PMOS tube M4, and port OUTP, port OUTN; The inductor L1, the capacitor array C1, and the variable capacitor C2 are connected in parallel, the NMOS tube M1 and the NMOS tube M2 form an NMOS mutual coupling pair, the substrate of the NMOS tube M1 is connected to the gate of the NMOS tube M1, the substrate of the NMOS tube M2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and then connected to the a end of the inductor L1, and the drain of the NMOS tube M2 is connected to the gate of the NMOS tube M1 and then connected to the b end of the inductor L1; The inductor L3, the variable capacitor C5, and the capacitor array C6 are connected in parallel, the PMOS tube M3 and the PMOS tube M4 form a PMOS mutual coupling pair, the substrate of the PMOS tube M3 is connected to the gate of the PMOS tube M3, the substrate of the PMOS tube M4 is connected to the gate of the PMOS tube M4, the drain of the PMOS tube M3 is connected to the gate of the PMOS tube M4 and then connected to the a-end of the inductor L3, the drain of the PMOS tube M4 is connected to the gate of the PMOS tube M3 and then connected to the b-end of the inductor L3, the source of the NMOS tube M1 and the NMOS tube M2 are connected and then connected to the a-end of the inductor L2, and the source of the PMOS tube M3 and the PMOS tube M4 are connected and then connected to the b-end of the inductor L2; The a-end of the capacitor C3 is connected to the drain of the NMOS tube M1, the b-end of the capacitor C3 is connected to the drain of the PMOS tube M3, the a-end of the capacitor C4 is connected to the drain of the NMOS tube M2, the b-end of the capacitor C4 is connected to the drain of the PMOS tube M4, the center tap of the inductor L1 is connected to the power supply, the center tap of the inductor L3 is grounded, the port OUTP is connected to the drain of the NMOS tube M1, the port OUTN is connected to the drain of the NMOS tube M2, and the differential signal flows out from the port OUTP and the port OUTN; The NMOS tube M1 is the same as the NMOS tube M2, the capacitor array C1 is the same as the capacitor array C6, the variable capacitor C2 is the same as the variable capacitor C5, the capacitor C3 is the same as the capacitor C4, and the PMOS tube M3 is the same as the PMOS tube M4.

5. The inverted complementary low noise voltage controlled oscillator with flicker noise reduction up-conversion according to claim 4, It is characterized in that The variable capacitor includes: transistor variable capacitors C1', C2', capacitors C3', C4', resistors R1, R2, four ports VOP, VON, VCTRL and VIBIAS; The port VOP is connected to the a-end of the capacitor C3', the b-end of the capacitor C3' is connected to the b-end of the resistor R1 and the a-end of the transistor variable capacitor C1'; the port VON is connected to the a-end of the capacitor C4', the b-end of the capacitor C4' is connected to the b-end of the resistor R2 and the a-end of the transistor variable capacitor C2'; the port VCTRL is connected to the b-end of the transistor variable capacitor C1' and the b-end of the transistor variable capacitor C2', and the port VIBIAS is connected to the a-end of the resistor R1 and the a-end of the resistor R2; The transistor variable capacitors C1' and C2' are identical, the capacitors C3' and C4' are identical, and the resistors R1 and R2 are identical.

6. A flip-complementary low-noise voltage-controlled oscillator circuit that generates IQ differential orthogonal signals. It is characterized in that It comprises a pair of flip complementary low noise voltage controlled oscillators as claimed in claim 4, characterized in that: a coupling relationship is generated between the inductors connected to the source stage of the MOS tube in the pair of flip complementary low noise voltage controlled oscillators, thereby forming an orthogonal I path and a Q path, and outputting an IQ orthogonal differential signal.

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