Dynamic bias C-type voltage-controlled oscillator based on CMOS (Complementary Metal Oxide Semiconductor) process

Abstract

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and more specifically to a dynamically biased Class C voltage-controlled oscillator based on CMOS technology. Background Technology

[0002] The frequency synthesizer is one of the core modules in an RF front-end system, typically used to provide a stable local oscillator signal for the RF transceiver system. A common frequency synthesizer is a phase-locked loop (PLL) system, consisting of a phase detector, loop filter, voltage-controlled oscillator (VCO), and frequency divider. It provides the circuit with a low-phase-noise, high-frequency, and stable local oscillator signal. Its performance directly affects the RF transceiver and limits system performance improvements; therefore, designing a high-performance PLL is essential. The phase noise and tuning range of the VCO have a significant impact on PLL performance, with phase noise being particularly critical. For example, at the receiver, the presence of phase noise can generate reciprocal mixing interference. When a strong interference approximately one intermediate frequency (IF) away from the local oscillator frequency exists, the phase noise of the local oscillator signal mixes with the strong interference, potentially overriding the effective IF signal and degrading the output signal-to-noise ratio (SNR). Therefore, designing a low-noise VCO is crucial.

[0003] CN117978093A discloses a low-phase-noise Class C voltage-controlled oscillator (VCO). This oscillator employs three LC networks to form a dual-mode resonant network. The second and third LC networks of the dual-mode resonant network provide bias for the cross-coupled pairs. The inductors in the second and third LC networks constitute a transformer, making the VCO a resistive path at both the fundamental and second harmonic frequencies. This improves the symmetry of the rising and falling edges of the oscillation waveform, reducing the impulse sensitivity function and achieving good noise performance. While this structure exhibits excellent phase noise performance, it does not solve the problem of difficult start-up for Class C VCOs, posing a risk of failure to start oscillate.

[0004] CN119921677A discloses a Class C voltage-controlled oscillator (VCO) with a negative voltage substrate bias. This scheme introduces an amplitude detection circuit to detect the amplitude of the output signal of the Class C VCO. The amplitude detection circuit controls the cross-coupling pair to the substrate through a negative voltage charge pump. In addition, this scheme also introduces a gate voltage control circuit. This scheme avoids the cross-coupling pair from operating in the linear region, forcing it to remain in the Class C operating region. However, this scheme fails to solve the problem of phase noise degradation caused by noise injection from the MOSFET to the gate during stable operation. Summary of the Invention

[0005] The purpose of this invention is to address the aforementioned problems by adding an operational amplifier to the traditional Class C voltage-controlled oscillator to control the initial oscillation operating range of the voltage-controlled oscillator, and introducing a bandwidth-adjustable network to enable the operational amplifier to obtain both broadband and narrowband operating modes, while simultaneously ensuring rapid stabilization during the oscillation stage and low noise performance in the steady state.

[0006] The technical solution adopted in this invention is as follows: A dynamically biased Class C voltage-controlled oscillator based on CMOS technology, the oscillator comprising a fixed LC resonant network, a switched capacitor array, a variable capacitor network, a cross-coupled network, a bandwidth-adjustable operational amplifier, a tail current source, and bandwidth control logic circuitry; The fixed LC resonant network includes a differential inductor and a capacitor; Each stage of the switched capacitor array includes a switch and two capacitors for digitally controlled tuning of the oscillator. The variable capacitor network adopts a varactor tube with bias structure for voltage-controlled tuning; The cross-coupling network is used to provide negative resistance for the oscillator; The bandwidth control logic circuit includes an RC low-pass filter, a comparator, and a NAND gate. The RC low-pass filter is used to filter out common-mode point VCM oscillations, and the comparator and NAND gate are used to obtain the control logic of the bandwidth-adjustable operational amplifier. The tail current source is used to provide current bias for the entire oscillator circuit.

[0007] Furthermore, in the fixed LC resonant network, the differential inductor and capacitor are connected in parallel, with their two ends connected to the positive output terminal and the negative output terminal of the oscillator, respectively. The switched capacitor array and the variable capacitor network are located between the positive output terminal and the negative output terminal of the oscillator, forming the resonant circuit of the entire circuit together with the fixed LC resonant network.

[0008] Furthermore, the switched capacitor array includes multiple levels of switched capacitor units; each level of switched capacitor unit includes a capacitor CP. <n>、CN <n>and switch SN <n>; Wherein, the capacitor CP <n>The first terminal is connected to the positive input terminal, and the second terminal is connected to switch SN. <n>The first end; the switch S <n>The second end is connected to capacitor CN <n>The first and third terminals are connected to the external input SW. <n>The capacitor CN <n>The second end is connected to the negative output end.

[0009] Furthermore, the variable capacitor network includes a first capacitor C1, a second capacitor C2, a first variable capacitor Cvar1 and a second variable capacitor Cvar2, a first resistor R1 and a second resistor R2; Wherein, the first terminal of the first capacitor C1 is connected to the positive output terminal, and the other terminal is connected to the first terminal of the first variable capacitor Cvar1 and the first terminal of the first resistor R1; the second terminal of the first variable capacitor Cvar1 is connected to the control voltage VCTRL and the first terminal of the second variable capacitor Cvar2; the second terminal of the second variable capacitor is connected to the first terminal of the second capacitor C2 and the first terminal of the second resistor R2; the second terminal of the second capacitor C2 is connected to the negative output terminal; the second terminals of the resistors R1 and R2 are connected to the bias voltage VB0.

[0010] Furthermore, the cross-coupled network includes a cross-coupled pair with a filter capacitor and a resistor gate bias structure, wherein the cross-coupled pair acts as a negative resistance structure to compensate for the energy loss of passive components in the circuit.

[0011] Furthermore, the cross-coupling network specifically includes a first transistor M1, a second transistor M2, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4; Wherein, the first end of the third capacitor C3 is connected to the positive output terminal, and the second end is connected to the gate terminal of the second transistor M2 and the first end of the third resistor R3; the first end of the fourth capacitor C4 is connected to the gate terminal of the first transistor M1 and the first end of the fourth resistor R4, and the second end is connected to the negative output terminal; the drain terminal of the first transistor M1 is connected to the positive output terminal, and the source terminal is connected to the source terminal of the second transistor M2 and the tail current source.

[0012] Furthermore, the tail current source includes a zeroth transistor M0, the drain of the zeroth transistor M0 is connected to the source of the first transistor M1, the connection point is the common mode point of the oscillator, the gate is connected to the external bias Vtail, and the source is grounded.

[0013] Furthermore, one end of the input terminal of the bandwidth-adjustable operational amplifier is connected to an externally provided reference voltage VREF, the other end is connected to the common-mode point of the oscillator, and the output is connected to the gate bias resistor of the cross-coupled pair.

[0014] Furthermore, the bandwidth-adjustable operational amplifier includes an operational amplifier OPA, a third transistor M3, a sixth resistor R6, and a sixth capacitor C6; The operational amplifier OPA has its positive input terminal connected to the reference voltage VREF, its negative input terminal connected to the common-mode point of the oscillator, and its output terminal connected to the drain terminal of the third transistor M3 and the second terminal of the sixth resistor R6. The source terminal of the third transistor M3 is connected to the common-mode point of the oscillator. The first terminal of the sixth resistor R6 is connected to the common-mode point of the oscillator, and the second terminal is grounded.

[0015] Furthermore, the bandwidth control logic circuit includes two comparators, a fifth resistor R5, a fifth capacitor C5, and a NAND gate; Specifically, the first end of the fifth resistor R5 is connected to the negative input of the first comparator COMP1, the positive input of the second comparator COMP2, and the first end of the fifth capacitor C5, while the second end is connected to the common-mode point; the second end of the fifth capacitor C5 is grounded; the positive input of the first comparator COMP1 is connected to the bias voltage VH, and its output is connected to the first input of the NAND gate; the negative input of the second comparator COMP2 is connected to the bias voltage VL, and its output is connected to the second input of the NAND gate; the output of the NAND gate is connected to the gate of the third transistor M3.

[0016] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. The oscillator of the present invention uses an operational amplifier as a clamp, and its output voltage is directly used as the gate bias of the VCO. During the start-up stage, the VCO operates in the Class B operating region with a large gain and easy start-up. Since the gate is dynamically biased, the VCO's operating mode gradually transitions from Class B to Class C during the start-up process, and finally stabilizes in the Class C operating region to obtain good noise performance.

[0017] 2. The operational amplifier used in the oscillator of this invention incorporates a bandwidth-adjustable network, which can adjust the bandwidth operating mode of the operational amplifier through a control signal. During the start-up phase, the control signal is adjusted to make the operational amplifier operate in wideband mode, at which time the loop bandwidth is large, making it easier for the VCO to quickly approach steady state. After the VCO stabilizes, the control signal is adjusted to make the operational amplifier operate in narrowband mode, at which time the bandwidth is narrow, which can filter out noise entering the VCO to obtain good phase noise performance.

[0018] 3. The bandwidth control logic circuit used in the oscillator of this invention provides an automatic control signal for the bandwidth adjustable operational amplifier. When the DC level of the common-mode voltage VCM of the VCO is between the two comparator inputs VH and VL, it is considered that the VCO is working in a steady state. At this time, a logic low level is obtained, and the bandwidth adjustable operational amplifier is controlled to work in narrowband mode to obtain good noise performance. In other cases, the logic circuit outputs a high level to make the operational amplifier work in wideband mode. Attached Figure Description

[0019] Figure 1 This is the overall circuit diagram of a dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to the present invention. Figure 2 This is a circuit diagram of a switched capacitor array in a dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to the present invention. Figure 3 This is a simulation diagram of the gain of the operational amplifier in two modes in a dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to the present invention. Figure 4 This is a transient simulation diagram of the gate bias during operation of a dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to the present invention. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings.

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Example The dynamically biased Class C voltage-controlled oscillator provided in this embodiment initially operates the VCO in the Class B region through dynamic gate bias during the start-up phase. In this region, the VCO's cross-coupling pair achieves higher gain, facilitating oscillation. Once the VCO stabilizes, the gate bias forces it to operate in Class C mode. To balance start-up speed and stable noise performance, a dual-mode bandwidth operational amplifier is introduced into the dynamic gate bias loop. This bandwidth control is implemented by a bandwidth control circuit. The bandwidth control circuit detects the VCO's common-mode point VCM and obtains a stable DC voltage VCM2 through a low-pass filter. This DC voltage is directly connected to two comparators with reference voltages VH and VL. When the DC voltage is between VH and VL, the operational amplifier operates in narrowband mode; otherwise, it operates in wideband mode. This embodiment balances start-up and stable noise performance, ultimately operating well around 4.7 GHz.

[0023] This embodiment provides a dynamically biased Class C voltage-controlled oscillator based on CMOS technology, such as... Figure 1 As shown, the circuit includes a fixed LC resonant network B7, a switched capacitor array B6, a variable capacitor network B5, a cross-coupling network B1, a bandwidth-adjustable operational amplifier B3, a tail current source B4, and a bandwidth control logic circuit B2. The fixed LC resonant network B7, switched capacitor array B6, and variable capacitor network B5 constitute a digitally controlled, voltage-tuned LC resonant cavity. The input voltage and digital control code can adjust the oscillator output frequency. The LC value determines the oscillation frequency of the VCO, and the quality factor Q value dominates the noise performance of the VCO. The cross-coupling network B1 and tail current source B4 act as negative resistance compensation circuits to maintain oscillation and enable the circuit to operate in Class C mode. The bandwidth-adjustable operational amplifier B3 and bandwidth control logic circuit B2 are used to automatically accelerate circuit startup and reduce the phase noise level after circuit stabilization. The specific structure is as follows: The fixed LC resonant network B7 includes a resonant cavity capacitor Cp and an inductor Lp. One end of the resonant cavity capacitor Cp is connected to the forward output port of the VCO, and the other end is connected to the reverse output port of the VCO. One end of the resonant cavity inductor Lp is connected to the forward output port of the VCO, and the other end is connected to the reverse output port of the VCO. This resonant network determines the highest operating frequency of the VCO, and the Q value of the inductor dominates the Q value of the entire VCO, thus dominating the phase noise level of the VCO.

[0024] Among them, the switched capacitor array B6 consists of multiple sets of switched capacitor units. One end of the entire array is connected to the positive output port VOP of the VCO, and the other end is connected to the negative output port VON of the VCO. A numerical control method is used to coarsely tune the oscillator to obtain multiple tuning curves; such as... Figure 2 As shown, the switched capacitor unit includes a positive terminal capacitor CP. <n>Negative terminal capacitor CN <n>and switch S <n>Among them, the positive terminal capacitor CP <n>The first terminal is connected to the positive output VOP of the VCO; capacitor CP <n>The second end is connected to switch S. <n>The first end. Switch S <n>The first terminal is connected to the positive terminal capacitor CP. <n>Second terminal; Switch S <n>The second terminal is connected to the negative terminal capacitor CN. <n>The first terminal; switch S <n>The third end is connected to the external input SW. <n>Negative terminal capacitor CN <n>The first end is connected to switch S <n>The second terminal; negative terminal capacitor CN <n>The second terminal is connected to the negative output terminal VON of the VCO. When switch S... <n>When powered on, the switch array conducts, increasing the capacitance connected to the VCO resonant cavity. This increases the oscillation constant, thus decreasing the VCO frequency. Different control bits S are then applied externally. <k-1:0>This allows for changing the total capacitance value connected to the LC resonant cavity, thereby achieving numerically controlled coarse tuning. The capacitance CP of the switched capacitor unit... <n>and CN <n>It exhibits a binary increasing relationship: , where n is the stage number of the switched capacitor unit.

[0025] The variable capacitor network B5 adopts a varactor diode with bias structure. One end of the network is connected to the positive output port of the VCO, and the other end is connected to the negative output port of the VCO to obtain the voltage-controlled tuning function. The specific structure is as follows: The variable capacitor network B5 includes a first variable capacitor Cvar1, a second variable capacitor Cvar2, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; wherein, the first end of the first capacitor C1 is connected to the positive output terminal VOP of the VCO; the second end of the capacitor C1 is connected to the first end of the first variable capacitor Cvar1 and the first end of the first resistor R1. The second terminal of the first variable capacitor Cvar1 is connected to the first terminal of the second variable capacitor Cvar2 and the control voltage VCTRL; the second terminal of the second variable capacitor Cvar2 is connected to the first terminal of the second capacitor C2 and the first terminal of the second resistor R2; the second terminal of the second capacitor C2 is connected to the negative output terminal VON of the VCO; the second terminal of the first resistor R1 is connected to the second terminal of the second resistor R2 and the bias voltage VB0; the second terminal of the second resistor R2 is connected to the second terminal of the first resistor R1 and the bias voltage VB0. Since the capacitance of the variable capacitor changes with the voltage across it, when VCTRL changes, the capacitance value connected to the LC resonant cavity can be controlled, thereby changing the LC time constant and realizing analog tuning, i.e., voltage control. In addition, the external bias voltage VB0 provides bias voltage to the variable capacitors through the first resistor R1 and the second resistor R2, thereby adjusting the operating voltage range of the first and second variable capacitors Cvar1 and Cvar2 to obtain better tuning linearity.

[0026] The variable capacitor network B5 and the switched capacitor array B6 together constitute the tuning network of the entire VCO. By employing digital coarse tuning and analog fine tuning, both frequency coverage and tuning gain are kept controllable.

[0027] The cross-coupling network B1 employs a cross-coupling pair plus a filter capacitor and a resistor gate bias structure. The cross-coupling pair acts as a negative resistor to compensate for the energy loss of passive components in the circuit to obtain a stable oscillation signal. The filter capacitor and the resistor gate bias structure ensure that the oscillator operates in Class C mode to obtain good noise performance. The specific structure includes: the cross-coupling network B1 includes a first transistor M1, a second transistor M2, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4. The source terminal of the first transistor M1 is connected to the source terminal of the second transistor M2 and the drain terminal of the zeroth transistor M0 in the tail current source B4; the gate terminal of transistor M1 is connected to the first terminal of the third resistor R3 and the first terminal of the fourth capacitor; the drain terminal of transistor M1 is connected to the positive output terminal VOP of the VCO and the first terminal of the third capacitor C3. The source terminal of the second transistor M2 is connected to the source terminal of the first transistor M1 and the drain terminal of the zeroth transistor M0 in the tail current source B4; the gate terminal of transistor M2 is connected to the second terminal of the third capacitor C3 and the first terminal of the fourth resistor R4; the drain terminal of transistor M2 is connected to the negative output terminal VON of the VCO and the second terminal of the fourth transistor C4. The second terminal of the third resistor R3 is connected to the second terminal of the fourth resistor R4 and the source terminal of the third transistor M3 in the bandwidth-adjustable operational amplifier B3, the first terminal of the sixth resistor R6, and the first terminal of the sixth capacitor C6. The second terminal of the fourth resistor R4 is connected to the second terminal of the third resistor R3 and the source terminal of the third transistor M3 in the bandwidth-adjustable operational amplifier B3, the first terminal of the sixth resistor R6, and the first terminal of the sixth capacitor C6. The cross-coupled pair formed by the first transistor M1 and the second transistor M2 provides negative resistance to the VCO to compensate for circuit losses and maintain oscillation; the third capacitor C3 and the fourth capacitor C4 are filter capacitors that transmit the AC signal from the output terminal to the gate terminal of the transistor; the bias voltage VB provides the DC operating point for the cross-coupled pair through the third resistors R3 and R4; when the VCO is stable, less than half of the oscillator period under the gate in the Class C operating region is greater than the threshold voltage of transistors M1 and M2, so the current conduction angle in this operating region is less than 180°, improving the conversion efficiency from DC level to oscillation signal and optimizing phase noise performance.

[0028] The bandwidth-adjustable operational amplifier B3 can be considered as an ideal amplifier and an RC network with a MOS transistor in parallel. One input is connected to an externally provided reference voltage VREF, and the other is connected to the oscillator common-mode point VCM. The output is connected to the gate bias resistor of the cross-coupled pair, used to switch between fast setup and low-noise operating modes. Specifically, the bandwidth-adjustable operational amplifier B3 includes an operational amplifier OPA, a third transistor M3, a sixth resistor R6, and a sixth capacitor C6. The positive input of the operational amplifier OPA is connected to the bias voltage VREF. The negative input of the operational amplifier OPA is connected to the source terminals of the first transistor M1 and the second transistor M2 in the cross-coupled network B1, and the drain terminal of the zeroth transistor M0 in the tail current source B4. The output terminal of the operational amplifier OPA is connected to the second terminal of the sixth resistor R6 and the drain terminal of the third transistor M3. The gate terminal of the third transistor M3 is connected to the output terminal of the NAND gate in the bandwidth control logic circuit B2. The second terminal of the sixth capacitor C6 is grounded. Figure 3 As shown, when the operational amplifier operates in wideband mode, its 3dB bandwidth is on the order of several MHz, while when it operates in narrowband mode, its 3dB bandwidth is on the order of several to tens of kHz. In wideband mode, the gate bias voltage approaches stability relatively quickly; in narrowband mode, since the 3dB bandwidth is on the order of kHz, it can effectively filter out the thermal noise contributed by the operational amplifier transistors and resistors, thereby reducing the noise level of the VCO.

[0029] The bandwidth control logic circuit B2 employs an RC low-pass filter, two comparators, and a NAND gate. The RC low-pass filter filters out common-mode point (VCM) oscillations. The two comparators and the NAND gate provide the control logic for circuit B3. B3 operates in narrowband mode only when the DC level of the common-mode point (VCM) is between the inputs VH and VL of the two comparators; otherwise, it operates in wideband mode. The specific structure includes a fifth resistor R5, a fifth capacitor C5, a first comparator COMP1, a second comparator COMP2, and a NAND gate. The first terminal of the fifth resistor R5 is connected to the first terminal of the fifth capacitor C5, the negative input of the first comparator COMP1, and the positive input of the second comparator COMP2. The second terminal is connected to the source terminals of the first transistor M1 and the second transistor M2 in the cross-coupled network B1, the negative input terminal of the operational amplifier OPA in the bandwidth-adjustable operational amplifier B3, and the source terminal of the zeroth transistor M0 in the tail current source B4. The positive input of the first comparator COMP1 is connected to the bias voltage VH; the output of comparator COMP1 is connected to the first input of the NAND gate. The negative input of the second comparator COMP2 is connected to the bias voltage VL; the output of comparator COMP2 is connected to the second input of the NAND gate. The output of the NAND gate is connected to the gate of the third transistor M3 in the bandwidth-adjustable operational amplifier B3. To enable automatic adjustment of the operating mode of operational amplifier B6, a logic circuit is introduced so that the operational amplifier operates in wideband mode to accelerate the start-up speed during the process of VCO approaching steady state (oscillation stage), and automatically switches to narrowband mode to reduce noise when VCO is operating in steady state. When the level at the positive input of comparators COMP1 and COMP2 is higher than that at the negative input, the comparator outputs a logic high level; when the level at the positive input is lower than that at the negative input, the comparator outputs a logic low level. The VCO common-mode point VCM filters out high-frequency signals through the fifth resistor R5 and the fifth capacitor C5, retaining the DC level VCM2. This DC level VCM2, after being processed by comparators COMP1 and COMP2, outputs a logic low level only when it is between VH and VL. In this case, the operational amplifier operates in narrowband mode, indicating that the VCO has approached or reached a steady state. Otherwise, the NAND gate outputs a logic high level, and the operational amplifier operates in wideband mode to accelerate VCO steady-state establishment.

[0030] The tail current source includes a zeroth transistor M0, whose gate is connected to the bias voltage Vtail; its source is grounded. The tail current source provides the DC operating point for the entire VCO and, together with the cross-coupled network B1, provides a negative resistance to obtain a stable oscillation signal.

[0031] In summary, the voltage-controlled oscillator (VCO) provided in this embodiment adopts a Class C structure. The cross-coupled network B1 adds two resistors and a capacitor to the cross-coupled transistor. By adjusting the bias voltage at the resistor terminals, the circuit operates in Class C. Together with the tail current source B4, the variable capacitor network B5, the switched capacitor array B6, and the fixed LC resonant network B7, it forms the core structure of a Class C VCO that can be digitally tuned and voltage-controlled tuned. An operational amplifier is added to control the initial oscillation operating region of the VCO, and a bandwidth-adjustable network is introduced to allow the operational amplifier to achieve both wideband and narrowband operating modes, while simultaneously ensuring rapid stabilization during the oscillation phase and low noise performance in the steady state. Furthermore, the bandwidth control logic circuit automatically controls the operating mode of the operational amplifier, ultimately achieving a fast-starting, low-noise Class C VCO without the need for external input control signals.

[0032] The advantages of this invention are as follows: This invention provides an oscillator that simultaneously achieves fast start-up speed, reduced start-up difficulty, and low noise in stable conditions, without requiring an external operating zone switching control signal. The core of this achievement lies in the introduction of a bandwidth-adjustable operational amplifier B3 and a logic circuit B2 that controls the operational amplifier's modes. The operational amplifier has both wideband and narrowband modes. Figure 3 The gain-frequency curves shown indicate that in narrowband mode, the 3dB bandwidth is approximately 20kHz, and in wideband mode, the 3dB bandwidth is approximately 3MHz. The entire circuit operates normally as follows: Figure 4 The diagram shows the simulated transient voltage waveforms at the gate terminals (the second terminals of the third resistor R3 and the fourth resistor R4) of the first transistor M1 and the second transistor M2. Stage one is the oscillation start-up stage, and stage two is the steady-state stage. After the circuit is enabled, the operational amplifier controls the gate bias voltage VB of the transistors in the cross-coupling network B1, making its level higher. This results in higher gains for transistors M1 and M2, and the VCO operates in the easily oscillating Class B operating region. When the bandwidth control logic circuit B2 outputs NAND_OUT at a logic high level, the operational amplifier operates in wideband mode, making it easier for the circuit to approach steady state more quickly. After a period of oscillation, through the action of the operational amplifier, the gate voltage VB of transistors M1 and M2 gradually decreases and stabilizes. At this time, the bandwidth control logic circuit outputs NAND_OUT at a logic low level and maintains it, controlling the operational amplifier to operate in narrowband mode to filter out high-frequency noise and obtain good noise performance. Figure 4 As shown, the voltage VCM2 after the common-mode point VCM is filtered by the fifth capacitor C5 and the fifth resistor R5 first increases and then decreases during the oscillation stage, and remains unchanged until it enters the stable stage.

[0033] Traditional Class C voltage-controlled oscillators (VCOs) either offer good noise performance but have low start-up gain, potentially leading to failure to oscillate, or while solving the start-up difficulty, the introduction of transistors or resistors worsens the noise level. This invention provides a dynamically biased Class C VCO that automatically biases the gate of the cross-coupled pair without external control signals, simultaneously balancing start-up speed and steady-state noise level. Multiple overlapping tuning curves are obtained through a switched capacitor array and a variable capacitor network.

[0034] This article uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology, the oscillator comprising a fixed LC resonant network, a switched capacitor array, a variable capacitor network, a cross-coupled network, a bandwidth-adjustable operational amplifier, a tail current source, and bandwidth control logic circuitry, characterized in that: The fixed LC resonant network includes a differential inductor and a capacitor; Each stage of the switched capacitor array includes a switch and two capacitors for digitally controlled tuning of the oscillator. The variable capacitor network adopts a varactor tube with bias structure for voltage-controlled tuning; The cross-coupling network is used to provide negative resistance for the oscillator; The bandwidth control logic circuit includes an RC low-pass filter, a comparator, and a NAND gate. The RC low-pass filter is used to filter out common-mode point VCM oscillations, and the comparator and NAND gate are used to obtain the control logic of the bandwidth-adjustable operational amplifier. The tail current source is used to provide current bias for the entire oscillator circuit.

2. The dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 1, characterized in that, In the fixed LC resonant network, the differential inductor and capacitor are connected in parallel, with their two ends connected to the positive output terminal and the negative output terminal of the oscillator, respectively. The switched capacitor array and the variable capacitor network are located between the positive output terminal and the negative output terminal of the oscillator, forming a resonant circuit for the entire circuit together with the fixed LC resonant network.

3. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 2, characterized in that, The switched capacitor array includes multiple levels of switched capacitor units; each level of switched capacitor unit includes a capacitor CP. <n>、CN <n>and switch SN <n> ；< / n> < / n> < / n> Wherein, the capacitor CP <n>The first terminal is connected to the positive input terminal, and the second terminal is connected to switch SN. <n>The first end; the switch S <n>The second end is connected to capacitor CN <n>The first and third terminals are connected to the external input SW. <n>The capacitor CN <n> The second end is connected to the negative output end.< / n> < / n> < / n> < / n> < / n> < / n> 4. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 2, characterized in that, The variable capacitor network includes a first capacitor C1, a second capacitor C2, a first variable capacitor Cvar1 and a second variable capacitor Cvar2, a first resistor R1 and a second resistor R2; Wherein, the first terminal of the first capacitor C1 is connected to the positive output terminal, and the other terminal is connected to the first terminal of the first variable capacitor Cvar1 and the first terminal of the first resistor R1; the second terminal of the first variable capacitor Cvar1 is connected to the control voltage VCTRL and the first terminal of the second variable capacitor Cvar2; the second terminal of the second variable capacitor is connected to the first terminal of the second capacitor C2 and the first terminal of the second resistor R2; the second terminal of the second capacitor C2 is connected to the negative output terminal; the second terminals of the resistors R1 and R2 are connected to the bias voltage VB0.

5. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 1, characterized in that, The cross-coupled network includes a cross-coupled pair with a filter capacitor and a resistor gate bias structure. The cross-coupled pair acts as a negative resistance structure to compensate for the energy loss of passive components in the circuit.

6. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 5, characterized in that, The cross-coupling network specifically includes a first transistor M1, a second transistor M2, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4; Wherein, the first end of the third capacitor C3 is connected to the positive output terminal, and the second end is connected to the gate terminal of the second transistor M2 and the first end of the third resistor R3; the first end of the fourth capacitor C4 is connected to the gate terminal of the first transistor M1 and the first end of the fourth resistor R4, and the second end is connected to the negative output terminal; the drain terminal of the first transistor M1 is connected to the positive output terminal, and the source terminal is connected to the source terminal of the second transistor M2 and the tail current source.

7. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 6, characterized in that, The tail current source includes a zeroth transistor M0, the drain of which is connected to the source of the first transistor M1. The connection point is the common mode point of the oscillator. The gate is connected to an external bias Vtail, and the source is grounded.

8. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 6, characterized in that, The bandwidth-adjustable operational amplifier has one input terminal connected to an externally provided reference voltage VREF, the other terminal connected to the oscillator common-mode point, and its output connected to the gate bias resistor of the cross-coupled pair.

9. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 8, characterized in that, The bandwidth-adjustable operational amplifier includes an operational amplifier OPA, a third transistor M3, a sixth resistor R6, and a sixth capacitor C6. The operational amplifier OPA has its positive input terminal connected to the reference voltage VREF, its negative input terminal connected to the common-mode point of the oscillator, and its output terminal connected to the drain terminal of the third transistor M3 and the second terminal of the sixth resistor R6. The source terminal of the third transistor M3 is connected to the common-mode point of the oscillator. The first terminal of the sixth resistor R6 is connected to the common-mode point of the oscillator, and the second terminal is grounded.

10. A dynamically biased Class C voltage-controlled oscillator based on CMOS technology according to claim 7, characterized in that, The bandwidth control logic circuit includes two comparators, a fifth resistor R5, a fifth capacitor C5, and a NAND gate; Specifically, the first end of the fifth resistor R5 is connected to the negative input of the first comparator COMP1, the positive input of the second comparator COMP2, and the first end of the fifth capacitor C5, while the second end is connected to the common-mode point; the second end of the fifth capacitor C5 is grounded; the positive input of the first comparator COMP1 is connected to the bias voltage VH, and its output is connected to the first input of the NAND gate; the negative input of the second comparator COMP2 is connected to the bias voltage VL, and its output is connected to the second input of the NAND gate; the output of the NAND gate is connected to the gate of the third transistor M3.

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