A Design Method for Broadband Continuous Doherty Power Amplifier

Abstract

The invention discloses a design method for a broadband continuous Doherty power amplifier, which comprises at least the following steps: step S1: designing a broadband equal-division power divider according to a target frequency band; step S2: constructing a Doherty power amplifier structure, and performing source pulling and load pulling on the power amplifier used in the target frequency band to obtain the impedance of the optimal power and the optimal efficiency point; step S3: designing an input matching circuit according to the optimal source impedance obtained in step S2; step S4: designing an impedance matching network of a carrier power amplifier according to the optimal load impedance obtained in step S2; step S5: designing an impedance matching network of a peak power amplifier according to the optimal load impedance obtained in step S2; step S6: designing a post-matching circuit; step S7: designing a phase compensation line circuit; and step S8: constructing the above-mentioned designed circuits into an integral circuit to obtain a broadband continuous Doherty power amplifier.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a design method for a broadband continuous Doherty power amplifier. Background Art

[0002] Radio frequency microwave technology is developing rapidly in today's era, and many fields of society have put forward high requirements for the advancement and innovation of communication industry technology. As an important part of the radio frequency communication module, the working performance of the radio frequency power amplifier also plays a decisive role in the power consumption of the entire system. However, when the power amplifier works in the saturation region, although high efficiency is achieved, it is also easy to generate distorted signals. Therefore, in order to avoid this situation, the power amplifier is often operated in the power back-off region, but the low efficiency at this time will greatly increase the power consumption. In response to the above problems, the Doherty power amplifier was proposed by researchers and has been continuously developed.

[0003] However, when designing traditional Doherty power amplifiers, the main consideration is the matching of fundamental impedance, which to some extent ignores the impact of harmonic signals on efficiency and bandwidth. At present, there are also some research results involving the control of harmonics. The usual approach is to add harmonic suppression networks to the output networks of the carrier power amplifier module and the peak power amplifier module, but this approach will affect the difficulty of matching the fundamental impedance under the two states of saturation power and power back-off.

[0004] Therefore, in view of the defects of the prior art, it is necessary to propose a technical solution to solve the technical problems existing in the prior art. Summary of the invention

[0005] In view of this, it is indeed necessary to provide a design method for a broadband continuous Doherty power amplifier to cover the commercial frequency band of 5G communications.

[0006] In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

[0007] A design method for a broadband continuous Doherty power amplifier comprises at least the following steps:

[0008] Step S1: designing a broadband equal-division power divider according to the target frequency band;

[0009] Step S2: constructing a Doherty power amplifier structure, performing source pulling and load pulling on the power amplifier used within the target frequency band, and obtaining the impedance of the optimal power and optimal efficiency points;

[0010] Step S3: designing an input matching circuit according to the optimal source impedance obtained in S2;

[0011] Step S4: designing an impedance matching network of the carrier power amplifier according to the optimal load impedance obtained in S2, wherein, under the condition of 6dB output power back-off, the 25 ohm terminal load is matched to the optimal load impedance; and at the same time, under the condition of saturated output power, when the terminal load is 50 ohms, the impedance matching network is also matched to the optimal load impedance;

[0012] Step S5: designing an impedance matching network of the peak power amplifier according to the optimal load impedance obtained in S2, wherein, under the condition of saturated output power, the 50 ohm terminal load is matched to the optimal load impedance, and two quarter-wavelength lines with open terminals are designed at two second harmonic frequency points to achieve the goal of harmonic suppression;

[0013] Step S6: designing a post-matching circuit, wherein firstly, a sixth-order Chebyshev low-pass filter structure with an input-output impedance ratio of 25:50 is designed using capacitors and inductors, and then two of the capacitors C1 and C2 are replaced with a series circuit of a capacitor and an inductor, and finally, the capacitor and the inductor are replaced with a microstrip line;

[0014] Step S7: Design a phase compensation line circuit, wherein the reverse peak fundamental impedance Z P1 ˊWhen the output power is backed off by 6dB, it is in or close to the open circuit region, and the reverse peak second harmonic impedance Z P2 ˊIn or near the short circuit area;

[0015] Step S8: construct the above designed circuit into an integral circuit to obtain a broadband continuous Doherty power amplifier.

[0016] As a further improvement scheme, it at least includes a power divider, a phase compensation line, a carrier power amplifier module, a peak power amplifier module and a post-matching network, wherein the power divider is used to divide the input power into equal parts and output it to the carrier power amplifier module and the peak power amplifier module respectively; the carrier power amplifier module at least includes a phase compensation line, a carrier power amplifier input bias / matching network, a power amplifier transistor, a bias network and a carrier impedance matching network; the peak power amplifier module includes a peak power amplifier input matching / bias network, a power amplifier transistor, a bias network, a peak harmonic suppression / matching network and a phase compensation line; the outputs of the carrier power amplifier module and the peak power amplifier module are combined and connected to the load through a post-matching network.

[0017] As a further improvement, the post-matching network adopts an elliptical low-pass filter network.

[0018] As a further improvement scheme, the carrier impedance matching network is composed of microstrip lines TL1, TL2, TL3, TL4 and a DC blocking capacitor C1; wherein, one end of the microstrip line TL1 is connected to the drain of the power amplifier transistor, the other end of the microstrip line TL1 is connected to one end of the microstrip line TL2, the other end of the microstrip line TL2 is connected to one end of the microstrip line TL3, the other end of the microstrip line TL3 is connected to one end of the DC blocking capacitor C1, and the other end of the DC blocking capacitor C1 is connected to the microstrip line TL4; the other end of the microstrip line TL4 is connected to the input end of the post-matching circuit.

[0019] As a further improvement scheme, the circuit of the peak harmonic suppression / matching network is composed of microstrip lines TL5, TL6, TL7, TL8, TL9, TL10 and a DC blocking capacitor C2, wherein one end of TL5 is connected to the drain of the power amplifier transistor, the other end of TL5 is connected to one end of the microstrip line TL6, the other end of the microstrip line TL6 is connected to one end of the microstrip lines TL7, TL8, TL9, wherein the other ends of the microstrip lines TL7 and TL8 remain open, the other end of TL9 is connected to one end of the microstrip line TL10, and the other end of the microstrip line TL10 is connected to one end of the DC blocking capacitor C2; the other end of the DC blocking capacitor C2 is connected to a microstrip line TL11 with a characteristic impedance of 50 ohms.

[0020] As a further improvement scheme, the post-matching network includes microstrip lines TL12, TL13, TL14, TL15, TL16, TL17, TL18 and TL19, wherein one end of the microstrip line TL12 is connected to the output ends of the carrier power amplifier module and the peak power amplifier module as the input end of the post-matching network, the other end of the microstrip line TL12 is connected to one end of the microstrip lines TL13 and TL15, the other end of the microstrip line TL13 is connected to one end of the microstrip line TL14, the other end of the microstrip line TL14 remains open, the other end of the microstrip line TL15 is connected to one end of the microstrip lines TL16 and TL18, the other end of the microstrip line TL16 is connected to one end of the microstrip line TL17, the other end of the microstrip line TL17 remains open, and the other end of the microstrip line TL18 is connected to one end of the microstrip line TL19.

[0021] As a further improvement, the post-matching network is obtained by replacing the lumped parameter elements of the elliptical low-pass filter structure with microstrip lines. The calculation formula used in the replacement process is as follows:

[0022]

[0023]

[0024] Among them, l L and l C Respectively represent the length of the microstrip line replacing the inductor and capacitor, ZL and Z C are the characteristic impedances of the microstrip lines replacing the inductors and capacitors, respectively, v p and β represent the phase velocity and propagation constant of the microstrip line, respectively, L and C represent the inductance and capacitance values, respectively;

[0025] The calculation formula used in the replacement process is as follows:

[0026]

[0027]

[0028]

[0029]

[0030] Among them, f TZ1 and f TZ2 represents the frequencies corresponding to the two selected transmission zeros, f H It represents the cut-off frequency.

[0031] Compared with the existing technology, the broadband continuous Doherty power amplifier obtained by this design method has an operating bandwidth of 2.8-3.6GHz, covering the 3.3-3.6GHz 5G commercial frequency band. The drain efficiency in the saturated state is 70.5-77%, and the saturated output power is 43.1-44.6dBm. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a broadband continuous Doherty power amplifier designed by the method of the present invention;

[0033] Figure 2 It is the carrier impedance matching network involved in the present invention;

[0034] Figure 3 The peak harmonic suppression / matching network and phase compensation line involved in the present invention;

[0035] Figure 4 is the post-matching network involved in the present invention;

[0036] Figure 5 The sixth-order Chebyshev low-pass filter network involved in the present invention and the elliptic low-pass filter network improved on this basis;

[0037] Figure 6 is the S parameter of the improved elliptic low-pass filter network involved in the present invention;

[0038] Figure 7are the real part and the imaginary part of the input impedance of the post-matching network involved in the present invention;

[0039] Figure 8 is the reverse peak fundamental impedance Z involved in the present invention P1 ˊ and reverse peak second harmonic impedance Z P2 ˊSimulation results;

[0040] Fig. 9 It is a schematic diagram of the large signal characteristic simulation results of a broadband continuous Doherty power amplifier of the present invention.

[0041] Fig.10 The present invention is a flow chart of a design method of a broadband continuous Doherty power amplifier.

[0042] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0043] The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.

[0044] See also Fig.10 , which is a flow chart of a design method of a broadband continuous Doherty power amplifier of the present invention, at least comprises the following steps:

[0045] Step S1: designing a broadband equal-division power divider according to the target frequency band;

[0046] Step S2: constructing a Doherty power amplifier structure, performing source pulling and load pulling on the power amplifier used within the target frequency band, and obtaining the impedance of the optimal power and optimal efficiency points;

[0047] Step S3: designing an input matching circuit according to the optimal source impedance obtained in S2;

[0048] Step S4: designing an impedance matching network of the carrier power amplifier according to the optimal load impedance obtained in S2, wherein, under the condition of 6dB output power back-off, the 25 ohm terminal load is matched to the optimal load impedance; and at the same time, under the condition of saturated output power, when the terminal load is 50 ohms, the impedance matching network is also matched to the optimal load impedance;

[0049] Step S5: designing an impedance matching network of the peak power amplifier according to the optimal load impedance obtained in S2, wherein, under the condition of saturated output power, the 50 ohm terminal load is matched to the optimal load impedance, and two quarter-wavelength lines with open terminals are designed at two second harmonic frequency points to achieve the goal of harmonic suppression;

[0050] Step S6: designing a post-matching circuit, wherein firstly, a sixth-order Chebyshev low-pass filter structure with an input-output impedance ratio of 25:50 is designed using capacitors and inductors, and then two of the capacitors C1 and C2 are replaced with a series circuit of a capacitor and an inductor, and finally, the capacitor and the inductor are replaced with a microstrip line;

[0051] Step S7: Design a phase compensation line circuit, wherein the reverse peak fundamental impedance Z P1 ˊWhen the output power is backed off by 6dB, it is in or close to the open circuit region, and the reverse peak second harmonic impedance Z P2 ˊIn or near the short circuit area;

[0052] Step S8: construct the above designed circuit into an integral circuit to obtain a broadband continuous Doherty power amplifier; and optimize the integral circuit.

[0053] The structure of the broadband continuous Doherty power amplifier designed according to the above method is as follows: Figure 1 As shown, it at least includes a power divider, a phase compensation line, a carrier power amplifier module, a peak power amplifier module and a post-matching network. The power divider is used to divide the input power equally and output it to the carrier power amplifier module and the peak power amplifier module respectively. Its input end is connected to the RF signal output end, and is divided into two outputs connected to the carrier power amplifier module and the peak power amplifier module respectively; the carrier power amplifier module at least includes a phase compensation line, a carrier power amplifier input bias / matching network, a power amplifier transistor, a bias network and a carrier impedance matching network; the peak power amplifier module includes a peak power amplifier input matching / bias network, a power amplifier transistor, a bias network, a peak harmonic suppression / matching network and a phase compensation line; the outputs of the carrier power amplifier module and the peak power amplifier module are connected to the load through the post-matching network, and the post-matching network adopts an elliptical low-pass filter network.

[0054] In the above circuit structure, the circuit structure of the carrier impedance matching network is as follows: Figure 2 As shown, it is composed of microstrip lines TL1, TL2, TL3, TL4 and a DC blocking capacitor C1. Among them, one end of the microstrip line TL1 is connected to the drain of the power amplifier transistor, the other end of the microstrip line TL1 is connected to one end of the microstrip line TL2, the other end of the microstrip line TL2 is connected to one end of the microstrip line TL3, the other end of the microstrip line TL3 is connected to one end of the DC blocking capacitor C1, and the other end of the DC blocking capacitor C1 is connected to the microstrip line TL4. Finally, the other end of the microstrip line TL4 is connected to the input end of the post-matching circuit. This network enables the carrier power amplifier to achieve higher efficiency in both saturated output power and 6dB output power back-off.

[0055] In the above circuit structure, the circuit structure of the peak harmonic suppression / matching network is as follows: Figure 3As shown, it is composed of microstrip lines TL5, TL6, TL7, TL8, TL9, TL10 and a DC blocking capacitor C2, wherein one end of TL5 is connected to the drain of the power amplifier transistor, the other end of TL5 is connected to one end of the microstrip line TL6, the other end of the microstrip line TL6 is connected to one end of the microstrip lines TL7, TL8, TL9, wherein the other ends of the microstrip lines TL7 and TL8 remain open, the other end of TL9 is connected to one end of the microstrip line TL10, and the other end of the microstrip line TL10 is connected to one end of the DC blocking capacitor C2. Finally, the other end of the DC blocking capacitor C2 is connected to a microstrip line TL11 with a characteristic impedance of 50 ohms. The microstrip line TL11 is a phase compensation line, so that the reverse peak fundamental impedance Z in the working frequency band P1 ˊWhen the output power is backed off by 6dB, it is in or close to the open circuit region, and the reverse peak second harmonic impedance Z P2 ˊIt is in or close to the short-circuit area. In addition, the microstrip lines TL7 and TL8 are quarter-wavelength lines corresponding to two second harmonic frequency points, which play a role in harmonic suppression.

[0056] In the above circuit structure, the post-matching network includes microstrip lines TL12, TL13, TL14, TL15, TL16, TL17, TL18 and TL19, wherein one end of the microstrip line TL12 is connected to the output ends of the carrier power amplifier module and the peak power amplifier module as the input end of the post-matching network, the other end of the microstrip line TL12 is connected to one end of the microstrip lines TL13 and TL15, the other end of the microstrip line TL13 is connected to one end of the microstrip line TL14, the other end of the microstrip line TL14 remains open, the other end of the microstrip line TL15 is connected to one end of the microstrip lines TL16 and TL18, the other end of the microstrip line TL16 is connected to one end of the microstrip line TL17, the other end of the microstrip line TL17 remains open, and the other end of the microstrip line TL18 is connected to one end of the microstrip line TL19, and the signal is outputted thereby.

[0057] See also Figure 2 , which shows the circuit structure of the carrier impedance matching network in the present invention. The present invention abandons the quarter-wavelength line in the traditional Doherty structure and adopts a matching network composed of four series microstrip lines. Through simulation software optimization, the 25-ohm terminal load can be matched to the optimal load impedance area under the condition of 6dB output power back-off; at the same time, under the condition of saturated output power, when the terminal load is changed to 50 ohms, the impedance matching network can also be matched to the optimal load impedance area.

[0058] See also Figure 3, which shows the peak harmonic suppression / matching network and phase compensation line involved in the present invention. The harmonic suppression network will effectively limit the second harmonic signal generated by the peak power amplifier to prevent it from entering the post-matching network. The harmonic suppression network is composed of microstrip lines TL7 and TL8. First, two second harmonic suppression frequency points f are selected. s1 and f s2 , and then determine the parameters of the two microstrip lines according to the following formula:

[0059]

[0060]

[0061] Where Z7 and Z8 are the characteristic impedances of microstrip lines TL7 and TL8, θ7 and θ8 are the electrical lengths of microstrip lines TL7 and TL8, and Z fs1 and Z fs2 They are the input impedances of microstrip lines TL7 and TL8 respectively. Then the parameters of microstrip lines TL5, TL6, TL9 and TL10 are optimized by simulation software, so that the entire peak harmonic suppression / matching network can match the 50 ohm terminal load to the optimal load impedance of the power amplifier transistor. Finally, by adjusting the length of the phase compensation line, the reverse fundamental impedance is located at or close to the open circuit area on the Smith chart, and the reverse second harmonic impedance is located at or close to the short circuit area on the Smith chart. Figure 8 is the reverse peak fundamental impedance Z involved in the present invention P1 ' and reverse peak second harmonic impedance Z P2 'The simulation results meet the above design goals.

[0062] See also Figure 4 , which shows the post-matching network involved in the present invention. Figure 5 The lumped parameter element of the elliptical low-pass filter structure shown in the figure is equivalently replaced by a microstrip line. The calculation formula used in the replacement process is as follows:

[0063]

[0064]

[0065] Among them l L and l C Respectively represent the length of the microstrip line replacing the inductor and capacitor, Z L and Z C are the characteristic impedances of the microstrip lines replacing the inductors and capacitors, respectively, v pand β represent the phase velocity and propagation constant of the microstrip line, respectively, and L and C represent the inductance and capacitance, respectively. The design process of the above-mentioned elliptical low-pass filter structure is as follows: first, a sixth-order Chebyshev low-pass filter structure with an impedance conversion ratio of 25:50 is designed, and then the capacitor C1 and the capacitor C2 are replaced with a series circuit of capacitor and inductor. The structure obtained after the replacement is the improved elliptical low-pass filter structure adopted by the present invention, which can form two transmission zeros in the stop band to effectively suppress the harmonic signal input from the carrier power amplifier module. The calculation formula used in the replacement process is as follows:

[0066]

[0067]

[0068]

[0069]

[0070] Among them, f TZ1 and f TZ2 represents the frequencies corresponding to the two selected transmission zeros, f H It represents the cut-off frequency. Figure 6 The S parameters of the improved elliptical low-pass filter network involved in the present invention are shown. It can be seen intuitively from the figure that the value of S11 in the working frequency band is better than -30dB, and the value of S22 in the second harmonic frequency band is better than -26dB. From the simulation data, it can be found that the structure is in line with the design purpose of the present invention. In addition, Figure 7 The input impedance Z of the post-matching network involved in the present invention is shown as follows: PMN The real and imaginary parts of Z PMN The real part is very close to the target value of 25 ohms throughout the entire operating frequency band, and the imaginary part is also close to the ideal value of 0.

[0071] See also Fig. 9 , which is a schematic diagram of the simulation results of the large signal characteristics of a broadband continuous Doherty power amplifier of the present invention. It can be seen from the results that the operating bandwidth of the designed broadband continuous Doherty power amplifier is 2.8-3.6GHz, covering the 5G commercial frequency band of 3.3-3.6GHz. The drain efficiency in the saturated state is 70.5-77%, and the saturated output power is 43.1-44.6dBm. When the output power is backed off by 6dB, the drain efficiency is 48-54%.

[0072] The above embodiments are only used to help understand the method and core idea of ​​the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0073] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A design method for a broadband continuous Doherty power amplifier, characterized in that: At least the following steps are included: Step S1: designing a broadband equal-division power divider according to the target frequency band; Step S2: constructing a Doherty power amplifier structure, performing source pulling and load pulling on the power amplifier used within the target frequency band, and obtaining the impedance of the optimal power and optimal efficiency points; Step S3: designing an input matching circuit according to the optimal source impedance obtained in step S2; Step S4: designing an impedance matching network of the carrier power amplifier according to the optimal load impedance obtained in step S2, wherein, under the condition of 6 dB output power back-off, the 25 ohm terminal load is matched to the optimal load impedance; and at the same time, under the condition of saturated output power, when the terminal load is 50 ohms, the impedance matching network is also matched to the optimal load impedance; Step S5: designing an impedance matching network of the peak power amplifier according to the optimal load impedance obtained in step S2, wherein, under the condition of saturated output power, the 50 ohm terminal load is matched to the optimal load impedance, and two quarter-wavelength lines with open terminals are designed at two second harmonic frequency points to achieve the goal of harmonic suppression; Step S6: designing a post-matching circuit, wherein firstly, a sixth-order Chebyshev low-pass filter structure with an input-output impedance ratio of 25:50 is designed using capacitors and inductors, and then two of the capacitors C1 and C2 are replaced with a series circuit of a capacitor and an inductor, and finally, the capacitor and the inductor are replaced with a microstrip line; Step S7: Design a phase compensation line circuit, wherein the reverse peak fundamental impedance Z P1 ˊ At 6dB output power back-off, it is in or close to the open circuit region, and the reverse peak second harmonic impedance Z P2 ˊ In or near a short circuit area; Step S8: construct the above designed circuit into an integral circuit to obtain a broadband continuous Doherty power amplifier.

2. The design method of a broadband continuous Doherty power amplifier according to claim 1, characterized in that: The invention at least comprises a power divider, a phase compensation line, a carrier power amplifier module, a peak power amplifier module and a post-matching circuit, wherein the power divider is used to divide the input power equally and output it to the carrier power amplifier module and the peak power amplifier module respectively; the carrier power amplifier module at least comprises a phase compensation line, a carrier power amplifier input bias / matching network, a power amplifier transistor, a bias network and a carrier impedance matching network; the peak power amplifier module comprises a peak power amplifier input matching / bias network, a power amplifier transistor, a bias network, a peak harmonic suppression / matching network and a phase compensation line; the outputs of the carrier power amplifier module and the peak power amplifier module are combined and connected to the load through the post-matching circuit.

3. The design method of a broadband continuous Doherty power amplifier according to claim 2, characterized in that: The post-matching circuit uses an elliptical low-pass filter network.

4. The design method of a broadband continuous Doherty power amplifier according to claim 2, characterized in that: The carrier impedance matching network is composed of microstrip lines TL1, TL2, TL3, TL4 and a DC blocking capacitor C1; wherein, one end of the microstrip line TL1 is connected to the drain of the power amplifier transistor, the other end of the microstrip line TL1 is connected to one end of the microstrip line TL2, the other end of the microstrip line TL2 is connected to one end of the microstrip line TL3, the other end of the microstrip line TL3 is connected to one end of the DC blocking capacitor C1, and the other end of the DC blocking capacitor C1 is connected to the microstrip line TL4; the other end of the microstrip line TL4 is connected to the input end of the post-matching circuit.

5. The design method of a broadband continuous Doherty power amplifier according to claim 2, characterized in that: The circuit of the peak harmonic suppression / matching network is composed of microstrip lines TL5, TL6, TL7, TL8, TL9, TL10 and a DC blocking capacitor C2, wherein one end of TL5 is connected to the drain of the power amplifier transistor, the other end of TL5 is connected to one end of the microstrip line TL6, the other end of the microstrip line TL6 is connected to one end of the microstrip lines TL7, TL8, TL9, wherein the other ends of the microstrip lines TL7 and TL8 remain open, the other end of TL9 is connected to one end of the microstrip line TL10, the other end of the microstrip line TL10 is connected to one end of the DC blocking capacitor C2; the other end of the DC blocking capacitor C2 is connected to a microstrip line TL11 with a characteristic impedance of 50 ohms.

6. The design method of a broadband continuous Doherty power amplifier according to claim 3, characterized in that: The post-matching circuit includes microstrip lines TL12, TL13, TL14, TL15, TL16, TL17, TL18 and TL19, wherein one end of the microstrip line TL12 is connected to the output ends of the carrier power amplifier module and the peak power amplifier module as the input end of the post-matching circuit, the other end of the microstrip line TL12 is connected to one end of the microstrip lines TL13 and TL15, the other end of the microstrip line TL13 is connected to one end of the microstrip line TL14, the other end of the microstrip line TL14 remains open, the other end of the microstrip line TL15 is connected to one end of the microstrip lines TL16 and TL18, the other end of the microstrip line TL16 is connected to one end of the microstrip line TL17, the other end of the microstrip line TL17 remains open, and the other end of the microstrip line TL18 is connected to one end of the microstrip line TL19.

7. The design method of a broadband continuous Doherty power amplifier according to claim 6, characterized in that: The post-matching circuit is obtained by replacing the lumped parameter elements of the elliptical low-pass filter structure with microstrip lines. The calculation formula used in the replacement process is as follows: Among them, l L and l C Respectively represent the length of the microstrip line replacing the inductor and capacitor, Z L and Z C are the characteristic impedances of the microstrip lines replacing the inductors and capacitors, respectively, v p and β represent the phase velocity and propagation constant of the microstrip line, respectively, L and C represent the inductance and capacitance values, respectively; The calculation formula used in the replacement process is as follows: Among them, f TZ1 and f TZ2 represents the frequencies corresponding to the two selected transmission zeros, f H It represents the cut-off frequency.

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