A body electrode isolated MOS transistor neutralization capacitor amplifier and terminal

Abstract

The present invention belongs to the field of wireless communication technologies, and discloses a body electrode isolated MOS transistor neutralization capacitor amplifier and a terminal. The body electrode isolated MOS transistor neutralization capacitor amplifier is provided with a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the gate in the first MOS transistor is connected to the positive-phase input signal terminal Vin+, and the drain in the first MOS transistor is connected to the positive-phase output signal terminal Vout+; the gate in the second MOS transistor is connected to the inverting input signal terminal Vin−, and the drain in the second MOS transistor is connected to the negative-phase output signal terminal Vout−; the source in the third MOS transistor is connected to a first resistor, and the body electrode in the third MOS transistor is connected to a second resistor; the source in the fourth MOS transistor is connected to the first resistor. The present invention can improve the gain of the amplifier, optimize the noise figure of the amplifier, and contribute to the improvement of the overall performance of the radio frequency chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communication, and particularly relates to a body electrode isolated MOS transistor neutralization capacitance amplifier and a terminal. Background Art

[0002] Currently, in the design process of a radio frequency amplifier, due to the feedback effect of the MOS transistor gate-drain capacitance C gd , the amplified signal at the drain is introduced into the gate input terminal, which easily causes oscillation of the amplifier and affects the operating state of the amplifier. Therefore, the neutralization capacitance technology is often used, and a capacitor is used to connect the gate of one MOS transistor at one end of the differential amplifier to the drain of the MOS transistor at the other end. Since the phases of the drains of the two MOS transistors are opposite, it can offset C gd . After introducing the neutralization capacitance C n , the stability factor of the amplifier is:

[0003]

[0004] where ω is the angular frequency, R g is the gate resistance, R d is the load resistance, and g m is the transconductance of the MOS transistor. When k is greater than or equal to 1, the amplifier is unconditionally stable. Therefore, only when the size of the neutralization capacitance C n is close to that of C gd , the denominator of k approaches zero and k becomes very large, and the amplifier can be stable.

[0005] Currently, the most commonly used neutralization capacitances are MIM capacitors composed of metal plates and MOM capacitors composed of metal fingers. The capacitance values of these two types of capacitors are related to the metal processing conditions and do not change with the process deviation of the MOS transistor. Therefore, it is impossible to ensure that the influence of C gd can be offset under different process corners. As Figure 6As shown, consider the metal capacitor as a capacitor with a constant capacitance value, design the capacitance value of the capacitor according to the standard process corner tt, and simulate the variation of Gmax with frequency at different process corners of the amplifier. The Gmax curve is usually divided into two segments. The low-frequency part is MSG, that is, the maximum gain that the amplifier can achieve in the stable state, and the high-frequency part is MAG, that is, the maximum gain that the amplifier can obtain. The MAG part indicates that the amplifier is unconditionally stable within this frequency band. In the figure, the solid line is the tt process corner, and the neutralization capacitor is designed according to this process corner, so there is almost no MSG curve. The dotted line is the ss process corner, and the dash line is the ff process corner. It can be seen that there are obvious MSG intervals in the Gmax curves of the amplifier at the ff and ss process corners, and the turning point from MSG to MAG is around 10 GHz. If the performance of the MOS transistors fabricated for the amplifier is at the ff or ss process corner, the amplifier may oscillate at frequencies within 10 GHz.

[0006] The closest prior art is a technology that uses the C of MOS transistors gd as a neutralization capacitor, and the body electrodes and source electrodes of the MOS transistors used as the neutralization capacitor are connected to a large resistor. Its basic circuit is as Figure 2 shown. In the figure, M1 and M2 are the core MOS transistors of the amplifier, used to amplify the signal, M3 and M4 are the neutralization capacitor MOS transistors, Load1 and Load2 are the loads of the amplifier, and R1 is the tail resistor. When the value of R1 is very large, almost no current will pass through M3 and M4, and M3 and M4 operate in an almost cutoff state. One end of the C of M3 and M1 gd is connected to the positive-phase input signal Vin+, and the other ends are connected to Vout- and Vout+ respectively, with opposite phases, so they can cancel each other out. Similarly, the C of M4 and M2 gd can also cancel each other out. Since the same type of MOS transistors placed together have synchronous changes in ion implantation concentration, gate oxide layer thickness, etc. caused by process deviations, the cancellation effect of C gd will basically not change due to process deviations, and the amplifier can be very stable at each process corner. Although the above-mentioned neutralization capacitor scheme makes the stability of the amplifier resistant to process fluctuations, there are still many problems, and the corresponding disadvantages are as follows: The gain will be reduced compared with the metal neutralization capacitor. The source electrodes and body electrodes of M3 and M4 are short-circuited to one end of the large resistor. The parasitic capacitance C db between the drain electrodes and body electrodes of M3 and M4 and some parasitic resistors will form a path between the drain electrodes of M1 and M2, and this path will consume the output power and reduce the gain of the amplifier. The noise performance of the amplifier is poor. The noise performance of the amplifier in the RF link is usually measured by the noise figure. This index is usually inversely proportional to the transconductance g of the amplifier m , so when the gain of the amplifier is reduced, the g of the amplifier is equivalently reduced m, thus increasing the noise figure. At the same time, in the path formed by C db between M3 and M4 and some parasitic resistors, the parasitic resistors will introduce resistor thermal noise into the output terminal, further deteriorating the output noise.

[0007] Through the above analysis, the problems and defects of the prior art are as follows:

[0008] (1) Compared with the prior art, the capacitance gain of the metal neutralization will decrease. The source and body electrodes of M3 and M4 are short-circuited to one end of a large resistor. The parasitic capacitance C db between the drain and body electrodes of M3 and M4 and some parasitic resistors will form a path between the drains of M1 and M2. This path will consume the output power and reduce the gain of the amplifier.

[0009] (2) The noise performance of the amplifier in the prior art is poor. The noise performance of the amplifier in the RF link is usually measured by the noise figure. This index is usually inversely proportional to the transconductance g m of the amplifier. Therefore, when the gain of the amplifier decreases, the g m of the amplifier is equivalently reduced, db thus increasing the noise figure. At the same time, in the path formed by C Summary of the Invention

[0010] Aiming at the problems existing in the prior art, the present invention provides a body electrode isolated MOS transistor neutralization capacitance amplifier and a terminal.

[0011] The present invention is implemented as follows. A body electrode isolated MOS transistor neutralization capacitance amplifier is provided with a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;

[0012] The gate of the first MOS transistor is connected to the positive input signal terminal Vin+, and the drain of the first MOS transistor is connected to the positive output signal terminal Vout+; the gate of the second MOS transistor is connected to the negative input signal terminal Vin-, and the drain of the second MOS transistor is connected to the negative output signal terminal Vout-.

[0013] The source of the third MOS transistor is connected to the first resistor, and the body electrode of the third MOS transistor is connected to the second resistor; the source of the fourth MOS transistor is connected to the first resistor, and the body electrode of the fourth MOS transistor is connected to the third resistor.

[0014] Further, the first MOS transistor is provided with a source and a body electrode, and the source and the body electrode are grounded.

[0015] Further, the second MOS transistor is provided with a source electrode and a body electrode, and the source electrode and the body electrode are grounded.

[0016] Further, the third MOS transistor is provided with a gate, the gate is connected to the positive-phase input signal terminal Vin+, and the drain in the third MOS transistor is connected to the negative-phase output signal terminal Vout-.

[0017] Further, the fourth MOS transistor is provided with a gate, the gate is connected to the inverting input signal terminal Vin-, and the drain in the fourth MOS transistor is connected to the positive-phase output signal terminal Vout+.

[0018] Further, the positive-phase output signal terminal Vout+ is connected to a first load, and the first load is connected to the power supply Vdd.

[0019] Further, the negative-phase output signal terminal Vout- is connected to a second load, and the second load is connected to the power supply Vdd.

[0020] Further, one end of the first resistor is grounded, one end of the second resistor is grounded, and one end of the third resistor is grounded.

[0021] Further, the first MOS transistor and the second MOS transistor have the same size, and the third MOS transistor and the fourth MOS transistor have the same size;

[0022] The second resistor and the third resistor have the same size, and the values of the first resistor, the second resistor, and the third resistor are in the order of kiloohms and above.

[0023] Another object of the present invention is to provide a wireless communication terminal, and the wireless communication terminal is equipped with the body electrode isolation MOS transistor neutralization capacitor amplifier.

[0024] Another object of the present invention is to provide a radio frequency chip, and the radio frequency chip includes the body electrode isolation MOS transistor neutralization capacitor amplifier.

[0025] Combined with the above technical solutions and the solved technical problems, the advantages and positive effects of the technical solution to be protected by the present invention are analyzed from the following aspects:

[0026] First, aiming at the technical problems existing in the above-mentioned prior art and the difficulty of solving this problem, closely combining the technical solution to be protected by the present invention and the results and data in the R & D process, etc., analyze in detail and deeply how the technical solution of the present invention solves the technical problems and the creative technical effects brought after solving the problems. The specific description is as follows:

[0027] In the present invention, the body electrodes of two MOS transistors are respectively connected to a large resistor to ground, and then the source electrodes are interconnected and connected to a large resistor to ground. These two MOS transistors operating in the cut-off region are cross-connected between the gates and drains of the two core MOS transistors of the amplifier, and the C of the two is gd mutually cancelled, thereby achieving full-band stability of the amplifier. The DC potentials of the drains and body electrodes of the MOS transistor used as the neutralizing capacitor and the core MOS transistor of the amplifier are the same, and C gd is similarly affected by process variations. Therefore, the neutralizing capacitor of the present invention can follow the process fluctuations of the core MOS transistor of the amplifier, so that the amplifier is full-band stable under different process corners, preventing the amplifier from self-exciting oscillation and generating unwanted output frequencies. The present invention designs the MOS transistor neutralizing capacitor using the body electrode isolation technology, cutting off the path introduced by the C db and parasitic resistance of the neutralizing capacitor MOS transistor, and will not cause loss at the differential output end, so it has good gain performance. The body electrode isolation large resistor of the present invention can cut off the AC path from the body electrode to the ground potential, suppressing the parasitic resistance of the body electrode as a noise source from transmitting thermal noise to the amplifier output end, which helps to improve the noise performance of the amplifier.

[0028] Second, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are specifically described as follows:

[0029] In the present invention, the body electrodes of the MOS transistors used as the neutralizing capacitor are respectively connected to a large resistor to ground, isolating the path formed by C db and parasitic resistance at both ends of the differential output of the amplifier. Therefore, the gain of the amplifier can be increased, the noise figure of the amplifier can be optimized, and it helps to improve the overall performance of the RF chip. The present invention optimizes the gain and noise performance of the amplifier by connecting the body electrodes of the MOS transistor capacitors to a large resistor to ground separately. By improving the original MOS transistor neutralizing capacitor technology, the present invention isolates the C db and the loss of the output gain caused by part of the parasitic resistance, and suppresses the thermal noise of the body electrode parasitic resistance transmitted to the output end. Therefore, the amplifier of the present invention has good gain and noise performance. The MOS transistor capacitor adopted in the present invention utilizes the consistency during the processing of the same type of MOS transistor, so it can follow the C gd change of the core MOS transistor of the amplifier, so that the amplifier is full-band stable under different process corners, preventing the amplifier from self-exciting oscillation from affecting the working state and generating interference frequencies. Considering from the perspectives of gain, noise, and stability, the amplifier solution of the present invention helps to improve the overall performance of the RF chip.

[0030] Third, as the creative auxiliary evidence of the claims of the present invention, it is also reflected in the following important aspects:

[0031] (1) The expected benefits and commercial value after the transformation of the technical solution of the present invention are as follows: By improving the neutralization capacitance technology, the present invention enhances the resistance of the amplifier's stability to process fluctuations and improves the product yield. The present invention improves the noise figure and gain performance of the amplifier compared with the traditional MOS transistor capacitance, and thus can be applied to amplifier products such as high-performance low-noise amplifiers and driver amplifiers.

[0032] (2) The technical solution of the present invention solves the technical problems that people have been eager to solve but have never been successful in

[0033] In the design of traditional RF amplifiers, if a metal capacitor is used as the neutralization capacitor, it is impossible to track the process fluctuations of MOS transistors, and stability problems are likely to occur; if the traditional MOS transistor neutralization capacitance technology is used, although the stability is good, the gain and noise figure will decrease, affecting the performance of the amplifier. The present invention takes into account both the gain and noise performance of the amplifier while ensuring the stability of the amplifier against process fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic structural diagram of a MOS transistor neutralization capacitor amplifier with a body electrode isolation provided by an embodiment of the present invention;

[0035] Figure 2 is a circuit diagram of an amplifier with a body electrode source short-circuited MOS transistor neutralization capacitor provided by an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of the simulation of Gmax varying with frequency at different process corners provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of the comparison of Gmax of the amplifier varying with frequency provided by an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of the comparison of NFmin of the amplifier varying with frequency provided by an embodiment of the present invention;

[0039] Figure 6 is a schematic diagram of the stability of an amplifier with a metal neutralization capacitor at different process corners provided by an embodiment of the present invention;

[0040] In the figure: 1. First load; 2. Positive-phase output signal terminal Vout+; 3. Third MOS transistor; 4. Positive-phase input signal terminal Vin+; 5. First MOS transistor; 6. Second resistor; 7. First resistor; 8. Third resistor; 9. Second MOS transistor; 10. Inverting input signal terminal Vin-; 11. Fourth MOS transistor; 12. Negative-phase output signal terminal Vout-; 13. Second load. Detailed implementation manners

[0041] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] I. Explanation of embodiments. This part is an explanatory embodiment that expands and explains the technical solutions of the claims in order to enable those skilled in the art to fully understand how the present invention is specifically implemented.

[0043] As Figure 1 shown, in the belt electrode isolation MOS transistor neutralization capacitor amplifier provided by the embodiment of the present invention, the source and body electrode of the first MOS transistor 5 are grounded, the gate of the first MOS transistor 5 is connected to the positive input signal terminal Vin+4, and the drain of the first MOS transistor 5 is connected to the positive output signal terminal Vout+2; the source and body electrode of the second MOS transistor 9 are grounded, the gate of the second MOS transistor 9 is connected to the negative input signal terminal Vin-10, and the drain of the second MOS transistor 9 is connected to the negative output signal terminal Vout-12; the source of the third MOS transistor 3 is connected to the first resistor 7, the body electrode of the third MOS transistor 3 is connected to the second resistor 6, the gate of the third MOS transistor 3 is connected to the positive input signal terminal Vin+4, and the drain of the third MOS transistor 3 is connected to the negative output signal terminal Vout-12;

[0044] the source of the fourth MOS transistor 11 is connected to the first resistor 7, the body electrode of the fourth MOS transistor 11 is connected to the third resistor 8, the gate of the fourth MOS transistor 11 is connected to the negative input signal terminal Vin-10, and the drain of the fourth MOS transistor 11 is connected to the positive output signal terminal Vout+2; the positive output signal terminal Vout+2 is connected to the first load 1, and the first load 1 is connected to the power supply Vdd; the negative output signal terminal Vout-12 is connected to the second load 13, and the second load 13 is connected to the power supply Vdd; one end of the first resistor 7 is grounded, one end of the second resistor 6 is grounded, and one end of the third resistor 8 is grounded. The sizes of the first MOS transistor 5 and the second MOS transistor 9 are the same, and the sizes of the third MOS transistor 3 and the fourth MOS transistor 11 are the same; the sizes of the second resistor 6 and the third resistor 8 are the same, and the values of the first resistor 7, the second resistor 6 and the third resistor 8 need to be in the order of kiloohms or above.

[0045] The working principle of the present invention is as follows: The first MOS transistor 5 and the second MOS transistor 9 are the core MOS transistors of the amplifier, used to amplify signals. The third MOS transistor 3 and the fourth MOS transistor 11 are neutralizing capacitor MOS transistors. When the value of the first resistor 7 is very large, almost no current flows through the third MOS transistor 3 and the fourth MOS transistor 11, and the third MOS transistor 3 and the fourth MOS transistor 11 operate in an almost cutoff state. One end of the C of the third MOS transistor 3 and the first MOS transistor 5 gd is connected to the positive-phase input signal terminal Vin+4, and the other ends are respectively connected to the negative-phase output signal terminal Vout-12 and the positive-phase output signal terminal Vout+2, with opposite phases, so they can cancel each other out. Similarly, the C of the fourth MOS transistor 11 and the second MOS transistor 9 gd can also cancel each other out. The body electrodes of the third MOS transistor 3 and the fourth MOS transistor 11 are respectively connected to the ground through the large second resistor 6 and the third resistor 8, so the DC potential of the body electrodes is the ground potential. The DC potentials of the drains and body electrodes of the first MOS transistor 5, the second MOS transistor 9, the third MOS transistor 3, and the fourth MOS transistor 11 are the same, and the depletion regions between the drains and body electrodes are similar.

[0046] II. Application embodiments. In order to prove the creativity and technical value of the technical solution of the present invention, this part is an application embodiment of the technical solution of the claims on specific products or related technologies.

[0047] The present invention improves the noise figure and gain performance of the amplifier compared with the traditional MOS transistor capacitor, so it can be applied to amplifier products such as high-performance low-noise amplifiers and driver amplifiers. It can be applied in RF chips, wireless communication chips, radar chips, etc.

[0048] III. Evidence of the related effects of the embodiments. Some positive effects have been achieved during the research and development or use of the embodiments of the present invention, and there are indeed great advantages compared with the prior art. The following content is described in combination with the data, charts, etc. of the test process.

[0049] In the prior art, as Figure 2 shown, the body electrodes of M3 and M4 are short-circuited to one end of the large resistor R1, and the body electrode potential is higher than the ground potential. Therefore, the depletion regions between the drains and body electrodes of M3, M4 and M1, M2 are different. And this depletion region has a great influence on the capacitor C gd . Therefore, compared with the prior art, the C of the core MOS transistor of the present invention gd and the C of the neutralizing capacitor MOS transistor gd have a more similar environment, the consistency between the two capacitors is better, and it is more resistant to process fluctuations. As Figure 3As shown, the dimensions of M3 and M4 are designed according to the tt process corner, and the curves of Gmax of the amplifier varying with frequency under the tt, ff, and ss process corners are simulated. Among them, the solid line represents the tt process corner, the dotted-dashed line represents the ff process corner, and the dashed line represents the ss process corner. Comparing Figure 6 and Figure 3 It can be seen that under different process corners, the amplifier does not have an obvious turning point from MSG to MAG in the full frequency band and is almost in the MAG state. Therefore, full-band stability can be achieved under different process corners. The body electrodes of M3 and M4 are connected to the ground through large resistors R2 and R3. Therefore, the C db and parasitic resistance of M3 and M4 cause the path to be cut off and will not exacerbate the loss of the output node. Therefore, compared with the scheme of short-circuiting the body electrode and the source electrode, the amplifier of the present invention has a higher gain.

[0050] As Figure 4 shown, it is the situation of the Gmax of the amplifier varying with frequency. Among them, the black solid line is the Gmax of the amplifier of the present invention, and the gray dotted-dashed line is the Gmax of the amplifier of the scheme of short-circuiting the body electrode and the source electrode. The dimensions of M1-2 and the DC bias voltage of the two schemes are the same. From Figure 4 it can be seen that the Gmax of the amplifier of the present invention is greater than that of the amplifier of the scheme of short-circuiting the body electrode and the source electrode at each frequency point. At 50 GHz, the Gmax of the present invention is 0.8 dB higher than that of the prior art. At 90 GHz, the Gmax of the present invention is 5.01 dB, and the Gmax of the prior art is 4.34 dB. The present invention is 0.67 dB higher than the prior art. The large resistors R2 and R3 have a strong isolation effect. The thermal noise generated by the parasitic resistance of the body electrode will encounter a high-resistance loop and will not be superimposed on the output end of the amplifier. Therefore, compared with the scheme of short-circuiting the body electrode and the source electrode, it has a lower noise coefficient. As Figure 5 shown, the black curve is the NFmin of the amplifier of the present invention, and the gray dotted-dashed line is the NFmin of the amplifier of the prior art. In the full frequency band, the NFmin of the amplifier of the present invention is less than that of the prior art. At 50 GHz, the NFmin of the present invention is 2.7662 dB, and the NFmin of the prior art is 2.9299 dB. The present invention is 0.1637 dB lower than the prior art. At 100 GHz, the NFmin of the present invention is 4.9113 dB, and the NFmin of the prior art is 5.1738 dB. The present invention is 0.2625 dB lower than the prior art. The higher the frequency, the more noise from the parasitic resistance at the body electrode of the prior art enters the output end through capacitors such as C db etc. Therefore, the higher the frequency, the more the present invention improves the NFmin.

[0051] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be covered by the protection scope of the present invention.

Claims

1. A body electrode isolated MOS transistor neutralization capacitor amplifier, characterized in that, The body electrode isolated MOS transistor neutralization capacitor amplifier is provided with: A first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; The gate of the first MOS transistor is connected to the positive phase input signal terminal Vin+, and the drain of the first MOS transistor is connected to the positive phase output signal terminal Vout+; the gate of the second MOS transistor is connected to the negative phase input signal terminal Vin-, and the drain of the second MOS transistor is connected to the negative phase output signal terminal Vout-; The source of the third MOS transistor is connected to a first resistor, and the body electrode of the third MOS transistor is connected to a second resistor; the source of the fourth MOS transistor is connected to the first resistor, and the body electrode of the fourth MOS transistor is connected to a third resistor; The first MOS transistor is provided with a source and a body electrode, and the source and the body electrode are grounded; The second MOS transistor is provided with a source and a body electrode, and the source and the body electrode are grounded; The third MOS transistor is provided with a gate, the gate is connected to the positive phase input signal terminal Vin+, and the drain of the third MOS transistor is connected to the negative phase output signal terminal Vout-; The fourth MOS transistor is provided with a gate, the gate is connected to the negative phase input signal terminal Vin-, and the drain of the fourth MOS transistor is connected to the positive phase output signal terminal Vout+.

2. The body electrode isolated MOS transistor neutralization capacitor amplifier according to claim 1, wherein The positive phase output signal terminal Vout+ is connected to a first load, and the first load is connected to the power supply Vdd.

3. The strip electrode isolation MOS tube neutralization capacitor amplifier according to claim 1, characterized in that The negative phase output signal terminal Vout- is connected to a second load, and the second load is connected to the power supply Vdd.

4. The body electrode isolated MOS transistor neutralization capacitor amplifier according to claim 1, characterized in that, One end of the first resistor is grounded, one end of the second resistor is grounded, and one end of the third resistor is grounded; The first MOS transistor and the second MOS transistor have the same size, and the third MOS transistor and the fourth MOS transistor have the same size; The second resistor and the third resistor have the same size, and the values of the first resistor, the second resistor, and the third resistor are in the order of kiloohms and above.

5. A wireless communication terminal, characterized in that, The wireless communication terminal is installed with the body electrode isolated MOS transistor neutralization capacitor amplifier according to any one of claims 1 to 4.

6. A radio frequency chip, characterized in that, The radio frequency chip includes the body electrode isolated MOS transistor neutralization capacitor amplifier according to any one of claims 1 to 4.

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