Voltage and current sensing circuit for measuring a load connected to a power amplifier

Abstract

A voltage sensing circuit for measuring a load connected to a power amplifier, the load for receiving first and second voltages that are opposite in phase, the voltage sensing circuit comprising a first input coupled to the first voltage, a second input coupled to the second voltage, a first voltage divider circuit comprising an input coupled to the first input and an output coupled to the first output, a second voltage divider circuit comprising an input coupled to the second input and an output coupled to the second output, and a driver circuit comprising a first input for receiving a reference voltage, a second input for receiving a common mode signal of the first and second voltage divider circuits, and an output for driving an output common mode voltage of the first and second voltage divider circuits with the reference voltage.

Description

[0001] This application claims priority to EP application No. 21214440.6, filed on December 14, 2021, with the European Patent Office, with the title “Voltage and current sense circuits for measuring a load connected to a power amplifier”, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present invention relates to a voltage sense circuit for measuring a load connected to a power amplifier. The present invention also relates to a current sense circuit for measuring a load connected to a power amplifier and to a method of operating said voltage and current sense circuits for measuring a load connected to a power amplifier. BACKGROUND

[0003] A typical configuration of the output stage of a power amplifier is a bridge-tied load (BTL), as shown in Figure 1A and where both sides of the load, e.g. a loudspeaker, are driven by two outputs in opposite phase. In this way, the current through the load can flow in two opposite directions. Typically, the power amplifier is operated in class D, which means that the output transistors are switched so that the output voltage is a modulated square wave with a typical fundamental frequency of about 500 kHz. Ferrite beads or inductors can be placed between the actual amplifier output and the loudspeaker to reduce electromagnetic radiation and / or filter the high frequency residue due to the modulation.

[0004] For various reasons, e.g. to provide loudspeaker protection, it can be desirable to measure the impedance of a load connected to the power amplifier. This can be achieved by simultaneously measuring the voltage across the load and the current through the load. For example, if the load is a loudspeaker, by measuring the load, it is possible to provide loudspeaker protection, because the impedance of the loudspeaker provides information about its voice coil temperature, which in turn is a measure of the loudspeaker membrane excursion, as Marco Berkhout, Dooper and Benno Krabbenborg in "A 4Ω 2.65W Class-D Audio Amplifier with Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for adaptive speaker protection", IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 2952-2961, 2013.

[0005] The measured voltage and current are usually converted to digital values, allowing further signal processing in the digital domain. Sigma-delta data converters provide a very cost-effective solution for this.

[0006] As shown in Figure 1B , measuring the voltage across the load can be done by observing the difference between the voltages V SP and V SN on both sides of the load. However, the measurement of the voltage is affected by the large common-mode voltage swing that occurs on the amplifier output node.

[0007] As shown in Figure 1C , measuring the current through the load can be done by adding a known measurement resistor R SENSE in series with the load and by measuring the differential voltage across the known measurement resistor. For power efficiency reasons, the impedance of the measurement resistor should be small compared to the load, typically about 1% or less of the load. If the measurement resistor is placed between the output of the amplifier and the load, the measurement resistor will experience the same common-mode voltage swing as the load, but the differential signal to be observed is much smaller than the voltage across the load. In other words, the common-mode rejection requirements of the current interface circuit will be extremely challenging if this sensing scheme is employed. This will come at the cost of chip area and / or current consumption.

[0008] Alternatively, the measurement resistor can be placed at a different location in the current path. A popular solution is to place two measurement resistors in series with the source of the low-voltage side output transistor, as shown in Figure 1D . Since one leg of each resistor is connected to ground, the common-mode problem is sufficiently solved this way. In terms of the AD modulation scheme, there are two possible circuit states:

[0009] 1.M HSP and M LSN Simultaneous conduction. Through R L The current will also flow through R LSN (Note: Due to the presence of an inductor connected in series with the load, the current can still have two polarities.)

[0010] 2.M HSN and M LSP Simultaneous conduction. Through R L The current will also flow through R LSP .

[0011] Now, by observing the differential voltage V LSP -V LSN This allows for a sufficient measurement of the load current.

[0012] However, for BD modulation schemes, measurement becomes complex due to the existence of four possible circuit states. Within each PWM cycle, the output stage will operate in one of three states, such as... Figure 1E As shown.

[0013] 1. For half of the audio signal (V) SP >V SN When the signal is positive, the circuit will operate in the following states in sequence:

[0014] State 1: V OP and V ON All are low

[0015] State 3: High V OP and low V ON

[0016] State 2: V OP and V ON All are high

[0017] State 3: High V OP and low V ON

[0018] Then return to state one. This is in Figure 1E The upper part is shown.

[0019] 2. For half of the audio signal (V) SP <V SN For a negative signal, the circuit will then operate in the following states:

[0020] State 1: V OP and V ON All are low

[0021] State 4: Low V OP and high VON

[0022] State two: V OP and V ON are both high

[0023] State four: low V OP and high V ON

[0024] Then it returns to state one. This is shown in part 1 of Figure 1E Figure 1.

[0025] Note that in state one, the load current is sensed by two resistors. In state three and four, the load current is sensed by one resistor. Finally, in state two, the load current is not sensed at all. This is obviously a source of distortion, which needs additional design measures to make the system work. In the previously described amplifier, compensation has been used to reduce the distortion, but its performance is limited. Alternatively, including a high-side sensing resistor in the measurement is the basic way to solve this problem. Figure 1F It is shown how the situation changes when a high-side sensing resistor is also included in the sensing scheme.

[0026] Adding a high-side sensing resistor solves the distortion problem of BD modulation, because the load current is sensed by two sensing resistors, independent of the state in which the output stage is running.

[0027] Figure 1G It is shown how the current interface, which is part of the invention, combines the four sensing voltages V HSN , V HSP , V LSP and V LSN into a signal that can be processed by the ADC.

[0028] Binet et al. in the paper “A fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing” published in ESSCIRC 2014 - 40th European Solid State Circuits Conference discloses an implementation of a current interface as shown in Figure 1H Figure 2. The operation of this circuit is briefly described as follows. The output transistors of the bridge have a sensing resistor (R 1HP , R 1HN , R 1LP , R 1LN ) in series with their source. In total, four local amplifiers and resistors R2HP together are configured as VI converters to generate a scaled copy of the sense current automatically. The intentionally added offset sources (called OffsetHP etc.) should be noted that even if the current through R 1HP changes direction, the current through R 2HP will not change polarity. Through additional current mirrors, the four scaled currents (two per half bridge) are then added in the current domain and will leave the circuit at nodes I OUTP and I OUTN .

[0029] Since the signal through the sense resistors is small, it is clear that the four amplifiers must be designed as low noise, which will come at the cost of power consumption and chip area. The mismatch of the offset sources and the current mirrors adds to the mismatch performance of the circuit, which must be compensated by improving the matching of the resistors R 2HP and R 1HP etc. Again, this will consume additional chip area. Finally, it must be noted that since current mirrors are used, the scaled copy of the sense current will flow in multiple branches. This will result in additional power consumption.

[0030] Furthermore, with respect to the voltage interface, the differential voltage across the load can become as large as the supply voltage of the power stage. This is typically too large to be handled by an Analog to Digital convertor (ADC) that can be connected to V op and V on . Therefore, the voltage interface must also contain attenuation. Furthermore, the supply voltage of the output stage is typically modulated with the (audio) signal to further improve efficiency (class-D operation). This means that the common mode voltage will vary with the audio signal. Furthermore, since class-D operation is performed, the output common mode voltage contains a lot of high frequency components. Therefore, common mode rejection is an important requirement for the voltage interface. Finally, the output common mode voltage level of the voltage interface should conveniently fit between the supply rails of the ADC.

[0031] A known technique to reject common mode in an amplifier is to use two matched voltage dividers as voltage interface, where the two matched voltage dividers have zero common mode rejection, as shown in Figure 1I In Figure 1I , a voltage level conversion is needed to adapt the signal to the ADC. However, this results in additional noise and distortion.

[0032] Binet et al. in "A fully Integrated Class-D Amplifier in 40nm CMOS with Dynamic Cascode Bias and Load Current Sensing", ESSCIRC 2014 - 40th European Solid State Circuits Conference, disclose a current interface in which the output transistor of the bridge has a sensing resistor in series with its source, and the four local amplifiers in total are configured with the sensing resistor as a converter to actively generate a scaled copy of the sensing current. It is noted that the intentionally added offset source that even if the current through the resistor changes direction, the current through the sensing resistor does not change polarity. Through an additional current mirror, the four scaled currents (two per bridge half) are then added in the current domain and will leave the circuit at the output node. Since the signal through the sensing resistor is small, the four amplifiers must be designed to be low noise, which will come at the cost of power consumption and chip area. The mismatch performance of the circuit is increased by the mismatch of the offset source and the current mirror, which must be compensated by improving the matching of the sensing resistor, which in turn will consume additional chip area. Finally, since a current mirror is used, the scaled copy of the sensing current will flow in multiple branches, which will result in additional power consumption.

[0033] It would be advantageous to implement a low cost and effective voltage and current sensing circuit for measuring a load connected to an amplifier that still performs well in terms of noise and distortion. SUMMARY

[0034] The present invention relates to a voltage sensing circuit for measuring a load connected to a power amplifier, wherein the load is for receiving a first voltage at a first end and a second voltage at a second end, wherein the first and second voltages are opposite in phase, wherein the voltage sensing circuit comprises a first input coupled to the first voltage, a second input coupled to the second voltage, a first output, a second output, a first voltage divider circuit comprising an input coupled to the first input and an output coupled to the first output, a second voltage divider circuit comprising an input coupled to the second input and an output coupled to the second output, and a drive circuit comprising a first input for receiving a reference voltage, a second input for receiving a common mode signal of the first and second voltage divider circuits, and an output for driving an output common mode voltage of the first and second voltage divider circuits with the reference voltage. This allows to suppress common mode variations, thereby converting a differential voltage into a current having an amplitude and a common mode voltage level that can be directly processed by an ADC. For example, the resulting output current can be directly integrated by a first integrator stage of an additional sigma-delta converter.

[0035] The second input of the drive circuit can be connected to the output of the drive circuit. This provides a suitable connection that allows to suppress common mode variations.

[0036] Each of the first and second voltage dividers can comprise a pair of resistors, wherein each of the pair of resistors comprises a first end and a second end, and wherein the first ends of the pair of resistors can be connected to the first and second outputs, respectively, wherein the second ends of the pair of resistors can be connected to each other. This is a very effective implementation that can reduce noise and distortion. In this way, the resulting output current can be directly integrated by a first integrator stage of a sigma-delta converter connected to the voltage sensing circuit.

[0037] Optionally, the first and second voltage dividers can be implemented by using voltage sources or in any other suitable way.

[0038] The voltage second input and output of the drive circuit can be connected to the second ends of the pair of resistors. This is a suitable connection that suppresses common mode variations. However, the voltage second input and output of the drive circuit can be coupled to the first and second voltage dividers in any suitable way.

[0039] The drive circuit can comprise first and second resistors connected in series between the first and second output terminals, such that a first end of the first resistor can be coupled to the first output terminal, a second end of the first resistor can be coupled to a first end of the second resistor, and a second end of the second resistor can be coupled to the second output terminal, and wherein the second input of the drive circuit can be coupled to the first end of the second resistor. This is a very effective implementation of the drive circuit which allows common mode rejection of the voltage sense circuit output. However, the drive circuit can be implemented in any other suitable way. This is a very effective implementation of using resistors which can reduce noise and distortion.

[0040] The drive circuit can comprise first and second output resistors R 3p -R 3n , wherein the first output resistor R 3p can be connected between the first output terminal I op and a first end of the first resistor R 2p , and the second output resistor R 3n can be connected between the second output terminal I on and a second end of the second resistor R 2n . In this way, the physical quantity that the ADC has to deal with is current, and therefore the same ADC can be connected to the voltage sense interface and the current sense interface to measure current and voltage to calculate the load. That is, by adding first and second output resistors R 3p -R 3n as a first stage of the ADC, the output variable of the voltage sense circuit is current. This would be beneficial because both the current and voltage sense ADCs can be the same circuit, both converting current to digital.

[0041] The present invention also relates to a current sense circuit for measuring a load connected to a power amplifier, wherein the load is for receiving a first voltage V ip at a first terminal, and a second voltage V in at a second terminal, wherein the first and second voltages are opposite in phase, wherein the current sense circuit comprises a first input terminal coupled to the first voltage V HSN , a second input terminal coupled to the second voltage V HSP , a third input terminal coupled to a third voltage V LSN , a fourth input terminal coupled to a fourth voltage V LSP , a first output terminal I op , a second output terminal I onA common-mode loop circuit, comprising a first input, a second input, a third input, and an output, wherein the first and second inputs are used for the first and second output terminals I. op and I on The common-mode voltage is received, the third input is used to receive a reference voltage, and a control signal is generated at the output to switch the current sensing circuit such that the common-mode voltage equals the reference voltage. In this way, two high-side sensed voltages and two low-side sensed voltages are converted into a current suitable for the common-mode voltage level of the ADC. For the high-side voltage, its definition is related to the supply voltage (and may include interference), and a differential amplifier is used to suppress common supply variations. An important feature is that when the differential amplifier is used for the high-side voltage, it does not need to be used for the low-side voltage. This is beneficial for noise and distortion. Furthermore, although a common-mode loop is used to achieve a suitable output common-mode voltage level, this voltage is replicated to the high-side sense resistor, thus reusing the branch current, which saves power and area. The resulting output current, obtained by combining conversion and addition operations, is directly integrated by the first integrator stage of an additional sigma-delta converter. This invention demonstrates the simplest possible implementation, where a minimal number of circuit elements contribute to output noise, mismatch, and distortion.

[0042] The current sensing circuit may further include a differential mode loop circuit, which includes a first input, a second input, and an output, wherein the first and second inputs are used to receive a voltage difference and generate a control signal to keep the voltage difference equal to zero.

[0043] The current sensing circuit further includes a first transistor M1, which includes a source, a gate, and a drain; a second transistor M2, which includes a source, a gate, and a drain; and first, second, third, and fourth switching resistors, each including a first terminal and a second terminal. The first terminals of the first, second, third, and fourth switching resistors are coupled to the first, second, third, and fourth input terminals, respectively. The second terminal of the first resistor is coupled to the first input of the differential-mode loop circuit and the source of the first transistor M1. The second terminal of the second resistor is coupled to the second input of the differential-mode loop circuit and the source of the second transistor M2. The second terminal of the third resistor is coupled to the first input of the common-mode loop circuit and the drain of the first transistor M1. The second terminal of the fourth resistor is coupled to the second input of the common-mode loop circuit and the drain of the second transistor M2. The control signals generated by the common-mode loop circuit and the differential-mode loop circuit control the gates of the first transistor M1 and the second transistor M2. This is a very efficient implementation.

[0044] The present invention also relates to a method of operating a current sensing circuit and / or a method of operating a voltage sensing circuit.

[0045] The person skilled in the art will understand that the above-mentioned features can be combined in any way deemed useful. Furthermore, the modifications and variations described in relation with the system can equally be applied to a method. BRIEF DESCRIPTION OF DRAWINGS

[0046] In the following, various aspects of the application will be explained by way of example with reference to the accompanying drawings. The drawings are schematic representations, and not drawn to scale.

[0047] Figures 1A-1I A known current or voltage sensing circuit is shown.

[0048] Figure 2 A voltage sensing circuit according to an embodiment of the application is shown.

[0049] Figure 3 A voltage sensing circuit according to another embodiment of the application is shown.

[0050] Figure 4 A voltage sensing circuit according to yet another embodiment of the application is shown.

[0051] Figure 5 A voltage sensing circuit according to another embodiment of the application is shown.

[0052] Figure 6 A current sensing circuit according to an embodiment of the application is shown.

[0053] Figure 7 An implementation of the current sensing circuit of Figure 6 is shown.

[0054] Figure 8 An implementation of the current sensing circuit according to an embodiment of the application is shown.

[0055] Figure 9 A power amplifier comprising a current sensing circuit and a voltage sensing circuit according to the application is shown.

[0056] Figure 10 A flow chart of a method of operating a voltage sensing circuit is shown.

[0057] Figure 11 A flow chart of a method of operating a current sensing circuit is shown. DETAILED DESCRIPTION

[0058] Figure 2 A voltage sensing circuit 200 according to a first embodiment of the application is shown. Figure 2 The voltage sensing circuit 200 in comprises a first input 202, a second input 204, a first output 206 and a second output 208. Figure 2The first input 202 of the voltage sensing circuit 200 is configured to receive a first input voltage V ip , the second input 204 is configured to receive a second input voltage V in , the first output 206 is configured to provide a first output voltage V op , and the second output 208 is configured to provide a second output voltage V on .

[0059] Figure 2 The voltage sensing circuit 200 further comprises a first voltage divider circuit 220 and a second voltage divider circuit 222. The first voltage divider circuit 220 comprises an input and an output, wherein the input is coupled to the first input 202 of the voltage sensing circuit 200 and the output is coupled to the first output 206. The second voltage divider circuit 222 comprises an input and an output, wherein the input is coupled to the second input 204 and the output is coupled to the second output 208.

[0060] Figure 2 The voltage sensing circuit 200 further comprises a driving circuit 232, wherein the driving circuit 232 comprises a first input 234, a second input 236 and an output 238. The first input 234 of the driving circuit 232 is configured to receive a reference voltage, the second input 236 is coupled to the first voltage divider circuit 220 and the second voltage divider circuit 222 and is configured to receive a common mode signal, and the output 238 is coupled to the first and second voltage divider circuits and is configured to drive the output common mode voltage of the first and second voltage divider circuits with the reference voltage.

[0061] Figure 2 The voltage sensing circuit 200 shown can be used for measuring a load connected to a power amplifier, wherein the load is configured to receive a first voltage (V ip ) at a first end of the load and a second voltage (V in ) at a second end of the load, wherein the first and second voltages are opposite in phase.

[0062] In case of large common mode voltage variations, the differential voltage is converted to a current having an amplitude and a common mode voltage level that can be conveniently processed by an ADC, thereby suppressing the common mode variations. The resulting output current can be directly integrated by a first integrator stage of an additional sigma-delta converter.

[0063] Figure 3 A voltage sensing circuit 300 according to yet another embodiment of the present application is shown, wherein the same reference numbers as in Figure 2 are used to indicate the same elements. Figure 3 The first voltage divider 220 in comprises a first resistor R1p and a second resistor R 2p wherein the first resistor R 1p comprises a first end 302 and a second end 304, and the second resistor R 2p comprises a first end 306 and a second end 308. The first end 302 of the first resistor R 1p is connected to the first input 202 of the voltage sensing circuit 300, the second end 304 of the first resistor R 1p is connected to the first output 206 of the voltage sensing circuit 300, and to the first end 306 of the second resistor R 2p The second end 308 of the second resistor R 2p is connected to the second input 236 and the output 238 of the drive circuit 232.

[0064] Figure 3 The second voltage divider 222 shown comprises a third resistor R 1n and a fourth resistor R 2n wherein the third resistor R 1n comprises a first end 312 and a second end 314, and the fourth resistor R 2n comprises a first end 316 and a second end 318. The first end 312 of the third resistor R 1n is connected to the second input 204, the second end 314 of the third resistor R 1n is connected to the second output 208 of the voltage sensing circuit 300 and to the first end 316 of the fourth resistor R 2n The second end 318 of the fourth resistor R 2n is connected to the second input 236 of the drive circuit 232 and the output 238 of the drive circuit 232 and to the second end 308 of the second resistor R 2p

[0065] In this way, Figure 3 the output common mode voltage of the voltage sensing circuit 300 shown is not particularly grounded, which can be inconvenient for an ADC that can be connected to the first and second outputs 206 and 208. Furthermore, common mode rejection is provided at the output of the voltage sensing circuit 300. The common ground node between the second end 308 of the second resistor R 2p and the second end 318 of the fourth resistor R 2n may be replaced by a voltage source, or by a buffer that drives this common ground node at a suitable voltage. In the example shown in Figure 4 the first and second outputs V op and V on ​will be around 0.9 volts if the ADC provides a voltage of 1.8 volts with respect to ground, which is convenient. However, this is not a limitation, the first and second outputs V op and V on may have any suitable value.

[0066] Figure 3 Another embodiment according to the application is shown, in which the drive circuit 400 comprises, in addition to the first resistor R Figure 5 compared to the drive circuit 232 shown. The drive circuit 400 further comprises a first resistor R 4p and a second resistor R 4n . The first resistor R 4p comprises a first end 402 and a second end 404. The second resistor R 4n comprises a first end 406 and a second end 408. The first end 402 of the first resistor R 4p of the drive circuit 400 is connected to the first output 206, the second end 408 of the second resistor R 4n is connected to the second output 208, and the second end 404 of the first resistor R 4p is connected to the first end 406 of the second resistor R 4n and to the output 420 of the amplifier 422.

[0067] This allows to suppress input common mode voltage variations. The loop around the amplifier is responsible for ensuring that the node between the second resistor R 2p and the fourth resistor R 2n will follow the reference voltage provided at the non-inverting input of the amplifier. Since there is no low-ohmic path to ground between the second resistor R 2p and the fourth resistor R 2n , the current through the second resistor R 2p must be equal to the current through the fourth resistor R 2n . Therefore, any positive excursion of V op must be accompanied by an equal negative excursion of V on . This means that the output common mode level (V op + V on ) / 2 remains equal to the reference voltage. Any variation of the input common mode voltage will result in an increase of the common mode current through the first resistor R 1p and the second resistor R 1n , which will be consumed by the output 420 of the amplifier 422 via the first resistor R 4p and the second resistor R 4n of the drive circuit 400. In this way common mode suppression is achieved.

[0068] Figure 4 Another embodiment of the invention is shown, wherein the drive circuit 510 and Figure 5 Compared to the drive circuit 400, it includes a first output resistor R. 3p Second output resistor R 3n The first output resistor R of the drive circuit 510 3p The second output resistor R of the drive circuit 510 includes a first terminal 512 and a second terminal 514. 3n It includes a first terminal 516 and a second terminal 518. The first output resistor R of the drive circuit 510 3p The second terminal 514 is connected to the first output terminal 204, and the first output resistor R of the drive circuit 510 3p The first end is connected to the first resistor R 4p The first terminal 402. The second output resistor R of the drive circuit 510 3n The second terminal 518 is connected to the second output terminal 208, and the second output resistor R of the drive circuit 510 3n The first terminal 516 is connected to the second resistor R. 4n The first end is 406. Figure 5 The first output terminal 204 and the second output terminal 206 of the voltage sensing circuit are coupled together. In this way, the voltage sensing circuit connected to... Figure 6 The physical quantity processed by the ADC in the voltage sensing circuit is current, due to the use of the first output resistor R. 3p Second output resistor R 3n And the coupling between the first and second output terminals, the differential voltage between the first output terminal 204 and the second output terminal 206 carries the current.

[0069] Figure 6 A current sensing circuit 600 according to an embodiment of the invention is shown. The current sensing circuit 600 includes components coupled to a first voltage V. HSN The first input terminal 602 is coupled to the second voltage V. HSP The second input terminal 604 is coupled to the third voltage V. LSN The third input terminal 606 is coupled to the fourth voltage V. LSP The fourth input terminal 608 and the first output terminal I op Second output terminal I on A common-mode loop circuit 610 is included. The common-mode loop circuit 610 includes a first input 612, a second input 614, a third input 616, and an output 618. The first and second inputs of the common-mode loop circuit 610 are respectively used at the first and second output terminals I. op and I onA common mode voltage is received. A third input 616 is used to receive a reference voltage. In this way, the common mode loop circuit 610 is used to generate a control signal at its output 618 to switch the first transistor Ml and the second transistor M2 such that the common mode voltage is equal to the reference voltage. The current sense circuit 600 further comprises a differential mode loop circuit 630 comprising a first input 632 and a second input 634 and an output 636, wherein the first and second inputs 632 and 634 are used to receive a voltage difference such that the differential mode loop circuit 630 generates a control signal to control the first transistor Ml and the second transistor M2 to keep the voltage difference equal to zero. Figure 6 The goal of the current sense interface in is to combine the four sense voltages V HSN , V HSP , V LSP and V LSN into one signal that can be processed by the ADC. The high side voltages V HSP and V HSN will vary around the positive supply voltage vddp. The low side sense voltages V LSP and V LSN will vary around the ground level, which is the reference node. The ADC will receive an input current I OUT with a voltage level of about half of the ADC supply voltage. This means that an analog voltage level conversion is part of the function. Furthermore, the high side sense voltages share one common vddp voltage. Some kind of differential amplifier can be used to suppress the power supply modulation.

[0070] The input voltages V HSP , V HSN , V LSP and V LSN are connected to four sense resistors. In the absence of load current, V HSP and V HSN will be equal to the power stage supply voltage vddp, V LSP and V LSN will be equal to ground. The four conversion resistors, called R SUM,HSP , R SUM,HSM , R SUM,HLP and R SUM,HLN are equal. The outputs I OP and I ON are differentially shorted by the first integrator of the sigma-delta loop of the ADC. This means that any current leaving the I OP node will return through the I ON node. Figure 7 The mathematical function that the circuit in is to implement is:

[0071] I OUT = (VHSP - V HSN - V LSP + V LSN ) / R sum

[0072] According to Kirchoff's first law, the sum of the currents at the output node and the current in the present domain occurs. As mentioned before, the common mode loop circuit 610 will measure the common mode voltage at nodes I OP and I ON and control the gates of M1 and M2 in phase until the common mode voltage equals the external reference voltage V REF,CM . This means that the current through R SUM,LSP and R SUM,LSN will both equal V REF,CM / R SUM . These currents will also flow through R SUM,HSP and R SUM,HSN , therefore, the external reference voltage will also drop across these high side resistors. No additional high side reference voltage is needed anymore. The excess voltage (because vddp is relatively large) will drop across the cascode transistors M1 and M2. Depending on the maximum supply voltage, these can have to be high voltage types. The differential mode loop circuit 630 will measure the difference between the voltage V S1 and the voltage V S2 and adjust this difference to zero by controlling the gates of M1 and M2 in opposite phase. One advantage of this circuit is that the entire voltage headroom between the common mode output voltage and ground will drop across the four conversion resistors called R SUM,HSP , R SUM,HSM , R SUM,HLP , and R SUM,HLN . This is the best case scenario for noise within a given current budget. If the cascode transistors are placed between the top branch of the conversion resistors and the current output, and if the same branch current must be maintained, the resistors must be smaller to allow for the voltage drop across the cascodes. Smaller resistors result in larger current noise.

[0073] Figure 8 and Figure 6 shows an implementation of a current sense circuit using transistors in Figure 8 . The only contribution to the differential output current noise is the resistor and the differential pair. Instead of directly controlling the gates of M1 and M2, as shown in Figure 9 , the in-phase control is done by adjusting the tail current source of the differential mode loop differential pair. The common mode loop becomes a two stage amplifier in this way, which increases the loop gain of this loop.

[0074] Figure 9 shows a power amplifier 900 comprising a current sense circuit 600 and a voltage sense circuit 200 according to the present invention.Figure 10 Also shown is a connection of the output of the current sense circuit 600 and the ADC 902 of the voltage sense circuit 200. Figure 11 A flowchart of a method of operating a voltage sense circuit for measuring a load connected to a power amplifier is shown, wherein the load is configured to receive a first voltage V ip at a first end and a second voltage V in at a second end, wherein the first and second voltages are in opposite phase. The method comprises a step 1002 comprising receiving the first voltage V ip at an input of a first voltage divider circuit 220 of the voltage sense circuit. The method further proceeds to step 1004 by receiving the second voltage V in at an input of a second voltage divider circuit 222 of the voltage sense circuit. In step 1006, the method comprises receiving a reference voltage at a first input 234 of a drive circuit 232 of the voltage sense circuit and receiving a common mode signal from the first and second voltage divider circuits at a second input 236 of the drive circuit 232. Finally, the method comprises a step 1008 comprising driving an output common mode voltage of the first and second voltage divider circuits with the reference voltage by the drive circuit.

[0075] ​ A flowchart of a method of operating a current sense circuit for measuring a load connected to a power amplifier is shown, wherein the load is configured to receive a first voltage V ip at a first end and a second voltage V in at a second end, wherein the first and second voltages are in opposite phase. The method comprises a step 1002, receiving the first voltage V HSN at a first input 602, receiving the second voltage V HSP at a second input 604, receiving a third voltage V LSN at a third input 606, and receiving a fourth voltage V LSP at a fourth input 608. The method further comprises a step 1104, receiving a common mode voltage of an output of the current sense circuit at a first and second input of a common mode loop circuit 610 and receiving a reference voltage at a third input of the common mode loop circuit 610. Finally, the method comprises a step 1106, generating a control signal 636 at an output of the common mode loop circuit 610 to switch the current sense circuit 600 such that the common mode voltage equals the reference voltage.

[0076] The examples and embodiments described herein are used to illustrate and not to limit the present application. Those skilled in the art will be able to design alternative embodiments without departing from the scope of the claims. The reference signs in brackets in the claims are not to be construed as limiting the scope of the claims. Items described as separate items in the claims or the specification can be implemented as a single item implemented jointly with the features of the separate items.

Claims

1. A voltage sensing circuit for measuring a load connected to a power amplifier, wherein the load is configured to receive a first voltage at a first terminal and a second voltage at a second terminal, wherein the first voltage and the second voltage are opposite in phase, wherein the voltage sensing circuit comprises: a first input coupled to the first voltage; a second input coupled to the second voltage; a first output; a second output; a first voltage divider circuit comprising an input coupled to the first input and an output coupled to the first output; a second voltage divider circuit comprising an input coupled to the second input and an output coupled to the second output; and a driver circuit comprising a first input for receiving a reference voltage, a second input for receiving a common mode signal from the first voltage divider circuit and the second voltage divider circuit, and an output for driving an output common mode voltage of the first voltage divider circuit and the second voltage divider circuit with the reference voltage; wherein the driver circuit further comprises a first resistor and a second resistor connected in series between the first output and the second output such that a first terminal of the first resistor is coupled to the first output, a second terminal of the first resistor is coupled to a first terminal of the second resistor, and a second terminal of the second resistor is coupled to the second output, and wherein the second input of the driver circuit is coupled to the first terminal of the second resistor.

2. The voltage sensing circuit of claim 1, wherein the second input of the driver circuit is connected to the output of the driver circuit.

3. The voltage sensing circuit of claim 1, wherein each of the first voltage divider and the second voltage divider comprises a pair of resistors, wherein each of the pair of resistors comprises a first terminal and a second terminal, and wherein the first terminals of the pair of resistors are connected to the first output and the second output, respectively, wherein the second terminals of the pair of resistors are connected to each other.

4. The voltage sensing circuit of claim 3, wherein the second input and the output of the driver circuit are connected to the second terminals of the pair of resistors.

6. The voltage sensing circuit of any one of claims 1-5, wherein the driver circuit comprises an operational amplifier.

5. The voltage sensing circuit of claim 1, wherein the drive circuit comprises a first output resistor and a second output resistor, wherein the first output resistor is connected between a first output terminal (I op ) and a first terminal of the first resistor, and the second output resistor is connected between a second output terminal (I on ) and a second terminal of the second resistor.

7. A current sensing circuit for measuring a load connected to a power amplifier, wherein the load is configured to receive a first voltage at a first terminal and a second voltage at a second terminal, wherein the first voltage and the second voltage are opposite in phase, wherein the current sensing circuit comprises: a first input coupled to the first voltage; a second input coupled to the second voltage; a third input coupled to a third voltage; a fourth input coupled to a fourth voltage; a first output; a second output; and a driver circuit comprising a first input for receiving a reference voltage, a second input for receiving a common mode signal from the first input and the second input, and an output for driving an output common mode voltage of the first input and the second input with the reference voltage. ​ a common mode loop circuit comprising a first input, a second input, a third input and an output, wherein the first input and the second input are for receiving a common mode voltage at the first output and the second output, the third input is for receiving a reference voltage, and a control signal is generated at the output to switch the current sense circuit such that the common mode voltage is equal to the reference voltage; wherein the current sense circuit further comprises a first conversion resistor, a second conversion resistor, a third conversion resistor and a fourth conversion resistor comprising a first end and a second end, wherein the first ends of the first conversion resistor, the second conversion resistor, the third conversion resistor and the fourth conversion resistor are coupled to the first input, the second input, the third input and the fourth input respectively.

8. The current sense circuit of claim 7, further comprising a differential mode loop circuit comprising a first input and a second input and an output, wherein the first input and the second input are for receiving a voltage difference and generating a control signal to reduce the voltage difference.

9. The current sense circuit of claim 8, further comprising a first transistor comprising a source, a gate and a drain, a second transistor comprising a source, a gate and a drain, and the second end of the first conversion resistor is coupled to the first input of the differential mode loop circuit and the source of the first transistor, the second end of the second conversion resistor is coupled to the second input of the differential mode loop circuit and the source of the second transistor, the second end of the third conversion resistor is coupled to the first input of the common mode loop circuit and the drain of the first transistor, the second end of the fourth conversion resistor is coupled to the second input of the common mode loop circuit and the drain of the second transistor, and the gates of the first transistor and the second transistor are controlled by the control signals generated by the common mode loop circuit and the differential mode loop circuit.

10. The current sense circuit of any one of claims 7-9, wherein the common mode loop circuit comprises a pair of differential amplifier circuits.

11. The current sense circuit of claim 8 or 9, wherein the differential mode loop circuit comprises a differential amplifier circuit.

12. A power amplification circuit comprising the current sense circuit of any one of claims 7-11 and / or the voltage sense circuit of any one of claims 1-6.

13. A method of operating a voltage sense circuit for measuring a load connected to a power amplifier, wherein the load is for receiving a first voltage at a first end and a second voltage at a second end, wherein the first voltage and the second voltage are opposite in phase, the method comprising the steps of: receiving the first voltage at an input of a first voltage divider circuit of the voltage sense circuit; receiving the second voltage at an input of a second voltage divider circuit of the voltage sense circuit; receiving a reference voltage at a first input of a driver circuit of the voltage sense circuit and a common mode signal from the first voltage divider and the second voltage divider circuit at a second input of the driver circuit; and and an output common mode voltage of the first voltage divider and the second voltage divider circuit is driven by the drive circuit with the reference voltage; wherein the drive circuit further comprises a first resistor and a second resistor coupled in series between a first output and a second output, such that a first end of the first resistor is coupled to the first output, a second end of the first resistor is coupled to a first end of the second resistor, and a second end of the second resistor is coupled to the second output, and wherein a second input of the drive circuit is coupled to the first end of the second resistor.

14. A method of operating a current sense circuit for measuring a load connected to a power amplifier, wherein the load is configured to receive a first voltage at a first terminal and a second voltage at a second terminal, wherein the first voltage and the second voltage are opposite in phase, the method comprising the steps of: receiving a first voltage at a first input, a second voltage at a second input, a third voltage at a third input, and a fourth voltage at a fourth input; receiving a common mode voltage of an output of the current sense circuit at a first input and a second input of a common mode loop circuit, and receiving a reference voltage at a third input of the common mode loop circuit; and generating a control signal at an output of the common mode loop circuit to switch the current sense circuit such that the common mode voltage is equal to the reference voltage; wherein the current sense circuit further comprises a first conversion resistor, a second conversion resistor, a third conversion resistor, and a fourth conversion resistor comprising a first end and a second end, wherein the first ends of the first conversion resistor, the second conversion resistor, the third conversion resistor, and the fourth conversion resistor are coupled to the first input, the second input, the third input, and the fourth input, respectively.

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