Polyphase filter

Abstract

The application discloses a polyphase filter, which comprises resistance-capacitance networks and resistance-inductance networks in series resonance to form multi-stage signal units, and the multi-stage signal units realize intrinsic impedance matching; if one resistance-capacitance network and one resistance-inductance network are arranged, the resistance-capacitance network or the resistance-inductance network is arranged as a first-stage signal unit or a last-stage signal unit; if at least two resistance-capacitance networks and / or resistance-inductance networks are arranged, the resistance-capacitance networks and the resistance-inductance networks are arranged alternately. According to the polyphase filter, the arrangement mode of the resistance-capacitance networks and the resistance-inductance networks in series resonance is adopted, so that the impedance of each stage is respectively capacitive and inductive, intrinsic impedance matching is realized, and the loss of the polyphase filter is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a polyphase filter. Background Technology

[0002] PPF (Polyphase Filter) consists of a resistor-capacitor network and is currently widely used in RF systems requiring quadrature generation and image suppression. Due to the demands for bandwidth and high precision, PPFs often require multiple cascaded stages.

[0003] Figure 1 This is a schematic diagram of a traditional PPF (Power Pulse Filter). The dashed box represents the basic unipolar PPF structure. Based on this basic structure, PPFs can be cascaded in multiple stages, for example... Figure 1 The diagram shows a three-stage structure. Because traditional PPFs are composed of a resistor-capacitor network, both their input and output impedances exhibit significant capacitive reactance. Therefore, when cascaded, impedance mismatch exists between the output of the preceding stage and the input of the following stage, resulting in substantial losses.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a polyphase filter that achieves intrinsic impedance matching and reduces losses.

[0006] To achieve the above objectives, embodiments of the present invention provide a polyphase filter, comprising: a resistor-capacitor network and a resistor-inductor network that resonate in series to form a multi-stage signal unit, wherein the multi-stage signal unit achieves intrinsic impedance matching; if one of each of the resistor-capacitor network and the resistor-inductor network is provided, the resistor-capacitor network or the resistor-inductor network serves as the first-stage signal unit or the last-stage signal unit; if at least two of the resistor-capacitor network and / or the resistor-inductor network are provided, the resistor-capacitor network and the resistor-inductor network are alternately provided to form the multi-stage signal unit.

[0007] In one or more embodiments of the present invention, the resistor-capacitor network includes a plurality of RC units connected in series to form a closed loop, the resistor-inductor network includes a plurality of RL units connected in series to form a closed loop, and the RC units are connected to the corresponding RL units.

[0008] In one or more embodiments of the present invention, the RC unit includes a first resistor and a first capacitor, the first resistor and the first capacitor being connected in series alternately to form a series connection of each RC unit, and the RL unit includes a second resistor and a first inductor, the second resistor and the first inductor being connected in series alternately to form a series connection of each RL unit.

[0009] In one or more embodiments of the present invention, the first resistor and the first capacitor are connected to form a first terminal of an RC unit, the other end of the first resistor forms a second terminal of an RC unit, the other end of the first capacitor forms a third terminal of an RC unit, the second resistor and the first inductor are connected to form a first node of an RL unit, the other end of the second resistor forms a second node of an RL unit, and the other end of the first inductor forms a third node of an RL unit.

[0010] In one or more embodiments of the present invention, if the resistor-capacitor network is used as a first-level signal unit, the resistor-inductor network is used as a next-level signal unit, the first terminal of the RC unit is used as an input terminal, the second terminal of the RC unit is connected to the second node of the RL unit, and the first node of the RL unit is used as an output terminal.

[0011] In one or more embodiments of the present invention, if the resistor-capacitor network is the last stage signal unit, the resistor-inductor network is the previous stage signal unit, the second terminal of the RC unit is the output terminal, the first terminal of the RC unit is connected to the first node of the RL unit, and the second node of the RL unit is the input terminal.

[0012] In one or more embodiments of the present invention, if the resistor-inductor network is used as a first-level signal unit, the resistor-capacitor network is used as a next-level signal unit, the second node of the RL unit is used as an input terminal, the first node of the RL unit is connected to the first endpoint of the RC unit, and the second endpoint of the RC unit is used as an output terminal.

[0013] In one or more embodiments of the present invention, if the resistor-inductor network is the last stage signal unit, the resistor-capacitor network is the previous stage signal unit, the first node of the RL unit is the output terminal, the second node of the RL unit is connected to the second node of the RC unit, and the first terminal of the RC unit is the input terminal.

[0014] In one or more embodiments of the present invention, if the resistor-capacitor network is used as the first-stage signal unit, the first endpoint of a portion of the RC unit is connected to the first total input terminal and at least one of the first endpoints is connected to the first total input terminal through a second inductor, and the first endpoint of another portion of the RC unit is connected to the second total input terminal and at least one of the first endpoints is connected to the second total input terminal through a third inductor.

[0015] In one or more embodiments of the present invention, if the resistor-inductor network is used as the first-stage signal unit, some of the second nodes of the RL units are connected to the first total input terminal and at least one of the second nodes is connected to the first total input terminal through a second capacitor, and other parts of the second nodes of the RL units are connected to the second total input terminal and at least one of the second nodes is connected to the second total input terminal through a third capacitor.

[0016] Compared with the prior art, the multiphase filter according to the embodiments of the present invention, by adopting an arrangement of resistor-capacitor network and resistor-inductor network, makes the impedance of each stage capacitive and inductive respectively, thereby achieving inherent impedance matching and reducing the loss of the multiphase filter. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a polyphase filter in the prior art.

[0018] Figure 2 This is a schematic diagram of the circuit structure of a polyphase filter according to Embodiment 1 of the present invention.

[0019] Figure 3 This is a schematic diagram of the circuit structure of a polyphase filter according to Embodiment 2 of the present invention.

[0020] Figure 4 This is a schematic diagram of the circuit structure of a polyphase filter according to Embodiment 3 of the present invention.

[0021] Figure 5 This is a schematic diagram of the circuit structure of a polyphase filter according to Embodiment 4 of the present invention. Detailed Implementation

[0022] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0023] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0024] Example 1

[0025] like Figure 2As shown, a multiphase filter includes a resistor-capacitor network 10 and a resistor-inductor network 20 that resonate in series to form multi-stage signal units, wherein the multi-stage signal units achieve intrinsic impedance matching. In this embodiment, one resistor-capacitor network 10 and one resistor-inductor network 20 are each provided, with the resistor-capacitor network 10 serving as the first-stage signal unit and the resistor-inductor network 20 serving as the last-stage signal unit, thereby forming two-stage signal units. In other embodiments, the resistor-inductor network 20 also serves as the first-stage signal unit, and the resistor-capacitor network 10 serves as the last-stage signal unit.

[0026] Specifically, the resistor-capacitor network 10 includes multiple RC units 11 connected in series to form a closed loop, and the resistor-inductor network 20 includes multiple RL units 21 connected in series to form a closed loop. Each RC unit 11 is connected to a corresponding RL unit 21. In this embodiment, four RC units 11 and four RL units 21 are provided. In other embodiments, eight or more RC units 11 and eight RL units 21 are provided.

[0027] like Figure 2 As shown, RC unit 11 includes a first resistor R1 and a first capacitor C1. Four RC units 11 have four first resistors R1 and four first capacitors C1. The first resistors R1 and first capacitors C1 are connected in series alternately to form the series connection of each RC unit 11. The first resistor R1 and the first capacitor C1 are connected to form the first terminal a1. The other end of the first resistor R1 forms the second terminal b1, and the other end of the first capacitor C1 forms the third terminal c1. Since the first resistors R1 and first capacitors C1 are connected in series alternately, the second terminal b1 of one RC unit 11 will be connected to the third terminal c1 of an adjacent RC unit 11, and the third terminal c1 will be connected to the second terminal b1 of another adjacent RC unit 11.

[0028] like Figure 2 As shown, each RL unit 21 includes a second resistor R2 and a first inductor L1. Four RL units 21 each have four second resistors R2 and four first inductors L1. The second resistors R2 and first inductors L1 are connected in series alternately to form the series connection of each RL unit 21. The second resistor R2 and the first inductor L1 are connected to form a first node d1. The other end of the second resistor R2 forms a second node e1, and the other end of the first inductor L1 forms a third node f1. Since the second resistor R2 and the first inductor L1 are connected in series alternately, the second node e1 of one RL unit 21 will be connected to the third node f1 of an adjacent RL unit 21, and the third node f1 will be connected to the second node e1 of another adjacent RL unit 21.

[0029] like Figure 2As shown, resistor-capacitor network 10 serves as the first-stage signal unit, resistor-inductor network 20 serves as the next-stage signal unit (equivalent to the last-stage signal unit), the first endpoint a1 of RC unit 11 serves as the input terminal, the second endpoint b1 of RC unit 11 is connected to the second node e1 of RL unit 21, and the first node d1 of RL unit 21 serves as the output terminal.

[0030] like Figure 2 As shown, in the four RC units 11, two adjacent RC units 11 and their corresponding RL units 21 form a group. The two first terminals a1 of one group of RC units 11 respectively receive the first input signal V. I,in+ Second input signal V Q,in+ Both first endpoints a1 are simultaneously connected to the first total input terminal to receive the first total input signal V. IN,+ Furthermore, one of the first endpoints a1 is connected to the first total input terminal through the second inductor L2, and the two first nodes d1 of the corresponding two RL units 21 respectively serve as output terminals to output the first output signal V. I,out+ Second output signal V Q,out+ The two first terminals a1 of another set of RC units 11 respectively receive the third input signal V. I,in- and the fourth input signal V Q,in- Both first terminals a1 are simultaneously connected to the second total input terminal to receive the second total input signal V. IN,- Furthermore, one of the first endpoints a1 is connected to the second total input terminal through the third inductor L3, and the two first nodes d1 of the corresponding two RL units 21 respectively serve as output terminals to output the third output signal V. I,out- and the fourth output signal V Q,out- .

[0031] In this embodiment, the first terminal a1 of the first RC unit 11 is connected to the first total input terminal through the second inductor L2, and the first terminal a1 of the third RC unit 11 is connected to the second total input terminal through the third inductor L3. By adding the second inductor L2 and the third inductor L3, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter and simultaneously achieving input matching and increasing the output image rejection ratio. In other embodiments, if there are eight RC units 11, they can be grouped into groups of four, with one RC unit 11 connected to one inductor in each group, or two RC units 11 each connected to one inductor, or three RC units 11 each connected to one inductor.

[0032] In other embodiments, the resistor-capacitor network 10 serves as the last stage signal unit (equivalent to the next stage signal unit after the first stage signal unit), and the resistor-inductor network 20 serves as the previous stage signal unit (equivalent to the first stage signal unit). The second node e1 of the RL unit 21 serves as the input terminal, the first node d1 of the RL unit 21 is connected to the first endpoint a1 of the RC unit 11, and the second endpoint b1 of the RC unit 11 serves as the output terminal. Furthermore, the second nodes e1 of two adjacent RL units 21 are connected to the first total input terminal to receive the first total input signal V. IN,+ Furthermore, one of the second nodes e1 is connected to the first total input terminal via a second capacitor. The second nodes e1 of the other two adjacent RL units 21 are connected to the second total input terminal to receive the second total input signal V. IN,- Furthermore, one of the second nodes e1 is connected to the second total input terminal via a third capacitor. Specifically, the second node e1 of the second RL unit 21 is connected to the first total input terminal via a second capacitor; the second node e1 of the fourth RL unit 21 is connected to the second total input terminal via a third capacitor. By adding the second and third capacitors, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter, while simultaneously achieving input matching and increasing the output image rejection ratio. In other embodiments, if there are eight RC units 11, they can be grouped into fours, with one RL unit 21 in each group corresponding to a capacitor, or two RL units 21 respectively connected to a capacitor, or three RL units 21 respectively connected to a capacitor.

[0033] Example 2

[0034] like Figure 3 As shown, compared to Embodiment 1, this embodiment adds a resistor-capacitor network, specifically two resistor-capacitor networks: a first resistor-capacitor network 10a and a second resistor-capacitor network 10b. A single resistor-inductor network 20 is also provided. The first resistor-capacitor network 10a serves as the first-stage signal unit, the resistor-inductor network 20 as the intermediate-stage signal unit, and the second resistor-capacitor network 10b as the final-stage signal unit, thus forming a three-stage signal unit. In other embodiments, the resistor-inductor network 20 can also serve as both the first-stage and final-stage signal unit, with the resistor-capacitor network serving as an intermediate-stage signal unit.

[0035] like Figure 3As shown, the first resistor-capacitor network 10a of the first-stage signal unit includes multiple first RC units 10a1, which are connected in series to form a closed loop. The second resistor-capacitor network 10b of the last-stage signal unit includes multiple second RC units 10b1, which are connected in series to form a closed loop. The intermediate-stage resistor-inductor network 20 includes multiple RL units 21, which are connected in series to form a closed loop. In this embodiment, four of each of the first RC units 10a1, second RC units 10b1, and RL units 21 are provided. In other embodiments, eight or more of each of the first RC units 10a1, second RC units 10b1, and RL units 21 are provided.

[0036] like Figure 3 As shown, the first RC unit 10a1 includes a first resistor R1 and a first capacitor C1. Four first RC units 10a1 each have four first resistors R1 and four first capacitors C1. The first resistors R1 and first capacitors C1 are connected in series alternately to form the series connection of each first RC unit 10a1. The first resistor R1 and the first capacitor C1 are connected to form the first terminal a1. The other end of the first resistor R1 forms the second terminal b1, and the other end of the first capacitor C1 forms the third terminal c1. Since the first resistors R1 and first capacitors C1 are connected in series alternately, the second terminal b1 of one first RC unit 10a1 will be connected to the third terminal c1 of an adjacent first RC unit 10a1, and the third terminal c1 will be connected to the second terminal b1 of another adjacent first RC unit 10a1.

[0037] like Figure 3 As shown, each RL unit 21 includes a second resistor R2 and a first inductor L1. Four RL units 21 each have four second resistors R2 and four first inductors L1. The second resistors R2 and first inductors L1 are connected in series alternately to form the series connection of each RL unit 21. The second resistor R2 and the first inductor L1 are connected to form a first node d1. The other end of the second resistor R2 forms a second node e1, and the other end of the first inductor L1 forms a third node f1. Because the second resistor R2 and the first inductor L1 are connected in series alternately, the second node e1 of one RL unit 21 will be connected to the third node f1 of an adjacent RL unit 21, and the third node f1 will be connected to the second node e1 of another adjacent RL unit 21.

[0038] like Figure 3As shown, the second RC unit 10b1 includes a first resistor R3 and a first capacitor C2. Four second RC units 10b1 each have four first resistors R3 and four first capacitors C2. The first resistors R3 and first capacitors C2 are connected in series alternately to form the series connection of each second RC unit 10b1. The first resistor R3 and the first capacitor C2 are connected to form the first terminal a2. The other end of the first resistor R3 forms the second terminal b2, and the other end of the first capacitor C2 forms the third terminal c2. Because the first resistor R3 and the first capacitor C2 are connected in series alternately, the second terminal b2 of one second RC unit 10b1 will be connected to the third terminal c2 of an adjacent second RC unit 10b1, and the third terminal c2 will be connected to the second terminal b2 of another adjacent second RC unit 10b1.

[0039] like Figure 3 As shown, the first resistor-capacitor network 10a serves as the first-stage signal unit, the second resistor-capacitor network 10b serves as the last-stage signal unit, the resistor-inductor network 20 serves as the intermediate-stage signal unit (equivalent to the previous stage signal unit of the last-stage signal unit), the first endpoint a1 of the first RC unit 10a1 serves as the input terminal, the second endpoint b1 of the first RC unit 10a1 is connected to the second node e1 of the RL unit 21, the second node e1 of the RL unit 21 serves as the input terminal of the RL unit 21, the first endpoint a2 of the second RC unit 10b1 is connected to the first node d1 of the RL unit 21, and the second endpoint b2 of the second RC unit 10b1 serves as the output terminal.

[0040] like Figure 3 As shown, in the four first RC units 10a1, two adjacent first RC units 10a1 and their corresponding RL units 21 and second RC units 10b1 form a group. The two first terminals a1 of one group of first RC units 10a1 respectively receive the first input signal V. I,in+ Second input signal V Q,in+ Both first endpoints a1 are simultaneously connected to the first total input terminal to receive the first total input signal V. IN,+ Furthermore, one of the first terminals a1 is connected to the first total input terminal through the second inductor L2, and the two second terminals b2 of the corresponding two second RC units 10b1 respectively serve as output terminals to output the first output signal V. I,out+ Second output signal V Q,out+ The two first terminals a1 of the other set of first RC units 10a1 respectively receive the third input signal V. I,in- and the fourth input signal V Q,in- Both first terminals a1 are simultaneously connected to the second total input terminal to receive the second total input signal V. IN,-Furthermore, one of the first terminals a1 is connected to the second total input terminal through the third inductor L3, and the two second terminals b2 of the corresponding two second RC units 10b1 respectively serve as output terminals to output the third output signal V. I,out- and the fourth output signal V Q,out- .

[0041] In this embodiment, the first terminal a1 of the first first RC unit 10a1 is connected to the first total input terminal through the second inductor L2, and the first terminal a1 of the third first RC unit 10a1 is connected to the second total input terminal through the third inductor L3. By adding the second inductor L2 and the third inductor L3, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter, while simultaneously achieving input matching and increasing the output image rejection ratio. In other embodiments, if there are eight first RC units 10a1, they can be grouped into groups of four, with one first RC unit 10a1 connected to one inductor in each group, or two first RC units 10a1 each connected to one inductor, or three first RC units 10a1 each connected to one inductor.

[0042] In other embodiments, two resistor-inductor networks are provided, serving as the first-stage signal unit and the last-stage signal unit, respectively, and one resistor-capacitor network is provided, serving as the intermediate-stage signal unit (equivalent to the previous stage signal unit of the last-stage signal unit). The second node of the RL unit of the first-stage signal unit serves as the input terminal, the first node of the RL unit is connected to the first endpoint of the RC unit of the intermediate-stage signal unit, the second endpoint of the RC unit of the intermediate-stage signal unit is connected to the second node of the RL unit of the last-stage signal unit, and the first node of the RL unit of the last-stage signal unit serves as the output. Furthermore, the second nodes of two adjacent RL units in the four RL units of the first-stage signal unit are connected to the first total input terminal to receive the first total input signal V. IN,+ Furthermore, one of the second nodes is connected to the first total input terminal via a second capacitor. Additionally, the second nodes of two adjacent RL units are connected to the second total input terminal to receive the second total input signal V. IN,- Furthermore, one of the second nodes is connected to the second total input terminal via a third capacitor. By adding the second and third capacitors, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter, while simultaneously achieving input matching and increasing the output image rejection ratio. Specifically, the second node of the second RL unit is connected to the first total input terminal via the second capacitor, and the second node of the fourth RL unit is connected to the second total input terminal via the third capacitor.

[0043] In other embodiments, if there are eight RL units, they can be grouped into groups of four, with one RL unit in each group connected to a capacitor, or two RL units connected to a capacitor, or three RL units connected to a capacitor.

[0044] Example 3

[0045] like Figure 4 As shown, compared to Embodiment 1, this embodiment adds a resistor-inductor network, meaning there are two resistor-capacitor networks and two resistor-inductor networks: a first resistor-capacitor network 10a and a second resistor-capacitor network 10b, and a first resistor-inductor network 20a and a second resistor-inductor network 20b. The first resistor-capacitor network 10a serves as the first-stage signal unit, the first resistor-inductor network 20a as an intermediate first-stage signal unit, the second resistor-capacitor network 10b as an intermediate second-stage signal unit, and the second resistor-inductor network 20b as the last-stage signal unit. The first resistor-capacitor network 10a serves as the previous-stage signal unit of the first resistor-inductor network 20a, and the second resistor-capacitor network 10b serves as the previous-stage signal unit of the second resistor-inductor network 20b, thus forming a four-stage signal unit. In other embodiments, the resistor-inductor networks can also serve as both the first-stage and intermediate second-stage signal units, and the resistor-capacitor networks can also serve as both the intermediate first-stage and last-stage signal units. In this case, the resistor-inductor network serves as the previous-stage signal unit of the corresponding resistor-capacitor network.

[0046] like Figure 4 As shown, the first resistor-capacitor network 10a of the first-stage signal unit includes multiple first RC units 10a1, which are connected in series to form a closed loop. The second resistor-capacitor network 10b of the intermediate second-stage signal unit includes multiple second RC units 10b1, which are connected in series to form a closed loop. The first resistor-inductor network 20a of the intermediate first stage includes multiple first RL units 20a1, which are connected in series to form a closed loop. The second resistor-inductor network 20b of the last stage includes multiple second RL units 20b1, which are connected in series to form a closed loop. In this embodiment, four of each of the first RC units 10a1, second RC units 10b1, first RL units 20a1, and second RL units 20b1 are provided. In other embodiments, eight or more of each of the first RC units 10a1, second RC units 10b1, first RL units 20a1, and second RL units 20b1 are provided.

[0047] like Figure 4As shown, the first RC unit 10a1 includes a first resistor R1 and a first capacitor C1. Four first RC units 10a1 each have four first resistors R1 and four first capacitors C1. The first resistors R1 and first capacitors C1 are connected in series alternately to form the series connection of each first RC unit 10a1. The first resistor R1 and the first capacitor C1 are connected to form the first terminal a1. The other end of the first resistor R1 forms the second terminal b1, and the other end of the first capacitor C1 forms the third terminal c1. Since the first resistors R1 and first capacitors C1 are connected in series alternately, the second terminal b1 of one first RC unit 10a1 will be connected to the third terminal c1 of an adjacent first RC unit 10a1, and the third terminal c1 will be connected to the second terminal b1 of another adjacent first RC unit 10a1.

[0048] like Figure 4 As shown, the first RL unit 20a1 includes a second resistor R2 and a first inductor L1. Four first RL units 20a1 each have four second resistors R2 and four first inductors L1. The second resistors R2 and first inductors L1 are connected in series alternately to form the series connection of each first RL unit 20a1. The second resistor R2 and the first inductor L1 are connected to form a first node d1. The other end of the second resistor R2 forms a second node e1, and the other end of the first inductor L1 forms a third node f1. Because the second resistor R2 and the first inductor L1 are connected in series alternately, the second node e1 of one first RL unit 20a1 will be connected to the third node f1 of an adjacent RL unit, and the third node f1 will be connected to the second node e1 of another adjacent first RL unit 20a1.

[0049] like Figure 4 As shown, the second RC unit 10b1 includes a first resistor R3 and a first capacitor C2. Four second RC units 10b1 each have four first resistors R3 and four first capacitors C2. The first resistors R3 and first capacitors C2 are connected in series alternately to form the series connection of each second RC unit 10b1. The first resistor R3 and the first capacitor C2 are connected to form the first terminal a2. The other end of the first resistor R3 forms the second terminal b2, and the other end of the first capacitor C2 forms the third terminal c2. Because the first resistor R3 and the first capacitor C2 are connected in series alternately, the second terminal b2 of one second RC unit 10b1 will be connected to the third terminal c2 of an adjacent second RC unit 10b1, and the third terminal c2 will be connected to the second terminal b2 of another adjacent second RC unit 10b1.

[0050] like Figure 4As shown, the second RL unit 20b1 includes a second resistor R4 and a first inductor L2. Four second RL units 20b1 each have four second resistors R4 and four first inductors L2. The second resistors R4 and first inductors L2 are connected in series alternately to form the series connection of each second RL unit 20b1. The second resistor R4 and the first inductor L2 are connected to form a first node d2. The other end of the second resistor R4 forms a second node e2, and the other end of the first inductor L2 forms a third node f2. Since the second resistor R4 and the first inductor L2 are connected in series alternately, the second node e2 of one second RL unit 20b1 will be connected to the third node f2 of an adjacent second RL unit 20b1, and the third node f2 will be connected to the second node e2 of another adjacent second RL unit 20b1.

[0051] like Figure 4 As shown, the second resistor-inductor network 20b serves as the last stage signal unit, the second resistor-capacitor network 10b serves as the intermediate second stage signal unit (equivalent to the previous stage signal unit of the last stage signal unit), the first resistor-inductor network 20a serves as the intermediate first stage signal unit (equivalent to the previous stage signal unit of the intermediate second stage signal unit), and the first resistor-capacitor network 10a serves as the first stage signal unit. The first endpoint a1 of each first RC unit 10a1 serves as the input terminal, the second endpoint b1 of each first RC unit 10a1 is connected to the second node e1 of the corresponding first RL unit 20a1, the first node d1 of each first RL unit 20a1 is connected to the first endpoint a2 of the corresponding second RC unit 10b1, the second endpoint b2 of each second RC unit 10b1 is connected to the second node e2 of the corresponding second RL unit 20b1, and the first node d2 of each second RL unit 20b1 serves as the output terminal.

[0052] like Figure 4 As shown, in the four first RC units 10a1, two adjacent first RC units 10a1 and their corresponding first RL units 20a1, second RC units 10b1, and second RL units 20b1 form a group. The two first terminals a1 of one group of first RC units 10a1 respectively receive the first input signal V. I,in+ Second input signal V Q,in+ Both first endpoints a1 are simultaneously connected to the first total input terminal to receive the first total input signal V. IN,+ Furthermore, one of the first endpoints a1 is connected to the first total input terminal through the second inductor L3, and the two first nodes d2 of the corresponding two second RL units 20b1 respectively serve as output terminals to output the first output signal V. I,out+ Second output signal V Q,out+ The two first terminals a1 of the other set of first RC units 10a1 respectively receive the third input signal V. I,in- and the fourth input signal VQ,in- Both first terminals a1 are simultaneously connected to the second total input terminal to receive the second total input signal V. IN,- Furthermore, one of the first endpoints a1 is connected to the second total input terminal through the third inductor L4, and the two first nodes d2 of the corresponding two second RL units 20b1 respectively serve as output terminals to output the third output signal V. I,out- and the fourth output signal V Q,out- .

[0053] In this embodiment, the first terminal a1 of the first first RC unit 10a1 is connected to the first total input terminal through the second inductor L3; the first terminal a1 of the third first RC unit 10a1 is connected to the second total input terminal through the third inductor L4. By adding the second inductor L3 and the third inductor L4, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter, while simultaneously achieving input matching and increasing the output image rejection ratio.

[0054] In other embodiments, if there are eight first RC units 10a1, they can be grouped into groups of four, with one first RC unit 10a1 in each group connected to an inductor, or two first RC units 10a1 connected to an inductor, or three first RC units 10a1 connected to an inductor.

[0055] Example 4

[0056] like Figure 5 As shown, the difference between this embodiment and embodiment 3 is that the second resistor-capacitor network 10b is the last stage signal unit, the second resistor-inductor network 20b is the intermediate second stage signal unit (equivalent to the previous stage signal unit of the last stage signal unit), the first resistor-capacitor network 10a is the intermediate first stage signal unit (equivalent to the previous stage signal unit of the intermediate second stage signal unit), and the first resistor-inductor network 20a is the first stage signal unit.

[0057] The second node e1 of each first RL unit 20a1 serves as an input terminal, the first node d1 is connected to the first endpoint a1 of the first RC unit 10a1, the second endpoint b1 of the first RC unit 10a1 is connected to the second node e2 of the second RL unit 20b1, the first node d2 of the second RL unit 20b1 is connected to the first endpoint a2 of the first RC unit 10b1, and the second endpoint b2 of the first RC unit 10b1 serves as an output terminal.

[0058] In the first-level signal unit, the second node e1 of two adjacent first RL units 20a1 are connected to the first total input terminal to receive the first total input signal V. IN,+Furthermore, one of the second nodes e1 is connected to the first total input terminal via the second capacitor C3. Additionally, the second nodes e1 of two adjacent first RL units 20a1 are connected to the second total input terminal to receive the second total input signal V. IN,- Furthermore, one of the second nodes e1 is connected to the second total input terminal via the third capacitor C4. In this embodiment, the second node e1 of the second first RL unit 20a1 is connected to the first total input terminal via the second capacitor C3; the second node e1 of the fourth first RL unit 20a1 is connected to the second total input terminal via the third capacitor C4. By adding the second capacitor C3 and the third capacitor C4, the voltage distribution of the input signal is utilized to achieve preliminary orthogonality of the input signal, thereby reducing the loss of the polyphase filter, while simultaneously achieving input matching and increasing the output image rejection ratio. The second capacitor C3 and the third capacitor C4 have an alternating arrangement with the second inductor L3 and the third inductor L4 in Embodiment 3.

[0059] In other embodiments, if there are eight first RL units 20a1, they can be grouped into groups of four, with one first RL unit 20a1 in each group connected to a capacitor, or two first RL units 20a1 connected to a capacitor, or three first RL units 20a1 connected to a capacitor.

[0060] In summary, based on the various embodiments and accompanying figures, it can be seen that the resistor-capacitor networks and resistor-inductor networks are alternately arranged, and their connections follow a predictable pattern. Based on this, the number of resistor-capacitor networks and resistor-inductor networks can be increased or decreased. Furthermore, for ease of description, some units, components, endpoints, nodes, etc., use the same naming convention with different labels; however, the parameters of each component are not specifically limited. In actual operation, the parameters of each component can be adjusted and replaced, ultimately ensuring that intrinsic impedance matching is achieved between the resistor-capacitor networks and resistor-inductor networks.

[0061] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A polyphase filter, characterized in that, include: A series resonance is used to form a resistor-capacitor network and a resistor-inductor network for multi-stage signal units. The multi-stage signal units achieve intrinsic impedance matching. If one resistor-capacitor network and one resistor-inductor network are provided, the resistor-capacitor network or the resistor-inductor network serves as the first-stage signal unit or the last-stage signal unit. If at least two resistor-capacitor networks and / or resistor-inductor networks are provided, the resistor-capacitor networks and resistor-inductor networks are provided alternately. The resistor-capacitor network includes multiple RC units, each RC unit having a first terminal, a second terminal, and a third terminal. The RC units are connected in series and form a closed loop. The resistor-inductor network includes multiple RL units, each RL unit having a first node, a second node, and a third node. The RL units are connected in series and form a closed loop. The RC units are connected to their corresponding RL units. If the resistor-capacitor network is used as the first-stage signal unit, the first endpoint of some of the RC units is connected to the first total input terminal and at least one of the first endpoints is connected to the first total input terminal through a second inductor, and the first endpoint of other RC units is connected to the second total input terminal and at least one of the first endpoints is connected to the second total input terminal through a third inductor; If the resistor-inductor network is used as the first-stage signal unit, some of the second nodes of the RL units are connected to the first total input terminal and at least one of the second nodes is connected to the first total input terminal through a second capacitor, while the second nodes of the other part of the RL units are connected to the second total input terminal and at least one of the second nodes is connected to the second total input terminal through a third capacitor.

2. The polyphase filter as described in claim 1, characterized in that, The RC unit includes a first resistor and a first capacitor, which are connected in series alternately to form a series connection of each RC unit. The RL unit includes a second resistor and a first inductor, which are connected in series alternately to form a series connection of each RL unit.

3. The polyphase filter as described in claim 2, characterized in that, The first resistor and the first capacitor are connected to form the first terminal of the RC unit, the other end of the first resistor forms the second terminal of the RC unit, the other end of the first capacitor forms the third terminal of the RC unit, the second resistor and the first inductor are connected to form the first node of the RL unit, the other end of the second resistor forms the second node of the RL unit, and the other end of the first inductor forms the third node of the RL unit.

4. The polyphase filter as described in claim 3, characterized in that, If the resistor-capacitor network is used as the first-level signal unit, the resistor-inductor network is used as the next-level signal unit, the first terminal of the RC unit is used as the input terminal, the second terminal of the RC unit is connected to the second node of the RL unit, and the first node of the RL unit is used as the output terminal.

5. The polyphase filter as described in claim 3, characterized in that, If the resistor-capacitor network is the last stage signal unit, the resistor-inductor network is the previous stage signal unit, the second terminal of the RC unit is the output terminal, the first terminal of the RC unit is connected to the first node of the RL unit, and the second node of the RL unit is the input terminal.

6. The polyphase filter as described in claim 3, characterized in that, If the resistor-inductor network is used as the first-level signal unit, the resistor-capacitor network is used as the next-level signal unit, the second node of the RL unit is used as the input terminal, the first node of the RL unit is connected to the first terminal of the RC unit, and the second terminal of the RC unit is used as the output terminal.

7. The polyphase filter as described in claim 3, characterized in that, If the resistor-inductor network is the last stage signal unit, the resistor-capacitor network is the previous stage signal unit, the first node of the RL unit is the output terminal, the second node of the RL unit is connected to the second node of the RC unit, and the first terminal of the RC unit is the input terminal.

Images