Dual mode single event double bit upset hardened latch based on dice cells

Abstract

The application discloses a double-working-mode single-event double-bit upset hardened latch based on a DICE unit, comprising an input circuit, a working mode switching circuit, a latch circuit, an input signal D, and an output node Q; the input signal D is electrically connected with a signal input end of the input circuit and a signal input end of the working mode switching circuit; a signal output end of the input circuit is electrically connected with a signal input end of the latch circuit and the output node Q; the signal input end of the latch circuit is further electrically connected with a signal output end of the working mode switching circuit; and a signal output end of the latch circuit is electrically connected with the output node Q. The application utilizes the working mode switching circuit to make two heterogeneous latch circuits realize the latch function in their corresponding working modes, plays the respective advantages of the two heterogeneous latch circuits, and makes the best use of advantages and avoids disadvantages, so that the single-event double-bit upset is completely tolerated. The application has high fault-tolerant performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a dual-mode single-event double-point flip-flop hardened latch based on DICE cells. Background Technology

[0002] Level-sensitive latches are fundamental units in digital circuit systems, typically used to construct edge-triggered master-slave flip-flops. Traditional latches usually use a loop of two inverters to store logic values; however, this structure is susceptible to single-event upsets (SEUs) caused by particle bombardment. High-energy radiated particles deposit charge on one or more sensitive areas of the circuit, causing a change in the node's potential. Ultimately, the latch's logic state changes from "0" to "1" or from "1" to "0," i.e., a single-event upset. Generally, single-event upsets do not cause permanent damage and are therefore also known as soft errors.

[0003] For many memory cells, including latches, there are classic radiation-hardened design techniques such as Triple Modular Redundancy (TMR), but these can only eliminate single-event upsets caused by radiation on a single node. However, as device sizes enter the nanometer scale and operating voltages decrease, single-event events can affect multiple nodes simultaneously through charge-sharing effects. A single-event double-node upset (DNU) occurs when a high-energy radiation particle strikes the memory cell, causing the logic values ​​of two state nodes to flip simultaneously due to charge-sharing effects.

[0004] Single-event double-spot flips (SIFs) pose a serious threat to electronic circuits because they can significantly increase soft error rates (SERs), and traditional radiation-hardened design methods may not be able to completely eliminate their effects. Therefore, for advanced semiconductor circuits using advanced processes, designing advanced circuits that tolerate SIFs is particularly important. Summary of the Invention

[0005] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, one objective of this invention is to propose a dual-mode single-event double-flip hardened latch based on a DICE cell, achieving full tolerance to single-event double-flip functionality.

[0006] According to the present invention, a dual-mode single-event double-point flip-flop hardened latch based on a DICE unit includes an input circuit, a mode switching circuit, a latching circuit, an input signal D, and an output node Q. The input signal D is electrically connected to the input terminal of the input circuit and the input terminal of the mode switching circuit. The output terminal of the input circuit is electrically connected to the input terminal of the latching circuit and the output node Q. The input terminal of the latching circuit is also electrically connected to the output terminal of the mode switching circuit. The output terminal of the latching circuit is electrically connected to the output node Q.

[0007] Preferably, the latching circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a node N2, a node N3, a node N4, a node N5, a node N6, a node N7, a node N8, a node CS, and a node CSF;

[0008] The node Q is connected to the gate of the first PMOS transistor, the gate of the fifth NMOS transistor, the drain of the fifth PMOS transistor, and the drain of the first NMOS transistor, respectively.

[0009] The node N2 is connected to the gate of the fourth PMOS transistor, the gate of the first NMOS transistor, the gate of the second NMOS transistor, the drain of the first PMOS transistor, the drain of the eleventh PMOS transistor, and the drain of the fourth NMOS transistor, respectively.

[0010] The node N3 is connected to the gate of the second PMOS transistor, the gate of the third NMOS transistor, the drain of the third PMOS transistor, and the drain of the eleventh NMOS transistor, respectively.

[0011] The node N4 is connected to the gate of the third PMOS transistor, the gate of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, and the drain of the third NMOS transistor, respectively.

[0012] The node N5 is connected to the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the fourth NMOS transistor, the gate of the eighth NMOS transistor, the drain of the fourth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the sixth NMOS transistor, and the drain of the twelfth NMOS transistor, respectively.

[0013] The node N6 is connected to the gate of the eighth PMOS transistor, the gate of the tenth NMOS transistor, the drain of the tenth PMOS transistor, and the drain of the thirteenth NMOS transistor, respectively.

[0014] The node N7 is connected to the gate of the tenth PMOS transistor, the gate of the ninth NMOS transistor, the drain of the fourteenth PMOS transistor, and the drain of the tenth NMOS transistor, respectively.

[0015] The node N8 is connected to the gate of the fifth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the sixth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the fifth NMOS transistor, and the drain of the fourteenth NMOS transistor, respectively.

[0016] The node CS is connected to the gate of the eleventh PMOS transistor, the gate of the twelfth PMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor, respectively.

[0017] The source of the eleventh PMOS transistor is connected to the drain of the second PMOS transistor, the source of the twelfth PMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the thirteenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to the drain of the ninth NMOS transistor.

[0018] The CSF node is connected to the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the gate of the eleventh NMOS transistor, and the gate of the twelfth NMOS transistor, respectively.

[0019] The source of the thirteenth PMOS transistor is connected to the drain of the eighth PMOS transistor, the source of the fourteenth PMOS transistor is connected to the drain of the ninth PMOS transistor, the source of the eleventh NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the twelfth NMOS transistor is connected to the drain of the seventh NMOS transistor.

[0020] The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth PMOS transistors are all connected to the power supply voltage VDD.

[0021] The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth NMOS transistors are all connected to ground (GND).

[0022] Preferably, the latching circuit includes a cross-interlock unit and a controlled cross-interlock unit.

[0023] Preferably, the cross-interlocking unit comprises six groups, wherein the six groups of cross-interlocking units are respectively the first PMOS transistor and the first NMOS transistor; the third PMOS transistor and the third NMOS transistor; the fourth PMOS transistor and the fourth NMOS transistor; the fifth PMOS transistor and the fifth NMOS transistor; the sixth PMOS transistor and the sixth NMOS transistor; and the tenth PMOS transistor and the tenth NMOS transistor.

[0024] The controlled cross-interlocking unit comprises four groups, namely the second PMOS transistor, the eleventh PMOS transistor, the second NMOS transistor, and the eleventh NMOS transistor; the seventh PMOS transistor, the twelfth PMOS transistor, the seventh NMOS transistor, and the twelfth NMOS transistor; the eighth PMOS transistor, the thirteenth PMOS transistor, the eighth NMOS transistor, and the thirteenth NMOS transistor; and the ninth PMOS transistor, the fourteenth PMOS transistor, the ninth NMOS transistor, and the fourteenth NMOS transistor.

[0025] Preferably, the input circuit includes a first inverter, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate. The signal input terminals of the first, second, third, and fourth transmission gates are connected to the input signal D. The signal output terminals of the first, second, third, and fourth transmission gates are connected to nodes Q, N3, N5, and N7, respectively. The first inverter is externally connected to a clock signal CLK. The clock signal CLK generates a clock signal CLKF through the inverter. The gates of the PMOS transistors in the first, second, third, and fourth transmission gates are all connected to the clock signal CLK. The gates of the NMOS transistors in the first, second, third, and fourth transmission gates are all connected to the clock signal CLKF.

[0026] Preferably, the operating mode switching circuit includes a fifth transmission gate and a second inverter. The signal input terminal of the fifth transmission gate is connected to the input signal D electrical signal, and the signal output terminal of the fifth transmission gate is a control signal CS. The control signal CS generates a control signal CSF through the second inverter. The gate of the PMOS transistor in the fifth transmission gate is connected to the clock signal CLK, and the gate of the NMOS transistor in the fifth transmission gate is connected to the clock signal CLKF.

[0027] The beneficial effects of this invention are: it utilizes the redundancy-feedback principle, its fault-tolerance principle is clear and easy to understand, it can fully tolerate single-event double-point flip-flops, and has strong fault tolerance capabilities, making it a self-recovering double-point hardened latch. Compared with other multi-point hardened latches based on DICE cells, such as single-event triple-flip hardened latches based on DICE cells using the classic triple modal redundancy hardening method, the hardened latch proposed in this invention determines the operating mode of the latch based on the latched logic value, realizing the switching of operating modes and utilizing the advantages of the latch circuits in the two operating modes. Furthermore, it has lower power consumption than existing double-point flip-flop hardened latches, and the fast D-to-Q path gives it an advantage in latency compared to other double-point flip-flop hardened latches, making it a low-overhead, high-speed double-point flip-flop hardened latch. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is a structural block diagram of a dual-mode single-particle dual-point flip-over reinforced latch based on a DICE unit proposed in this invention.

[0030] Figure 2 The present invention proposes Figure 1 The circuit schematic of the input circuit.

[0031] Figure 3 The present invention proposes Figure 1 The circuit diagram of the working mode switching circuit.

[0032] Figure 4 The present invention proposes Figure 1 The circuit diagram of the latch circuit.

[0033] Figure 5 The equivalent circuit diagram of the 0-mode latch circuit when CS=0 proposed in this invention is shown.

[0034] Figure 6 The equivalent circuit diagram of the 1-mode latch circuit when CS=1 proposed in this invention is shown.

[0035] Figure 7 The waveform diagrams for the proposed invention, which tolerate single-point and double-point flipping, are shown below.

[0036] In the diagram: 101 - Input circuit, 102 - Operating mode switching circuit, 103 - Latch circuit, 201 - First inverter, 202 - First transmission gate, 203 - Second transmission gate, 204 - Third transmission gate, 205 - Fourth transmission gate, 301 - Fifth transmission gate, 302 - Second inverter, 401 - First PMOS transistor, 402 - Second PMOS transistor, 403 - Third PMOS transistor, 404 - Fourth PMOS transistor, 405 - Fifth PMOS transistor, 406 - Sixth PMOS transistor, 407 - Seventh PMOS transistor, 408 - Eighth PMOS transistor, 409 - Ninth PMOS transistor, 410 - Tenth PMOS transistor. 411 - First NMOS transistor, 412 - Second NMOS transistor, 413 - Third NMOS transistor, 414 - Fourth NMOS transistor, 415 - Fifth NMOS transistor, 416 - Sixth NMOS transistor, 417 - Seventh NMOS transistor, 418 - Eighth NMOS transistor, 419 - Ninth NMOS transistor, 420 - Tenth NMOS transistor, 421 - Eleventh PMOS transistor, 422 - Twelfth PMOS transistor, 423 - Thirteenth PMOS transistor, 424 - Fourteenth PMOS transistor, 425 - Eleventh NMOS transistor, 426 - Twelfth NMOS transistor, 427 - Thirteenth NMOS transistor, 428 - Fourteenth NMOS transistor. Detailed Implementation

[0037] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0038] Reference Figure 1A dual-mode single-event dual-point flip-flop hardened latch based on a DICE cell is disclosed, comprising an input circuit 101, a mode switching circuit 102, and a latch circuit 103. The latch circuit 103 is further divided into a 0-mode latch circuit and a 1-mode latch circuit according to different operating modes. The output signal Q of the latch circuit 103 serves as the output signal of the dual-point flip-flop hardened latch. When the clock signal CLK=0, the latch is in the transparent period. The input circuit transmits the external input signal D to the output node Q, and also to the input nodes of the mode switching circuit 102 and the latch circuit 103, thereby biasing the internal nodes of the mode switching circuit 102 and the latch circuit 103. When the clock signal CLK=1, the latch is in latching mode. The control signal CS output by the operating mode switching circuit 102 remains in its previous state, i.e., it has the same logic value as the output signal Q. When Q=0, CS=0, and the latch circuit 103 is controlled to operate in mode 0, implementing the latching function. When Q=1, CS=1, and the latch circuit 103 is controlled to operate in mode 1, implementing the latching function. When a high-energy particle impacts an internal node of the latch, causing a single-particle flip, the output Q can always be restored to the correct logic value because the mode 0 latch circuit and the mode 1 latch circuit have the ability to completely tolerate double-point flips in their respective operating modes.

[0039] The input circuit 101 consists of one inverter and four transmission gates; the operating mode switching circuit 101 consists of one transmission gate cascaded with one inverter; the latch circuit 103 is composed of a right-angled structure consisting of one DICE unit and two controlled DICE units. The DICE unit is constructed from four cross-interlocked units, each consisting of one PMOS transistor and one NMOS transistor. The controlled DICE unit replaces a set of opposite cross-interlocked units of the DICE unit with controlled cross-interlocked units, each consisting of two PMOS transistors and two NMOS transistors.

[0040] like Figure 2As shown, the input circuit 101 includes a first inverter 201, a first transmission gate 202, a second transmission gate 203, a third transmission gate 204, and a fourth transmission gate 205. The signal input terminals of the first transmission gate 202, the second transmission gate 203, the third transmission gate 204, and the fourth transmission gate 205 are connected to the input signal D. The signal output terminals of the first transmission gate 202, the second transmission gate 203, the third transmission gate 204, and the fourth transmission gate 205 are respectively connected to nodes Q, N3, and N5. Node N7 is connected. The first inverter 201 is externally connected to a clock signal CLK. The clock signal CLK generates a clock signal CLKF through the inverter (201). The gates of the PMOS transistors in the first transmission gate 202, the second transmission gate 203, the third transmission gate 204, and the fourth transmission gate 205 are all connected to the clock signal CLK. The gates of the NMOS transistors in the first transmission gate 202, the second transmission gate 203, the third transmission gate 204, and the fourth transmission gate 205 are all connected to the clock signal CLKF.

[0041] like Figure 3 As shown, the working mode switching circuit 102 includes a fifth transmission gate 301 and a second inverter 302. The signal input terminal of the fifth transmission gate 301 is connected to the input signal D electrical signal, and the signal output terminal of the fifth transmission gate 301 is the control signal CS. The control signal CS generates a control signal CSF through the second inverter 302. The gate of the PMOS transistor in the fifth transmission gate 301 is connected to the clock signal CLK, and the gate of the NMOS transistor in the fifth transmission gate 301 is connected to the clock signal CLKF.

[0042] like Figure 4 As shown, the latch circuit 103 includes a first PMOS transistor 401, a second PMOS transistor 402, a third PMOS transistor 403, a fourth PMOS transistor 404, a fifth PMOS transistor 405, a sixth PMOS transistor 406, a seventh PMOS transistor 407, an eighth PMOS transistor 408, a ninth PMOS transistor 409, a tenth PMOS transistor 410, an eleventh PMOS transistor 421, a twelfth PMOS transistor 422, a thirteenth PMOS transistor 423, a fourteenth PMOS transistor 424, a first NMOS transistor 411, and a second NMOS transistor 405. NMOS transistors 412, 413, 414, 415, 416, 417, 418, 419, 420, 425, 426, 427, 428, 428, N2, N3, N4, N5, N6, N7, N8, CS, and CSF;

[0043] Node Q is connected to the gate of the first PMOS transistor 401, the gate of the fifth NMOS transistor 415, the drain of the fifth PMOS transistor 405, and the drain of the first NMOS transistor 411, respectively.

[0044] Node N2 is connected to the gate of the fourth PMOS transistor 404, the gate of the first NMOS transistor 411, the gate of the second NMOS transistor 412, the drain of the first PMOS transistor 401, the drain of the eleventh PMOS transistor 421, and the drain of the fourth NMOS transistor 414, respectively.

[0045] Node N3 is connected to the gate of the second PMOS transistor 402, the gate of the third NMOS transistor 413, the drain of the third PMOS transistor 403, and the drain of the eleventh NMOS transistor 425, respectively.

[0046] Node N4 is connected to the gate of the third PMOS transistor 403, the gate of the seventh NMOS transistor 417, the drain of the twelfth PMOS transistor 422, and the drain of the third NMOS transistor 413, respectively.

[0047] Node N5 is connected to the gate of the sixth PMOS transistor 406, the gate of the seventh PMOS transistor 407, the gate of the fourth NMOS transistor 414, the gate of the eighth NMOS transistor 418, the drain of the fourth PMOS transistor 404, the drain of the thirteenth PMOS transistor 423, the drain of the sixth NMOS transistor 416, and the drain of the twelfth NMOS transistor 426, respectively.

[0048] Node N6 is connected to the gate of the eighth PMOS transistor 408, the gate of the tenth NMOS transistor 420, the drain of the tenth PMOS transistor 410, and the drain of the thirteenth NMOS transistor 427, respectively.

[0049] Node N7 is connected to the gate of the tenth PMOS transistor 410, the gate of the ninth NMOS transistor 419, the drain of the fourteenth PMOS transistor 424, and the drain of the tenth NMOS transistor 420, respectively.

[0050] Node N8 is connected to the gate of the fifth PMOS transistor 405, the gate of the ninth PMOS transistor 409, the gate of the sixth NMOS transistor 416, the drain of the sixth PMOS transistor 406, the drain of the fifth NMOS transistor 415, and the drain of the fourteenth NMOS transistor 428, respectively.

[0051] Node CS is connected to the gate of the eleventh PMOS transistor 421, the gate of the twelfth PMOS transistor 422, the gate of the thirteenth NMOS transistor 427, and the gate of the fourteenth NMOS transistor 428, respectively.

[0052] The source of the eleventh PMOS transistor 421 is connected to the drain of the second PMOS transistor 402; the source of the twelfth PMOS transistor 422 is connected to the drain of the seventh PMOS transistor 407; the source of the thirteenth NMOS transistor 427 is connected to the drain of the eighth NMOS transistor 418; and the source of the fourteenth NMOS transistor 428 is connected to the drain of the ninth NMOS transistor 419.

[0053] Node CSF is connected to the gate of the thirteenth PMOS transistor 423, the gate of the fourteenth PMOS transistor 424, the gate of the eleventh NMOS transistor 425, and the gate of the twelfth NMOS transistor 426, respectively.

[0054] The source of the thirteenth PMOS transistor 423 is connected to the drain of the eighth PMOS transistor 408; the source of the fourteenth PMOS transistor 424 is connected to the drain of the ninth PMOS transistor 409; the source of the eleventh NMOS transistor 425 is connected to the drain of the second NMOS transistor 412; and the source of the twelfth NMOS transistor 426 is connected to the drain of the seventh NMOS transistor 417.

[0055] The sources of the first PMOS transistor 401, the second PMOS transistor 402, the third PMOS transistor 403, the fourth PMOS transistor 404, the fifth PMOS transistor 405, the sixth PMOS transistor 406, the seventh PMOS transistor 407, the eighth PMOS transistor 408, the ninth PMOS transistor 409, and the tenth PMOS transistor 410 are all connected to the power supply voltage VDD.

[0056] The sources of the first NMOS transistor 411, the second NMOS transistor 412, the third NMOS transistor 413, the fourth NMOS transistor 414, the fifth NMOS transistor 415, the sixth NMOS transistor 416, the seventh NMOS transistor 417, the eighth NMOS transistor 418, the ninth NMOS transistor 419, and the tenth NMOS transistor 420 are all connected to ground GND.

[0057] Figure 5 for Figure 1 The schematic diagram of the 0-mode latch circuit is also... Figure 4 The equivalent circuit diagram of the latch circuit in 0 operating mode. Figure 4In the latch, when CS=0 and CSF=1, the eleventh PMOS transistor 421, the twelfth PMOS transistor 422, the eleventh NMOS transistor 425, and the twelfth NMOS transistor 426 are turned on. The two controlled cross-interlock units containing these transistors can be simplified to two cross-interlock units. The thirteenth PMOS transistor 423, the fourteenth PMOS transistor 424, the thirteenth NMOS transistor 427, and the fourteenth NMOS transistor 428 are turned off. At this time, the logic value changes of nodes N6 and N7 cannot affect nodes N5 and N8. Therefore, the logic value of node Q is independent of nodes N6 and N7. In this case, the latching function is implemented by the 0-mode latch circuit, so nodes N6 and N7, as well as the two controlled cross-interlock units and one cross-interlock unit connected to them, can be simplified. After the above simplification, Figure 4 The schematic diagram of the latch circuit shown is simplified to... Figure 5The diagram shows the structural principle of the 0-mode latch circuit. The 0-mode latch circuit consists of seven cross-interlocking units. These seven units are composed of the first PMOS transistor 401, the first NMOS transistor 411, the second PMOS transistor 402, the second NMOS transistor 412, the third PMOS transistor 403, the third NMOS transistor 413, the fourth PMOS transistor 404, the fourth NMOS transistor 414, the fifth PMOS transistor 405, the fifth NMOS transistor 415, the sixth PMOS transistor 406, the sixth NMOS transistor 416, and the seventh PMOS transistor 407, the seventh NMOS transistor 417. The input circuit transmits the input signal D to nodes Q, N3, and N5. Node Q is also the output node of the 0-mode latch circuit. Node Q is connected to the gates of the first PMOS transistor 401 and the fifth NMOS transistor 415, and the drains of the fifth PMOS transistor 405 and the first NMOS transistor 411, respectively; Node N2 is connected to the gates of the fourth PMOS transistor 404, the first NMOS transistor 411 and the second NMOS transistor 412, and the drains of the first PMOS transistor 401, the second PMOS transistor 402 and the fourth NMOS transistor 414, respectively; Node N3 is connected to the gates of the second PMOS transistor 402 and the third NMOS transistor 413, and the drains of the third PMOS transistor 403 and the second NMOS transistor 412, respectively. Node N4 is connected to the gates of the third PMOS transistor 403 and the seventh NMOS transistor 417, and the drains of the seventh PMOS transistor 407 and the third NMOS transistor 413, respectively. Node N5 is connected to the gates of the sixth PMOS transistor 406, the seventh PMOS transistor 407, and the fourth NMOS transistor 414, and the drains of the fourth PMOS transistor 404, the sixth NMOS transistor 416, and the seventh NMOS transistor 417, respectively. Node N8 is connected to the gates of the fifth PMOS transistor 405 and the sixth NMOS transistor 416, and the drains of the sixth PMOS transistor 406 and the fifth NMOS transistor 415, respectively. The sources of the first PMOS transistor 401, the second PMOS transistor 402, the third PMOS transistor 403, the fourth PMOS transistor 404, the fifth PMOS transistor 405, the sixth PMOS transistor 406, and the seventh PMOS transistor 407 are all connected to the power supply voltage VDD. The sources of the first NMOS transistor 411, the second NMOS transistor 412, the third NMOS transistor 413, the fourth NMOS transistor 414, the fifth NMOS transistor 415, the sixth NMOS transistor 416, and the seventh NMOS transistor 41 are all connected to ground (GND).

[0058] Figure 6 for Figure 1 The schematic diagram of the 1-mode latch circuit is also... Figure 4 The equivalent circuit diagram of the latch circuit in operating mode 1. Figure 4In the latch, when CS=1 and CSF=0, the thirteenth PMOS transistor 423, the fourteenth PMOS transistor 424, the thirteenth NMOS transistor 427, and the fourteenth NMOS transistor 428 are turned on. The two controlled cross-interlock units containing these transistors can be simplified to two cross-interlock units. The eleventh PMOS transistor 421, the twelfth PMOS transistor 422, the eleventh NMOS transistor 425, and the twelfth NMOS transistor 426 are turned off. At this time, the logic value changes of nodes N3 and N4 cannot affect nodes N2 and N5. Therefore, the logic value of node Q is independent of nodes N3 and N4. In this case, the latching function is implemented by a 1-mode latch circuit, so nodes N3 and N4, as well as the two controlled cross-interlock units and one cross-interlock unit connected to them, can be simplified. After the above simplification, Figure 4 The schematic diagram of the latch circuit shown is simplified to... Figure 6The diagram shows the structural principle of a mode-1 latch circuit. The mode-1 latch circuit consists of seven cross-interlocking units. These seven cross-interlocking units are respectively composed of the first PMOS transistor 401, the first NMOS transistor 411, the fourth PMOS transistor 404, the fourth NMOS transistor 414, the fifth PMOS transistor 405, the fifth NMOS transistor 415, the sixth PMOS transistor 406, the sixth NMOS transistor 416, the eighth PMOS transistor 408, the eighth NMOS transistor 418, the ninth PMOS transistor 409, the ninth NMOS transistor 419, and the tenth PMOS transistor 410 and the tenth NMOS transistor 420. The input circuit transmits the input signal D to nodes Q, N5, and N7. Node Q is also the output node of the mode-1 latch circuit. Node Q is connected to the gates of the first PMOS transistor 401 and the fifth NMOS transistor 415, and the drains of the fifth PMOS transistor 405 and the first NMOS transistor 411, respectively; Node N2 is connected to the gates of the fourth PMOS transistor 404 and the first NMOS transistor 411, and the drains of the first PMOS transistor 401 and the fourth NMOS transistor 414, respectively; Node N5 is connected to the gates of the sixth PMOS transistor 406, the fourth NMOS transistor 414 and the eighth NMOS transistor 418, and the drains of the fourth PMOS transistor 404, the eighth PMOS transistor 408 and the sixth NMOS transistor 416, respectively. Node N6 is connected to the gates of the eighth PMOS transistor 408 and the tenth NMOS transistor 420, and the drains of the tenth PMOS transistor 410 and the eighth NMOS transistor 418, respectively. Node N7 is connected to the gates of the tenth PMOS transistor 410 and the ninth NMOS transistor 419, and the drains of the ninth PMOS transistor 409 and the NMOS transistor (420), respectively. Node N8 is connected to the gates of the fifth PMOS transistor 405, the ninth PMOS transistor 409 and the sixth NMOS transistor 416, and the drains of the sixth PMOS transistor 406, the ninth NMOS transistor 419 and the fifth NMOS transistor 415, respectively. The sources of the first PMOS transistor 401, the fourth PMOS transistor 404, the fifth PMOS transistor 405, the sixth PMOS transistor 406, the eighth PMOS transistor 408, the ninth PMOS transistor 409 and the tenth PMOS transistor 410 are all connected to the power supply voltage VDD. The sources of the first NMOS transistor 411, the fourth NMOS transistor 414, the fifth NMOS transistor 415, the sixth NMOS transistor 416, the eighth NMOS transistor 418, the ninth NMOS transistor 419, and the tenth NMOS transistor 420 are all connected to ground (GND).

[0059] The following analysis examines the invention's resistance to single-point and double-point flipping:

[0060] When the clock signal CLK=0, the latch is in the transparent period. The input circuit transmits the external input signal D to the output node Q, and also to the input nodes of the operating mode control circuit and the latch circuit, thus biasing the internal nodes of the operating mode control circuit and the latch circuit. When the clock signal CLK=1, the latch is in the latching period. The control signal CS output by the operating mode control circuit remains in the previous state, that is, it has the same logic value as the output signal Q.

[0061] When Q=0, CS=0, CSF=1, the eleventh PMOS transistor 421, the twelfth PMOS transistor 422, the eleventh NMOS transistor 425, and the twelfth NMOS transistor 426 are turned on; the thirteenth PMOS transistor 423, the fourteenth PMOS transistor 424, the thirteenth NMOS transistor 427, and the fourteenth NMOS transistor 428 are turned off. As mentioned earlier, the latching function is implemented by the 0-mode latch circuit at this time. In the 0-mode operating mode, the internal nodes of the 0-mode latch circuit are Q=N3=N5=0, N2=N4=N8=1. (1) If any one of the six internal nodes experiences a logic value flip due to a high-energy particle impact, the fault can only propagate longitudinally within the flipped node and cannot propagate laterally. Four internal nodes will still maintain the correct logic value. After the fault pulse disappears, the two erroneous nodes will recover the correct logic value through the lateral cross-interlock unit connected to the correct node. (2) If any two internal nodes experience a logic value flip due to a high-energy particle impact, at least two nodes will maintain the correct logic value because in mode 0, the fault can only propagate longitudinally and cannot propagate laterally. After the fault pulse disappears, the two erroneous nodes will recover the correct logic value through the lateral cross-interlock unit connected to the correct node. The two erroneous nodes that have recovered the correct logic value will continue to recover the logic values ​​of the remaining erroneous nodes through the lateral cross-interlock units connected to the remaining erroneous nodes.

[0062] When Q=1, CS=1, CSF=0, the thirteenth PMOS transistor 423, the fourteenth PMOS transistor 424, the thirteenth NMOS transistor 427, and the fourteenth NMOS transistor 428 are turned on; the eleventh PMOS transistor 421, the twelfth PMOS transistor 422, the eleventh NMOS transistor 425, and the twelfth NMOS transistor 426 are turned off. As mentioned earlier, the latching function is implemented by the 1-mode latch circuit at this time. In the 1-mode operating mode, the internal nodes of the 1-mode latch circuit are Q=N5=N7=1, N2=N6=N8=0. (3) If any one of the six internal nodes experiences a logic value flip due to a particle impact, the fault can only propagate laterally within the flipped node and cannot propagate longitudinally. Four internal nodes will still maintain the correct logic value. After the fault pulse disappears, the two erroneous nodes will restore the correct logic value through the longitudinal cross-interlock unit connected to the correct node. (4) If any two of the six internal nodes experience a logic value flip due to a high-energy particle impact, at least two nodes will maintain the correct logic value because in working mode 1, the fault can only propagate laterally and cannot propagate longitudinally. After the fault pulse disappears, the two erroneous nodes will restore the correct logic value through the longitudinal cross-interlock unit connected to the correct node. After restoring the correct logic value, the two erroneous nodes will continue to restore the logic values ​​of the remaining erroneous nodes through the longitudinal cross-interlock unit connected to the remaining erroneous nodes.

[0063] If a single-point flip occurs at the CS or CSF node, it will change the operating mode of the hardened latch, but the logic value of the internal nodes of the latch circuit will not change, so the output signal Q of the hardened latch will not change. If one of the two-point flips occurs at the CS or CSF node, it will also change the operating mode of the hardened latch. However, regardless of whether the latching function is implemented by a 0-mode latch circuit or a 1-mode latch circuit, as analyzed above, they are completely immune to single-point flips. In summary, the hardened latch proposed in this invention can completely tolerate two-point flips.

[0064] Figure 7 This diagram illustrates the operating waveforms of the present invention under different conditions, tolerating single-point and double-point flip-flops. Simulations were performed in the HSPICE simulation software using a 16nm PTM process model at 25°C, with a power supply voltage VDD of 0.7V. From top to bottom, the waveforms represent the clock signal CLK, input signal D, control signal CSF, internal nodes N3, N5, N6, N7, and N8, and the circuit output signal Q. The fault injection model uses a double exponential current source.

[0065] First, we analyze the simulation results of tolerating single-point flipping under different conditions.

[0066] At 2ns, the clock signal CLK is 1, and the circuit enters the latching period. The logic value of the input signal D at the previous moment is 0, so the internal nodes N3, N5, N7, control signal CS, and circuit output signal Q are all 0; the internal nodes N2, N4, N6, N8, and control signal CSF are all 1, and the latching circuit is in the 0 working mode. The waveform diagram shown is consistent with the expected working state of the hardened latch proposed in this invention.

[0067] At 2.5ns, the circuit is still in the latching period. A positive fault pulse is injected into the internal node N3. Because the latching circuit is operating in 0 mode, the fault can only propagate vertically to the internal node N4 and cannot affect the output node Q. After the fault pulse disappears, nodes N3 and N4 are restored through nodes N2 and N5, which maintain the correct logic values, respectively.

[0068] At 4ns, the clock signal CLK is 1, and the circuit enters the latching period, latching the logic value of the input signal D from the previous moment as 1. Therefore, the internal nodes N3, N5, and N7, the control signal CS, and the circuit output signal Q are all 1; the internal nodes N2, N4, N6, and N8, and the control signal CSF are all 0, and the latching circuit is in 1-mode operation. At 4.5ns, a negative fault pulse is injected into the internal node N7. The fault can only propagate laterally to the internal node N6 and cannot affect the output node Q. After the fault pulse disappears, nodes N6 and N7 recover through nodes N5 and N8, respectively, which maintain the correct logic values.

[0069] At 6ns, the clock signal CLK is 1, the circuit enters the latching period, the latched logic value is 0, that is, the output signal Q is 0, and the latching circuit is in 0 operating mode. At 6.5ns, a negative fault pulse is injected into the control signal CSF, the operating mode of the latching circuit switches, but the logic value of the internal nodes is not affected, so the output node Q still maintains the correct logic value.

[0070] Then, the simulation results for tolerating double-point flipping under different conditions are analyzed.

[0071] At 8ns, the clock signal CLK is 1, and the circuit enters the latching period. The latched logic value is 0, meaning the output signal Q is 0, and the latch circuit is in 0 operating mode. At 8.5ns, a positive fault pulse and a negative fault pulse are injected into internal nodes N3 and N8, respectively. Because the latch circuit is operating in 0 operating mode, the fault can only propagate vertically to internal node N4 and the output signal Q. After the fault pulse disappears, node N3 and the output signal Q are restored through node N2, which maintains the correct logic value, and nodes N8 and N4 are restored through node N5, which also maintains the correct logic value. The simulation waveform shows that the output signal Q only produces a small glitch at 8.5ns.

[0072] At 10ns, the clock signal CLK is 1, and the circuit enters the latching period. The latched logic value is 1, meaning the output signal Q is 1, and the latch circuit is in operating mode 1. At 10.5ns, a negative fault pulse and a positive fault pulse are injected into internal nodes N5 and N6, respectively. Because the latch circuit is operating in operating mode 1, the fault can only propagate vertically to internal nodes N8 and N7. After the fault pulses disappear, nodes N5 and N8 recover through internal node N2, which maintains the correct logic value, and the output signal Q, respectively. Then, nodes N6 and N7 recover through nodes N5 and N8, which have recovered their correct logic values, respectively.

[0073] At 16ns, the clock signal CLK is 1, and the circuit enters the latching period. The latched logic value is 1, meaning the output signal Q is 1, and the latch circuit is in mode 1. At 16.5ns, a positive fault pulse and a negative fault pulse are injected into the control signal CSF and the output signal Q, respectively. The change in the control signal CSF causes the operating mode of the latch circuit to switch. However, as analyzed earlier, regardless of whether the latching function is implemented by a mode 0 latch circuit or a mode 1 latch circuit, they are completely immune to single-point flips. Therefore, the output signal Q only experiences a glitch and quickly recovers to the correct logic value.

[0074] Based on the above analysis, it can be seen that the dual-point reinforced latch proposed in this invention can fully tolerate dual-point flipping.

[0075] The dual-mode single-event double-flip hardened latch based on DICE cells proposed in this invention employs the redundancy-feedback principle, with a clear and easy-to-understand fault-tolerance principle. It can fully tolerate single-event double-flip, exhibiting strong fault tolerance and is a self-recovering dual-point hardened latch. Compared to other multi-point hardened latches based on DICE cells, such as the single-event triple-flip hardened latch based on DICE cells using the classic triple modulo redundancy hardening method, the hardened latch proposed in this invention determines the latch's operating mode based on the latched logic value, achieving mode switching and utilizing the advantages of the latch circuits in both operating modes. Furthermore, it has lower power consumption than existing dual-point flip hardened latches, and the fast D-to-Q path provides a delay advantage compared to other dual-point flip hardened latches, making it a low-overhead, high-speed dual-point flip hardened latch.

[0076] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A dual-mode single-event two-point flip-flop hardened latch based on a DICE unit, characterized in that: It includes an input circuit, a working mode switching circuit, a latch circuit, an input signal D, and an output node Q. The input signal D is electrically connected to the signal input terminal of the input circuit and the signal input terminal of the working mode switching circuit. The signal output terminal of the input circuit is electrically connected to the signal input terminal of the latch circuit and the output node Q. The signal input terminal of the latch circuit is also electrically connected to the signal output terminal of the working mode switching circuit. The signal output terminal of the latch circuit is electrically connected to the output node Q. The input circuit includes a first inverter, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate. The signal input terminals of the first, second, third, and fourth transmission gates are connected to the input signal D. The signal output terminals of the first, second, third, and fourth transmission gates are connected to nodes Q, N3, N5, and N7, respectively. The first inverter is externally connected to a clock signal CLK. The clock signal CLK generates a clock signal CLKF through the first inverter. The gates of the PMOS transistors in the first, second, third, and fourth transmission gates are all connected to the clock signal CLK. The gates of the NMOS transistors in the first, second, third, and fourth transmission gates are all connected to the clock signal CLKF. The working mode switching circuit includes a fifth transmission gate and a second inverter. The signal input terminal of the fifth transmission gate is connected to the input signal D electrical signal, and the signal output terminal of the fifth transmission gate is a control signal CS. The control signal CS generates a control signal CSF through the second inverter. The gate of the PMOS transistor in the fifth transmission gate is connected to the clock signal CLK, and the gate of the NMOS transistor in the fifth transmission gate is connected to the clock signal CLKF. The latching circuit consists of a right-angled structure composed of one DICE unit and two controlled DICE units. The controlled DICE unit is formed by replacing the cross-interlocking units on opposite sides of the DICE unit with controlled cross-interlocking units. Each controlled cross-interlocking unit consists of two PMOS transistors and two NMOS transistors.

2. The dual-mode single-event two-point flip-flop hardened latch based on a DICE unit according to claim 1, characterized in that: The latching circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a node N2, a node N3, a node N4, a node N5, a node N6, a node N7, a node N8, a node CS, and a node CSF; The node Q is connected to the gate of the first PMOS transistor, the gate of the fifth NMOS transistor, the drain of the fifth PMOS transistor, and the drain of the first NMOS transistor, respectively. The node N2 is connected to the gate of the fourth PMOS transistor, the gate of the first NMOS transistor, the gate of the second NMOS transistor, the drain of the first PMOS transistor, the drain of the eleventh PMOS transistor, and the drain of the fourth NMOS transistor, respectively. The node N3 is connected to the gate of the second PMOS transistor, the gate of the third NMOS transistor, the drain of the third PMOS transistor, and the drain of the eleventh NMOS transistor, respectively. The node N4 is connected to the gate of the third PMOS transistor, the gate of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, and the drain of the third NMOS transistor, respectively. The node N5 is connected to the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the fourth NMOS transistor, the gate of the eighth NMOS transistor, the drain of the fourth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the sixth NMOS transistor, and the drain of the twelfth NMOS transistor, respectively. The node N6 is connected to the gate of the eighth PMOS transistor, the gate of the tenth NMOS transistor, the drain of the tenth PMOS transistor, and the drain of the thirteenth NMOS transistor, respectively. The node N7 is connected to the gate of the tenth PMOS transistor, the gate of the ninth NMOS transistor, the drain of the fourteenth PMOS transistor, and the drain of the tenth NMOS transistor, respectively. The node N8 is connected to the gate of the fifth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the sixth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the fifth NMOS transistor, and the drain of the fourteenth NMOS transistor, respectively. The node CS is connected to the gate of the eleventh PMOS transistor, the gate of the twelfth PMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor, respectively. The source of the eleventh PMOS transistor is connected to the drain of the second PMOS transistor, the source of the twelfth PMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the thirteenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to the drain of the ninth NMOS transistor. The CSF node is connected to the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the gate of the eleventh NMOS transistor, and the gate of the twelfth NMOS transistor, respectively. The source of the thirteenth PMOS transistor is connected to the drain of the eighth PMOS transistor, the source of the fourteenth PMOS transistor is connected to the drain of the ninth PMOS transistor, the source of the eleventh NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the twelfth NMOS transistor is connected to the drain of the seventh NMOS transistor. The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth PMOS transistors are all connected to the power supply voltage VDD. The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth NMOS transistors are all connected to ground (GND).

3. A dual-mode single-event two-point flip-flop hardened latch based on a DICE unit according to claim 2, characterized in that: The latching circuit includes a cross-interlock unit and a controlled cross-interlock unit.

4. A dual-mode single-event two-point flip-flop hardened latch based on a DICE unit according to claim 3, characterized in that: The cross-interlocking unit comprises six groups, which are respectively the first PMOS transistor and the first NMOS transistor; the third PMOS transistor and the third NMOS transistor; the fourth PMOS transistor and the fourth NMOS transistor; the fifth PMOS transistor and the fifth NMOS transistor; the sixth PMOS transistor and the sixth NMOS transistor; and the tenth PMOS transistor and the tenth NMOS transistor. The controlled cross-interlocking unit comprises four groups, namely the second PMOS transistor, the eleventh PMOS transistor, the second NMOS transistor, and the eleventh NMOS transistor; the seventh PMOS transistor, the twelfth PMOS transistor, the seventh NMOS transistor, and the twelfth NMOS transistor; the eighth PMOS transistor, the thirteenth PMOS transistor, the eighth NMOS transistor, and the thirteenth NMOS transistor; and the ninth PMOS transistor, the fourteenth PMOS transistor, the ninth NMOS transistor, and the fourteenth NMOS transistor.

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