Variable refresh rate control using PWM aligned frame period

Abstract

PWM frame rate misalignment is mitigated by implementing a discrete variable refresh rate (VRR) scheme. The target frame rate is limited to frame rates selected only from those frame rates that facilitate alignment of each frame period with a specified edge of a PWM cycle of a brightness control signal for a display panel. This alignment causes each frame period at the selected frame rate to start at the same point in the corresponding PWM cycle and end at the same point in the corresponding PWM cycle to help ensure a constant effective duty cycle across each consecutive frame period, which in turn mitigates the perception of flicker that would otherwise occur. In addition, the discrete VRR scheme is able to employ a compensation mode to compensate for delays in rendering or otherwise obtaining a frame for display so as to maintain a consistent duty cycle in the brightness control signal.

Description

Background Art

[0001] Some video display systems utilize a pulse width modulation (PWM) scheme to control the brightness of a display panel displaying a corresponding video frame. The digital control signal that controls the backlight in a transmissive display panel or directly controls the pixel intensity in an emissive display panel is pulse width modulated so that the final brightness of the display panel is proportional to the duty cycle of the final PWM signal. Therefore, any change in the effective duty cycle of the control signal between two consecutive frame periods will introduce a corresponding brightness change at the display panel between two consecutive frame periods. In a display system that employs a variable refresh rate, the rendering or other generated delay of a video frame can cause the display of a delayed frame or a subsequent frame to be misaligned with respect to the PWM control signal. As a result, the effective duty cycle of the PWM control signal can vary between consecutive frames. Therefore, this change in the effective duty cycle of the PWM control signal can cause one frame to have a lower or greater brightness than the next frame (depending on whether the effective duty cycle between the two frames increases or decreases), and this brightness change between consecutive frames is usually perceived by the observer as flicker, which detracts from the viewing experience. Summary of the invention

[0002] One aspect of the proposed technical solution relates to a method, comprising: controlling the brightness of a frame displayed at a display panel via pulse width modulation (PWM) of a brightness control signal provided to the display panel; selecting a target frame rate for displaying the frame at the display panel so that the corresponding frame period for the target frame rate is an integer multiple of the PWM period of the brightness control signal; and providing frames for display based on the target frame rate so that the frame period of each frame is aligned with the corresponding PWM cycle of the brightness control signal.

[0003] In an example embodiment, selecting a target frame rate may include: determining a maximum frame rate and a minimum frame rate, the maximum frame rate and the minimum frame rate being integer submultiples of a PWM frequency of a brightness control signal; and selecting a frame rate between the minimum frame rate and the maximum frame rate as a target frame rate, wherein the target frame rate is an integer submultiple of the PWM frequency.

[0004] Additionally or alternatively, the method may include detecting a delay in rendering of the first frame based on the target frame rate, and in response to detecting the delay in rendering of the first frame based on the target frame rate, implementing a compensatory variable refresh rate (VRR) scheme that maintains an effective PWM duty cycle of the brightness control signal within each display frame period of at least a subset of the frame periods consistent with the delay in rendering. In an example embodiment, a timing controller may be used to detect the delay in rendering. The timing controller may monitor the frame rendering process to find an indication that the rendering of the current first frame is "delayed" or will be "delayed"; that is, the rendering of the current first frame takes a sufficiently long time that the current frame may not or is not ready to be scanned out to the display panel 106 at the end of the frame period of the previous frame (i.e., the frame currently being displayed) and the beginning of the frame period of the next frame to be displayed. For example, a specified signal may be provided (e.g., by the frame generation subsystem) to notify the completion of the rendering of the frame, such as through the transmission of a data packet. For a given frame rate, a synchronization signal, such as a tearing effect (TE) signal, is provided within a specified delay after assertion of the synchronization signal. Such a synchronization signal may be used to synchronize the transmission of the next frame from the frame generation subsystem to the buffer. Thus, failure to receive the specified signal within a corresponding delay after assertion of the synchronization signal indicates that rendering of the frame is delayed.

[0005] In an example embodiment, the compensatory VRR scheme may include two different modes for compensating for delays in rendering. In this context, the method may also include selecting between the two modes based on the target frame rate, such as a frame insertion mode and a frame stretching mode (as examples of two different compensatory discrete VRR modes). For example, in the case where the target frame rate is less than the maximum frame rate, the frame insertion mode may be selected, and in the case where the target frame rate is equal to the maximum frame rate, the frame stretching mode may be selected.

[0006] In an example embodiment, implementing a compensatory VRR scheme may include: implementing a frame insertion mode by displaying a second frame at a target frame rate within a first frame period, the second frame being rendered immediately before the first frame (i.e., directly or just before the first frame in a sequence of rendered frames); in response to detecting a delay in rendering of the first frame, providing the second frame for display again at a maximum frame rate within a second frame period, the second frame period starting from the termination of the first frame period and being an integer multiple of the PWM period of the brightness control signal; and displaying the first frame at the target frame rate within a third frame period, the third frame period starting from the termination of the second frame period.

[0007] Implementing the compensatory VRR scheme may also include implementing a frame stretching mode. Such a frame stretching mode may include: displaying a second frame at a target frame rate within a first frame period, the second frame being rendered immediately before the first frame; determining a scan-in delay, the scan-in delay being an integer multiple of the PWM period and representing a delay between scanning a frame into a frame buffer and scanning the frame out of the frame buffer to a display panel; in response to detecting a delay in rendering of the first frame, providing the first frame for display within a second frame period, the second frame period starting from the termination of the first frame period and being equal to the sum of the first frame period and the scan-in delay; and displaying a third frame at the target frame rate within a third frame period, the third frame period starting from the termination of the second frame period.

[0008] The proposed solution also relates to a system, the system comprising: a frame rendering subsystem, the frame rendering subsystem being configured to render a sequence of frames at a variable rate; and a display control subsystem, the display control subsystem being coupled to the frame rendering subsystem and being coupleable to a display panel. The display control subsystem may be configured to: provide a brightness control signal to the display panel, the brightness control signal being configured to control the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of the brightness control signal; select a target frame rate for displaying the frame on the display panel such that a corresponding frame period of the target frame rate is an integer multiple of a PWM period of the brightness control signal; and transmit the frame to the display panel for display based on the target frame rate such that a frame period of each frame is aligned with a corresponding PWM cycle of the brightness control signal.

[0009] In an example embodiment, a system may perform an embodiment of the proposed method.

[0010] For example, the display panel can be a transmissive display panel, and the brightness control signal is a backlight control signal for the transmissive display panel, or the display panel can be an emissive display panel, and the brightness control signal is an emission control signal for the emissive display panel. Typically, the brightness control signal can be a pulse width modulated digital signal for controlling the brightness of the display panel. In an embodiment where the display panel is implemented as an LCD panel or other transmissive display panels, the brightness control signal represents a PWM control signal for activating the backlight of the transmissive display panel. For an emissive display panel, such as an OLED and AMOLED display panel, an emission control (EM) signal provided to each effective pixel is pulse width modulated with a specific duty cycle to control the brightness of the corresponding pixel, and in this case, the brightness control signal represents the EM signal.

[0011] While variable refresh rates can mitigate screen tearing and jitter and provide smoother perceived motion, it can cause synchronization issues between the display of frames and the timing of the PWM control signal used to control the brightness (also known as "intensity") of the display panel used to display the frames. This lack of synchronization can result in variations in the effective PWM duty cycle between consecutive frames, which can appear as flicker to an observer. The present disclosure describes systems and techniques for mitigating PWM frame rate misalignment, for example by implementing a discrete variable refresh rate (VRR) scheme. In such a discrete VRR scheme, the target frame rate employed by the display system is limited to a frame rate selected only from those frame rates that facilitate alignment of each frame period with a specified edge of a PWM cycle of a PWM-based brightness control signal used to control the display panel. This alignment causes each frame period at the selected frame rate to start at the same point in the corresponding PWM cycle and end at the same point in the corresponding PWM cycle, and thereby helps ensure a constant effective duty cycle with the same expected brightness across each consecutive frame period. This, in turn, mitigates the perception of any flicker that would otherwise occur from variations in the effective duty cycle of the brightness control signal between frames.

[0012] Furthermore, in some embodiments, as described above, the discrete VRR scheme may employ one or more compensation modes to compensate for delays in rendering or otherwise obtaining a frame for display so as to maintain a consistent duty cycle in the brightness control signal. One such compensation mode may be a frame insertion mode in which, in response to delayed rendering of a next frame (i.e., rendering of a frame that takes longer than the allotted or otherwise specified time for rendering at a target frame rate), the last displayed frame is again displayed or "inserted" with a frame period corresponding to a specified maximum frame rate that facilitates alignment of the PWM cycles of the frame periods. Another such compensation mode may be a frame stretching mode in which, in response to delayed rendering of the next frame, the next frame is displayed with an extended or "stretched" frame period that is longer than the frame period corresponding to the target frame rate and has a duration selected to allow realignment of the corresponding timing control signal with the display of the next non-delayed frame. In both compensation modes, the frame rate and therefore the frame period for re-inserting the frame period of the previous frame or stretching the current frame with rendering delay are selected so as to align the inserted / stretched frames with the PWM cycle of the brightness control signal and thereby avoid distortion of the effective duty cycle of the frame period affected by delayed rendering. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure will be better understood, and its numerous features and advantages will become apparent to those skilled in the art by referencing the accompanying drawings.The use of the same reference numbers in different drawings indicates similar or identical items.

[0014] Figure 1is a block diagram illustrating a display system employing a discrete variable refresh rate (VRR) control technique with PWM cycle alignment according to at least one embodiment.

[0015] Figure 2 is a flow chart illustrating a method of displaying a sequence of frames using dynamic discrete VRR control mode switching according to some embodiments.

[0016] Figure 3 is a flow chart illustrating a method of setting a target frame rate for a default discrete VRR control mode according to some embodiments.

[0017] Figure 4 is a flow chart illustrating a method of compensating for delayed frame rendering using a frame interpolation mode according to some embodiments.

[0018] Figure 5 is a diagram showing a method according to some embodiments Figure 4 A timing diagram of an example of frame insertion mode.

[0019] Figure 6 is a flow chart illustrating a method of compensating for delayed frame rendering using a frame stretching mode according to some embodiments.

[0020] Figure 7 is a diagram showing a method according to some embodiments Figure 6 A timing diagram of an example of frame stretching mode. DETAILED DESCRIPTION

[0021] Figure 1A display system 100 is shown that employs a discrete VRR scheme to mitigate PWM duty cycle distortion in a brightness control signal in accordance with at least one embodiment. The display system 100 can include any of a variety of systems for rendering, decoding, or otherwise generating a sequence of video frames for display, such as a desktop computer, a notebook computer, a tablet computer, a computing-enabled cellular phone, a server, a game console, a television, a computing-enabled watch or other wearable device, etc. The display system 100 includes a frame generation subsystem 102, a display control subsystem 104, and a display panel 106. The frame generation subsystem 102 operates to generate a sequence of video frames (hereinafter referred to as "frames") for display, and includes a system memory 108 storing one or more software applications 110 and a collection of one or more processors, such as one or more central processing units (CPUs) 112, one or more graphics processing units (GPUs) 114, and one or more display processing units (DPUs) 116. In one embodiment, the display control subsystem 104 includes a graphics random access memory (GRAM) 118 or other memory that operates as a frame buffer, a pixel driver 120, a timing controller 122, one or more clock sources 124, and one or more counters 126. The pixel driver 120 and the timing controller 122 are implemented via hardwired logic (e.g., an integrated circuit), programmable logic (e.g., a programmable logic device), one or more processors that execute software instructions, or a combination thereof. In the illustrated embodiment, the components of the frame generation subsystem 102 are implemented together in a host system on a chip (SoC) 128, while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130. However, in other embodiments, the components of the two subsystems 102, 104 are implemented on the same IC or the same SoC, or different combinations of the components are implemented on different ICs or SoCs. The display panel 106 can include any of a variety of display panels that can be configured to provide brightness control via PWM duty cycle control, such as a liquid crystal display (LCD) panel, a light emitting diode (LED) panel, an organic LED (OLED) panel, an active matrix OLED (AMOLED) panel, etc.

[0022] As a general operational overview, the CPU 112 executes a software application 110, which may represent a video game, a virtual reality (VR) or augmented reality (AR) application, or other software application that is executed to produce a series of frames for display. As part of this execution process, the CPU 112 instructs the GPU 114 to render or otherwise generate each frame in the sequence, and the DPU 116 performs one or more post-rendering processes on the frame, such as gamma correction or other filtering, color format conversion, etc. The frame data 131 of the final frame 132 is then transmitted to the display control subsystem 104 for buffering in the GRAM 118.

[0023] At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, a brightness control signal 138, and a vertical retrace (VSYNC) signal and a scan start signal (not shown). Figure 1 106 ). The TE signal 136 is used to synchronize the transmission of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 in order to mitigate screen tearing artifacts caused by overwriting the current frame before the last line of the current frame has been displayed at the display pane 106. The brightness control signal 138 is a pulse width modulated digital signal used to control the brightness of the display panel 106. In embodiments where the display panel 106 is implemented as an LCD panel or other transmissive display panel, the brightness control signal 138 represents a PWM control signal for activating the backlight of the transmissive display panel. For emissive display panels, such as OLED and AMOLED display panels, the emission control (EM) signal provided to each effective pixel is pulse width modulated at a specific duty cycle to control the brightness of the corresponding pixel, and in this case, the brightness control signal 138 represents the EM signal. Since the following description mainly relates to OLED or AMOLED-based embodiments of the display pane 106, the backlight control signal 138 is also referred to as "EM signal 138" herein, but unless otherwise specified, references to EM signals are equally applicable to other forms of PWM-based brightness control.

[0024] The timing controller 122 uses the timing signaling and other control signaling 140 to control the pixel driver 120 to drive the display panel 106 to display the frame 132 from the GRAM 118 by scanning the frame data 131 of the frame 132 from the GRAM 118 into the pixel array (not shown) of the display panel 106 using row-line addressing, wherein the transmission of the pixel data from the pixel driver 120 to the display panel 106 is represented by the SCAN signal 142. The pixels of each row are activated to emit display light according to the corresponding pixel values ​​of the row, wherein the brightness of the emitted display light during the frame period for displaying the corresponding frame 132 is at least partially controlled by the PWM duty cycle of the EM signal 138. In some embodiments, the amplitude of the EM signal 138 can also be adjusted to further control the intensity of the emitted light.

[0025] In at least one embodiment, the display system 100 supports a variable refresh rate, so that rather than requiring a sequence of frames to be rendered and displayed at a fixed frame rate, the frame rate can be modified to accommodate frames that may take different amounts of time to render. For example, the complexity of the frames to be rendered or the current resources available to render a given frame may cause the preparation of a rendered frame to take more time than the time available at the nominal current frame rate, so the system can instead dynamically and temporarily adjust the frame period of rendering delayed frames. However, because in a variable refresh rate configuration, the frame period of a first frame may be different from the frame period of a second frame adjacent to the first frame, the effective duty cycle of the EM signal 138 during the frame period of the first frame may be different from the effective duty cycle of the EM signal 138 during the frame period of the second frame, which in turn results in a change in brightness from the first frame to the second frame, which can be detected by an observer as disturbing flicker.

[0026] Thus, in at least one embodiment, the timing controller 122 employs a discrete VRR scheme 144 that provides an implementation of a frame rate that allows alignment and synchronization of corresponding frame periods with the PWM cycles of the EM signal 138, such that each frame period is aligned with the PWM cycle and spans only one PWM cycle in their entirety, and thus allows variations in the frame rate to accommodate delayed rendering of frames, thereby avoiding distortion of the effective duty cycle of the frame or frames preceding or following the frame. As used herein, "alignment" of a frame period with the EM signal 138 or "alignment" of a frame period with the corresponding PWM cycle of the EM signal 138 refers to the timing of each frame period such that the frame period begins at the same designated point in the corresponding PWM cycle and ends at the same designated point in a subsequent corresponding PWM cycle. An embodiment of the discrete VRR scheme 144 is described below.

[0027] Figure 2 According to some embodiments Figure 1A method 200 of operating the display system 100 when rendering and displaying a frame stream or other frame sequence utilizing a discrete VRR scheme 144 is provided. In the example shown, the method 200 consists of two concurrent processes: a rendering / display process 202 for generating and displaying a frame sequence, and a frame selection process 204 (representing the discrete VRR scheme 144) for selecting an appropriate frame rate and, in the event of a delayed frame being rendered, selecting an appropriate discrete VRR mode to compensate for the delayed frame being rendered.

[0028] An iteration of the rendering / display process 202 begins at block 206, whereby the frame generation subsystem 102 renders the frame 132 and buffers the frame 132 in the GRAM 118. At block 206, the timing controller 122 (or other component of the display control subsystem 104) selects the next frame to be provided to the display panel 106 for display. At block 210, the timing controller 122 and the pixel driver 120 cooperate to transfer the pixel data of the selected frame 132 from the GRAM 118 to the display panel 106 via the SCAN signal 142, and at block 212, the display panel 106 displays the selected frame 132 at a specified frame rate, wherein the brightness is controlled at least in part based on the effective PWM duty cycle of the EM signal 138 over a frame period corresponding to the specified frame rate. In some embodiments, the display panel 106 begins displaying the already received pixel row of the selected frame 132 while subsequent rows are still being transmitted. In other embodiments, the entire selected frame 132 is transmitted to the display panel 106 before display of the frame 132 is initiated.

[0029] As described above, iterations of the rendering / display process 202 include selecting the next frame to be displayed (block 208) and specifying a frame rate, and therefore a frame period, for which the selected frame is to be displayed (block 212). In one embodiment, both of these aspects are controlled according to a discrete VRR scheme 144 employed by the timing controller 122 of the display control subsystem 104 and represented by the frame selection subprocess 204. As a general overview of the discrete VRR scheme 144, in the absence of a rendering delayed frame, a default VRR mode is employed in which the next frame to be selected for display is generally the most recently rendered frame. However, in the presence of a rendering delayed frame, an alternative VRR mode can be employed to compensate for the delayed rendering in a manner that avoids distortion of the per-frame period PWM duty cycle of the EM signal 138.

[0030] As described above, one aspect facilitated by the discrete VRR scheme 144 is the alignment of the frame period with the edges of the PWM cycle of the EM signal 138 so that any given frame period does not distort the intended duty cycle of the EM signal 138. As part of this alignment process, at block 214, the timing controller 122 determines, in part, the maximum frame rate (represented herein as “F H”), minimum frame rate (represented as “F L ”) and the target frame rate (denoted as “F C ”). These frame rates may be defined in part by the frame rendering capabilities of the frame generation subsystem 102, the display frame rate capabilities of the display panel 106, based on user settings or preferences, based on the requirements of the software application 110, etc. As an example, the maximum frame rate F H can be set to a maximum display frame rate (e.g., 120 frames per second (fps)) supported by the display panel 106 or the software application 110, while the minimum frame rate F L Can be set to the lowest frame rate that is considered to provide a minimum sufficient quality viewing experience (e.g., 30fps). C represents the target frame rate between the minimum frame rate and the maximum frame rate (i.e., F L <=F C <=F H ), and is selected based on one or more considerations including user preferences or settings, current rendering bandwidth capacity, etc.

[0031] In addition, as described below, the current frame rate F C Limited to F L With F M A subset of possible frame rates between 1 and 2 that satisfies the number of PWM cycles in a given frame period, F L and F M For example, as described in more detail below, to facilitate alignment of the frame period with the PWM cycle of the EM signal 138, in at least one embodiment, the maximum frame rate F H , minimum frame rate F L and the target frame rate F C Each of the candidate frame rates is selected only from those candidate frame rates that represent integer subdivisions of the PWM frequency of the EM signal 138; that is, the integer PWM frequency can divide the integer candidate frame rate without a remainder. For example, assume that the PWM frequency is 360 Hz, and the actual maximum frame rate supported by the display system 100 is 130 fps. In this case, 130 is not an integer subdivision of 360, but 120 is the closest integer subdivision of 360, so 120 fps is selected as the maximum frame rate. In doing so, the corresponding frame period at any of the maximum frame rate, the minimum frame rate, or the target frame rate has a duration equal to an integer multiple of the PWM cycle / period of the EM signal 138, and thus the alignment of the frame period with the EM signal 138 is facilitated.

[0032] With the timing controller 122 so initialized, at box 216 of the frame selection process 204, the timing controller 122 monitors the frame rendering process of box 206 for an indication that the rendering of the current frame is "delayed" or will be "delayed"; that is, the rendering of the current frame takes a sufficiently long time that the current frame may not or is not ready to be scanned out to the display panel 106 (box 210) at the end of the frame period of the previous frame (i.e., the frame currently being displayed) and the beginning of the frame period of the next frame to be displayed. For example, in some embodiments, a specified signal is provided by the frame generation subsystem 102 to notify the completion of the rendering of the frame, such as through the transmission of a 2C data packet. For a given frame rate, the signal is provided within a specified delay after the assertion of the TE signal 136. Therefore, failure to receive the specified signal within a corresponding delay after the assertion of the TE signal 136 indicates that the rendering of the frame is delayed.

[0033] In the absence of an indication of late / delayed rendering of the current frame being rendered (e.g., in response to a determination that the current frame has completed rendering before a particular time or threshold associated with the target frame rate), then at box 218, the timing controller 122 uses a default discrete VRR mode for the upcoming display frame period. When the timing controller 122 is in the default discrete VRR mode, the most recently rendered frame is selected as the next image to be displayed in box 208, and the frame rate of the rendered frame is set to the selected target frame rate in box 212, and the frame period for displaying the rendered frame is therefore set to the target frame period corresponding to the target frame rate. That is, in response to a determination at box 216 that the frame being rendered will be rendered and ready in time, the display control subsystem 104 is set to discrete VRR mode such that the frame is selected as the next frame to be scanned out to the display, and the nominal target frame rate is used for timing and control signals for displaying the frame at the display panel 106. Reference is made below to Figure 3 The default discrete VRR mode is described in more detail.

[0034] Returning to block 216, if the timing controller 122 instead detects delayed rendering of the current frame, then in one embodiment, the discrete VRR scheme 144 selects one of two compensatory discrete VRR modes to compensate for the delayed rendering while maintaining the same effective PWM duty cycle in each frame period of at least a subset of the frame periods that coincide with the delayed frame rendering, and thereby mitigating the presence of flicker associated with delayed rendering. The two modes include a frame stretching mode and a frame insertion mode. As described in more detail below, even when the current frame rate is set to the maximum frame rate (i.e., when F C <=F H ), the frame stretching mode can also be used, while the frame insertion mode is only used when the current frame rate is less than the maximum frame rate (i.e., when F C <FH Therefore, for the purpose of the following examples, it is assumed that the frame stretching mode is implemented when the current frame rate is equal to the maximum frame rate, and it is further assumed that the frame insertion mode is implemented whenever the current frame rate is less than the maximum frame rate. However, in other embodiments, when the current frame rate is less than the maximum frame rate, additional selection criteria can be used to select between the frame stretching mode or the frame insertion mode. Furthermore, in other embodiments, when a delayed rendering situation is detected, only a single compensatory discrete VRR mode is available. For example, the display control subsystem 104 may only implement the frame insertion mode to compensate for the detected rendering delay, and thus limit the current frame rate to less than the maximum frame rate F. H As another example, the display control subsystem 104 may implement a frame stretching mode only to compensate for delayed rendering conditions.

[0035] For the illustrated embodiment, in response to detecting delayed rendering, at block 220, the timing controller 122 determines whether the current frame rate is set to the maximum frame rate (F C =F H If not, the timing controller 122 utilizes the frame insertion mode at block 222 to control the timing and display of the upcoming display frame period. In general, when in the frame insertion mode, the most recently displayed frame (i.e., the "previous" frame) is again selected as the next frame to be displayed at block 208, and a faster frame rate (e.g., the maximum frame rate F is selected for the repeated display of the previous frame at block 212. H ), so that the corresponding display frame period of the previous frame displayed again is shortened compared to the nominal target frame period while maintaining alignment with the pulse of the EM signal 138, and then the delayed rendering frame is selected for display in the next display frame period (block 208), and displayed at the target frame rate (block 212). Figure 4 and Figure 5 The frame insertion mode is described in more detail.

[0036] Returning to block 220, if the current frame rate is equal to the maximum frame rate, the timing controller 122 utilizes the frame stretching mode at block 224 to control the timing and display of the upcoming display frame period. In summary, when in the frame stretching mode, the rendering delay frame is selected as the next frame to be displayed at block 208, and for the display of the rendered display frame at block 212, a "slower" frame rate is selected so that the corresponding display frame period of the rendering delay frame is "stretched" compared to the target frame period while also being aligned with the pulses of the EM signal 138. Figure 6 and Figure 7 The frame stretching mode is described in more detail.

[0037] Now turn to Figure 3, a method 300 representing a default discrete VRR mode is shown according to some embodiments. As described above, the discrete VRR scheme 144 implemented by the display control subsystem 104 attempts to mitigate duty cycle distortion in the PWM-based brightness control signal (i.e., EM signal 138) by aligning each display frame period with the PWM cycle of the brightness control signal (EM signal 138) so that each such display frame period maintains the same effective PWM duty cycle during its duration to obtain the same given expected brightness level for displaying the corresponding frame. Therefore, in at least one embodiment, the frame rate and therefore the frame period selected and implemented for any given frame being displayed are set so that each frame period starts at the same point within the corresponding PWM cycle of the brightness control signal and has a duration that is an integer multiple of the PWM cycle of the brightness control signal. That is:

[0038] FramePeriod(X)=Y*PWMPeriod

[0039] Wherein X is a given frame X, FramePeriod(X) is the frame period of frame X, PWMPeriod is the PWM period of the PWM cycle of the brightness control signal, and Y is an integer.

[0040] Therefore, at block 302, the timing controller 122 determines the maximum frame rate F H The number of complete PWM cycles that occur in one frame period, where the maximum frame rate F H is selected or set to a frame rate that is an integer multiple of the PWM frequency of the EM signal 138, and the variable N is set to that determined number. Thus, the maximum frame rate F H The PWM frequency of the EM signal 138 can be set based on a specified PWM frequency of the EM signal 138, which can be set based on a specified maximum frame rate F H Similarly, the minimum frame rate F L is set to an integer multiple of the PWM frequency of the EM signal 138. It should be understood that the greater the number N of complete PWM cycles within a frame period, the greater the frequency that can be provided by the timing controller 122 with finer resolution. At block 304, the maximum frame rate F is used based on the following relationship: H and the minimum frame rate F L To determine the variable M:

[0041]

[0042] or

[0043]

[0044] At block 306, the target frame rate F Cis then set to a frame rate that will result in a frame period that is an integer multiple of the PWM period of the EM signal 138. Thus, rather than setting the target frame rate F C Set to F L With F M , but the target frame rate F C The frame rate is limited to produce frame rates with frame periods that are integer multiples of the PWM period of the EM signal 138 (i.e., frame rates that are integer submultiples of the integer PWM frequency of the EM signal 138). Frame rates that meet this requirement are referred to herein as "discrete" frame rates. L 、F M and M, target frame rate F C Set to F L 、F M or F I One of the I is the discrete frame rate, defined as:

[0045]

[0046] To illustrate the process of method 300, assume that the maximum frame rate is set to 120 fps (F M = 120), the minimum frame rate is set to 60fps (F L =60), and the PWM frequency of the EM signal 138 is 360 PWM cycles per second (N=360 / 120=3). Thus, in this example, M would be set to 6 (120*3 / 60). Thus, K can be selected to be one of the integer values ​​4 or 5, and thus the candidate set of discrete frame rates from which the target frame rate can be selected is: 60fps, 72fps, 90fps, or 120fps (each of which is an integer submultiple of the PWM frequency of 360). A frame period at one of these frame rates will thus span an integer number of PWM cycles of the EM signal 138, and if each such frame period is aligned to start at the same point within the corresponding PWM cycle (e.g., at the rising edge of a high pulse in the PWM cycle), then the effective duty cycle of the EM signal 138 for each frame period remains the same, thereby avoiding distortion of the effective duty cycle of the EM signal 138 from one display frame to the next.

[0047] Figure 4 A method 400 is shown depicting the operation of a frame insertion mode for compensating for delayed rendering according to some embodiments. The method 400 begins at block 402, which indicates that in the method 200 ( Figure 2), a delay in the completion of rendering of the frame 132 currently being rendered by the GPU 114 (referred to as "frame N" for purposes of the following description), is detected at box 216 of the display control module 110, and a frame insertion mode is selected when there are multiple compensatory discrete VRR modes. Since the frame insertion mode involves reinserting a previously displayed frame (referred to as frame "N-1" for purposes of the following description), which is a frame rendered immediately before the rendering of the current frame N, so that it is displayed again, at box 404, the timing controller 122 asserts the TE signal 136 (assuming a high level is active) at the end of the current display system to signal the frame generation subsystem 102 to temporarily prohibit the transfer of pixel data from the rendering delayed frame N to the GRAM 118 (and thereby overwrite the previous frame N-1 stored therein). For the next frame cycle, at box 406, the timing controller 122 and the pixel driver 120 together repeat the previous frame N-1 ( Figure 2 210) to the scanning transmission of the display panel 106, and at a maximum frame rate F H (or greater than the target frame rate F C The previous frame N-1 is displayed again (block 212) at some other discrete frame rate of the EM signal 1330, wherein the frame period of the repeated frame N-1 is aligned with the same point (e.g., rising edge) of the corresponding PWM period of the EM signal 1330.

[0048] As the next frame period ends, at block 408, the timing controller 122 determines whether the rendering of the current frame N has been completed or will be completed in sufficient time for the next frame period. If so, at block 410, the timing controller 122 switches back to the default discrete VRR mode, in which the current frame N is selected for scanout to the display panel 106 (block 210) and then rendered at the target discrete frame rate F C , where the corresponding frame period is aligned with the PWM cycle of the EM signal 138, as described above. However, if the rendering of frame N is not completed in time, then in the second iteration of block 406, the timing controller 122 again selects the previous frame N-1 for rendering at the maximum frame rate F. H or other higher discrete frame rate for a third scan-out and display. The process is then repeated until the rendering of the current frame N has been completed and is therefore ready to be scan-out and displayed, or until a threshold number of reinsertion times of the previously displayed frame N-1 has been met for repeated display.

[0049] Figure 5 A timing diagram 500 is depicted showing an example of entering a frame insertion mode in response to rendering delay according to some embodiments. For timing diagram 500, the abscissa represents time (increasing from left to right). Timing row 502 represents GPU 114 ( Figure 1) for each corresponding frame, starting with frame N-1 and ending with frame N+2. Timing row 504 represents the buffering process used to transfer the rendered frame data of the frame from the frame generation subsystem 102 to the GRAM 118. Timing row 506 represents the state of the TE signal 136, where in this example, the high active pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118. Timing row 508 represents the state of the vertical retrace (VSYNC) signal generated and used by the timing controller 122 to control the scan output of the frame from the GRAM 118 to the display panel 106 for display, and thus the VSYNC signal represents the timing of each frame cycle. For this example, the VSYNC signal is synchronized with the high active pulse in the TE signal 136, wherein the VSYNC signal becomes a low active pulse in response to a corresponding pulse in the TE signal 136, and the pulse in the VSYNC signal initiates the start of a frame period of a corresponding frame that is scanned out and displayed at the display panel 106. Timing line 510 represents the progressive scan output of a frame for a corresponding frame period (represented in the VSYNC signal). Timing line 512 represents the PWM-based EM signal 138. For this example, F H =120, F L =60, the PWM frequency is 360 Hz. Therefore, N = 3 (i.e., at the frame rate F H The frame period is equal to three complete PWM cycles of the EM signal 138), so M=6, K=4 or 5. Therefore, the candidate frame rates that can be selected are 60fps, 72fps, 90fps or 120fps to ensure that each frame period is an integer multiple of the PWM period of the EM signal 138. For the purpose of the following examples, the target frame rate is set to 90fps (i.e., F C =F I =90fps).

[0050] Timing diagram 500 begins with the transfer of pixel data for frame N-2 to GRAM 118 in response to the first pulse (pulse 514) in TE signal 136. At the same time, the GPU begins rendering frame N-1. At the end of the first pulse (pulse 516) in the VSYNC signal, timing controller 122 and pixel driver 120 begin rendering at a frame rate F. C(=90fps) scan out and display frame N-2 of frame period 561. Note that the delay 515 between the end of the first pulse 514 in the TE signal 136 and the end of the first pulse 516 in the VSYNC signal represents the delay between the time when the frame 132 is buffered in the GRAM 118 and the time when the same frame 132 can begin to be scanned out to the display panel 106. As shown, the end of this first pulse 516 in the VSYNC signal, and therefore the beginning of the frame period 561, is aligned with the rising edge of the corresponding PWM cycle 518 of the EM signal 138, and for a frame period of 1 / 90 seconds and a PWM period of 1 / 360 seconds, the frame period 561 spans four PWM cycles, from the rising edge of the first PWM cycle 518 to the rising edge of the fifth PWM cycle 520. Similarly, as shown in timing diagram 500, the rendering of frame N-1 is completed on time, and therefore the pixel data of the rendered frame N-1 is transferred to GRAM 118 using the second pulse 522 in TE signal 136, and the VSYNC signal is pulsed into a second pulse 524 to start the next frame cycle 562 for displaying the image at the target frame rate F C Frame N−1 is scanned out and displayed, with frame period 562 aligned with the rising edge of the fifth PWM cycle 520 , spanning four complete PWM cycles, and ending with the rising edge of the ninth PWM cycle 526 .

[0051] However, with the end of the second frame period 562 and the corresponding third pulse 528 of the TE signal 136 to trigger the third frame period 563, as shown in the timing line 502, the rendering of frame N is not completed in time; that is, frame N is a rendering delayed frame. Therefore, frame N is not ready for display in the third frame period 563. Therefore, the timing controller 122 switches to the frame insertion mode in response to detecting the delayed rendering (and where the target discrete frame rate is less than the maximum frame rate). Therefore, in the frame insertion mode, the timing controller 122 instead returns to the previously displayed frame, i.e., frame N-1, and with the start of the third frame period 563 signaled by the third pulse 530 in the VSYNC signal (and aligned with the rising edge of the third PWM cycle 526), ​​the timing controller 122 and the pixel driver 120 cooperate to scan out the previous frame N-1 from the GRAM 118 to the display panel 106 again for display at the display panel 106. However, the timing controller 122 does not scan the previous frame N-1 at the target discrete frame rate F C The second iteration of frame N-1 is displayed, but a faster frame rate is selected, such as the maximum frame rate F H, and thus in this example a shorter frame period 563 of three PWM cycles of the EM signal 138. By displaying repeated frames at a faster frame rate, the display system 100 is able to more quickly turn to displaying the rendered delayed frame N after its rendering is complete. However, as with the previous frame periods 561 and 562, the frame period 563 is aligned with the rising edge of the corresponding PWM cycle (in this case, PWM cycle 526) and spans an integer number of PWM cycles (in this case, 3) so as to terminate at the rising edge of the twelfth PWM cycle 532.

[0052] In this example, the GPU 114 completes rendering of frame N before the end of the third frame period 563. Therefore, with the termination of the third frame period 563, the GPU begins rendering frame N+1, and frame N is transmitted to the GRAM 118 in response to the fourth pulse 534 in the TE signal 136, which in turn triggers a fourth frame period 564 that is aligned with the fourth pulse 536 in the VSYNC signal (which in turn is aligned with the rising edge of the twelfth PWM cycle 532 of the EM signal 138). Therefore, during the fourth frame period 564, frame N is scanned out from the GRAM 118 and displayed at the display panel 106, and the fourth frame period 564 has the F set to the PWM period. C 532 and spans four complete PWM cycles, terminating with the rising edge of the sixteenth PWM cycle 538. This process is repeated for the fifth frame cycle 565, and so on, for displaying frame N+1 while rendering frame N+2. In the event that the GPU 114 has not completed rendering frame N by the end of the third frame cycle 563, a third instance of frame N-1 can be rendered at a faster frame rate F. M It is displayed in the second insertion frame period, and the process of reusing frame N-1 can be repeated until the rendering of frame N has been completed, or until a threshold number of frame reuses is met.

[0053] As shown in the timing diagram 500, according to the default discrete VRR mode, non-delayed frames are rendered at a discrete frame rate that results in a frame period that is an integer multiple of the PWM period of the EM signal 138, and thus allows each frame period to be aligned with the PWM cycle of the EM signal 138, so that the effective duty cycle of the EM signal 138 is constant between frame periods. In addition, when a delayed frame is present, entering a frame insertion mode allows the previous frame to be displayed at a faster rate while waiting for the delayed frame to be ready for display. The use of a discrete frame rate (i.e., a frame rate that results in a frame period that is an integer multiple of the PWM period) thus allows a shorter frame period to be used for the inserted frame, while still allowing the shorter frame period to be aligned to the same point in the PWM cycle as the other frame periods, and span an integer number of PWM cycles, and thus maintain the same effective PWM duty cycle for the inserted frame / repeated frame as the frames before and after it, thereby mitigating any flicker that would otherwise be perceived by inserting the repeated frame to compensate for the delayed rendering of frame N.

[0054] Steering Figure 6 , a method 600 illustrating an implementation of a frame stretching method is shown according to some embodiments. The method 600 begins at block 602, which indicates that in the method 200 ( Figure 2 ), a delay in the completion of rendering of a frame 132 currently being rendered by the GPU 114 (referred to as "frame N" for purposes of the following description), and a frame stretching mode is selected when there are multiple compensatory discrete VRR modes. In the event that a delayed rendering situation is detected, at block 604, the timing controller 122 monitors the progress of the rendering of frame N. If the rendering exceeds a specified delay threshold, which indicates that the rendering of frame N will not be completed in time to use frame N in the next frame cycle, then at block 606, the timing controller 122 and the pixel driver 120 together repeat the scan transmission of the previous frame N-1 to the display panel 106 (block 210, Figure 2 ), and in the next frame period at the maximum frame rate F H (or greater than the target frame rate F C The previous frame N-1 is displayed again (block 212) at some other discrete frame rate of the EM signal 138, wherein the frame period of the repeated frame N-1 is aligned with the same point (e.g., rising edge) of the corresponding PWM cycle of the EM signal 138.

[0055] Otherwise, in the event that rendering of frame N will be completed in time, rather than pulsing or asserting the TE signal 136 at the end of the current frame period to begin the next frame period, at block 608, the timing controller 122 delays assertion of the TE signal 136 by a delay period equal to or otherwise based on the scan-in delay of the display system 100, where the scan-in delay represents the delay between the time when the display control subsystem 104 is able to receive a frame in the GRAM 118 and the time when the same frame is able to be scanned out to the display panel 106. Shifting the assertion of the TE signal 136 by the scan-in delay provides the GPU 114 with a delay period equal to or otherwise based on the scan-in delay of the display system 100. Figure 1 ) provides additional time to complete rendering of the delayed frame before the start of the next display frame cycle. The scan-in delay can be calculated as described in the next paragraph. As shown in block 610, this shift of the TE signal 136 is not a temporary shift, but rather represents a permanent realignment of the timing of the TE signal 136; that is, until another delayed rendering causes a subsequent shift from the default discrete VRR mode to the compensating discrete VRR mode, all subsequent assertions or pulses of the TE signal 136 are aligned with the now delayed TE assertion of block 612 at the target frame rate.

[0056] In anticipation of the upcoming display frame cycle, at block 614, the timing controller determines a stretched frame rate, and therefore a stretched frame cycle, for displaying the rendered delayed frame and in order to realign the timing of the subsequent display frame cycle. In at least one embodiment, the process is represented by the following expression:

[0057]

[0058]

[0059] Among them, F J Indicates the stretched frame rate, F H represents the maximum frame rate, N represents the number of PWM cycles in a frame period at the maximum frame rate, K and X are integers, ICPros represents the minimum time required for the display control subsystem 104 to receive, process, and output pixel data, and ScanIn represents the scan input delay used to delay the assertion of the TE signal 136 at block 608. Note that given the above constraints, by selecting K and X, the frame rate F J This results in the frame period being an integer multiple of the PWM period of the EM signal 138 and thus allows alignment of the PWM cycles of the final display frame period.

[0060] When the TE signal 136 is then asserted after the injected scan-in delay (as indicated by block 612), at block 616 the timing controller 122 and the pixel driver 120 operate at the stretched frame rate F during the corresponding display frame period. JThe now completed frame N is scanned out and displayed, and wherein the display frame period is aligned to span a set of complete or full PWM cycles of the EM signal 138. After displaying the rendered delayed frame N during the stretched frame period, the timing controller 122 then returns to the default discrete VRR mode for displaying the frame at the target frame rate F C The next rendered frame is displayed (unless the next rendered frame is also rendered delayed). Due to the process of stretching the frame period of the rendered delayed frame by an amount equal to or otherwise based on the scan-in delay, the timing controller 122 is able to "correct" or "realign" the timing between the TE signal 136, the rendering of the frame, and the frame period following the stretched frame period.

[0061] Figure 7 A timing diagram 700 is depicted showing an example of entering a frame stretching mode in response to rendering delay according to some embodiments. For timing diagram 700, the abscissa represents time (increasing from left to right). Timing row 702 represents GPU 114 ( Figure 1 ) for each corresponding frame, starting with frame N-1 and ending with frame N+3. Timing row 704 represents the buffering process used to transfer the rendered pixel data for each frame from the frame generation subsystem 102 to the GRAM 118. Timing row 706 represents the state of the TE signal 136, wherein in this example, an active high pulse in the TE signal 136 signals the frame generation subsystem 102 to begin transferring the next rendered frame to the GRAM 118. Timing row 708 represents the state of the VSYNC signal generated and used by the timing controller 122 to control the scanning out of frames from the GRAM 118 to the display panel 106 for display. For this example, the VSYNC signal is synchronized with the active high pulse in the TE signal 136, wherein the VSYNC signal is pulsed to an active low level in response to a corresponding pulse in the TE signal 136, and this pulse in the VSYNC signal initiates the start of a frame period for the corresponding frame to be scanned out and displayed at the display panel 106. Timing line 710 represents the scan output of a frame for a corresponding frame period (represented in the VSYNC signal). Timing line 712 represents the PWM-based EM signal 138. Figure 5 For this example, F H =120, F L =60, the PWM frequency is 360 Hz. Therefore, N = 3 (i.e., at the frame rate F H The frame period is equal to three complete PWM cycles of the EM signal 138), so M=6, K=4 or 5. Therefore, the candidate frame rates that can be selected are 60fps, 72fps, 90fps or 120fps, so as to ensure that each frame period is an integer multiple of the PWM period of the EM signal 138. For the purpose of the following examples, the target discrete frame rate is set to 90fps (i.e., FC =90).

[0062] Timing diagram 700 begins with the transfer of pixel data for frame N-2 to GRAM 118 in response to the first pulse (pulse 714) in TE signal 136. At the same time, the GPU begins rendering frame N-1. At the end of the corresponding first pulse (pulse 716) in the VSYNC signal, timing controller 122 and pixel driver 120 begin rendering at a frame rate F. C (=90fps) scans out and displays frame N-2 of frame period 761. Note that the delay 715 between the end of the first pulse 714 in the TE signal 136 and the end of the first pulse 716 in the VSYNC signal represents the scan-in delay used in the frame stretch mode as described above, and is illustrated as having a greater magnitude than the scan-in delay 515 depicted in the timing diagram 500 for illustrative purposes.

[0063] The end of this first pulse 716 in the VSYNC signal, and therefore the beginning of the frame period 761, is aligned with the rising edge of the corresponding PWM cycle 718 of the EM signal 138, and for a target frame rate F of 90 fps, C and thus a frame period of 1 / 90 second, and for a PWM period of 1 / 360 second, the frame period 761 spans four PWM cycles, from the rising edge of the first PWM cycle 718 to the rising edge of the fifth PWM cycle 720. Similarly, the rendering of frame N-1 is completed on time, and thus with the second pulse 722 in the TE signal 136, the pixel data for the rendered frame N-1 is transferred to the GRAM 118, and the VSYNC signal is pulsed into a second pulse 724 at the scan input delay 715 after the pulse 722 in the TE signal 136 to start the next frame period 762 for the frame rate F. C Frame N−1 is scanned out and displayed, with frame period 762 aligned with the rising edge of the fifth PWM cycle 720 , spanning four complete PWM cycles, and ending with the rising edge of the ninth PWM cycle 726 .

[0064] However, in this example, the rendering of frame N is delayed, and thus the timing controller 122 detects the delayed rendering of frame N, and thus enters a frame stretching mode for frame N, when the TE signal 136 would otherwise pulse (pulse 728) to trigger the third frame period. As a result, the timing of the next pulse (pulse 732) in the TE signal 136 is shifted by an amount 730 equal to or otherwise based on the scan-in delay 715, so that the next pulse 732 is timed to occur aligned with a corresponding pulse 734 in the VSYNC signal (which itself is aligned with the rising edge of the PWM cycle 726), which is used to terminate the second frame period 762 and begin the third frame period 763. The shift amount 730 in the timing of the next pulse in the TE signal 136 is used to delay the frame generation subsystem 102 from attempting to scan-in the pixel data of frame N until the display frame period of frame N-1 has been completed. However, this shift has also resulted in a misalignment of the timing of the VSYNC signal relative to the TE signal 136.

[0065] Therefore, for the third frame period 763, the timing controller 122 uses the above process to calculate the stretched frame rate F J , which results in correct alignment between the TE signal 136 and the VSYNC signal at the end of the final stretched frame period (frame period 763). Specifically, the stretched frame period is set to the target discrete frame rate F C The sum of the effective frame period (4 PWM cycles in this example) and the period represented by the scan input delay (as an integer multiple of the PWM period) gives a stretched frame period of 6 PWM cycles or a stretched frame rate of 60 fps. J , the period represented by the scan input delay is two PWM cycles in this example. Thus, the subsequent pulse 736 in the TE signal 136 to initiate buffering of pixel data for rendered frame N+1 is followed by a corresponding pulse 738 in the VSYNC signal to end the third frame period 763 and begin the fourth frame period 764, such that the timing or delay between the pulse 736 in the TE signal 136 and the subsequent pulse 736 in the VSYNC signal is restored to the correct previous timing relationship between the two signals that existed prior to delayed rendered frame N. That is, by stretching the display frame period for displaying the delayed rendered frame in the manner and amount described, the timing controller 122 is able to reestablish the correct alignment between the TE signal 136 and the VSYNC signal (representing the display frame timing) after the delayed rendered frame, and thereby compensate for the delay introduced by the delayed rendered frame, while maintaining consistent alignment between the frame period of the EM signal 138 and the PWM cycle, and thereby avoiding or mitigating distortion of the PWM duty cycle for any frame period. This, in turn, avoids the introduction of observer-perceptible flicker.

[0066] In some embodiments, certain aspects of the above-mentioned techniques are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly contained on a non-transitory computer-readable storage medium. The software can include instructions and certain data, which, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the above-mentioned techniques. Non-transitory computer-readable storage media can include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM) or other non-volatile memory devices, and the like. Executable instructions stored on a non-transitory computer-readable storage medium can be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executable by one or more processors.

[0067] Computer-readable storage media include any storage media or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS)-based storage media. Computer-readable storage media can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disc or flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0068] Note that not all activities or elements described above in the general description are required, a portion of a particular activity or device may not be required, and one or more additional activities may be performed or one or more additional elements may be included in addition to those described. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. In addition, these concepts have been described with reference to specific embodiments. However, it is understood by those of ordinary skill in the art that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0069] The benefits, other advantages and solutions to the problems have been described above with reference to specific embodiments. However, the benefits, advantages, solutions to the problems, and any features that may cause any benefit, advantage or solution to appear or become more significant should not be interpreted as key, essential or necessary features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, because the disclosed subject matter can be modified and practiced in different but equivalent ways for those skilled in the art who benefit from the teachings herein. Except as described in the appended claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is apparent that the specific embodiments disclosed above can be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is set forth in the appended claims.

Claims

1. A method comprising: controlling the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of a brightness control signal supplied to the display panel; selecting a target frame rate for displaying frames at the display panel, the target frame rate being between a maximum frame rate and a minimum frame rate and being an integer submultiple of a PWM frequency of the brightness control signal, such that a corresponding frame period of the target frame rate is an integer multiple of a PWM period of the brightness control signal; as well as Frames are provided for display based on the target frame rate such that a frame period of each frame is aligned with a corresponding PWM cycle of the brightness control signal.

2. The method according to claim 1, further comprising: detecting a delay in rendering of a first frame based on the target frame rate; as well as In response to detecting a delay in rendering of the first frame based on the target frame rate, a compensatory variable refresh rate (VRR) scheme is implemented, which maintains an effective PWM duty cycle of the brightness control signal during each display frame period in at least a subset of frame periods consistent with the delay in rendering.

3. The method according to claim 2, wherein: The compensatory variable refresh rate VRR scheme includes two different modes for compensating for delays in rendering.

4. The method according to claim 2, wherein: Implementing the compensatory variable refresh rate VRR scheme includes implementing a frame insertion mode in the following manner: Displaying a second frame at the target frame rate within a first frame period, the second frame being rendered immediately before the first frame; In response to detecting the delay in rendering of the first frame, providing the second frame again for display at a maximum frame rate within a second frame period, the second frame period starting from the termination of the first frame period and being an integer multiple of a PWM period of the brightness control signal; as well as The first frame is displayed at the target frame rate during a third frame period, and the third frame period starts from the end of the second frame period.

5. The method according to claim 2, wherein: Implementing the compensatory variable refresh rate VRR scheme includes implementing a frame stretching mode by: Displaying a second frame at the target frame rate within a first frame period, the second frame being rendered immediately before the first frame; determining a scan-in delay, the scan-in delay being an integer multiple of a PWM period and representing a delay between scan-in of a frame into a frame buffer and scan-out of the frame from the frame buffer to the display panel; In response to detecting the delay in rendering of the first frame, providing the first frame for display within a second frame period, the second frame period beginning at a termination of the first frame period and equal to a sum of the first frame period and the scan-in delay; as well as A third frame is displayed at the target frame rate in a third frame period, the third frame period starting from the termination of the second frame period.

6. The method according to any one of claims 1 to 5, wherein: The display panel is a transmissive display panel, and the brightness control signal is a backlight control signal for the transmissive display panel; or The display panel is an emissive display panel, and the brightness control signal is an emission control signal for the emissive display panel.

7. A system comprising: a frame rendering subsystem configured to render a sequence of frames at a variable rate; as well as A display control subsystem is coupled to the frame rendering subsystem and can be coupled to a display panel, the display control subsystem being configured to: providing a brightness control signal to the display panel, the brightness control signal being configured to control the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of the brightness control signal; selecting a target frame rate for displaying frames at the display panel, the target frame rate being between a maximum frame rate and a minimum frame rate and being an integer submultiple of a PWM frequency of the brightness control signal, such that a corresponding frame period of the target frame rate is an integer multiple of a PWM period of the brightness control signal; as well as Frames are transmitted to the display panel for display based on the target frame rate such that a frame period of each frame is aligned with a corresponding PWM cycle of the brightness control signal.

8. The system according to claim 7, wherein: The display control subsystem is further configured to: In response to detecting a delay in rendering of the first frame based on the target frame rate, a compensatory variable refresh rate (VRR) scheme is implemented, which maintains an effective PWM duty cycle of the brightness control signal during each display frame period in at least a subset of frame periods consistent with the delay in rendering.

9. The system according to claim 8, wherein: The compensatory variable refresh rate VRR scheme includes two different modes for compensating for delays in rendering.

10. The system according to claim 8, wherein: The display control subsystem is used to implement the compensatory variable refresh rate (VRR) scheme by implementing a frame insertion mode, including: Displaying a second frame at the target frame rate within a first frame period, the second frame being rendered immediately before the first frame; In response to detecting the delay in rendering of the first frame, providing the second frame again for display at a maximum frame rate within a second frame period, the second frame period starting from the termination of the first frame period and being an integer multiple of the PWM period of the brightness control signal; and The first frame is displayed at the target frame rate during a third frame period, and the third frame period starts from the end of the second frame period.

11. The system according to claim 8, wherein: The display control subsystem is used to implement the compensatory variable refresh rate (VRR) scheme by implementing a frame stretching mode, including: Displaying a second frame at the target frame rate within a first frame period, the second frame being rendered immediately before the first frame; determining a scan-in delay, the scan-in delay being an integer multiple of a PWM period and representing a delay between scan-in of a frame into a frame buffer and scan-out of the frame from the frame buffer to the display panel; In response to detecting the delay in rendering of the first frame, providing the first frame for display within a second frame period, the second frame period beginning at a termination of the first frame period and equal to the first frame period plus the scan-in delay; and A third frame is displayed at the target frame rate in a third frame period, the third frame period starting from the termination of the second frame period.

12. The system according to any one of claims 7 to 11, further comprising: The display panel, wherein: The display panel is a transmissive display panel, and the brightness control signal is a backlight control signal for the transmissive display panel; or The display panel is an emissive display panel, and the brightness control signal is an emission control signal for the emissive display panel.

13. A method comprising: controlling the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of a brightness control signal supplied to the display panel; as well as providing frames at a variable refresh rate for display at the display panel such that the start of each frame period is aligned with a corresponding PWM cycle of the brightness control signal and such that each frame period spans an integer multiple of the PWM cycle of the brightness control signal; as well as In response to detecting a delay in rendering of the first frame based on the target frame rate, a compensatory variable refresh rate (VRR) scheme is implemented that maintains an effective PWM duty cycle of the brightness control signal within each display frame period.

14. The method according to claim 13, further comprising: determining a maximum frame rate and a minimum frame rate, wherein the maximum frame rate and the minimum frame rate are integer submultiples of a PWM frequency of the brightness control signal; as well as A frame rate between the minimum frame rate and the maximum frame rate is selected as a target frame rate for providing frames for display, and the target frame rate is an integer submultiple of the PWM frequency.

15. The method of claim 13, wherein: The display panel is a transmissive display panel, and the brightness control signal is a backlight control signal for the transmissive display panel; or The display panel is an emissive display panel, and the brightness control signal is an emission control signal for the emissive display panel.

16. A system for performing the method according to any one of claims 13 to 15.

17. A system comprising: a frame rendering subsystem configured to render a sequence of frames at a variable rate; as well as A display control subsystem is coupled to the frame rendering subsystem and can be coupled to a display panel, the display control subsystem being configured to: providing a brightness control signal to the display panel, the brightness control signal being configured to control the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of the brightness control signal; providing a first frame at a target frame rate for display at the display panel during a first frame period, the target frame rate being an integer submultiple of a PWM frequency of the brightness control signal; as well as In response to detecting a delay in rendering of the second frame based on the target frame rate: providing the first frame again for display at a maximum frame rate in a second frame period, the second frame period starting from the end of the first frame period, being an integer multiple of the PWM period of the brightness control signal and being aligned with a corresponding PWM cycle of the brightness control signal; as well as The second frame is provided for display at the target frame rate during a third frame period, the third frame period starting from the termination of the second frame period.

18. A method of operating a system according to claim 17.

19. A system comprising: a frame rendering subsystem configured to render a sequence of frames at a variable rate; as well as A display control subsystem is coupled to the frame rendering subsystem and can be coupled to a display panel, the display control subsystem being configured to: providing a brightness control signal to the display panel, the brightness control signal being configured to control the brightness of a frame displayed at the display panel via pulse width modulation (PWM) of the brightness control signal; providing a first frame at a target frame rate for display at the display panel during a first frame period, the target frame rate being an integer submultiple of a PWM frequency of the brightness control signal; determining a scan-in delay, the scan-in delay being an integer multiple of a PWM period of the brightness control signal and representing a delay between scanning a frame into a frame buffer and scanning the frame from the frame buffer out to the display panel; as well as In response to detecting a delay in rendering of the second frame based on the target frame rate: providing the second frame for display during a second frame period, the second frame period starting from the end of the first frame period, being equal to the sum of the first frame period and the scan-in delay, and being aligned with a corresponding PWM cycle of the brightness control signal; as well as A third frame is displayed at the target frame rate in a third frame period, the third frame period starting from the termination of the second frame period.

20. A method of operating a system according to claim 19.

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