Tri-state programming of memory cells

Abstract

The present disclosure includes apparatuses, methods, and systems for tri-state programming of memory cells. Embodiments include a memory having a plurality of memory cells and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by: applying a voltage pulse to the memory cell; determining whether the memory cell is flipped back in response to the applied voltage pulse; and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell is flipped back.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly to tri-state programming of memory cells. BACKGROUND

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices and / or external removable devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistive variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

[0003] Memory devices can be used as volatile and non-volatile memory in a wide range of electronic applications, including personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular phones, portable music players such as MP3 players and movie players, and other electronic devices.

[0004] Resistive variable memory devices can include resistive variable memory cells that can store data based on a resistive state of a storage element, such as a memory element having a variable resistance. As such, a resistive variable memory cell can be programmed to store data corresponding to a target data state by changing a resistance level of the memory element. A resistive variable memory cell can be programmed to a target data state (e.g., corresponding to a particular resistive state) by applying an electric field source or energy source, such as a positive or negative electrical pulse (e.g., a positive or negative voltage or current pulse), to the cell (e.g., to a memory element of the cell) for a particular duration. The state of a resistive variable memory cell can be determined by sensing a current through the cell in response to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.

[0005] Various memory arrays can be organized in a cross-point architecture in which memory cells (e.g., resistive variable cells) are located at intersections of first and second signal lines used to access the cells (e.g., at intersections of word lines and bit lines). Some resistive variable memory cells can include a selection element (e.g., a diode, transistor, or other switching device) in series with a storage element (e.g., a phase change material, metal oxide material, and / or some other material that can be programmed to different resistance levels). Some resistive variable memory cells (which can be referred to as self- selecting memory cells) include a single material that can function as both a selection element and a storage element of the memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A three-dimensional view of an example of a memory array according to an embodiment of the disclosure.

[0007] Figure 2A Illustrating threshold voltage distributions associated with memory states of memory cells according to an embodiment of the disclosure.

[0008] Figure 2B An example of a current versus voltage curve corresponding to a memory state of Figure 2A according to an embodiment of the disclosure.

[0009] Figure 2C An example of a current versus voltage curve corresponding to another memory state of Figure 2A according to an embodiment of the disclosure.

[0010] Figure 3 Illustrating an example of a portion of a memory array and associated circuitry according to an embodiment of the disclosure.

[0011] Figure 4 Illustrating an example of current through a memory cell according to an embodiment of the disclosure.

[0012] Figures 5A-5B Illustrating an example of programming a memory cell to a third data state according to an embodiment of the disclosure.

[0013] Figure 6 A block diagram illustration of an example device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0014] The present disclosure includes apparatuses, methods, and systems for tri-state programming of memory cells. One embodiment includes a memory having a plurality of memory cells and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell toggles in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell toggled.

[0015] Embodiments of the present disclosure can provide benefits such as increased density, reduced cost, reduced power consumption, and / or faster and / or more complex operations compared to previous memory devices. For example, previous approaches for programming resistive variable memory cells, such as self-selecting memory cells, can be able to produce two different states of the cell such that the cell can be programmed to one of two possible data states, such as state 0 or state 1. However, programming approaches for resistive variable memory cells according to the present disclosure can produce an additional (e.g., third) state of the cell such that the cell can be programmed to one of three possible data states.

[0016] This tri-state programming can be suitable for supporting complex memory operations, such as machine learning applications, in which data is encoded and a matching function or partial matching function (e.g., Hamming distance) is computed. For example, this tri-state programming can support computation of a matching function or partial matching function for an input vector model having many stored vectors in an efficient manner.

[0017] Furthermore, this tri-state programming can be suitable for reducing cost and / or increasing density of standard memory applications. For example, this tri-state programming can reduce the number of bits needed to encode an equivalent number of data states with previous two-state programming approaches (e.g., by 63%). These additional bits can be used for error correction code (ECC) and / or data redundancy operations, for example.

[0018] As used herein, “a” or “an” can mean one or more, and “multiple” can mean two or more. For example, a memory device can mean one or more memory devices, and multiple memory devices can mean two or more memory devices. Additionally, as used herein, designators “N” and “M” as used with reference to figures in the drawings indicate that a particular feature so designated can be included in multiple embodiments of the present disclosure.

[0019] The figures herein follow a numbering convention in which the first digit corresponds to the figure number and the remaining digits identify the element or component within the figure. Similar elements or components between different figures can be identified by the use of similar digits.

[0020] Figure 1 is a three-dimensional view of an example of a memory array 100, such as a cross-point memory array, according to an embodiment of the disclosure. The memory array 100 can include a plurality of first signal lines (e.g., first access lines), which can be referred to as word lines 110-0 to 110-N, and a plurality of second signal lines (e.g., second access lines), which can be referred to as bit lines 120-0 to 120-M, that cross each other (e.g., intersect in different planes). For example, each of the word lines 110-0 to 110-N can cross the bit lines 120-0 to 120-M. Memory cells 125 can be between the bit lines and the word lines (e.g., at each bit / word line intersection).

[0021] For example, the memory cells 125 can be resistive variable memory cells. The memory cells 125 can include a material that can be programmed to different data states. In some examples, each of the memory cells 125 can include a single material that can act as a selection element (e.g., switching material) and a storage element, such that each memory cell 125 can act as both a selector device and a memory element. Such a memory cell can be referred to herein as a self-selecting memory cell. For example, each memory cell can include a chalcogenide material that can be formed of various doped or undoped materials, can or can not be a phase change material, and / or can or can not undergo a phase change during reading and / or writing of the memory cell. In some examples, each memory cell 125 can include a ternary composition that can include selenium (Se), arsenic (As), and germanium (Ge), a quaternary composition that can include silicon (Si), Se, As, and Ge, and / or the like.

[0022] In various embodiments, a threshold voltage of a memory cell 125 can snap back in response to a magnitude of an applied voltage difference thereon exceeding a threshold voltage thereof. Such a memory cell can be referred to as a snap-back memory cell. For example, a memory cell 125 can change (e.g., snap back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., lower impedance) state in response to an applied voltage difference exceeding a threshold voltage. For example, a memory cell snap-back can refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to a voltage difference applied across the memory cell being greater than a threshold voltage of the memory cell. The threshold voltage of a memory cell snap-back can be referred to as, for example, a snap-back event.

[0023] Figure 2A An illustration of threshold distributions associated with various states of a memory cell (e.g., a memory cell 125) as illustrated in Figure 1 For example, as shown in Figure 2A For example, as shown inFigure 2A This describes the distribution of threshold voltages associated with three possible data states that are programmable in a memory cell.

[0024] exist Figure 2A In this context, the voltage VCELL can correspond to the voltage difference applied to a memory cell (e.g., on the memory cell), such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL - VWL). Threshold voltage distributions (e.g., ranges) 200-1, 200-2, 201-1, 201-2, 202-T1, and 202-T2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a specific state. Figure 2A The distribution described in the text corresponds to further combination Figure 2B and 2C The described current and voltage curves illustrate the sudden return asymmetry associated with the assigned data state.

[0025] In some instances, the threshold voltage of memory cell 125 in a specific state can be asymmetric for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of memory cell 125 programmed to state 0 or state 1 may have different values ​​in one polarity than in the opposite polarity. For example, in Figure 2A In the example described, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) whose magnitudes are greater with respect to negative polarity than positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 200-1 and 200-2) whose magnitudes are greater with respect to positive polarity than negative polarity. In this example, the applied voltage magnitude sufficient to cause a sudden return of memory cell 125 may differ from other applied voltage magnitudes (e.g., higher or lower) for one applied voltage polarity.

[0026] In some instances, the threshold voltage of memory cell 125 in a specific state can be symmetrical with respect to different polarities, such as... Figure 2A As shown in the diagram. For example, the threshold voltage of memory cell 125 programmed to state T can have the same value under opposite polarities. For example, in Figure 2A In the example described, the third data state (e.g., state T) is associated with a symmetrical threshold voltage distribution (e.g., threshold voltage distributions 202-T1 and 202-T2) whose magnitudes are substantially equal (e.g., higher) for both positive and negative polarities. In this example, the applied voltage magnitude sufficient to cause a sudden return of memory cell 125 may be the same for different applied voltage polarities.

[0027] Figure 2A The demarcation voltages VDM1 and VDM2 are illustrated that can be used to determine the state of a memory cell (e.g., to distinguish between states as part of a read operation). In this example, VDM1 is a positive voltage used to distinguish between cells in state 0 (e.g., in threshold voltage distribution 201-2) and cells in state 1 (e.g., threshold voltage distribution 200-2) or state T (e.g., threshold voltage distribution 202-T2). Similarly, VDM2 is a negative voltage used to distinguish between cells in state 1 (e.g., threshold voltage distribution 200-1) and cells in state 0 (e.g., threshold voltage distribution 201-1) or state T (e.g., threshold voltage distribution 202-T1). In Figures 2A-2C In the example of FIG. 2, memory cells 125 in positive state 1 or T do not snap back in response to the application of VDM1; memory cells 125 in positive state 0 snap back in response to the application of VDM1; memory cells 125 in negative state 1 snap back in response to the application of VDM2; and memory cells 125 in negative state 0 or T do not snap back in response to the application of VDM2.

[0028] Embodiments are not limited to Figure 2A the examples illustrated in FIG. 2. For example, the designation of state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be designated as state 1, and distributions 200-1 and 200-2 can be designated as state 0).

[0029] Figure 2B and 2C are examples of current versus voltage curves corresponding to memory states of Figure 2A In this example, the curves in FIG. 2 correspond to cells in which state 1 is designated as the higher threshold voltage state in a particular polarity (in this example, the positive polarity direction), and in which state 0 is designated as the higher threshold voltage state in the opposite polarity (in this example, the negative polarity direction). As noted above, the state designations can be interchanged such that state 0 can correspond to the higher threshold voltage state in the positive polarity direction, with state 1 corresponding to the higher threshold voltage state in the negative direction. Figure 2B 2C

[0030] Figure 2B and 2C illustrates a memory cell snapping back as described herein. VCELL can represent an applied voltage on a memory cell. For example, VCELL can be a voltage applied to a top electrode corresponding to a cell minus a voltage applied to a bottom electrode corresponding to a cell (e.g., via respective word lines and bit lines). As Figure 2B ​​As shown, in response to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 200-2) remains in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be called a backsliding event, which occurs when the voltage applied to the cell (in a specific polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be called the backsliding voltage. Figure 2B In this context, voltage Vtst01 corresponds to the sudden return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 200-1). That is, as... Figure 2B As shown, when VCELL crosses Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

[0031] Similarly, such as Figure 2C As shown, in response to an applied negative polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 201-1) remains in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly reverts to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the sudden return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown in the figure, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell suddenly changes from a high-impedance non-conductive state to a low-impedance conductive state.

[0032] In various situations, a backslip event can cause a memory cell to switch states. For example, if a VCELL exceeding Vtst02 is applied to a state 1 cell, the resulting backslip event can reduce the cell's threshold voltage to a level below VDM1, which will cause the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Thus, in several embodiments, a backslip event can be used to write a cell to the opposite state (e.g., from state 1 to state 0, and vice versa).

[0033] In one embodiment of this disclosure, the memory cell (e.g. Figure 1The memory cell 125) described in the middle can be programmed to one of three possible data states (e.g., state 0, state 1, or state T) by applying a voltage pulse to the memory cell, determining whether the memory cell has flipped in response to the applied voltage pulse, and applying (e.g., determining whether to apply) an additional voltage pulse to the memory cell based on the determination of whether the memory cell has flipped. For example, the current data state of the memory cell can be determined based on the determination of whether the memory cell has flipped, and the additional voltage pulse can be applied to the memory cell based on the determination of the current data state of the cell (e.g., it can be determined whether to apply the additional voltage pulse to the memory cell).

[0034] For example, a bias pulse (e.g., VCELL) having a magnitude high enough to cause (e.g., capable of causing) the memory cell to flip can be applied to the cell. For example, the bias pulse can include a voltage pulse having a first polarity and / or a voltage pulse having a second polarity opposite the first polarity. For example, applying the bias pulse can include applying a positive 5.5 volt (V) pulse and / or a negative 5.5 V pulse to the memory cell.

[0035] Once (e.g., if) the memory cell flips to a conductive state in response to the applied bias pulse, a current pulse (e.g., a transient current) can flow through the memory cell. After a particular amount of time, the transient current through the cell can dissipate, and a DC current can be established across the cell. An example of this current through the memory cell will be further described herein (e.g., in connection with Figure 4 ).

[0036] After a voltage pulse (e.g., a bias pulse) has been applied to the memory cell, it can be determined whether the memory cell has flipped in response to the applied voltage pulse (e.g., in response to the positive pulse or the negative pulse). This determination can be made by, for example, sensing a voltage change associated with the memory cell (e.g., on a signal line coupled to the cell) that has occurred in response to the applied voltage pulse. For example, sensing this voltage change can indicate that the memory cell has flipped, while sensing no voltage change can indicate that a flip event has not occurred. An example of this determination of whether the memory cell has flipped and circuitry that can be used to perform this determination will be further described herein (e.g., in connection with Figure 3 ).

[0037] The current data state of the memory cell can then be determined based on the determination of whether the memory cell has flipped. For example, a data value indicative of the current data state (e.g., stored in a latch) can be latched when it is determined that the memory cell has flipped, as will be further described herein (e.g., in connection with Figure 3 ).

[0038] After determining that the memory cell has flipped back (e.g., after a delay to allow transient current to dissipate through the memory cell), the current to the memory cell (e.g., current through a signal line coupled to the memory cell) can be disconnected (e.g., inhibited). An additional voltage pulse can then be applied to the memory cell based on the determination of whether the memory cell has flipped back (e.g., based on a determination of the current data state of the memory cell) (e.g., it can be determined whether to apply an additional voltage pulse to the memory cell). For example, the additional voltage pulse can be a single short pulse or can include multiple pulses based on whether the memory cell has flipped back, and / or can be positive or negative polarity based on whether the memory cell has flipped back, as will be further described herein. As used herein, a short pulse can refer to a pulse having a duration that is shorter than a duration of a bias. For example, the additional voltage pulse can have a magnitude that is the same as a magnitude of the bias. As an additional example, the initial bias pulse can be extended after determining that the memory cell has flipped back.

[0039] Applying an additional voltage pulse (or extending the initial bias pulse) to a memory cell that is currently in a 0 state or a 1 state can not change the magnitude of the threshold voltage of the cell when the threshold voltage is of a first polarity, but can change the magnitude of the threshold voltage of the cell when the threshold voltage is of a second polarity that is opposite the first polarity. For example, the additional voltage pulse can not change a high magnitude threshold voltage having one polarity, but can cause a low magnitude threshold voltage having an opposite polarity to increase from the low magnitude to the high magnitude. For example, the additional voltage pulse can not change threshold voltages within distribution 201-1, but can cause threshold voltages to move from distribution 201-2 to 200-2. Similarly, the additional voltage pulse can not change threshold voltages within distribution 200-2, but can cause threshold voltages to move from distribution 200-1 to 201-1.

[0040] In contrast, applying an additional voltage pulse to a memory cell that is currently in a T state can not change the high magnitude of the threshold voltage of the cell, regardless of the polarity of the threshold voltage. For example, the additional voltage pulse can not change threshold voltages within distribution 202-T1 or 202-T2. As such, embodiments of the disclosure can also program a memory cell to a third data state (e.g., state T) in addition to states 0 and 1.

[0041] As an example, to program a memory cell to state T, a first bias (e.g., detection bias) pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell has flipped back in response to the applied first bias pulse. If it is determined (e.g., detected) that the memory cell has flipped back, the current data state of the cell can be 0. Upon determining that the memory cell has flipped back in response to the first bias pulse (e.g., the current data state of the cell is 0), a single (e.g., one) shorter additional pulse having a negative polarity can be applied to the cell to program the cell to state T.

[0042] If no toggle of the memory cell in response to the first bias pulse is detected, the current data state of the cell can be 1 or T. Upon determining that the memory cell did not toggle in response to the first bias pulse, a second bias pulse having a negative polarity can be applied to the cell, and it can be determined whether the cell toggled in response to the applied second bias pulse.

[0043] If it is determined that the memory cell has toggled in response to the second bias pulse, the current data state of the cell can be 1. Upon determining that the memory cell has toggled in response to the second bias pulse (e.g., the current data state of the cell is 1), a single, short additional voltage pulse having a positive polarity can be applied to the cell to program the cell to state T. If no toggle of the memory cell in response to the second bias pulse is detected, the current data state of the cell can be T, and no additional pulse can be needed to program the cell to state T. Thus, upon determining that the memory cell has not toggled in response to the second bias pulse (e.g., the current data state of the cell is T), no additional short voltage pulse can be applied. A further example of programming a memory cell to state T will be further described herein (e.g., in connection with FIG. 3). Figures 5A-5B ).

[0044] Additionally or alternatively, a memory cell can be programmed to state T without applying one or more bias pulses to the cell (e.g., without attempting to detect a toggle of the memory cell or a current data state of the memory cell). For example, two short voltage pulses having opposite polarities (e.g., one positive and one negative, or vice versa) can be applied to a memory cell to program the cell to state T, regardless of the current data state of the cell.

[0045] As an additional example, to program a memory cell to state 0, a bias pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell toggled in response to the applied bias pulse. If it is determined (e.g., detected) that the memory cell has toggled, the current data state of the cell can be 0, and no additional pulse can be needed to program the cell to state 0. Thus, upon determining that the memory cell has toggled in response to the bias pulse (e.g., the current data state of the cell is 0), no additional voltage pulse can be applied to the memory cell.

[0046] If no snapback of the memory cell in response to the bias pulse is detected, the current data state of the cell can be 1 or T. Upon determining that the memory cell did not snapback in response to the bias pulse (e.g., the current data state of the cell is 1 or T), a plurality of shorter additional voltage pulses each having a positive polarity can be applied to the cell to program the cell to state 0. For example, six shorter additional positive voltage pulses can be applied to the cell. However, embodiments of the present disclosure are not limited to a particular number of additional voltage pulses. Further, as an additional example, a single voltage pulse having a greater magnitude and / or duration than the bias pulse can be applied to the cell to program the cell to state 0.

[0047] Additionally or alternatively, the memory cell can be programmed to state 0 without applying a bias pulse to the cell (e.g., without attempting to detect a snapback of the memory cell or a current data state of the memory cell). For example, a plurality of shorter voltage pulses each having a positive polarity can be applied to the memory cell to program the cell to state 0, regardless of the current data state of the cell. Further, as an additional example, a single voltage pulse having a greater magnitude and / or duration than the bias pulse can be applied to the cell to program the cell to state 0.

[0048] As an additional example, to program the memory cell to state 1, a first bias pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell snapped back in response to the applied first bias pulse. If it is determined (e.g., detected) that the memory cell has snapped back, the current data state of the cell can be 0. Upon determining that the memory cell has snapped back in response to the first bias pulse (e.g., the current data state of the cell is 0), a plurality of shorter additional voltage pulses each having a negative polarity can be applied to the cell to program the cell to state 1. For example, six shorter additional negative voltage pulses can be applied to the cell. However, embodiments of the present disclosure are not limited to a particular number of additional voltage pulses. Further, as an additional example, a single voltage pulse having a greater magnitude and / or duration than the first bias pulse can be applied to the cell to program the cell to state 1.

[0049] If no snapback of the memory cell in response to the first bias pulse is detected, the current data state of the cell can be 1 or T. Upon determining that the memory cell did not snapback in response to the first bias pulse, a second bias pulse having a negative polarity can be applied to the cell, and it can be determined whether the cell snapped back in response to the applied second bias pulse.

[0050] If it is determined that the memory cell has flipped in response to the second bias pulse, the current data state of the cell can be 1. Upon determining that the memory cell has flipped in response to the second bias pulse (e.g., the current data state of the cell is 1), and possibly without the need for an additional negative voltage pulse to program the cell to state 1. Thus, upon determining that the memory cell has flipped in response to the second bias pulse (e.g., the current data state of the cell is 1), an additional negative voltage pulse can not be applied to the memory cell.

[0051] If no flip of the memory cell in response to the second bias pulse is detected, the current data state of the cell can be T. Upon determining that the memory cell has not flipped in response to the second bias pulse (e.g., the current data state of the cell is T), a plurality of shorter additional negative voltage pulses can be applied to the cell to program the cell to state 1. Further, as an additional example, a single voltage pulse having a greater magnitude and / or duration than the second bias pulse can be applied to the cell to program the cell to state 1.

[0052] Additionally or alternatively, the memory cell can be programmed to state 1 without applying one or more bias pulses to the cell (e.g., without attempting to detect a flip of the memory cell or the current data state of the memory cell). For example, a plurality of shorter voltage pulses each having a negative polarity can be applied to the memory cell to program the cell to state 1, regardless of the current data state of the cell. Further, as an additional example, a single voltage pulse having a greater magnitude and / or duration than the one or more bias pulses can be applied to the cell to program the cell to state 1.

[0053] Figure 3 An example of a portion of a memory array 300 and associated circuitry for detecting a flip event in accordance with an embodiment of the present disclosure is illustrated. The memory array 300 can be a portion of the memory array 100 previously described in connection with Figure 1 A portion of the memory array 100 described. The memory cell 325 is coupled to the word line 310 and the bit line 320, and can be operated as described herein.

[0054] Figure 3The example shown in FIG. 3 includes a driver 350 (e.g., a word line driver 350) coupled to the word line 310. The word line driver 350 can supply bipolar (e.g., positive and negative) current and / or voltage signals to the word line 310. A sense amplifier 330, which can include a cross-coupled latch, is coupled to the word line driver 350 and can detect positive and negative current and / or positive and negative voltage on the word line 310. In some examples, the sense amplifier 330 can be part of (e.g., included in) the word line driver 350. For example, the word line driver 350 can include the sensing functionality of the sense amplifier 330. A bit line driver 352 is coupled to the bit line 320 to supply positive and / or negative current and / or voltage signals to the bit line 320.

[0055] The sense amplifier 330 and the word line driver 350 are coupled to a latch 340 that can be used to store a data value that indicates whether a snapback event of the memory cell 325 has occurred in response to the applied voltage difference. For example, an output signal 354 of the sense amplifier 330 is coupled to the latch 340 such that, in response to detecting a snapback of the memory cell 325 via the sense amplifier 330, the output signal 354 causes the appropriate data value to be latched in the latch 340 (e.g., a data value of “1” or “0,” depending on which data value is used to indicate a detected snapback event). As an example, if a latched data value of “1” is used to indicate a detected snapback event, then the signal 354 will cause the latch 340 to latch a logical data value of 1 in response to a detected snapback of the cell 325, and vice versa.

[0056] When a positive voltage difference VDM1 is applied to the memory cell 325 (e.g., a word line voltage VWL1 is low and a bit line voltage VBL1 is high) and the memory cell 325 stores a state of 0, the voltage difference VDM1 can be greater than a threshold voltage Vtst12 Figure 2C ), and the memory cell 325 can snapback to a conductive state, resulting in Figure 2C a positive current from the bit line 320 through the memory cell 325 to the word line 310 shown in FIG. 3. The sense amplifier 330 can detect this current and / or a voltage associated therewith, for example, and can output a signal 354 to the latch 340 in response to detecting this current and / or voltage. For example, the signal 354 can indicate to the latch 340 (e.g., by having a logical high value) that the current is positive and, thus, the word line voltage is high. In response to the signal 354 indicating that the word line voltage is high, the latch 340 can output a signal 356 (e.g., a voltage) to circuitry 358 of the word line driver 350 or circuitry coupled to the word line driver 350 that turns off (e.g., inhibits) the current through the word line 310 and, thus, the memory cell 325.

[0057] In an example, when a negative voltage difference VDM2 is applied to memory cell 325 (e.g., word line voltage VwL2 is high and bit line voltage VBL2 is low) and memory cell 325 stores state 1, voltage difference VDM2 (in the negative direction) is greater than threshold voltage Vtst01 Figure 2B ), and memory cell 328 can snap back to a conductive state, resulting in a negative current from word line 310 through memory cell 325 to bit line 320, as shown in Figure 2B Sensing amplifier 330 can detect this current and / or a voltage associated therewith, for example, and can output signal 354 to latch 340 in response to detecting this current and / or voltage. For example, signal 354 can indicate to latch 340 that the current is negative (e.g., by having a logical low value), and thus the word line voltage is low. In response to signal 354 indicating that the word line voltage is low, latch 340 can output signal 360 (e.g., a voltage) to circuitry 362 of word line driver 350 or circuitry 362 coupled to word line driver 350, which signal 360 turns off the current through word line 310. In some examples, sensing amplifier 330, as well as circuitry 358 and 362, can be referred to as detection circuitry.

[0058] Figure 4 An example of current through a memory cell according to an embodiment of the disclosure is illustrated in the form of graph 435. For example, graph 435 can illustrate current through a memory cell during an operation to program the memory cell to one of three possible data states according to the disclosure. For example, the memory cell can be memory cell 325 and / or 125 previously described in connection with Figure 3 and 1 respectively.

[0059] At time tl, shown in Figure 4 , a bias pulse is applied to the memory cell having a magnitude high enough to cause the memory cell to snap back. When the memory cell snaps back, a current pulse 437 flows through the memory cell, as illustrated in Figure 4 , which can be used to detect the snap back event, as previously described herein. As shown in Figure 4 , the current then dissipates after time tl, and a DC current is established on the memory cell.

[0060] At time t2, shown in Figure 4 (e.g., after the memory cell has snapped back and the snap back event has been detected), the current to the memory cell is turned off (e.g., inhibited). When the current to the memory cell is turned off, no current flows through the cell, as illustrated in Figure 4 .

[0061] At time t2, shown in Figure 4At time t3, as shown in the middle, an additional voltage pulse can be applied to the memory cell (e.g., after the current flow to the memory cell has been turned off). The additional voltage pulse can be applied to the memory cell based on a determination that the memory cell has popped back, as previously described herein. Further, as Figure 4 illustrated in the middle, the additional pulse is applied to the memory cell for a short amount of time (e.g., from time t3 to time t4) and can have a negative polarity or a positive polarity, as previously described herein. As an additional example, the additional pulse can have a longer duration and / or include multiple voltage pulses, as previously described herein.

[0062] When the additional voltage pulse is applied to the memory cell, an additional current pulse 439 flows through the memory cell, as Figure 4 illustrated in the middle. The additional current pulse 439 can cause the memory cell to be programmed to one of three possible data states, as previously described herein.

[0063] Figures 5A-5B An example of programming a memory cell to a third data state (e.g., state T) is illustrated in accordance with an embodiment of the present disclosure. For example, Figure 5A An example 551 of programming a memory cell that is currently in a first data state (e.g., state 0) to state T is illustrated, and Figure 5B An example 553 of programming a memory cell that is currently in a second data state (e.g., state 1) to state T is illustrated. For example, the memory cell can be the memory cell 325 and / or 125 previously described in connection with Figure 3 and 1 Further, Figures 5A-5B The demarcation voltages VDM1 and VDM2 illustrated in the middle can be similar to the demarcation voltages VDM1 and VDM2 previously described in connection with Figures 2A-2C Further, although the high magnitude threshold voltage distribution associated with state T is shown in Figures 5A-5B as being separate from the high magnitude threshold voltage distributions associated with states 0 and 1, such distributions can overlap, as in the examples previously described in connection with Figure 2A

[0064] As shown in the example illustrated in Figure 5A applying a single short voltage pulse to a memory cell that is currently in state 0, having a negative polarity and a magnitude greater than VDM1 and VDM2 (e.g., sufficient to reach the high threshold voltage state of the target memory cell) can program the cell to state T (e.g., change the state of the cell from 0 to T). For example, as Figure 5A ​As shown in the middle, a single shorter voltage pulse can not change the threshold voltage of a cell observed (e.g., measured) with a high magnitude threshold in the negative direction. However, the threshold voltage of a cell observed with a low magnitude threshold in the positive direction can increase to a high magnitude threshold, as shown in the right. Figure 5A As shown in the middle.

[0065] As Figure 5B As shown in the example illustrated in the middle, applying a single shorter voltage pulse with a positive polarity and a magnitude greater than VDM 1 and VDM2 (e.g., sufficient to reach a high threshold voltage state of a target memory cell) to a memory cell currently in state 1 can program the cell to state T (e.g., change the state of the cell from 1 to T). For example, as shown in the right, the threshold voltage of the cell observed with a low magnitude threshold in the positive direction can increase to a high magnitude threshold. Figure 5B As shown in the middle, a single shorter voltage pulse can not change the threshold voltage of a cell observed (e.g., measured) with a high magnitude threshold in the negative direction. However, the threshold voltage of a cell observed with a low magnitude threshold in the positive direction can increase to a high magnitude threshold, as shown in the right. Figure 5B As shown in the middle.

[0066] Figure 6 A block diagram illustration of an example device (e.g., electronic memory system 600) in accordance with an embodiment of the present disclosure. Memory system 600 includes a device, such as memory device 602; and a controller 604, such as a memory controller (e.g., host controller). Controller 604 can include, for example, a processor. Controller 604 can be coupled to, for example, a host and can receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host and can output data to the host.

[0067] Memory device 602 includes a memory array 606 of memory cells. For example, memory array 606 can include one or more of the memory arrays of memory cells disclosed herein, such as a cross-point array.

[0068] Memory device 602 includes address circuitry 608 to latch address signals provided via I / O connections 610 via I / O circuitry 612. The address signals are received and decoded by row decoder 614 and column decoder 616 to access memory array 606. For example, row decoder 614 and / or column decoder 616 can include drivers, such as drivers 350, as previously described in connection with Figure 3

[0069] ​The memory device 602 can sense (e.g., read) data in the memory array 606 by sensing voltage and / or current changes in a memory array column using sense / buffer circuitry, which in some examples can be read / latch circuitry 620. The read / latch circuitry 620 can read and latch data from the memory array 606. Included is I / O circuitry 612 for bidirectional data communication with the controller 604 via I / O connections 610. Included is write circuitry 622 to write data to the memory array 606.

[0070] The control circuitry 624 can decode signals provided by control connections 626 from the controller 604. Such signals can include chip signals to control operations on the memory array 606, including data read and data write operations, write enable signals, and address latch signals.

[0071] The control circuitry 624 may, for example, be included in the controller 604. The controller 604 can include other circuitry, firmware, software, or the like, whether alone or in combination. The controller 604 can be an external controller (e.g., in a die separate from the memory array 606, in whole or in part) or an internal controller (e.g., included in the same die as the memory array 606). For example, an internal controller can be a state machine or a memory sequencer.

[0072] In some examples, the controller 604 can be configured to cause the memory device 602 to perform at least the methods disclosed herein, such as programming memory cells of the array 606 to one of three possible data states. In some examples, the memory device 602 can include previously described circuitry. For example, the memory device 602 can include the sense amplifier circuitry and latches disclosed herein, such as the sense amplifier 330 and the latch 340. Figure 3 The described circuitry. For example, the memory device 602 can include the sense amplifier circuitry and latches disclosed herein, such as the sense amplifier 330 and the latch 340.

[0073] As used herein, the term“coupled” can include electrically coupled, directly coupled, and / or indirectly coupled and / or connected, without passing through an intervening element (e.g., by direct physical contact). The term coupled can further include two or more elements that cooperate or interact with each other (e.g., as in a cause an effect relationship).

[0074] Those of skill in the art will appreciate that additional circuitry and signals can be provided, and that the memory system 600 has been simplified for Figure 6 functionality of the various block components described with reference to Figure 6 may necessarily be segregated to distinguish components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functions of multiple components described as separate components.Figure 6 Alternatively, one or more components or component parts of an integrated circuit device can be combined to perform the functionality of a single block component. Figure 6 Alternatively, one or more components or component parts of an integrated circuit device can be combined to perform the functionality of a single block component.

[0075] While specific embodiments have been illustrated and described herein, it will be appreciated that various arrangements can be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description is intended to be illustrative, and not restrictive, of the disclosure. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the disclosure includes other applications that have not been described in detail herein. Accordingly, the scope and spirit of the disclosure should be judged in terms of the claims below, and the full scope of equivalents thereof, instead of being limited only by the specifics of which the claims were drafted.

[0076] In the foregoing embodiments, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of the disclosure should not be interpreted to mean that disclosed embodiments of the disclosure must use more features than are explicitly recited in each claim. Indeed, as reflected in the claims below, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the claims below are hereby incorporated into the embodiments, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus (600) for tri-state programming, comprising: a memory (100, 300, 606) having a plurality of memory cells (125, 325); and circuitry (604) configured to program a memory cell (125, 325) of the plurality of memory cells (125, 325) to one of three data states by: applying a first voltage pulse having a first polarity to the memory cell (125, 325); determining whether the memory cell (125, 325) flips back in response to the applied first voltage pulse; and upon determining that the memory cell (125, 325) does not flip back in response to the applied first voltage pulse: applying a second voltage pulse to the memory cell (125, 325), wherein the second voltage pulse has a second polarity opposite the first polarity; determining whether the memory cell (125, 325) flips back in response to the applied second voltage pulse; and upon determining that the memory cell (125, 325) does not flip back in response to the applied second voltage pulse, applying a plurality of additional voltage pulses to the memory cell (125, 325), wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein each of the plurality of additional voltage pulses has a duration shorter than a duration of the first voltage pulse and a duration of the second voltage pulse.

2. The apparatus of claim 1, wherein the circuitry is configured to turn off a current (437) to the memory cell after determining that the memory cell flips back in response to the applied first voltage pulse.

3. The apparatus of claim 1 or 2, wherein the circuitry comprises sensing circuitry having a sense amplifier (330) configured to sense a flip back of the memory cell in response to the applied first voltage pulse.

4. The apparatus of claim 1 or 2, wherein each of the plurality of memory cells is a self-selecting memory cell, wherein a single material acts as a select element and a storage element.

5. The apparatus of claim 1 or 2, wherein the three data states include: a first data state associated with a first threshold voltage distribution having a magnitude greater for the first polarity than the second polarity; a second data state associated with a second threshold voltage distribution having a magnitude greater for the second polarity than the first polarity; and a third data state associated with a third threshold voltage distribution having a magnitude equal for the first polarity and the second polarity.

6. A method of operating a memory (100, 300, 606), comprising: programming a memory cell (125, 325) to one of three data states by: applying a first voltage pulse having a first polarity to the memory cell (125, 325); ​ determining whether the memory cell (125, 325) is responsive to the applied first voltage pulse; determining a current data state of the memory cell (125, 325) based on the determination of whether the memory cell (125, 325) is responsive; and when it is determined that the memory cell (125, 325) is not responsive to the applied first voltage pulse: applying a second voltage pulse to the memory cell (125, 325), wherein the second voltage pulse has a second polarity opposite the first polarity; determining whether the memory cell (125, 325) is responsive to the applied second voltage pulse; and when it is determined that the memory cell (125, 325) is not responsive to the applied second voltage pulse, applying a plurality of additional voltage pulses to the memory cell (125, 325), wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein each respective duration of the plurality of additional voltage pulses is shorter than a duration of the first voltage pulse and a duration of the second voltage pulse.

7. The method of claim 6, wherein: if a threshold voltage is of the first polarity, then applying the second voltage pulse to the memory cell does not change a magnitude of the threshold voltage of the memory cell; and if the threshold voltage is of the second polarity opposite the first polarity, then applying the second voltage pulse to the memory cell increases the magnitude of the threshold voltage of the memory cell.

8. The method of claim 6, wherein determining whether the memory cell is responsive to the applied first voltage pulse includes: sensing a voltage change associated with the memory cell in response to the applied first voltage pulse.

9. The method of claim 6, wherein the method further includes latching a data value, the data value indicative of the determined current data state of the memory cell.

10. An apparatus (600) for tri-state programming, comprising: a memory (100, 300, 606) having a plurality of memory cells (125, 325); and circuitry (604) configured to program a memory cell (125, 325) of the plurality of memory cells (125, 325) to one of three data states by: applying a first voltage pulse having a first polarity to the memory cell (125, 325); determining whether the memory cell (125, 325) is responsive to the applied first voltage pulse; and when it is determined that the memory cell (125, 325) is not responsive to the applied first voltage pulse: applying a second voltage pulse to the memory cell (125, 325), wherein the second voltage pulse has a second polarity opposite the first polarity; determining whether the memory cell (125, 325) is responsive to the applied second voltage pulse; applying a plurality of additional voltage pulses to the memory cell (125, 325), wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein each respective duration of the plurality of additional voltage pulses is shorter than the duration of the first voltage pulse and the duration of the second voltage pulse; and not applying the plurality of additional voltage pulses to the memory cell (125, 325) upon determining that the memory cell (125, 325) toggled in response to the applied second voltage pulse.

11. The apparatus of claim 10, wherein the one of the three data states is associated with a symmetric threshold voltage distribution (202-T1, 202-T2) having a magnitude equal for a positive polarity and the negative polarity.

12. A method of operating a memory (100, 300, 606), comprising: programming a memory cell (125, 325) to one of three data states by: applying a first voltage pulse having a first polarity to the memory cell (125, 325); determining whether the memory cell (125, 325) toggled in response to the applied first voltage pulse; and upon determining that the memory cell (125, 325) did not toggle in response to the applied first voltage pulse: applying a second voltage pulse to the memory cell (125, 325), wherein the second voltage pulse has a second polarity opposite the first polarity; determining whether the memory cell (125, 325) toggled in response to the applied second voltage pulse; and upon determining that the memory cell (125, 325) did not toggle in response to the applied second voltage pulse, applying a plurality of additional voltage pulses to the memory cell (125, 325), wherein each of the plurality of additional voltage pulses has a negative polarity, and wherein each respective duration of the plurality of additional voltage pulses is shorter than the duration of the first voltage pulse and the duration of the second voltage pulse.

13. The method of claim 12, wherein the method further includes programming the memory cell to the one of the three data states by: not applying the plurality of additional voltage pulses to the memory cell upon determining that the memory cell toggled in response to the applied second voltage pulse.

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