Three-dimensional stacked semiconductor assembly with near-zero bond wire thickness

Abstract

A semiconductor device package assembly and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes: (1) a substrate assembly having a front side and a back side opposite the first side, the substrate assembly having a first metallization structure at the front side, the first metallization structure being exposed in a contact area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) metal bumps that are at least partially located in recesses and are electrically coupled to the second metallization structure and the first metallization structure.

Description

Technical Field

[0001] The present technology relates to semiconductor assemblies having stackable semiconductor packages. More specifically, some embodiments of the present technology relate to semiconductor assemblies fabricated by a three-dimensional stacking (3DS) process. In such embodiments, semiconductor packages are directly electrically coupled to each other with a negligible (e.g., near-zero) bond line thickness (BLT) and without using through-silicon vias (TSVs). Background Art

[0002] Encapsulated semiconductor dies (including memory chips, microprocessor chips, logic chips, and imager chips) typically include semiconductor dies mounted on a substrate and encapsulated in a plastic protective cover. Individual semiconductor dies may include functional features (such as memory cells, processor circuits, imager devices, and other circuitry), as well as bond pads electrically connected to the functional features. Semiconductor manufacturers are constantly reducing the size of die packages to fit within the space constraints of electronic devices. One way to increase the processing power of semiconductor packages is to vertically stack multiple semiconductor dies on top of each other within a single package. Dies in such vertically stacked packages can be electrically interconnected by using TSVs (which require multiple processing steps, such as lithography, to fabricate). Brief Description of the Drawings

[0003] Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating the principles of the present technology.

[0004] Figure 1 is a schematic cross-sectional view of a semiconductor device package assembly according to the present technology.

[0005] Figures 2A through 2J is a schematic cross-sectional view illustrating a method of forming a semiconductor device package according to the present technology.

[0006] Figures 3A through 3I is a schematic cross-sectional view illustrating a method of forming a semiconductor device package according to the present technology.

[0007] Figures 4A through 4D is a schematic cross-sectional view illustrating a method of processing multiple semiconductor device package assemblies according to the present technology.

[0008] Figures 5A through 5D is a schematic cross-sectional view illustrating a method of processing multiple semiconductor device package assemblies according to the present technology.

[0009] Figure 6 is a block diagram of a system having a semiconductor assembly according to the present technology. Detailed Description

[0010] The following describes specific details of several embodiments of a stacked semiconductor die package and a method of manufacturing such die packages. The term "semiconductor device" generally refers to a solid-state device that includes one or more semiconductor materials. For example, a semiconductor device may include a semiconductor substrate or wafer, or a die singulated from the wafer or substrate. Throughout the present disclosure, semiconductor dies are generally described in the context of semiconductor devices, but are not limited thereto.

[0011] The term "semiconductor device package" may refer to an arrangement of one or more semiconductor devices incorporated into a common package. A semiconductor package may include a housing or enclosure that partially or completely encapsulates at least one semiconductor device. The term "semiconductor device package assembly" may refer to an assembly that includes a plurality of stacked semiconductor device packages. As used herein, the terms "vertical", "lateral", "upper", and "lower" may refer to the relative direction or position of features in a semiconductor device or package in view of the orientation shown in the figures. However, these terms should be interpreted to include semiconductor devices having other orientations (e.g., inverted or tilted orientations).

[0012] Figure 1 is a schematic cross-sectional view of a semiconductor device package assembly 100 in accordance with an embodiment of the present technology. As shown, the semiconductor device package assembly 100 includes a base component 101 and a plurality of semiconductor device packages 103 stacked on the base component 101. Although the illustrated embodiment shows thirteen (13) separate stacked semiconductor device packages 103, it will be understood that in other embodiments, the semiconductor device package assembly 100 may include any suitable number (e.g., 10, 12, 14, 16, 18, etc.) of stacked semiconductor device packages 103. The semiconductor device package assembly 100 includes an encapsulation material 104 that covers the base component 101 and the semiconductor device packages 103. In some embodiments, the encapsulation material 104 may include a resin, plastic, silicon, oxide, polymer, or other suitable dielectric material.

[0013] As Figure 1 shown, the semiconductor device package 103 is electrically coupled to an electrical coupler 106 via a metallization structure 108. In some embodiments, the electrical coupler 106 may include solder bumps, solder balls, conductive pads, and / or other suitable devices. The metallization structure 108 may include a conductive material (e.g., a metal (e.g., copper)) configured to define traces, vias, planes, etc. of a circuit system that electrically connects the semiconductor device package 103 to the electrical coupler 106. By this arrangement, the base component 101 and the semiconductor device packages 103 may be electrically coupled to external devices via the electrical coupler 106 and the metallization structure 108.

[0014] The semiconductor device package assembly 100 has a vertically compact design. For example, the substrate assembly 101 and the plurality of semiconductor device packages 103 are directly stacked together such that the bond line thickness (BLT) between the plurality of semiconductor device packages 103 can be zero or near zero. In some embodiments, the BLT between the substrate assembly 101 and the adjacent semiconductor device packages 103 can also be zero or near zero.

[0015] In some embodiments, the substrate assembly 101 may include one or more semiconductor components 102 (e.g., integrated circuit systems) therein. The substrate assembly 101 can be a circuit board or other types of substrates commonly used in semiconductor device packages, or the substrate assembly can be a semiconductor device, such as a logic device, a memory device, or a processor. As shown, the substrate assembly 101 has a first side 1011 (e.g., front side / active side) and a second side 1013 (e.g., back side / passive side) opposite the first side 1011.

[0016] The substrate assembly 101 may include a passivation layer 1015 at the first side 1011 of the substrate assembly 101. In some embodiments, the passivation layer 1015 may include an oxide layer, an inert layer (e.g., a layer less likely to chemically react with air or be corroded), or other suitable protective layers. For example, the passivation layer 1015 may include a protective film. The passivation layer 1015 protects the substrate assembly 101. In some embodiments, the substrate assembly 101 may be further coupled to an interposer substrate by an electrical coupler (e.g., solder bumps or solder balls).

[0017] As shown, the substrate assembly 101 includes a metallization structure 105 electrically coupled to the semiconductor components 102 in the substrate assembly 101. In the illustrated embodiment, the metallization structure 105 may include one or more metallization layers defining traces, vias, and / or planes. In some embodiments, the metallization layer may include aluminum (e.g., aluminum pads), copper, or other suitable metals or conductive materials.

[0018] In the illustrated embodiment, the metallization structure 105 may be formed during a backend of line (BEOL) manufacturing process. The metallization structure 105 may include a contact region 107 configured to contact the bottommost semiconductor device package 103 (e.g., electrically and physically) when the semiconductor device packages 103 are stacked on the substrate 101.

[0019] In Figure 1In the illustrated exemplary embodiments, an individual semiconductor device package 103 has a first side 1031 (e.g., front side / active side / face side) and a second side 1033 (e.g., back side / passive side) opposite the first side 1031. As shown, the individual semiconductor device package 103 may also include a passivation layer 1035 at the first side 1031 of the semiconductor device package 103 to protect the semiconductor device package 103. In some embodiments, the passivation layer 1035 may include an oxide layer, an inert layer (e.g., a layer less likely to chemically react with air or be corroded), or other suitable protective layers. The passivation layer 1035 may alternatively be a pre-formed protective film.

[0020] As shown, the individual semiconductor device package 103 may also include a dielectric layer 1037 at the second side 1033 of the semiconductor device package 103 to protect the semiconductor device package 103. In some embodiments, the dielectric layer 1037 may be a dielectric film.

[0021] The individual semiconductor device package 103 may also include a metallization structure 109 electrically coupled to one or more semiconductor components 1032 (e.g., an integrated circuit system, etc.) in the semiconductor device package 103. The metallization structure 109 may extend through the thickness of the semiconductor device package 103. The metallization structure 109 may include layers of aluminum, copper, or other suitable metal or conductive materials. The metallization structure 109 may be formed during a BEOL manufacturing process and includes multiple layers of traces, vias, or other electrical features. The metallization structure 109 may have a conductive pad 109a at the first side 1031 and a contact region 109b at the back side 1033.

[0022] As Figure 1 shown, the substrate assembly 101 and the bottommost semiconductor device package 103 are stacked in a "face-to-face" manner such that the first side 1011 (e.g., "front" side) of the substrate assembly 101 faces the first side 1031 (e.g., "front" side) of the bottommost semiconductor device package 103. The passivation layer 1035 on the bottommost semiconductor device package 103 may directly contact the passivation layer 1015 on the substrate assembly 101 such that there is zero BLT between the bottommost semiconductor device package 103 and the substrate assembly 101. However, in some embodiments, there may be a very small gap between the bottommost semiconductor device package 103 and the substrate assembly 101 such that there is a near-zero BLT. Also as Figure 1As shown, additional semiconductor device packages 103 are stacked on top of the bottommost semiconductor device package 103 in a "back-to-back" manner. For example, the second side 1033 ("back" side) of one semiconductor device package 103 is directly coupled to the first side 1031 ("front" side) of an adjacent semiconductor device package 103. With this arrangement, the substrate assembly 101 and the semiconductor device packages 103 can be stacked quickly. As more semiconductor device packages 103 are stacked on top of each other, the semiconductor device package assembly 100 can have a higher device density.

[0023] The semiconductor device package assembly 100 further includes metal bumps 111 (or metal pillars) at the first side 1031 of the bottommost semiconductor device package 103. The metal bumps 111 are electrically coupled to the metallization structure 109 of the bottommost semiconductor device package 103 and the metallization structure 105 of the substrate assembly 101 (e.g., at the contact region 107). The metal bumps 111 can be made of indium or other suitable conductive materials. In some embodiments, the metal bumps 111 can be electrically coupled to the first metallization layer 105 of the substrate assembly 101 through an annealing process (e.g., heating the metal bumps 111 at 100 degrees Celsius to 200 degrees Celsius for a period of time).

[0024] Individual semiconductor device packages 103 have recesses 113 (e.g., "divots" or "trenches") at their second sides 1033, and metal bumps 115 (or metal pillars) can be positioned in the recesses 113. The metal bumps 115 can be electrically coupled to the metallization structure 109 of an adjacent semiconductor device package 103. With this arrangement, the present technology enables the substrate assembly 101 to be electrically coupled to the semiconductor device packages 103 without using TSVs in either the substrate assembly 101 or the semiconductor device packages 103. In some embodiments, the metal bumps 115 can be electrically coupled to the semiconductor device packages 103 through an annealing process (e.g., heating the metal bumps 115 to about 100 degrees Celsius to 300 degrees Celsius (e.g., 200 °C) for about 50 seconds to 200 seconds (e.g., 100 seconds)).

[0025] In some embodiments, the semiconductor device package assembly 100 can be a memory device, where the semiconductor device packages 103 are memory dies (e.g., DRAM, LPDRAM, SRAM, flash, etc.). In some embodiments, the substrate assembly 101 can be a logic device, a processor, and / or another memory device.

[0026] Figures 2A through 2J is a schematic cross-sectional view of a method for manufacturing a semiconductor device package 203 (e.g., Figure 1 the semiconductor device package 103 described in Figures 2A through 2J throughout, like element symbols refer to like components. Refer toFigure 2A , at this stage of the method, the semiconductor device package 203 has a substrate 2037 having a first side 2031 (e.g., front side / active side) and a second side 2033 (e.g., back side / passive side) opposite the first side 2031. The semiconductor device package 203 may have a metallization structure 205 formed during the BEOL manufacturing process, and the metallization structure 205 includes a first metallization layer 205a, a second metallization layer 205b, and a third metallization layer 205c in the substrate 2037. In some embodiments, the first metallization layer 205a may include aluminum or another suitable metal or conductive material. For example, the first metallization layer 205a may be an aluminum pad. The second metallization layer 205b may include copper or another suitable metal or conductive material, and the third metallization layer 205c may include copper or another suitable metal or conductive material. The metallization structure 205 is electrically coupled to one or more semiconductor components 202 (e.g., integrated circuit system) in the semiconductor device package 203.

[0027] In some embodiments, the semiconductor device package 203 may also have a barrier layer 217 between a portion of the metallization structure 205 and the substrate 2037. For example, the barrier layer 217 may be adjacent to the second metallization layer 205b. The barrier layer 217 may be made of a metal (e.g., tantalum) to prevent diffusion into the substrate 2037. For example, the second metallization layer 205b may include copper, and the barrier layer 217 may be made of tantalum to inhibit copper diffusion into the substrate 2037.

[0028] Figure 2A The semiconductor device package 203 is shown after the passivation layer 2035 has been applied to the first side 2031 of the semiconductor device package 203 to protect the semiconductor device package 203. In some embodiments, the passivation layer 2035 may include an oxide layer, an inert layer (e.g., a layer that is unlikely to chemically react with air or be corroded), other suitable protective layers, or a pre-formed protective film. The semiconductor device package 203 may also include a contact region 207 on the first metallization layer 205a at the first side 2031.

[0029] Figure 2B The semiconductor device package 203 is shown after the metal bumps 211 have been formed on the contact region 207. The metal bumps 211 are electrically coupled to the metallization structure 205 and are configured to provide electrical and mechanical connections to the metallization structure of another semiconductor device package stacked on the semiconductor device package 203 (e.g., see Figure 1 ). The metal bumps 211 may be made of indium or other suitable conductive materials.

[0030] In some embodiments, the metal bump 211 may have a vertical dimension VD of about 10 μm to 20 μm, or more specifically about 15 μm. The metal bump 211 may be formed by an electroplating process, in which a seed material is deposited on the contact region 207 of the first metallization layer 205a, and then a conductive material is electroplated onto the seed material to form the metal bump 211 on the first metallization layer 205a. Alternatively, the metal bump 211 may be formed by an inkjet process, cold annealing, or other suitable methods.

[0031] Figure 2C Shown is the semiconductor device package 203 after the semiconductor device package 203 has been coupled to the carrier 215 by the bonding layer 213. The carrier 215 is configured to temporarily hold and support the semiconductor device package 203 during the manufacturing process described below Figures 2D through 2J The carrier 215 may be reusable or disposable, such as a glass carrier, a silicon carrier, or a plastic carrier. In some embodiments, the bonding layer 213 may be a release tape (e.g., gas-sensitive or temperature-sensitive), a flowable adhesive, or other suitable material. A fluid (gas or liquid) may be used to dissolve the bonding layer 213 or a laser may be used to ablate the bonding layer 213 to release the semiconductor device package 203 from the carrier 215.

[0032] Figure 2D Illustrated is the semiconductor device package 203 after the substrate 2037 has been thinned. Referring to Figure 2D , the substrate 2037 may be thinned to a thickness D between the thinned surface 219 and the first side 2031. In some embodiments, the thickness D of the substrate 2037 may range from 5 μm to 30 μm, and for example not exceed 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, or 5 μm.

[0033] By thinning the substrate 2037 to this extent, the metallization structure 205 of the semiconductor device package 203 can be accessed and electrically coupled to other metallization structures or semiconductor components of the stacked semiconductor device packages without using TSVs. Generally, the minimum thickness of a semiconductor substrate for forming TSVs in a semiconductor structure may be about 50 μm. This is 200% to 1000% thicker than the semiconductor device package 203 and the semiconductor device package 103 of the present technology ( Figure 1 ). Thus, the improved method provided by the present technology is advantageous, at least because it provides semiconductor device packages having a smaller thickness (or vertical dimension) and that can be stacked without forming TSVs. It is particularly advantageous for manufacturing compact semiconductor devices or packages.

[0034] Figure 2EDescribe the stage of the process after the first patterned photoresist layer 221 has been formed on the second side 2033 (back side / non-active side) of the semiconductor device package 203. As shown, the first patterned photoresist layer 221 has a plurality of openings 223a to c ( Figure 2E Only three openings are shown in the figure, the first opening 223a, the second opening 223b, and the third opening 223c). As shown, the first opening 223a and the third opening 223c are on opposite sides of the semiconductor device package 203. The first opening 223a and the third opening 223c can be used to separate or "singulate" the semiconductor device package 203 at a later stage of the process. The second opening 223b is aligned with at least a portion of the metallization structure 205 in the semiconductor device package 203.

[0035] Figure 2F Show the stage of the process after the openings 226 have been formed through the substrate 2037 by the first opening 223a and the third opening 223c to expose the passivation layer 2035. The openings 226 can be formed by etching the substrate 2037 of the semiconductor device package 203. In the same etching process, a recess 225 (e.g., a pit or a trench) can be formed in the substrate 2037 through the second opening 223b (e.g., the second opening 223b extends in the direction towards the first side 2031 of the semiconductor device package 203). The recess 225 can be another opening exposing the barrier layer 217. As shown, the recess 225 has sloped sidewalls (both at the left and right sides of the recess 225, as Figure 2F shown in the figure), which can facilitate coupling the metal bumps of another semiconductor device package to the metallization structure 205. Alternatively, the openings 226 and the recess 225 can be formed by laser ablation of the substrate 2037 without forming the patterned photoresist layer 221.

[0036] Figure 2G Show the stage of the process after the first photoresist layer 221 has been removed and the dielectric layer 227 has been formed on the second side 2033 of the semiconductor device package 203. The dielectric layer 227 can be formed by a chemical vapor deposition (CVD) process, such as a CVD tetraethyl orthosilicate (TEOS) layer. Alternatively, the dielectric layer 227 can be formed by a spin coating process.

[0037] Figure 2H and 2I Show the stage of the process after the second patterned photoresist layer 229 (or the second photo-pattern mask) has been formed on the second side 2033 (back side / non-active side) of the semiconductor device package 203. The second patterned photoresist layer 229 fills the first opening 223a and the third opening 223c, and has an opening 231 aligned with the metal structure 205.Figure 2I A stage of the process after the dielectric layer 227 and the barrier layer 217 shown within the opening 231 have been removed to expose the third metallization layer 205c through the opening 2133. In some embodiments, the barrier layer 217 is not removed. Factors considered for removing the barrier layer 217 include, for example, the types of materials used in the barrier layer 217, the third metallization layer 205c, and the metal bumps 211.

[0038] Figure 2J A stage of the process after the second photoresist layer 229 has been removed. The recess 225 has a lateral dimension L greater than that of the metal bumps 211 (shown in dashed lines) to be attached to the metal structure 205. 2 The lateral dimension L 1 . Accordingly, the sidewalls 225a of the recess 225 and the sidewall portions 227a of the dielectric layer 227 are spaced apart from the sidewalls 211a of the metal bumps 211. At this stage of the process, the carrier 215 can be removed and one or more semiconductor device packages 203 can be stacked on top of each other.

[0039] Figures 3A through 3I is a schematic cross-sectional view illustrating a method of forming a semiconductor device package according to the present technology. Throughout Figures 3A through 3I , like reference numerals refer to like components. Referring to Figure 3A , the semiconductor device package 300 has a first side 301 (e.g., front side / active side) and a second side 303 (e.g., back side / passive side) opposite the first side 301. The semiconductor device package 300 can have a substrate 307 and a metallization structure 305 formed during a BEOL manufacturing process, the metallization structure 305 including a first metallization layer 305a, a second metallization layer 305b, and a third metallization layer 305c. The semiconductor device package 300 can have conductive vias 331 coupled to features in the metallization structure 305. In the illustrated embodiment shown in Figures 3A through 3I , the conductive vias 331 are coupled to the second metallization layer 305b. In other embodiments, the conductive vias 331 can be coupled to other metallization layers (e.g., the first metallization layer 305a or the third metallization layer 305c). The metallization layers 305a to 305c can include conductive traces, pads, conductive planes, and / or electrical components (e.g., capacitors, resistors, etc.) that form one or more circuits (e.g., live circuits, open circuits, etc.).

[0040] The substrate 307 may be a semiconductor substrate formed of silicon or other suitable materials, and an integrated circuit system may be formed on / in the substrate to form a memory device, a logic device, or a processor. In the illustrated embodiment, the metallization structure 305 is electrically coupled to a semiconductor component 302 (e.g., an integrated circuit system) in the substrate 307. The first metallization layer 305a may comprise aluminum or other suitable metal or conductive material and is formed as one or more pads. In some embodiments, the second metallization layer 305b and the third metallization layer 305c may comprise copper or other suitable metal or conductive material.

[0041] In some embodiments, the semiconductor device package 300 may have a barrier layer ( Figure 3A not shown in, similar to Figure 2A the barrier layer 217 shown in). The barrier layer may alternatively be adjacent to the second metallization layer 305b. In some embodiments, the barrier layer may be made of a metal (e.g., tantalum), and the second metallization layer 305b may comprise copper such that the tantalum barrier layer inhibits copper diffusion into the substrate 307.

[0042] The semiconductor device package 300 may also include a passivation layer (not shown) similar to Figure 2A the passivation layer 2035 shown in at the first side 301 of the semiconductor device package 300. The passivation layer may protect the semiconductor device package 300. In some embodiments, the passivation layer may comprise an oxide layer, an inert layer (e.g., a layer less likely to chemically react with air or be corroded), or other suitable protective layer or protective film.

[0043] As Figure 3A shown in, the semiconductor device package 300 includes a central metal bump 308a and side metal bumps 308b on both sides of the central metal bump 308a ( Figure 3A four side metal bumps 308b are shown in). As shown, the central metal bump 308a has a vertical dimension greater than that of the side metal bumps 308b. For example, the central metal bump 308a may have a vertical dimension VDC of about 10 μm to 20 μm, and the side metal bumps 308b may have a vertical dimension VDS of about 5 μm to 10 μm. The vertical dimension VDC may be about 15 μm, while the vertical dimension VDS may be about 7.5 μm. The central metal bump 308a is taller than the side metal bumps 308b such that when the semiconductor device package 300 is stacked on another semiconductor device package, the central metal bump 308a may be positioned in the cavity of the semiconductor device package, as described below with respect to Figure 3G and 3H description.

[0044] The central metal bump 308a and the side metal bumps 308b are electrically coupled to the metallization structure 305 and are configured to make electrical contact with a metallization layer of another semiconductor device package (see, e.g., Figure 3H ). In some embodiments, the metal bumps 308a, 308b may comprise indium bumps. In other embodiments, the metal bumps 308a, 308b may comprise other suitable conductive materials.

[0045] In some embodiments, the central metal bump 308a and the side metal bumps 308b may be pillars formed by an electroplating process. For example, the metal bumps 308a, 308b may be formed by having a seed material adjacent to the first metallization layer 305a, and a conductive material may be electroplated onto the seed material. In other embodiments, the metal bumps 308a, 308b may be formed by an inkjet process or other suitable methods. In some embodiments, the metal bumps 308a, 308b may be cold annealed (e.g., at 200 °C).

[0046] Figure 3B Shown is the semiconductor device package 300 after the semiconductor device package 300 has been inverted and coupled to the carrier 315 via the adhesive 316. The carrier 315 is configured to hold and support the semiconductor device package 300 during the manufacturing process described below with respect to Figures 3C through 3H . The carrier 315 may be a reusable or non-reusable carrier made of glass, silicon, or plastic. The metal bumps 308a and 308b are embedded in the adhesive 316, and the adhesive 316 may be a partially cured layer of resin or other suitable material.

[0047] Figure 3C Illustrated is the semiconductor device package 300 after the substrate 307 has been thinned. Referring to Figure 3C , the semiconductor device package 300 may be thinned such that the depth H between the thinned surface 319 and the first side 2031 of the semiconductor device package 203 1 is approximately 10 μm. The depth H 1 may range from 5 μm to 30 μm, and more specifically, the depth H 1 does not exceed 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, or 5 μm.

[0048] By thinning the substrate 307 to this extent, access to the metallization structure 305 can be achieved without using TSVs and it can be electrically coupled to other metallization layers or semiconductor components of another semiconductor device package. Generally, for forming TSVs in a semiconductor structure, the minimum depth to which a semiconductor structure can be thinned is about 50 μm. Thus, the improved method provided by the present technology is advantageous, at least in part because it can fabricate and stack semiconductor device packages having a smaller depth (or vertical dimension) without the processing steps for forming TSVs. It is particularly advantageous for fabricating compact semiconductor devices or packages.

[0049] Figure 3C Also shown is the semiconductor package 300 after the coating layer 333 has been formed on the thinned surface 319. The coating layer can be an oxide layer that protects the thinned substrate 307 in subsequent processing (such as the lithography and other processes discussed below with respect to Figure 3D and 3E ).

[0050] Figure 3D Illustrated is the semiconductor package 300 after the patterned photoresist layer 321 (or optical pattern mask) has been formed on the second side 303 (back side / non-active side) of the semiconductor device package 300. As shown, the photoresist layer 321 has a plurality of openings 323a to c (identified as the first opening 323a, the second opening 323b, and the third opening 323c). The first opening 323a and the third opening 323c are formed on opposite sides of the semiconductor device package 300 and can be later used in the process to separate or "singulate" the semiconductor device package 300. The second opening 323b is at the midline, and more particularly it can be aligned with the central metal bump 308a.

[0051] Figure 3E Shown is the semiconductor device package 300 after the channels 326a, 326c have been formed through the semiconductor device package 300 by the first opening 323a and the third opening 323c. The channels 326a, 326c can be formed by etching the substrate 307 through the openings 323a, 323c.

[0052] In the same process as forming the channels 326a, 326c, a cavity 326b can be formed through the substrate 307 and a portion of the metallization structure 305 via the second opening 323b. The cavity 326b can extend to the second metallization layer 305b and thereby expose a portion of the second metallization layer 305b.

[0053] Figure 3FFIG. 300 shows a semiconductor device package 300 after the photoresist layer 321 and the coating layer 333 have been removed and a dielectric layer 327 has been formed on the second side 303 of the semiconductor device package 300. In some embodiments, the dielectric layer 327 may be formed by a chemical vapor deposition (CVD) process, such as a CVD tetraethyl orthosilicate (TEOS) layer. Alternatively, the dielectric layer 327 may be formed by a spin coating process or by applying a pre-formed dielectric film. In some embodiments, a portion of the substrate 307 may also be removed to further thin the substrate. In such embodiments, the depth H as indicated in Figure 3F may be less than the depth H 2 as indicated in 1 .

[0054] Figure 3G FIG. 300 shows the semiconductor device package 300 after portions of the dielectric layer 327 at the bottoms of the channels 326a and 326c and at the bottom of the cavity 326b have been removed. In some embodiments, portions of the dielectric layer 327 may be removed by an etching process. As shown in Figure 3G , after portions of the dielectric layer 327 within the cavity 326b have been removed, portions of the second metallization layer 305b are exposed within the cavity 326b.

[0055] Figure 3H FIG. 300 shows the semiconductor device package 300 after connection sites 350 ( Figure 3H showing four connection sites 350 therein) have been formed on the second side 303 of the semiconductor device package 300. The connection sites 350 are aligned with the side metal bumps 308b and are configured to be coupled to and contact side metal bumps (similar to the side metal bumps 308b discussed above) of another semiconductor device package in a stacked arrangement. In some embodiments, the plurality of connection sites 350 may be formed by a masking / etching process. The plurality of connection sites 350 may be made of a metal, such as aluminum, titanium, copper, etc.

[0056] Figure 3I FIG. 300 shows the semiconductor device package 300 after the carrier 315 has been removed and another semiconductor device package 300a of the same configuration has been stacked on the semiconductor device package 300. As shown, the central metal bump 308a of the semiconductor package 300a is aligned and positioned within the cavity 326b of the semiconductor device package 300 and is electrically coupled to the second metallization layer 305b of the semiconductor device package 300. The side metal bumps 308b of the semiconductor device package 300a are respectively aligned with and electrically coupled to the corresponding connection sites 350 of the semiconductor device package 300. In this manner, a plurality of semiconductor device packages 300 may be stacked on one another with zero or near-zero BLT and without forming TSVs through the substrate 307.

[0057] Figures 4A through 4D A method of processing a semiconductor device package assembly 401 similar to or identical to the semiconductor device package assembly 100 described herein, but the semiconductor device package can also be used in a die stack. Each of the semiconductor device package assemblies 401 has a front side 4011 and a back side 4013. In Figure 1 , the semiconductor device package assemblies 401 are carried by a temporary carrier 403. Each of the plurality of semiconductor device package assemblies 401 includes a substrate (e.g., Figure 4A the substrate component 101 in Figure 1 ) at the back side 4013 and a plurality of semiconductor device packages (e.g., semiconductor device packages 103 or 203) at the front side 4011. In the illustrated embodiment, the back side 4013 of the semiconductor device package assembly 401 is coupled to the temporary carrier 403 such that the device package assemblies 401 are spaced apart from each other.

[0058] Figure 4B The assembly is shown after the semiconductor device package assembly 401 has been covered with an encapsulation material 405. In some embodiments, the encapsulation material 405 may include a resin, plastic, silicon, oxide, polymer, or other suitable dielectric material.

[0059] Figure 4C The assembly is shown after the temporary carrier 403 has been removed from the semiconductor device package assembly 401. In Figure 4C , the semiconductor device package assemblies 401 are inverted compared to Figure 4B . The upper part of the assembly shown in Figure 4C (e.g., the part above the plane P as indicated) can be removed so that the metallization structure 4018 of the semiconductor device package assembly 401 can be exposed.

[0060] Figure 4D The assembly is shown after a polymer layer 407 has been formed on the semiconductor device package assembly 401. The method may include using the polymer layer 407 to form a redistribution structure 409. The redistribution structure 409 is electrically coupled to the metallization layer 4018 in the individual semiconductor device package assemblies 401. In some embodiments, the redistribution structure 409 may include copper or other suitable conductive material.

[0061] As shown in Figure 4D , a plurality of connectors 411 may be formed on the redistribution structure 409 and electrically coupled to the redistribution structure 409. The connectors 411 are further electrically coupled to the metallization structure of the semiconductor device package and the substrate component in the individual semiconductor device package assemblies 401. In some embodiments, the connectors 411 may be a ball grid array (BGA), including solder balls, pads, or other suitable connection devices. Then, it can be carried out by Figure 4DAt the position indicated by the dashed line shown in, the semiconductor device package assembly 401 is "singulated" or separated by cutting through the encapsulation material 405.

[0062] Figures 5A through 5D Describe a method of processing a semiconductor device package assembly 501 according to the present technology. In Figure 5A , the semiconductor device package assembly 501 is carried by a temporary carrier 503, and each of the semiconductor device package assemblies 501 has a front side 5011 and a back side 5013. In this embodiment, the front side 5011 of the semiconductor device package assembly 501 is coupled to the temporary carrier 503, opposite to Figure 4A and 4B the back side 5013 in. The semiconductor device package assemblies 501 are spaced apart so that they can be separated later during the singulation process.

[0063] Figure 5B Show the assembly after the semiconductor device package assembly 501 has been covered with an encapsulation material 505. In some embodiments, the encapsulation material 505 may include resin, plastic, silicon, oxide, polymer, or other suitable dielectric material.

[0064] Figure 5C Show the assembly after the temporary carrier 503 has been removed from the semiconductor device package assembly 501. In Figure 5C , compared with Figure 5B , the semiconductor device package assembly 501 covered with the encapsulation material 505 is inverted.

[0065] Figure 5D Show the assembly after a polymer layer 507 has been formed on the semiconductor device package assembly 501. The method may include using the polymer structure 507 to form a redistribution structure 509. The redistribution structure 509 is electrically coupled to a metallization layer (e.g., metallization structure 105 or 205) in an individual semiconductor device package assembly 501. In some embodiments, the redistribution structure 509 may include copper or other suitable conductive material.

[0066] As Figure 5D shown in, a plurality of connectors 511 may be formed on the redistribution structure 509 and electrically coupled to the redistribution structure 509. The connectors 511 are further electrically coupled to the metallization structure of the semiconductor device package and the substrate assembly in an individual semiconductor device package assembly 501. In some embodiments, the connectors 511 may be BGA connectors, which include solder balls, pads, or other suitable connection devices. Then, the semiconductor device package assembly 501 can be "singulated" or separated by cutting through the encapsulation material 505 at the position indicated by the dashed line shown in Figure 5D .

[0067] Having the above regardingFigures 1 through 5D Any of the semiconductor devices described herein may be incorporated into any of a number of larger and / or more complex systems, representative examples of which are Figure 6 the system 600 schematically shown in. The system 600 may include a processor 601, a memory 603 (e.g., SRAM, DRAM, flash, and / or other memory devices), input / output devices 605, and / or other subsystems or components 607. As described above with respect to Figures 1 through 5D the semiconductor assemblies, devices, and device packages described herein may be included in Figure 6 any of the components shown in. The resulting system 600 may be configured to perform any of a variety of suitable computing, processing, storing, sensing, imaging, and / or other functions. Thus, representative examples of the system 600 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system 600 include lights, cameras, vehicles, etc. With respect to these and other examples, the system 600 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Accordingly, the components of the system 600 may include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0068] The present disclosure is not intended to be exhaustive or to limit the technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without departing from the technology, as will be recognized by those of ordinary skill in the relevant art. In some instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. Although the steps of the methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, some aspects of the technology disclosed in the context of a particular embodiment may be combined or eliminated in other embodiments. Additionally, although advantages associated with the embodiments of the technology may have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the present disclosure and the associated technology may cover other embodiments not expressly shown or described herein.

[0069] Throughout this disclosure, the singular terms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Similarly, with respect to a list of two or more items, unless the word "or" is explicitly limited to mean a single item that excludes the other items, the use of "or" in such a list shall be construed to include (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, the term "comprising" is used throughout to mean including at least the recited features, such that any greater number of the same features and / or additional types of other features are not excluded. References herein to "one embodiment", "some embodiments", or similar phrases mean that a particular feature, structure, operation, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present technology. Thus, such phrases or statements appearing herein do not necessarily all refer to the same embodiment. Furthermore, the various specific features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0070] From the foregoing it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without departing from the scope of the invention. The present technology is not limited except as by the appended claims.

Claims

1. A semiconductor device packaging assembly, which comprises: a substrate assembly having a front side and a back side, the substrate assembly having a first metallization structure at the front side, and the first metallization structure being exposed in a contact area at the front side; a stack of semiconductor device dies, each semiconductor device die having a first side, a second side having a recess, and a second metallization structure, the second metallization structure having a contact pad at the first side and a contact area exposed in the recess at the second side; and metal bumps, at least part of which are located in the recess at the second side of the semiconductor device die, wherein the metal bumps are electrically coupled to the contact pad of the second metallization structure of one semiconductor device assembly and the contact area of an adjacent semiconductor device assembly, and wherein additional metal bumps are coupled to the contact pad of the lowermost semiconductor device die in the stack of semiconductor device dies and the first metallization structure of the substrate assembly; wherein the semiconductor devices are electrically coupled to each other and to the substrate assembly via the first metallization structure and the second metallization structure without through-silicon vias; wherein the first metallization structure and the second metallization structure have traces and vias without using through-silicon vias (TSVs) that extend directly from the first side to the second side of the stack of semiconductor device dies.

2. The semiconductor device packaging assembly according to claim 1, wherein the metal bumps extend from the contact pad of one semiconductor device to the contact area of an adjacent semiconductor device over a distance of no more than 20 μm.

3. The semiconductor device packaging assembly according to claim 1, wherein the metal bumps are central metal bumps, and wherein the semiconductor device packaging assembly further comprises side metal bumps located at one side of the central metal bumps.

4. The semiconductor device packaging assembly according to claim 1, wherein the vertical dimension of the metal bumps does not exceed 15 μm.

5. The semiconductor device packaging assembly according to claim 1, wherein the vertical dimension of the metal bumps is 10 μm.

6. The semiconductor device packaging assembly according to claim 1, wherein at least one of the first metallization structure and the second metallization structure comprises aluminum.

7. The semiconductor device packaging assembly according to claim 1, wherein at least one of the first metallization structure and the second metallization structure comprises copper.

8. The semiconductor device packaging assembly according to claim 1, wherein the second metallization structure comprises a first metallization layer, a second metallization layer, and a third metallization layer, and wherein the first metallization layer is electrically coupled to the metal bumps.

9. The semiconductor device packaging assembly according to claim 8, wherein the first metallization layer comprises aluminum, the second metallization layer comprises copper, and the third metallization layer comprises copper.

10. A stack of semiconductor device dies assembly, which comprises: A first semiconductor device die having a front side and a back side, the first semiconductor device die having a first metallization structure at the front side and a first substrate at the back side, the first metallization structure being exposed from the back side via a cavity; A second semiconductor device die having a first side and a second side, the second semiconductor device die having a second metallization structure at the first side and a second substrate at the second side; A metal pillar at least partially positioned in the cavity and electrically coupled to the second metallization structure and the first metallization structure; and The first semiconductor device die and the second semiconductor device die are electrically coupled to each other without through-silicon vias.

11. The semiconductor device stacked die assembly according to claim 10, wherein the metal pillar comprises indium.

12. The semiconductor device stacked die assembly according to claim 10, wherein the metal pillar is a central metal pillar, and wherein the semiconductor device stacked die assembly further comprises side metal pillars positioned at one side of the central metal pillar.

13. The semiconductor device stacked die assembly according to claim 10, wherein a vertical dimension of the metal pillar does not exceed 20 μm.

14. The semiconductor device stacked die assembly according to claim 10, wherein the vertical dimension of the metal pillar is 10 μm.

15. The semiconductor device stacked die assembly according to claim 10, wherein the first metallization structure and the second metallization structure are electrically coupled without using through-silicon vias.

16. The semiconductor device stacked die assembly according to claim 10, wherein at least one of the first metallization structure and the second metallization structure comprises aluminum.

17. The semiconductor device stacked die assembly according to claim 10, wherein at least one of the first metallization structure and the second metallization structure comprises copper.

18. The semiconductor device stacked die assembly according to claim 10, wherein the second metallization structure comprises a first metallization layer, a second metallization layer, and a third metallization layer, and wherein the first metallization layer is electrically coupled to the metal pillar.

19. The semiconductor device stacked die assembly according to claim 18, wherein the first metallization layer comprises aluminum, and wherein the second metallization layer comprises copper, and wherein the third metallization layer comprises copper.

20. The semiconductor device stacked die assembly according to claim 10, wherein the first metallization structure comprises a first metallization layer, a second metallization layer, and a third metallization layer, and wherein the third metallization layer is electrically coupled to the metal pillar.

21. The semiconductor device stacked die assembly according to claim 20, wherein the first metallization layer comprises aluminum, and wherein the second metallization layer comprises copper, and wherein the third metallization layer comprises copper.

22. A semiconductor device stacked die assembly, which comprises: A first semiconductor device die having a front side and a back side, the semiconductor device die having a first metallization structure at the front side, the first metallization structure being exposed from the back side via a first recess; A second semiconductor device die having a first side and a second side, the semiconductor device die having a second metallization structure at the first side, the second metallization structure being exposed from the second side via a second recess, the second recess being aligned with the first recess; and Metal bumps at least partially located in the first recess and electrically coupled to the second metallization structure and the first metallization structure, wherein the first semiconductor device die is directly stacked on the second semiconductor device die, and the first semiconductor device die and the second semiconductor device die are electrically coupled to each other without through-silicon vias.

23. The semiconductor device stacked die assembly according to claim 22, wherein the metal bumps comprise indium.

24. The semiconductor device stacked die assembly according to claim 22, wherein the metal bumps are center metal bumps, and wherein the semiconductor device stacked die assembly further comprises side metal bumps located at one side of the center metal bumps.

25. The semiconductor device stacked die assembly according to claim 22, wherein a vertical dimension of the metal bumps does not exceed 15 μm.

26. The semiconductor device stacked die assembly according to claim 22, wherein the vertical dimension of the metal bumps is 10 μm.

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