Semiconductor module

Abstract

To improve the resistance to heat, the number of connections of main wiring is ensured. A semiconductor module (1) is provided with: a laminated substrate (2) in which a plurality of circuit boards (22, 23) are arranged on the upper surface of an insulating board (20); a semiconductor element (3) arranged on a prescribed circuit board (22) and having a main electrode, a gate pad (30), and a gate runner (31) electrically connected to the gate pad on the upper surface thereof; and a wiring member (4) electrically connecting the main electrode and another circuit board (23). The gate runner extends in a manner of dividing the main electrode into one side and the other side. The wiring member is arranged in a manner of spanning over the upper side of the gate runner.

Description

Technical Field

[0001] This invention relates to a semiconductor module. Background Technology

[0002] The semiconductor device has a substrate incorporating semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor), power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and FWD (Free Wheeling Diode), and is used in inverter devices, etc.

[0003] In this semiconductor module, a semiconductor element disposed on a defined substrate has a main electrode (also referred to as a surface electrode) and a gate electrode formed on its upper surface. The main electrode and the gate electrode are arranged separately from each other. Main wiring (main current wiring) such as bonding leads is connected to the main electrode, and control wiring is connected to the gate electrode (for example, see Patent Documents 1-3).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2020 / 059285

[0007] Patent Document 2: International Publication No. 2018 / 225571

[0008] Patent Document 3: Japanese Patent Application Publication No. 2010-016103 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] Furthermore, consider the possibility that with the increasing capacity of semiconductor modules, the number of main wirings connected to the main electrodes will increase. In this case, the number of main wirings may be limited depending on the configuration between the main electrodes and the gate electrodes. If the number of main wirings decreases, the heat generated by each main wiring will increase, potentially affecting the durability of the semiconductor module.

[0011] The present invention has been made in view of the following aspects, one of the objects of which is to provide a semiconductor module that can improve heat resistance by ensuring the number of connections of the main wiring.

[0012] Solution for solving the problem

[0013] One aspect of the present invention provides a semiconductor module comprising: a multilayer substrate in which a plurality of circuit boards are disposed on an upper surface of an insulating plate; a semiconductor element disposed on a predetermined circuit board, the upper surface of the semiconductor element having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad; and a wiring member electrically connecting the main electrode to other circuit boards, the gate channel extending in a manner that divides the main electrode into one side and another side, and the wiring member being disposed over the gate channel.

[0014] The effects of the invention

[0015] According to the present invention, the number of connections in the main wiring can be ensured to improve heat resistance. Attached Figure Description

[0016] Figure 1 This is a top view of the semiconductor module involved in this embodiment.

[0017] Figure 2 yes Figure 1 A partial enlarged view of the stacked substrate unit.

[0018] Figure 3 This is a schematic diagram illustrating the circuit involved in this embodiment.

[0019] Figure 4 This is a top view of the area surrounding the semiconductor element in the reference example.

[0020] Figure 5 This is a top view of the area surrounding the semiconductor element involved in this embodiment.

[0021] Figure 6 It is along Figure 5 The cross-sectional view of the ZX plane cut off.

[0022] Figure 7 yes Figure 6 Enlarged view of part A.

[0023] Figure 8 This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0024] Figure 9 This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0025] Figure 10 This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0026] Figure 11 This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0027] Figure 12This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0028] Figure 13 This is a top view of the area surrounding the semiconductor element according to the second embodiment.

[0029] Figure 14 yes Figure 14 A magnified view of a portion of the image.

[0030] Figure 15 This is a top view of the periphery of the semiconductor element involved in a variation of the second embodiment. Detailed Implementation

[0031] The following describes a semiconductor module to which the present invention can be applied. Figure 1 This is a top view of the semiconductor module involved in this embodiment. Figure 2 yes Figure 1 A partial enlarged view of the stacked substrate unit. Figure 3 This is a schematic diagram illustrating the circuit involved in this embodiment. Figure 1 For ease of explanation, the main wiring on the casing and chip has been omitted. Additionally, in Figure 2 The diagram shows only the main wiring, omitting the control wiring. Furthermore, the semiconductor module shown below is merely an example and is not limited to this; appropriate modifications are permissible.

[0032] In the following diagrams, the long side direction of the semiconductor module (the direction in which multiple stacked substrates are arranged) is defined as the X direction, the short side direction as the Y direction, and the height direction (the thickness direction of the substrate) as the Z direction. The X, Y, and Z axes shown are orthogonal to each other, forming a right-handed system. Additionally, depending on the situation, the X direction may sometimes be referred to as the left-right direction, the Y direction as the front-back direction, and the Z direction as the up-down direction. These directions (front-back, left-right, up-down) are terms used for ease of explanation, and their correspondence with the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor module. For example, the heat dissipation surface side (cooler side) of the semiconductor module may be called the lower surface side, and the opposite side as the upper surface side. Furthermore, in this specification, "top view" refers to the view of the upper surface of the semiconductor module from the Z-direction. Also, in this specification, the descriptions of directions and angles need only be approximate and are permissible within ±10 degrees.

[0033] The semiconductor module involved in this embodiment, for example, is used in power conversion devices such as power modules, and is a power module constituting an inverter circuit. Figure 1 and Figure 2As shown, the semiconductor module 1 is configured to include a substrate 10, a plurality of stacked substrates 2 disposed on the substrate 10, and a plurality of semiconductor elements 3 disposed on the stacked substrates 2. Although not specifically illustrated, the semiconductor module 1 may also include a housing that houses the stacked substrates 2 and the plurality of semiconductor elements 3, and a sealing resin (not shown) filled into the housing.

[0034] The base plate 10 is a rectangular plate having an upper surface and a lower surface. The base plate 10 functions as a heat sink. Furthermore, the base plate 10 has a rectangular shape when viewed from above, having a long side in the X direction and a short side in the Y direction. The base plate 10 is, for example, a metal plate made of copper, aluminum, or their alloys, and the surface of the base plate 10 may be electroplated.

[0035] A housing that appears rectangular when viewed from above is disposed on the upper surface of the substrate 10. The housing is formed as a box with an opening at the bottom to cover the upper part of the substrate 10 and multiple semiconductor components. The housing defines a space for accommodating the laminated substrate 2, semiconductor components, sealing resin, etc.

[0036] In addition, external terminals are provided on the housing. For example, external terminals include a positive terminal (P terminal), a negative terminal (N terminal), and an output terminal (M terminal), and may also include control terminals. The positive terminal, negative terminal, and output terminal can also be referred to as main terminals. Furthermore, external terminals may include multiple control terminals. Each external terminal is formed by pressure processing of metal plates made of copper, copper alloys, aluminum alloys, iron alloys, etc.

[0037] Additionally, six stacked substrates 2 are disposed inside the housing 11 and on the upper surface of the base plate 10. The stacked substrates 2 are, for example, rectangular in shape when viewed from above. The six stacked substrates 2 are arranged in the X-direction. The stacked substrates 2 are formed by laminating metal layers and insulating layers, and are, for example, composed of a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal substrate. Specifically, the stacked substrate 2 has an insulating plate 20, a heat sink (not shown) disposed on the lower surface of the insulating plate 20, and circuit boards 21-24 disposed on the upper surface of the insulating plate 20.

[0038] The insulating plate 20 has a predetermined thickness in the Z direction and is formed into a flat plate having an upper surface and a lower surface. The insulating plate 20 is formed from insulating materials such as ceramic materials like alumina (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4), resin materials like epoxy, or epoxy resin materials using ceramic materials as fillers. Furthermore, the insulating plate 20 may also be referred to as an insulating layer or insulating film.

[0039] The heat sink has a specified thickness in the Z direction and is formed as a generally integral structure covering the lower surface of the insulating plate. The heat sink is formed, for example, from a metal plate with good thermal conductivity such as copper or aluminum.

[0040] On the upper surface (main surface) of the insulating plate 20, multiple circuit boards 21-24 (four in this embodiment) are independently formed into an island shape, electrically insulated from each other. Three circuit boards 21-23 constitute the main wiring for the main current to flow through. Circuit board 24 constitutes the control wiring for control purposes. These circuit boards are made of a metal layer of a predetermined thickness formed from copper foil or the like. For example, circuit boards 21-23 can also be referred to as the main wiring layer, and circuit board 24 can also be referred to as the control wiring layer.

[0041] Circuit board 21 is disposed on the upper surface of insulating plate 20 with its orientation biased towards the negative side in the X direction. Circuit board 21 extends along one side of insulating plate 20 in the Y direction, and its end with the negative side in the Y direction bends towards the positive side in the X direction, forming an L-shape when viewed from above. At the end of circuit board 21 on the negative side in the Y direction and the positive side in the X direction, a pad C1 for external connection of the collector electrode of the upper arm is disposed. The pad C1 is connected to an external power supply positive potential point (P terminal) (see reference). Figure 3 That is, circuit board 21 constitutes the main wiring layer of the upper arm.

[0042] Circuit board 22 is disposed on the upper surface of insulating plate 20 with its orientation biased towards the positive side in the X direction. Circuit board 22 extends along one side of insulating plate 20 in the Y direction, and when viewed from above, it has an L-shape with its end on the positive side in the Y direction bending towards the negative side in the X direction. At the corner of the L-shape of circuit board 22, there is a pad E1C2 for external connection, to which the emitter electrode of the upper arm and the collector electrode of the lower arm are connected. The pad E1C2 serves as an intermediate potential point (M terminal) connected to an external load (see reference). Figure 3 That is, circuit board 22 forms part of the main wiring layer of the lower arm.

[0043] Circuit board 23 is disposed on the upper surface of insulating plate 20 with its orientation more biased towards the positive X-direction than circuit board 22. Circuit board 23 extends along one side of insulating plate 20 in the Y-direction, and when viewed from above, has an L-shaped end with its negative Y-direction end bent towards the negative X-direction. At the corner of the L-shape of circuit board 23, there is a pad E2 for external connection of the emitter electrode of the lower arm to which is connected. The pad E2 is connected to an external power supply positive potential point (N terminal) (see...). Figure 3 That is, circuit board 23 forms part of the main wiring layer of the lower arm.

[0044] The circuit board 24 is disposed on the upper surface of the insulating plate 20 in a manner biased towards the negative side of the Y direction. The circuit board 24 extends along one side of the insulating plate 20 in the X direction and has an L-shaped appearance when viewed from above, with the end having the negative side of the X direction slightly bent towards the positive side of the Y direction.

[0045] The ends of the aforementioned external terminals are connected to the upper surface of these circuit boards. Each end of these external terminals is directly connected to the upper surface of the specified circuit board via ultrasonic bonding, laser bonding, or other methods, or is connected to the upper surface of the specified circuit board using bonding materials such as solder or sintered metal. Thus, the ends of each external terminal are electrically connected to the specified circuit board. For convenience, the description of the connection relationship between each external terminal and the circuit board is omitted.

[0046] On the upper surface of the specified circuit board, a bonding material S (refer to) is used with the aid of solder or other bonding materials. Figure 6 The device is equipped with a semiconductor element 3. The semiconductor element 3 is formed from a semiconductor substrate such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) in a square (or rectangular) shape when viewed from above. Furthermore, as the semiconductor element 3, switching elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes such as FWDs (Free Wheeling Diodes) are used.

[0047] In this embodiment, the case where an RC (Reverse Conducting)-IGBT element, which integrates an IGBT and a FWD, is used as the semiconductor element 3 is described. Alternatively, the semiconductor element 3 may also be a power MOSFET element, or an RB (Reverse Blocking)-IGBT, which has sufficient withstand voltage for reverse bias. Furthermore, the shape, number, and placement of the semiconductor element 3 can be appropriately varied. In addition, the semiconductor element 3 in this embodiment is a vertical switching element obtained by forming functional elements such as transistors on a semiconductor substrate.

[0048] In semiconductor element 3, electrodes are formed on the upper and lower surfaces respectively (see reference). Figure 6 For example, the electrode on the upper surface (upper surface electrode T1) is composed of an emitter electrode (source electrode). The electrode on the lower surface (lower surface electrode B1) is composed of a collector electrode (drain electrode). The upper surface electrode T1 and the lower surface electrode B2 can also be referred to as main electrodes. In addition, a gate pad 30 and a gate channel 31 (see reference) are formed on the upper surface of the semiconductor element 3. Figure 5 , Figure 6).

[0049] Gate pad 30 represents the entry point for the main current of semiconductor element 3. Gate pad 30 is formed in a region separate (independent) from the aforementioned upper surface electrode. Gate pad 30 is disposed on the outer periphery of the upper surface of semiconductor element 3. More specifically, gate pad 30 is disposed at the center of one side of semiconductor element 3. Figure 2 In this configuration, the gate pad 30 is disposed on the side of the semiconductor element 3 located on the negative side in the X direction. Furthermore, the gate pad 30 may also be referred to as the gate electrode.

[0050] The gate channel 31 forms a gate wiring connected to the gate pad 30. That is, the gate channel 31 forms part of a current path for allowing current to flow into the semiconductor element 3. The gate channel 31 is formed by extending along the Y direction in such a way that it divides the center of the semiconductor element 3 into two in the X direction. The detailed construction of the gate channel 31 and the surface of the semiconductor element 3 is described later.

[0051] Multiple semiconductor elements 3 are disposed on the upper surfaces of circuit boards 21 and 22 using bonding materials such as solder (not shown). As a result, the lower surface electrodes of each semiconductor element 3 are electrically connected to circuit boards 21 and 22. Consequently, each external terminal is electrically connected to each semiconductor element.

[0052] In this embodiment, two semiconductor elements 3 are disposed on the upper surface of each of circuit boards 21 and 22, for a total of four. In circuit board 21, the two semiconductor elements 3 are arranged along the Y direction. The two semiconductor elements 3 on circuit board 21 constitute an upper arm. In circuit board 22, the two semiconductor elements 3 are arranged along the Y direction. The two semiconductor elements 3 on circuit board 22 constitute a lower arm. The upper arm and lower arm are arranged facing each other in the X direction. The upper arm is located on the negative side of the X direction, and the lower arm is located on the positive side of the X direction.

[0053] The upper surface electrode of the semiconductor element 3 and the designated circuit board are electrically connected via wiring members 4, such as leads. For example, the upper surface electrode of the semiconductor element 3 constituting the upper arm is connected to the circuit board 22 via the wiring member 4. The upper surface electrode of the semiconductor element 3 constituting the lower arm is electrically connected to the circuit board 23 via the wiring member 4.

[0054] Semiconductor element 3 is connected to a specified circuit board via so-called stitch bonding, a bonding method in which multiple bonding points are continuously joined without cutting the leads at each bonding point. Specifically, as... Figure 2 As shown, the wiring component 4 has two connection points 40 and 41 on the upper surface of the semiconductor element 3 (refer to...). Figure 4 , Figure 5), having one connection point 42 on the specified circuit board (circuit board 22 or circuit board 23) (refer to Figure 4 , Figure 5 Furthermore, the number of connection points is not limited to this and can be changed appropriately.

[0055] The wiring member 4 is configured to extend along the X direction when viewed from above. Furthermore, the wiring member 4 extends in a manner that forms an arch between adjacent connection points when viewed from the Y direction. Details will be described later. The wiring member 4 is configured to cross the gate channel 31 extending along the Y direction. That is, the gate channel 31 is configured to pass under the wiring member 4 between connection points 40 and 41.

[0056] Furthermore, each semiconductor element 3 is provided with a plurality of wiring members 4. More specifically, for example, seven wiring members 4 are arranged along the Y direction. However, the number of wiring members 4 is not limited to this and can be varied as appropriate.

[0057] These wiring components 4 use conductor wires (connecting leads). The conductor wires can be made of any one of gold, copper, aluminum, gold alloys, copper alloys, aluminum alloys, or combinations thereof. Alternatively, components other than conductor wires can be used as wiring components 4. For example, a ribbon can be used as a wiring component 4. Furthermore, the wiring component 4 is not limited to being formed from leads, etc., and can also be formed from ribbons or metal plates made of copper, copper alloys, aluminum alloys, iron alloys, etc.

[0058] Furthermore, consider the possibility that as semiconductor modules increase in capacity, the number of wiring components (main wiring) connecting to the upper surface electrodes (main electrodes) of semiconductor elements will increase. In this case, the number of wiring components may be limited depending on the configuration between the main electrodes and the gate electrodes (gate pads). If the number of wiring components decreases, the heat generated by each wiring component will increase, potentially affecting the durability of the semiconductor module.

[0059] Therefore, the inventors of this application conceived of this invention by focusing on the internal structure of semiconductor devices and the positional relationship between the gate channels on the surface and the wiring components.

[0060] Here, refer to Figures 4 to 7 This will be explained in detail regarding the surface structure of the semiconductor device involved in this embodiment. Figure 4 This is a top view of the area surrounding the semiconductor element in the reference example. Figure 5 This is a top view of the periphery of the semiconductor element involved in this embodiment. Furthermore, in Figure 4 and Figure 5In this illustration, the internal structure (IGBT region and FWD region described later) is shown in a top-down view, omitting the top surface electrodes of the semiconductor elements. The actual internal structure is covered by the top surface electrodes and therefore not visible on the surface. Furthermore, in... Figures 4 to 7 While the internal layouts differ only slightly, the basic structural elements are common. Therefore, structures with common names are labeled with the same reference numerals, and descriptions are omitted appropriately. Furthermore, in the following figures, the lower arm side is used as an example for illustration. That is, the upper arm side can also have the same structure as described below.

[0061] As described above, semiconductor device 3 is an RC-IGBT device that integrates IGBT and FWD. The RC-IGBT device has an IGBT region 3a and an FWD region 3b that appear as a strip when viewed from above, below the upper surface electrode.

[0062] like Figure 4 As shown, the semiconductor element 3 has a plurality of IGBT regions 3a extending along the Y direction and a plurality of FWD regions 3b extending along the Y direction. The IGBT regions 3a and FWD regions 3b are arranged alternately in the X direction. Figure 4 The system is configured with 4 IGBT zones 3a and 3 FWD zones 3b.

[0063] Furthermore, as described above, a gate pad 30 is disposed on the side of the semiconductor element 3 located on the negative side in the X direction. That is, the gate pad 30 is disposed biasedly on the side of the semiconductor element 3 located at the outer periphery. In addition, a gate channel 31 connected to the gate pad 30 is disposed on the upper surface of the semiconductor element 3.

[0064] The gate channel 31 extends from the gate pad 30 located on the negative side of the X direction toward the positive side of the X direction. The gate channel 31 divides the center of the upper surface of the semiconductor element 3 into two parts in the Y direction. The extension direction of the gate channel 31 is orthogonal to the extension directions of the IGBT region 3a and the FWD region 3b.

[0065] Furthermore, a circuit board 23 is disposed on the outer side of the semiconductor element 3, opposite to the side where the gate pad 30 is disposed. That is, the circuit board 23 is disposed on the opposite side of the gate pad 30, across the other side of the semiconductor element 3.

[0066] Furthermore, the upper surface electrode of the semiconductor element 3 is connected to the circuit board 23 via a wiring member 4. The wiring member 4 has two connection points 40 and 41 on the upper surface of the semiconductor element 3, and one connection point 42 on the circuit board 23. Additionally, the wiring member 4 extends along the X-direction when viewed from above. The wiring member 4 extends parallel to the gate channel 31. Furthermore, the extension direction of the wiring member 4 is orthogonal to the extension directions of the IGBT region 3a and the FWD region 3b.

[0067] like Figure 4 As shown, in the reference example, two wiring members 4 extending in the X direction are arranged in a Y-direction. The wiring members 4 cannot be configured with connection points overlapping the gate channel 31. As described above, in the reference example, the wiring members 4 are parallel to the gate channel 31. Therefore, if it is desired to configure the wiring members 4 in a way that avoids the gate channel 31, the number of wiring members 4 is limited.

[0068] In addition, not limited to Figure 4 Furthermore, it is envisioned that the extension direction of the gate current channel 31 is parallel to the extension directions of the IGBT region 3a and the FWD region 3b. In this case, there is a concern that the current may not flow evenly from the gate current channel to each region. As a result, current imbalance occurs, which can easily cause timing deviations in the switching.

[0069] In contrast, in this embodiment, such as Figure 5 As shown, the gate channel 31 is formed as a rectangular frame that surrounds the entire outer periphery of the semiconductor element 3. Specifically, the gate channel 31 has an outer peripheral portion 32 and a straight portion 33.

[0070] The outer peripheral portion 32 extends from the gate pad 30 along the outer periphery of the semiconductor element 3. More specifically, the outer peripheral portion 32 extends from both ends of the gate pad 30 in the Y direction along the outer periphery of the semiconductor element 3, forming a rectangular frame shape to surround the outer periphery of the semiconductor element 3 (the outer periphery of the upper surface electrode). The straight portion 33 connects the opposing sides of the outer peripheral portion 32 in the Y direction at the center in the X direction. In addition, the straight portion 33 extends along the Y direction in a manner that divides the center of the semiconductor element 3. That is, the straight portion 33 divides the upper surface (upper surface electrode) of the semiconductor element into one side (negative side in the X direction) and the other side (positive side in the X direction).

[0071] Furthermore, the outer peripheral portion 32 is not limited to a structure that surrounds the entire outer periphery of the semiconductor element 3. For example, the outer peripheral portion 32 may be located on at least one side (the negative side in the X direction), that is, on the negative side in the X direction, compared to the straight portion 33.

[0072] Here, the cross-sectional shape of the gate flow channel 31 will be described. For example... Figure 6 and Figure 7As shown, the gate channel 31 (outer peripheral portion 32 and straight portion 33) includes a gate wiring layer 34 and an insulating film 35. The gate wiring layer 34 is formed independently of the upper surface electrode T1, and is made of, for example, a metal layer of the same material as the upper surface electrode T1. The insulating film 35 is used to cover the gate wiring layer 34, and is formed of, for example, a resin such as polyimide. The insulating film 35 covers the top of the gate wiring layer 34 and also covers the edge of the upper surface electrode T1. Therefore, the insulating film 35 has an outer surface shape that bulges upwards from the gate wiring layer 34 and the upper surface electrode T1.

[0073] Additionally, similarly to the above, the wiring member 4 extends along the X direction when viewed from above. The wiring member 4 has two connection points 40 and 41 on the upper surface of the semiconductor element 3, and one connection point 42 on the circuit board 23. Preferably, the plurality of wiring members 4 have at least one connection point on each side of the upper surface of the semiconductor element 3, divided by the straight portion 33. Furthermore, as detailed later, it is preferable that each connection point overlaps with both the IGBT region 3a and the FWD region 3b.

[0074] In particular, in this embodiment, the straight section 33 extends from below the wiring member 4. That is, the wiring member 4 is arranged to cross above the straight section 33. Specifically, the wiring member 4 also has a first arch 4a and a second arch 4b (see reference). Figure 6 ).

[0075] The first arch 4a is connected to connection points 40 and 41, forming an arch that bulges upward between connection points 40 and 41. The second arch 4b is connected to connection points 41 and 42, forming an arch that bulges upward between connection points 41 and 42. The first arch 4a spans over a portion of the gate channel 31 (the straight portion 33). Similarly, the second arch 4b spans over a portion of the gate channel 31 (a portion of the outer peripheral portion 32).

[0076] By arranging the wiring member 4 to intersect with the gate channel 31 (straight section 33) in a top view, the placement of the wiring member 4 is not critical, allowing for the arrangement of more wiring members 4 on the upper surface electrode. For example, in Figure 5 In the middle, a type of electrode is configured on the upper surface electrode. Figure 4 There are 3 more wiring components 4.

[0077] In this way, according to this embodiment, the number of connections of the wiring member 4 (main wiring) can be ensured, and the number of connection points 40 and 41 between the wiring member 4 and the upper surface electrode can be increased. As a result, the heat generation at each connection point can be reduced, thereby reducing the unevenness of heat distribution. Therefore, the heat resistance of the semiconductor module 1 can be improved.

[0078] In this embodiment, the semiconductor element 3 has a rectangular shape when viewed from above, and a gate pad 30 is disposed on one side of the rectangular shape (the side of the semiconductor element 3 corresponding to the negative X-direction side). Furthermore, relative to the circuit board 22, the circuit board 23 (another circuit board) is disposed on the opposite side of the gate pad 30, across the other side of the semiconductor element 3 (the side of the semiconductor element 3 corresponding to the positive X-direction side). According to this structure, control wiring (not shown) connected to the gate pad 30 can be disposed on the negative X-direction side. Conversely, wiring members 4, which are main wiring, can be disposed at a position closer to the positive X-direction side than the control wiring. That is, the control wiring and the main wiring can be disposed separately without overlapping.

[0079] In this embodiment, the semiconductor element 3 is an RC-IGBT element that integrates the IGBT and FWD. The RC-IGBT element has an IGBT region 3a and an FWD region 3b that appear as a strip when viewed from above, below the upper surface electrode.

[0080] like Figure 5 As shown, the semiconductor element 3 has a plurality of IGBT regions 3a extending along the X direction and a plurality of FWD regions 3b extending along the X direction. The IGBT regions 3a and FWD regions 3b are arranged alternately in the Y direction. Figure 5 The system is configured with 4 IGBT zones 3a and 3 FWD zones 3b.

[0081] In particular, Figure 5 In the diagram, the IGBT region 3a and the FWD region 3b extend in the direction (X direction) intersecting the straight portion 33 of the gate channel 31. That is, the IGBT region 3a and the FWD region 3b extend in the same X direction as the wiring member 4 when viewed from above. Furthermore, the extending direction of the IGBT region 3a and the FWD region 3b can also be referred to as the trench direction.

[0082] In RC-IGBT devices, current tends to flow along the trench direction. That is, the current flow direction in RC-IGBT devices is directional. Specifically, the main current flows from the gate pad 30 into the outer periphery 32 and the straight section 33 of the gate channel 31. Then, the main current flows from the straight section 33 along the trench direction to both sides in the X direction in each IGBT region 3a and FWD region 3b.

[0083] Furthermore, since the wiring component 4 supplying the main current extends in the same direction as the aforementioned trench, the direction of the main current flow is unified into a single direction (X direction) as a whole module. As a result, the current flow distribution becomes uniform, thereby suppressing noise and oscillations, and further preventing localized heating.

[0084] Furthermore, in this embodiment, it is preferable that the IGBT region 3a has a wider width than the FWD region 3b. According to this structure, the current distribution in each region can be leveled, thereby suppressing abnormal heating or damage in any one region.

[0085] Furthermore, in this embodiment, it is preferable that the wiring component 4 has at least one connection point that overlaps with both the IGBT region 3a and the FWD region 3b when viewed from above. For example, in the IGBT and FWD, the timing of switching on and off is opposite, and the timing of current flow is also different. If the connection point overlaps only with one of the regions, there is a concern about localized heat generation. Therefore, by making the connection point overlap with both regions, heat distribution can be made uniform and localized heat generation can be suppressed.

[0086] As explained above, according to this embodiment, by arranging the gate flow channel 31 (straight section 33) so as to pass through the bottom of the arched wiring member 4, the number of wiring connections can be ensured to improve heat resistance.

[0087] The following is for reference Figures 8 to 12 Let's illustrate with a variation example. Figures 8 to 12 This is a top view of the area surrounding the semiconductor element involved in the variation example.

[0088] For example, in the above embodiment, the wiring member 4 extends parallel to the extending direction of the IGBT region 3a and the FWD region 3b, but this structure is not limited to this. For example Figure 8 As shown, the wiring component 4 can also be tilted relative to the extension direction of the IGBT region 3a and the FWD region 3b when viewed from above. That is, the wiring component 4 only needs to cross above the gate channel 31 (straight section 33).

[0089] Furthermore, in the above embodiment, the case where each connection point of the wiring component 4 overlaps with the IGBT area 3a and the FWD area 3b when viewed from above was described, but this structure is not limited to this one. For example... Figure 9 As shown, there may also be connection points that overlap only with either IGBT region 3a or FWD region 3b.

[0090] Furthermore, while the above embodiment describes a case where the wiring component 4 is pin-connected, it is not limited to this structure. For example... Figure 10 As shown, it is also possible that for each wiring component, there is only one connection point on the semiconductor element 3. Figure 10In addition to the wiring member 4, a wiring member 5 (second wiring member) shorter than the wiring member 4 is also provided. The wiring member 4 crosses a portion of the outer periphery 32 located on the negative side in the X direction and above the straight section 33. The connection point 40 of the wiring member 4 is located on the negative side in the X direction, closer to the straight section 33. In contrast, the wiring member 5 does not cross above the straight section 33, but crosses above a portion of the outer periphery 32 located on the negative side in the X direction. The connection point 51 of the wiring member 5 is located on the positive side in the X direction, closer to the straight section 33. Furthermore, the connection point 52 of the wiring member 5 is disposed on the circuit board 23.

[0091] Furthermore, in the above embodiment, it was described that the number of connection points on the semiconductor element 3 on the wiring member in the negative X-direction compared to the straight section 33 is the same as the number of connection points in the positive X-direction compared to the straight section 33, but this structure is not limited to this. For example... Figure 11 As shown, the number of connection points of wiring components 4 and 5 on the positive side of the X direction, which is the other side, can also be more than the number of connection points on the negative side of the X direction, which is one side.

[0092] Furthermore, in the above embodiment, the case where the straight portion 33, which is part of the gate flow channel 31, extends along the Y direction at the center of the outer peripheral portion 32 to divide the upper surface electrode into two is described, but this structure is not limited to this. For example, it could also be... Figure 12 The structure shown. In Figure 12 In the middle section, two straight sections 33 extending along the Y direction are connected to each other on opposite sides of the outer peripheral section 32 in the Y direction. The two straight sections 33 divide the upper surface electrode into three regions in the X direction. The wiring member 4 may also have connection points 40 to 42 arranged in each of the divided regions. In addition, the connection points 43, which are the ends of the wiring member 4, are arranged on the circuit board 23.

[0093] Next, refer to Figures 13 to 15 The second embodiment will now be described. Figure 13 This is a top view of the area surrounding the semiconductor element according to the second embodiment. Figure 14 yes Figure 14 A magnified view of a portion of the image. Figure 15 This is a top view of the periphery of the semiconductor element involved in a variation of the second embodiment. Furthermore, in the following, only the layout of the wiring components (especially the bonding locations) differs from the above embodiment; therefore, common structures are labeled with the same reference numerals and descriptions are appropriately omitted.

[0094] As mentioned above, to ensure the robustness of the semiconductor module, the heat generated by the wiring components needs to be considered. For example, even within the short time of a few milliseconds required for the semiconductor module to start operating, localized heat (dissipation) will occur near the chip. Heat dissipation occurs on the back side of the chip via solder and insulating substrate, and on the chip surface via wiring components (bonding leads). In this case, it is conceivable that if there are connection points (bonding points) of the wiring components near the outer periphery of the chip, the heat dissipation area cannot be sufficiently guaranteed.

[0095] Especially in RC-IGBT devices that integrate the IGBT and FWD, as mentioned above, the IGBT region and FWD region are formed as strips extending along a predetermined direction. Therefore, during the short period of a few milliseconds at startup, heat dissipation is not carried out across the entire chip surface, but rather tends to occur in a strip-like pattern. That is, compared to the case where the IGBT and FWD are separate, there are problems such as a smaller heat dissipation area and a larger transient thermal resistance during this short period.

[0096] Therefore, the inventors of this application further focused on the heat dissipation distribution and wiring component layout in RC-IGBT elements, and came up with the present invention.

[0097] like Figure 13 As shown, in the second embodiment, a plurality of IGBT regions 3a and FWD regions 3b extending in a strip shape are arranged alternately along the Y direction. Furthermore, a gate channel 31 is arranged to surround the outer periphery of the semiconductor element 3. As described above, the gate channel 31 is formed as a rectangular frame that surrounds the entire outer periphery of the semiconductor element 3. Specifically, the gate channel 31 has an outer peripheral portion 32 and a straight portion 33.

[0098] The outer peripheral portion 32 extends from the gate pad 30 along the outer periphery of the semiconductor element 3. More specifically, the outer peripheral portion 32 extends from both ends of the gate pad 30 in the Y direction along the outer periphery of the semiconductor element 3, forming a rectangular frame shape to surround the outer periphery of the semiconductor element 3 (the outer periphery of the upper surface electrode). The straight portion 33 connects the opposing sides of the outer peripheral portion 32 in the Y direction at the center in the X direction. In addition, the straight portion 33 extends along the Y direction in a manner that divides the center of the semiconductor element 3. That is, the straight portion 33 divides the upper surface (upper surface electrode) of the semiconductor element into one side (negative side in the X direction) and the other side (positive side in the X direction).

[0099] Here, the straight section 33 is referred to as the first straight section 33, and the two straight sections of the outer peripheral section 32 arranged opposite to the first straight section 33 are referred to as the second straight section 32a. The second straight section 32a is composed of a portion of the outer peripheral section 32 extending along the outer periphery of the semiconductor element 3 from the gate pad 30. Such an outer peripheral section 32 constitutes a heat-resistant structural portion of the semiconductor element 3.

[0100] As described above, the first straight section 33 is connected to the outer peripheral section 32 and extends in such a way that it divides the center of the semiconductor element 3. In addition, the first straight section 33 is located in the center between the two second straight sections 32a. The first straight section 33 and the two second straight sections 32a are parallel to each other along the Y direction and extend in a direction that intersects the extension direction (X direction) of the IGBT region 3a and the FWD region 3b.

[0101] Furthermore, the wiring component 4 is configured to extend along the X direction above the semiconductor element 3, crossing above the first straight section 33 and the second straight section 32a. As described above, the wiring component 4 is electrically connected to the main electrode and the designated circuit board 23 via pin-type connections, and has multiple connection points 40, 41, and 42 (connection points). Additionally, in Figure 13 In the middle, three wiring components 4 are arranged along the Y direction.

[0102] Connection point 40 is disposed in a rectangular region on the negative side of the X-direction within a region that is rectangular in shape when viewed from above, surrounded by gate channel 31. Furthermore, connection point 40 is configured to overlap with center line C, which is located at an equidistant position from the first straight section 33 and the second straight section 32a when viewed from above. Center line C extends parallel to the first straight section 33 and the second straight section 32a between them.

[0103] Connection point 41 is disposed in a rectangular region on the positive side in the X direction within a region that is rectangular in shape when viewed from above, surrounded by gate channel 31. Connection point 41, like connection point 40, is also disposed so that it overlaps with the center line C located at a position equidistant from the first straight section 33 and the second straight section 32a when viewed from above.

[0104] By arranging connection points 40 and 41 at equal distances from the gate flow channels 31 (first straight section 33, second straight section 32a) extending along the Y direction, the heat dissipation area can be maximized uniformly. As a result, transient thermal resistance can be reduced, and temperature ripple can be further reduced.

[0105] In addition, Figure 13 In the diagram, connection points 40 and 41, in whole or in part, overlap with IGBT region 3a when viewed from above. When the semiconductor module begins operation, current flows through IGBT region 3a, thus suppressing transient thermal resistance for a short period and preventing localized heating during startup.

[0106] Furthermore, the above description illustrates the case where connection points 40 and 41 are formed into a rectangular shape (approximately square) when viewed from above, but this structure is not limited to this configuration. For example... Figure 14 A, Figure 14As shown in B, connection points 40 and 41 can also have an elongated oval shape that is longer in the extension direction (X direction) of wiring member 4 when viewed from above.

[0107] Additionally, in the above, such as Figure 14 As shown in Figure A, this illustrates the case where centerline C overlaps (is consistent with) the centerlines of connecting points 40 and 41, but it is not limited to this and can be appropriately modified. For example... Figure 14 As shown in B, it is sufficient that at least a portion of the connection points 40 and 41 overlap with the center line C. The center line C1 in the X direction (long side direction) of the connection points 40 and 41 does not necessarily have to be consistent with the center line C.

[0108] For example, when the distance between centerline C and centerline C1 is set as dx, and the width along the long side of connecting points 40 and 41 is set as X1, it is preferable to satisfy the relationship 0 ≤ dx ≤ X1. If it is within this range, the above-mentioned effects can be fully enjoyed.

[0109] In addition, Figure 13 The text describes situations where connection points 40 and 41, in whole or in part, overlap with IGBT region 3a when viewed from above, but is not limited to this structure. For example... Figure 15 As shown, the connection points 40 and 41 can also be configured such that they overlap entirely or mostly with the FWD region 3b when viewed from above. In this case, localized heating can be suppressed when current flows in the FWD region 3b due to back electromotive force.

[0110] Furthermore, in the above embodiments, the number and layout of the circuit boards are not limited to the above structure and can be appropriately changed.

[0111] Furthermore, in the above embodiment, the laminated substrate 2 and the semiconductor element are configured to have a rectangular or square shape when viewed from above, but are not limited to this structure. The laminated substrate 2 and the semiconductor element may also be configured to have a polygonal shape other than those described above.

[0112] Furthermore, while this embodiment and its variations have been described, other embodiments may also be obtained by combining the above-described embodiments and variations in whole or in part.

[0113] Furthermore, this embodiment is not limited to the above-described embodiments and variations, and various changes, substitutions, and modifications can be made without departing from the spirit of the technical concept. Moreover, if the technical concept can be realized in other ways due to technological advancements or derived technologies, this method can also be used. Therefore, the claims cover all embodiments that can be included within the scope of the technical concept.

[0114] The feature points in the above embodiments are summarized below.

[0115] The semiconductor module described in the above embodiments includes: a laminated substrate in which a plurality of circuit boards are disposed on the upper surface of an insulating plate; a semiconductor element disposed on a predetermined circuit board, the upper surface of the semiconductor element having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad; and a wiring member that electrically connects the main electrode to other circuit boards, the gate channel extending in a manner that divides the main electrode into one side and another side, and the wiring member being disposed across the top of the gate channel.

[0116] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element has a rectangular shape when viewed from above, the gate pad is disposed on one side of the semiconductor element corresponding to one side, the other circuit board is disposed on the opposite side of the gate pad across the other side of the semiconductor element corresponding to the other side, and the gate channel intersects the wiring member when viewed from above.

[0117] Furthermore, in the semiconductor module described in the above embodiments, the gate channel extends in such a way that it divides the upper surface of the semiconductor element into the center, thereby dividing the main electrode into at least two.

[0118] Furthermore, in the semiconductor module described in the above embodiments, the wiring component is composed of multiple conductor lines.

[0119] In addition, the semiconductor module described in the above embodiments also includes a second wiring member, which is shorter than the wiring member and has at least one connection point on the other side.

[0120] Furthermore, in the semiconductor module described in the above embodiments, the wiring member has at least one connection point on one side of the upper surface of the semiconductor element.

[0121] Furthermore, in the semiconductor module described in the above embodiments, the number of connection points of the wiring member and the second wiring member on the other side is greater than the number of connection points on the one side.

[0122] Furthermore, in the semiconductor module described in the above embodiments, the number of connection points of the wiring member and the second wiring member on one side is the same as the number of connection points on the other side.

[0123] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element is an RC (Reverse Conducting)-IGBT element that integrates an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode). The semiconductor element also has a plurality of IGBT regions and FWD regions that extend in a strip shape when viewed from above, and the plurality of IGBT regions and the FWD regions are arranged alternately.

[0124] Furthermore, in the semiconductor module described in the above embodiments, the IGBT region and the FWD region extend in a direction that intersects with the gate flow channel.

[0125] Furthermore, in the semiconductor module described in the above embodiments, the IGBT region has a width larger than that of the FWD region.

[0126] Furthermore, in the semiconductor module described in the above embodiments, the wiring member is tilted relative to the extension direction of the IGBT region and the FWD region when viewed from above.

[0127] Furthermore, in the semiconductor module described in the above embodiments, the wiring component has at least one connection point that overlaps with both the IGBT region and the FWD region when viewed from above.

[0128] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element has a rectangular shape when viewed from above, and the semiconductor element also has a gate pad disposed on one side of the rectangular shape. The gate channel has: an outer peripheral portion that extends from the gate pad along the outer periphery of the semiconductor element; and a straight portion that is connected to the outer peripheral portion and extends in a manner that divides the center of the semiconductor element. The wiring member is disposed over the straight portion and / or the outer peripheral portion.

[0129] Furthermore, the semiconductor module described in the above embodiments includes: a laminated substrate in which a plurality of circuit boards are disposed on the upper surface of an insulating plate; a semiconductor element disposed on a predetermined circuit board, the upper surface of the semiconductor element having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad; and wiring members that electrically connect the main electrode to other circuit boards, wherein the semiconductor element is an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Transistor). The semiconductor device is an RC (Reverse Conducting)-IGBT element integrated with a diode. The semiconductor device also has a plurality of IGBT regions and FWD regions that extend in a strip and are alternately arranged when viewed from above. The gate channel has: a first straight portion that extends in a manner that divides the main electrode into one side and another side; and a second straight portion that is arranged opposite to the first straight portion and extends along the outer periphery of the semiconductor device. The first straight portion and the second straight portion extend in a direction that intersects with the IGBT regions and the FWD regions. The wiring member is arranged in a manner that at least crosses the top of the first straight portion. At least a portion of the connection point of the wiring member to the main electrode overlaps with the center line located at a position equidistant from the first straight portion and the second straight portion when viewed from above.

[0130] Furthermore, in the semiconductor module described in the above embodiments, the center line extends parallel to the first straight section and the second straight section between the first straight section and the second straight section.

[0131] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element has a rectangular shape when viewed from above, and the gate pad is disposed on one side of the rectangular shape. The second straight portion is formed by a portion of an outer peripheral portion extending from the gate pad along the outer periphery of the semiconductor element. The outer peripheral portion constitutes a heat-resistant structural portion of the semiconductor element. The first straight portion is connected to the outer peripheral portion and extends in a manner that divides the center of the semiconductor element.

[0132] Furthermore, in the semiconductor module described in the above embodiments, the wiring member extends in a direction that intersects with the first straight portion when viewed from above, and the connection point of the wiring member has an elongated oval shape that is longer in the extending direction of the wiring member when viewed from above.

[0133] Furthermore, in the semiconductor module described in the above embodiments, the connection point of the wiring member overlaps with the IGBT region when viewed from above.

[0134] Furthermore, in the semiconductor module described in the above embodiments, the connection point of the wiring component overlaps with the FWD area when viewed from above.

[0135] Industrial availability

[0136] As explained above, the present invention has the effect of improving heat resistance by ensuring the number of connections in the main wiring, which is particularly useful for semiconductor modules.

[0137] This application is based on Japanese Special Application 2020-117233, filed on July 7, 2020. Its entire contents are hereby included.

Claims

1. A semiconductor module, comprising: A laminated substrate in which multiple circuit boards are disposed on the upper surface of an insulating plate; A semiconductor element disposed on a defined circuit board, having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad on its upper surface; and Wiring components that electrically connect the main electrode to other circuit boards. The gate channel extends in a manner that divides the main electrode into one side and the other side. The wiring components are configured to extend over the gate channel. in, The wiring component has a first arch and a second arch. The first arch is connected to a connection point located on one side and a connection point located on the other side, forming an upwardly convex arch between these two connection points. The second arch is connected to a connection point located on the other side and a connection point located on the other circuit board, forming an upwardly convex arch between these two connection points. It also includes a second wiring component, which is shorter than the first wiring component and has at least one connection point on the other side.

2. The semiconductor module according to claim 1, wherein, The semiconductor element has a rectangular shape when viewed from above. The gate pad is disposed on one side of the semiconductor element corresponding to one of the sides. The other circuit boards are positioned on the opposite side of the gate pad, separated from the semiconductor element by the other side. The gate channel intersects with the wiring component when viewed from above.

3. The semiconductor module according to claim 1 or 2, wherein, The gate channel extends in a manner that divides the upper surface of the semiconductor element, dividing the main electrode into at least two. The wiring component is divided into multiple regions on the upper surface of the semiconductor element, and each region has at least one connection point.

4. The semiconductor module according to claim 1 or 2, wherein, The wiring component is composed of multiple conductor wires.

5. The semiconductor module according to claim 1 or 2, wherein, The gate channel extends on the upper surface of the semiconductor device in a manner that divides the main electrode into three or more regions. The wiring component is divided into multiple regions on the upper surface of the semiconductor element, and each region has at least one connection point.

6. The semiconductor module according to claim 1, wherein, The number of connection points on the other side of the wiring component and the second wiring component is greater than the number of connection points on the first side.

7. The semiconductor module according to claim 1, wherein, The number of connection points on one side of the wiring component and the second wiring component is the same as the number of connection points on the other side.

8. The semiconductor module according to claim 1 or 2, wherein, The semiconductor device is an RC-IGBT device, which integrates an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD). The semiconductor device also has multiple IGBT regions and FWD regions that extend in a strip-like shape when viewed from above. Multiple IGBT regions are alternately configured with the FWD region. The IGBT region and the FWD region extend in a direction that intersects with the gate flow channel.

9. The semiconductor module according to claim 8, wherein, The connection points of the wiring components are configured to be biased toward the IGBT region.

10. The semiconductor module according to claim 8, wherein, The IGBT region has a width that is larger than the width of the FWD region.

11. The semiconductor module according to claim 8, wherein, The wiring component is tilted relative to the extension direction of the IGBT area and the FWD area when viewed from above.

12. The semiconductor module according to claim 8, wherein, The wiring component has at least one connection point that overlaps with both the IGBT area and the FWD area when viewed from above.

13. The semiconductor module according to claim 1 or 2, wherein, The semiconductor element has a rectangular shape when viewed from above, and the semiconductor element also has a gate pad disposed on one side of the rectangular shape. The gate channel has: The outer peripheral portion extends from the gate pad along the outer periphery of the semiconductor element; as well as A straight section, which is connected to the outer peripheral section, extends in a manner that divides the center of the semiconductor element. The wiring component is configured to span over the straight portion and / or the outer periphery.

14. A semiconductor module comprising: A laminated substrate in which multiple circuit boards are disposed on the upper surface of an insulating plate; A semiconductor element disposed on a defined circuit board, having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad on its upper surface; and Wiring components that electrically connect the main electrode to other circuit boards. The gate channel extends in a manner that divides the main electrode into one side and the other side. The wiring components are configured to extend over the gate channel. in, The wiring component has a first arch and a second arch. The first arch is connected to a connection point located on one side and a connection point located on the other side, forming an upwardly convex arch between these two connection points. The second arch is connected to a connection point located on the other side and a connection point located on the other circuit board, forming an upwardly convex arch between these two connection points. The gate channel extends on the upper surface of the semiconductor device in a manner that divides the main electrode into three or more regions. The wiring component is divided into multiple regions on the upper surface of the semiconductor element, and each region has at least one connection point.

15. A semiconductor module comprising: A laminated substrate in which multiple circuit boards are disposed on the upper surface of an insulating plate; A semiconductor element disposed on a defined circuit board, having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad on its upper surface; and Wiring components that electrically connect the main electrode to other circuit boards. The semiconductor device is an RC-IGBT device, which integrates an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD). The semiconductor device also has multiple IGBT regions and FWD regions that extend in a strip and are alternately arranged when viewed from above. The gate channel has: A first straight section extends in such a manner that it divides the main electrode into one side and another side; and The second straight section is disposed opposite to the first straight section and extends along the outer periphery of the semiconductor element. The first straight section and the second straight section extend in a direction intersecting the IGBT region and the FWD region. The wiring member is configured to at least extend above the first straight section, and at least a portion of the connection point of the wiring member to the main electrode overlaps with a centerline located at an equidistant position from the first and second straight sections when viewed from above. in, The wiring component has a first arch and a second arch. The first arch is connected to a connection point located on one side and a connection point located on the other side, forming an upwardly convex arch between these two connection points. The second arch is connected to a connection point located on the other side and a connection point located on the other circuit board, forming an upwardly convex arch between these two connection points. It also includes a second wiring component, which is shorter than the first wiring component and has at least one connection point on the other side.

16. The semiconductor module according to claim 15, wherein, The center line extends parallel to both the first straight section and the second straight section between them.

17. The semiconductor module according to claim 15 or 16, wherein, The semiconductor element has a rectangular shape when viewed from above, and the gate pad is disposed on one side of the rectangular shape. The second straight portion is formed by a portion of an outer peripheral portion extending from the gate pad along the outer periphery of the semiconductor element. The outer peripheral portion constitutes the heat-resistant structural portion of the semiconductor element. The first straight portion is connected to the outer peripheral portion and extends in a manner that divides the center of the semiconductor element.

18. The semiconductor module according to claim 15 or 16, wherein, The wiring component extends in a direction that intersects with the first straight section when viewed from above. The connection point of the wiring component has an elongated oval shape that is long in the extending direction of the wiring component when viewed from above.

19. The semiconductor module according to claim 15 or 16, wherein, The connection point of the wiring component overlaps with the IGBT area and the FWD area when viewed from above.

20. A semiconductor module comprising: A laminated substrate in which multiple circuit boards are disposed on the upper surface of an insulating plate; A semiconductor element disposed on a defined circuit board, having a main electrode, a gate pad, and a gate channel electrically connected to the gate pad on its upper surface; and Wiring components that electrically connect the main electrode to other circuit boards. The semiconductor device is an RC-IGBT device, which integrates an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD). The semiconductor device also has multiple IGBT regions and FWD regions that extend in a strip and are alternately arranged when viewed from above. The gate channel has: A first straight section extends in such a manner that it divides the main electrode into one side and another side; and The second straight section is disposed opposite to the first straight section and extends along the outer periphery of the semiconductor element. The first straight section and the second straight section extend in a direction intersecting the IGBT region and the FWD region. The wiring member is configured to at least extend above the first straight section, and at least a portion of the connection point of the wiring member to the main electrode overlaps with a centerline located at an equidistant position from the first and second straight sections when viewed from above. in, The wiring component has a first arch and a second arch. The first arch is connected to a connection point located on one side and a connection point located on the other side, forming an upwardly convex arch between these two connection points. The second arch is connected to a connection point located on the other side and a connection point located on the other circuit board, forming an upwardly convex arch between these two connection points. The gate channel extends on the upper surface of the semiconductor device in a manner that divides the main electrode into three or more regions. The wiring component is divided into multiple regions on the upper surface of the semiconductor element, and each region has at least one connection point.

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