Method for operating a power electronic converter device having a floating unit

Abstract

The invention relates to a method for operating a power electronic converter device (36) for a power conversion system, the converter device (36) comprising a converter circuit (10) and a control device (40), the converter circuit (10) comprising an input side (12) with input terminals (14), an output side (16) with output terminals (18), a first converter (20) with semiconductor devices (26) and at least one second converter (22) connected in series with the first converter (20), the second converter (22) comprising a floating unit (28) with a DC intermediate circuit (32) and semiconductor devices (30), or a plurality of second converters (22) with DC intermediate circuits (32) and semiconductor devices (30). A series connection of a C intermediate circuit (32) and a floating unit (28) of a semiconductor device (30), the floating unit (28) and a control device (40) for driving the semiconductor device (26, 30) of at least one of the converters (20, 22) via a pulse-shaped signal, wherein the two converters (20, 22) generate voltages (42, 44) with step voltage changes, and an output voltage (46) of a power electronic converter device (36) is generated due to the superposition of the voltages (42, 44) of the two converters (20, 22), wherein the voltage (42) of the first converter (20) is a fundamental component of the output voltage (46). The control device (40) drives the semiconductor devices (30) of the at least one floating cell (28) in such a way that the voltage (44) of the second converter (22) has a temporary voltage characteristic (56) which reduces the step size at the output voltage (46) compared to the step size at the voltage (42) of the first converter (20) if the step size at the voltage (42) of the first converter (20) exceeds a step size limit. The invention also relates to a corresponding computer program product and a corresponding power electronic converter device (36) for a power conversion system.

Description

Technical Field

[0001] The present invention relates to a method, a computer program product and a computer readable medium for operating a power electronic converter device for a power conversion system. Furthermore, the present invention relates to a power electronic converter device. Background Art

[0002] Document EP 1 253 706 B1 discloses a power conversion system having a power electronic converter device, comprising: (i) a converter circuit including an input side having input terminals, a three-phase output side having output terminals, a first converter, and three second converters, each of the second converters being connected in series with the first converter relative to a corresponding phase, each of the second converters including a floating unit having a capacitive element in a DC intermediate circuit and a semiconductor device; and (ii) a control device for driving the semiconductor device of at least one converter via a pulse-shaped signal. The two converters are arranged to generate a voltage with a step voltage variation, and the output voltage of the power electronic converter device is generated by superimposing the voltages of the two converters, wherein the voltage of the first converter is the fundamental component of the output voltage at the output terminals. Specifically, the converter circuit comprises a first converter as a main converter and three auxiliary floating units, one for each phase. In such a converter circuit, the number of floating units per phase is not fixed, and a larger number of floating units can be accommodated. The complete DC-to-AC conversion circuit thus takes the form of a main power converter, comprising a first converter, an auxiliary switching element of a second converter, and a passive filtering circuit. The main converter is shown as a three-level neutral-point clamped converter using IGCTs, but other topologies and semiconductor types are possible. With the aid of a floating element, a DC voltage can be added to or subtracted from the DC voltage of the first converter.

[0003] Documents RU 2 269 196 C1 and US Pat. No. 7,825,540 B2 each describe a very similar power conversion system having a power electronic converter device.

[0004] The main difficulty with such power electronic converter devices using state-of-the-art hybrid multilevel and universal OPP modulation schemes is the occurrence of large voltage steps in the output voltage. The voltage steps of the power electronic converter device should be as small as possible to minimize overvoltages at the load terminals and in the resistors of the corresponding EMC filters (EMC: electromagnetic compatibility).

[0005] US 2019 / 190397 A1 describes a converter system having a main converter and floating converter cells connected to the output of the main converter. Each floating converter cell is controlled by quantizing the output voltage error and the cell capacitor voltage and selecting the switching command for the floating converter cell from a lookup table indexed by the quantized output voltage error and the quantized capacitor voltage. The main converter and floating cells are modulated separately.

[0006] US Pat. No. 6,009,002 A) describes a power electronics circuit having an NPC converter and a floating cell connected to the AC output of the NPC converter. The floating cell's DC link is powered via a dedicated rectifier and transformer. The third harmonic is mixed with the reference oscillation of the power electronics circuit to ensure that the cell's active power never goes negative at any operating point. This is necessary because the cell is powered by a diode rectifier. Energy feedback from the floating cell can be avoided, thereby improving the efficiency of the entire system. Switching losses can therefore be kept extremely low.

[0007] Rufer A et al., "Control of a Hybrid Asymmetric Multilevel Inverter for Competitive Medium-Voltage Industrial Drives" (IEEE Transactions on Industrial Applications, IEEE Service Center, Piscataway, New Jersey, USA, Vol. 41, No. 2, March 1, 2005, pp. 655-664), describes a converter system consisting of an NPC converter and a floating cell connected to the AC output of the NPC converter. The ratio between the DC link voltages of the NPC converter and the floating cell is an integer, in this case three, resulting in a nine-level converter system. This converter system is modulated using a carrier-based PWM level. Furthermore, this approach does not guarantee a zero fundamental voltage component for the floating cell, which is necessary to maintain a constant average capacitor voltage and avoid undesirable capacitor charging / discharging of the cell when no voltage source is present.

[0008] EP 3 142 236 A1 relates to a converter control with an optimized pulse pattern calculated offline, wherein the optimized pulse pattern is adjusted online such that the difference between a converter flux reference and a converter flux estimate is minimized.

[0009] WO 2018 / 072 837 A1 describes a modular multilevel converter with a star-connected branch made of series-connected converter cells. The converter is controlled using an optimized pulse pattern calculated offline, which is further optimized online using model predictive control. Summary of the Invention

[0010] It is therefore an object of the present invention to provide means for overcoming the above difficulties.It is another object of the present invention to provide means for controlling a converter having a floating cell connected to the AC output of a main converter in a simple, computationally inexpensive manner and with low harmonic distortion.

[0011] Advantageous embodiments are given in the further description and in the drawings, wherein the described embodiments can provide the features of the invention individually or in any combination of the individual embodiments, unless explicitly excluded.

[0012] A method for operating a converter device for a power conversion system is described, the power electronic converter device comprising a converter circuit including an input side having input terminals, an output side having at least one AC output terminal (such as three AC output terminals), a first converter having semiconductor devices (wherein the first converter is connected to the input terminals), and at least one second converter connected between the AC output of the first converter and the AC output terminals. The second converter comprises a floating cell having a DC intermediate circuit and semiconductor devices, or a series connection of a plurality of floating cells, each floating cell having a DC intermediate circuit and semiconductor devices.

[0013] The power electronic converter device may comprise a control device for driving semiconductor devices of at least one converter, for example via pulse-shaped signals. The method may be performed by the control device.

[0014] The first converter and the second converter are switched in a switching pattern, which includes a first switching instant for the semiconductor device of the first converter and a second switching instant for the semiconductor device of the second converter, so that the two converters generate a voltage with a step voltage change, and the output voltage of the power electronic converter device is produced due to the superposition of the voltages of the two converters.

[0015] The switching instants of the switching pattern are selected such that if the step size of the first switching instant of the first converter exceeds a step size limit, a compensating switching instant for the second converter is included in the switching pattern, the compensating switching instant resulting in a voltage at the second converter that is reduced by the step size at the output voltage compared to the step size at the voltage of the first converter. This can reduce load stress and losses in passive filters that may be present between the converters and the load.

[0016] The switching pattern includes a switching instant for the second converter, the switching instant being adjacent to the compensating switching instant, and the direction and timing of the switching instant being selected such that the voltage of the second converter maintains the fundamental voltage component of the voltage of the first converter. The second converter and / or the floating unit are controlled such that they do not generate the fundamental component of the output voltage. This simplifies control and / or optimization of the optimized pulse pattern.

[0017] The voltage of the first converter provides the fundamental component of the output voltage. According to several embodiments of the present invention, the control device drives the semiconductor device of at least one floating cell so that the voltage of the second converter has a temporary voltage characteristic that reduces the step size of the output voltage compared to the step size of the voltage of the first converter if the step size of the voltage of the first converter exceeds a step size limit. This measure can reduce the height of the voltage step of the power electronic converter device to minimize overvoltages in the load terminals and in the resistors of the corresponding EMC filter (EMC: electromagnetic compatibility). The compensating switching instants of the second converter and the corresponding adjacent switching instants can be regarded as temporary voltage characteristics that reduce the step size at the output.

[0018] According to an embodiment of the present invention, the switching pattern is stored in a table of pre-calculated optimized pulse patterns. Such a table may be provided in a controller. Pre-calculation may refer to the optimization and / or calculation of the optimized pulse pattern before the converter device is operated. This may be performed in a computing device remote from the converter device.

[0019] According to an embodiment of the present invention, the switching pattern has been optimized offline so that the first switching instant generates the fundamental voltage component and the second switching instant maintains the fundamental voltage component unchanged. Generally, the switching pattern may include a first optimized pulse pattern for the first converter (which provides the first switching instant) and a second optimized pulse pattern for the second converter (which provides the second switching instant). The optimization objectives of these two optimized pulse patterns may be different. The optimization objective of the first optimized pulse pattern may be to generate the fundamental voltage component alone. The optimization objective of the second optimized pulse pattern may be to not generate the fundamental voltage component at all.

[0020] According to an embodiment of the invention, the switching pattern is modified on-line by including compensating switching transients and adjacent switching transients into a pre-calculated optimized pulse pattern.

[0021] The control device may generate the temporary voltage characteristic by driving the semiconductor device of the at least one floating cell using the modified pulse pattern.

[0022] According to an embodiment of the present invention, the switching times of the included adjacent switching transients are optimized online so that the voltage of the second converter maintains the fundamental voltage component of the voltage of the first converter unchanged. Compensating switching transients and / or adjacent switching transients can also be included online in the pre-calculated optimized pulse pattern. At least one time interval of the step voltage change at the temporary voltage characteristic can be at least partially smaller than the time constant of the step voltage change of the remaining voltages of the two converters.

[0023] According to an embodiment of the present invention, the compensation switching transient results in a double-step voltage change between the positive and negative voltages of the floating cell. The floating cell can switch between states of providing no voltage, providing a positive voltage, and providing a negative voltage, that is, switching between three different output voltages. The floating cell can provide one double voltage step and two single voltage steps, one in the positive and one in the negative direction. By using the double step, voltage steps exceeding the limit of the first converter can be compensated.

[0024] According to an embodiment of the present invention, adjacent switching instants result in a single-step voltage change between a positive voltage and zero voltage or a negative voltage and zero voltage. By a single step, a double step can be prepared, and the voltage change caused by different switching seconds can be compensated by another single step.

[0025] According to an embodiment of the present invention, in order to compensate for a step size exceeding a step size limit at a first switching instant of the first converter, the second switching instant includes a single step voltage change in a first direction prior to a switching time of the first switching instant. Furthermore, the second switching instant includes a compensating switching instant at a switching time of the first switching instant, with a double step voltage change in an opposite direction.

[0026] According to an embodiment of the invention, the second switching instant comprises a single step voltage change exceeding a step size limit in the first direction after a switching time of the first switching instant.

[0027] According to an embodiment of the invention, the second switching instant comprises two single step voltage changes exceeding a step size limit in the first direction at different switching times before the switching time of the first switching instant.

[0028] According to an embodiment of the invention, the second switching instant comprises two single step voltage changes exceeding a step size limit in the first direction at different switching times after the switching time of the first switching instant.

[0029] For example, the step voltage change at the temporary voltage characteristic is one of: (a) a positive-negative scheme, (b) a negative-positive scheme, (c) a positive-negative-positive scheme, and (d) a negative-positive-negative scheme.

[0030] According to another embodiment of the invention, the compensating switching transients and the adjacent switching transients are included into the pre-calculated optimized pulse pattern.The temporary voltage characteristic may be generated by online post-processing by means of a multi-level modulation scheme.

[0031] According to an embodiment of the present invention, the temporary voltage characteristic is generated by online post-processing by means of an OPP modulator.

[0032] According to another embodiment of the present invention, a pre-calculated switching pattern is optimized based on at least one cost function and a constraint. Based on the at least one cost function and the constraint, a control device can drive a semiconductor device by using an offline-calculated OPP. The offline-calculated optimized pulse pattern (OPP) is also known as synchronous optimized PWM (SO-PWM). OPP is a specific pulse width modulation (PWM) method that can achieve an optimal distribution of harmonic energy across the entire frequency spectrum based on a user-defined cost function and constraints.

[0033] According to a further embodiment of the invention, the switching pattern consists of an optimized pulse pattern of the first converter and the second converter, the optimized pulse pattern being based on individual cost functions and constraints. The OPP of the first converter and each DC intermediate circuit is based on individual cost functions and constraints.

[0034] Another aspect of the invention relates to a computer program product comprising a computer-executable program code portion having program code instructions configured to carry out the above-described method when loaded into a control device, in particular into a processor of a computer-based control device. Another aspect of the invention relates to a computer-readable medium having such a computer program product stored therein.

[0035] Another aspect of the present invention relates to a power electronic converter device for use in a power conversion system as described above and below. The power electronic converter device includes a control device configured to perform the method described above and below. The control device can be arranged to drive the semiconductor devices of at least one floating cell so that the voltage of the second converter has a temporary voltage characteristic that reduces the step size of the output voltage compared to the step size of the voltage of the first converter if the step size of the voltage of the first converter exceeds a step size limit. Hereinafter, the voltage of the intermediate circuit is also referred to as the voltage of the floating cell.

[0036] Advantageous embodiments mentioned in connection with the process for operating a power electronic converter device shall also apply mutatis mutandis to the corresponding power electronic converter device and vice versa.

[0037] The control device may be arranged to drive the semiconductor device of the at least one floating cell by using the modified pulse pattern to generate the temporary voltage characteristic.

[0038] According to an embodiment of the invention, at least one time interval of the step voltage change at the temporary voltage characteristic is at least partially smaller than a time constant of the step voltage change of the residual voltages of the two converters.

[0039] The step voltage change at the temporary voltage characteristic may be one of the following schemes: (a) a positive-negative scheme, (b) a negative-positive scheme, (c) a positive-negative-positive scheme, and (d) a negative-positive-negative scheme.

[0040] According to a further embodiment of the converter device according to the invention, the power electronic converter is arranged to generate the temporary voltage characteristic by using a multi-level modulation scheme and / or an online post-processing of an OPP modulator.

[0041] According to an embodiment of the present invention, the control apparatus is adapted to drive the semiconductor device based on at least one cost function and a constraint by using an OPP calculated offline.

[0042] Further features of the invention are apparent from the drawings and the description of the drawings. All features and feature combinations mentioned above in the description as well as features and feature combinations mentioned below in the description of the drawings and / or shown only in the drawings can be used not only in the respectively specified combination but also in other combinations or alone.

[0043] Now, the present invention is explained in more detail based on preferred embodiments and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] These and other aspects of the invention will become apparent from and will be elucidated with reference to the embodiments described hereinafter. The various features disclosed in the embodiments may constitute an aspect of the invention alone or in combination. Features of different embodiments may be transferred from one embodiment to another.

[0045] In the attached figure:

[0046] Figure 1 A schematic diagram showing a converter circuit having a first converter and a second converter of a power electronic converter device according to a first embodiment of the present invention;

[0047] Figure 2 shows a schematic diagram of a power electronic converter device according to a second embodiment of the present invention together with a three-phase load connected to the power electronic converter device,

[0048] Figure 3 Two-level switching mode signals for 3LANPC and AFC configurations are shown;

[0049] Figure 4 shows a schematic diagram of a two-stage modulator;

[0050] Figure 5 shows a switching mode of a step size reduction scheme according to a preferred embodiment of the present invention;

[0051] Figure 6 Three implementation options (a)-(c) of a step size reduction scheme for a modulation scheme with controllable number of individual pulses are shown;

[0052] Figure 7 shows the TDD as a function of modulation index when a 3LNPC converter is connected in series with an AFC;

[0053] Figure 8 shows the AFC fundamental component as a function of modulation index when a 3LANPC converter is connected in series with an AFC; and

[0054] Figure 9 A comparison of 3LANPC switching transitions without and with the proposed step size reduction scheme is shown. DETAILED DESCRIPTION

[0055] Figure 1 A schematic diagram of a converter circuit 10 is shown. The converter circuit 10 shows a single phase of a three-phase converter device, comprising an input side 12 with input terminals 14, an output side 16 with output terminals 18, a first converter 20, and a second converter 22 connected in series with the first converter 20. The first converter 20 is a neutral point clamped (NPC) converter or an active neutral point clamped (ANPC) converter. It can be another three-level converter, a two-level converter, or a converter with more than three levels. The first (main) converter 20 comprises a capacitive element 24 (depicted as a capacitor) and a semiconductor device 26. The second converter 22 comprises a series connection of a plurality of floating cells 28. These floating cells 28 act as active filters (AF) and are therefore also referred to as "AF cells" (AFCs) or "H-bridge AF cells." Each floating cell 28 comprises two pairs of semiconductor devices 30 and a DC intermediate circuit 32, wherein a capacitive element 34 (depicted as a capacitor) is interconnected between the two pairs of semiconductor devices 30. The capacitive element 34 has a voltage V that results in a corresponding voltage V at the DC intermediate circuit 32. C AF Capacitor C AF .

[0056] The basic AF control goal is to compensate the three-phase (3L)(A) NPC output waveform harmonics while reducing the capacitor voltage V C AFThe average value of the floating cells 28 is maintained at its reference value (AF balance). The balanced control concept should also be able to use floating cells 28 as an add-on to existing converters. An additional control requirement is its suitability for a modular concept to ensure that it can easily scale to higher DC bus voltages and higher capacitor voltages as well as a greater number of floating cells 28.

[0057] Figure 2 The figure shows a power electronic converter device 36 according to a first embodiment and a load 38 connected to the output side 20 of the converter device 36. The converter device 36 includes a converter circuit 10 and a control device 40 for driving the semiconductor devices 26, 30 of at least one of the converters 20, 22 via a pulse-shaped signal. The control device 40 drives the semiconductor devices 26, 30, for example, by using an OPP.

[0058] In this example, the first converter 20 and the floating cell 28 are modulated by the OPP for the three-phase load 38. The step size of the switching transitions for the 3L(A)NPC is higher than the step size of the AF switching transitions. The fundamental voltage component must be generated only by the first converter 20 (the 3L(A)NPC converter), and the fundamental voltage component of the floating cell(s) 28 is zero because it cannot provide active power. The resulting voltage 46 at the load 38 is depicted as a three-phase voltage curve.

[0059] According to a preferred embodiment, the series-connected converters 20, 22 (such as Figure 2 The topology depicted in FIG3 is modulated with an offline-calculated optimized pulse pattern (OPP), also known as synchronized optimal PWM (SO-PWM). OPP is a specific pulse width modulation (PWM) method that can achieve an optimal distribution of harmonic energy across the entire frequency spectrum based on a user-defined cost function and constraints. Compared to classic CB-PWM, improved voltage and current quality, such as lower TDD (Total Demand Distortion), can be achieved. OPP has been successfully applied to medium-voltage multilevel converters. For the calculation of the multilevel OPP, only the different levels of the waveform are usually considered, without any special consideration of the type (cascaded H-bridge, modular multilevel converter, etc.) and individual characteristics (voltage level, number of pulses, fundamental component) of the different converter stages of the power electronic converter device 36.

[0060] For a power electronic converter arrangement 36 having converters 20, 22 connected in series, the optimization problem can be formulated and solved for each converter 20, 22 separately, thereby generating an individual OPP based on an individual cost function and a set of constraints. However, for converters 20, 22 connected in series, the voltage 46 applied to the load 38 (e.g., an electric machine such as a motor) is the sum of the individual voltage contributions 42, 44, as shown in FIG. Figure 2 and Figure 3This key observation demonstrates that, if the goal is to improve voltage and current quality, as determined by the spectrum of the total voltage, solving the individual optimization problem for each converter 20, 22 will generally not yield an optimal solution. It is therefore advisable to simultaneously consider the switching instants of the series-connected converters 20, 22 in an attempt to optimize a single cost function, thereby yielding a common OPP. At the same time, the voltage levels, number of pulses, and fundamental components of the individual converters 20, 22 can be selected independently of one another.

[0061] There are four main criteria for evaluating the performance of a particular modulation scheme:

[0062] 1. Total demand distortion (TDD): The ratio of the rms value (rms: root mean square) of all (load / motor) current harmonics to the nominal fundamental (motor) current. TDD should be limited as much as possible to avoid additional losses and temperature rise in the load (e.g., motor).

[0063] 2. Pulse number: 3LANPC and AFC pulse number. The pulse number (number of output voltage transitions per period) of a given TDD should be as low as possible to minimize semiconductor switching losses.

[0064] 3. Voltage step size: Size of the voltage step at the output terminal 18 of the converter device: The voltage step should be as small as possible to (i) minimize overvoltage at the load terminals (due to reflections) and (ii) minimize losses in the resistors of the corresponding EMC (EMC: Electromagnetic Compatibility) filter.

[0065] 4. Static AFC balance: Modulation of whether the fundamental component is generated for AFC. Due to the floating capacitance element 24, the AFC cannot contribute to the fundamental voltage generation.

[0066] Figure 2 and Figure 4 An example of the resulting OPP for a two-stage converter device 36 consisting of a 3LANPC with one AFC in series is shown in FIG. The individual OPPs have different heights and pulse numbers. Adding the individual voltage contributions at the motor results in an optimal waveform that is close to a sinusoidal waveform with low harmonic current. Furthermore, only the waveform of the voltage 42 of the first converter 20 (the 3LANPC voltage in the example) generates a fundamental component, while the fundamental component of the voltage 44 of the second converter 22 (the AFC voltage in the example) is zero, as shown in FIG. Figure 3 This means that the fundamental component of the total output voltage waveform comes only from the first converter 20 (3LANPC in the example), which is necessary to keep the average value of the AFC floating capacitance element voltage constant. For the case of two converters 20, 22 connected in series, the switching angles of the individual converters 20, 22 are stored for each modulation index η, and the modulator switches the individual converters 20, 22 accordingly, as shown in FIG. Figure 4shown. Figure 4 A schematic diagram of a two-level OPP modulator system is shown that represents a multi-level modulation scheme 50 (a two-level modulation scheme in the example shown). The system 50 includes a first modulator block 52 that generates a pulse pattern for the first converter 20 according to the modulation index η and a second modulator block 54 that generates a pulse pattern for the second converter 22 according to the modulation index η. The pulse pattern corresponds to the associated converter voltages 42, 44, as shown in FIG. Figure 3 shown.

[0067] Evaluating the modulation schemes against the four main criteria mentioned above to assess the performance of a particular modulation scheme yields the following findings:

[0068] TDD: The spectrum of the sum of the individual voltage contributions can be optimized for a given number of pulses of the individual converters 20 , 22 using a suitable cost function, such as load TDD (eg motor TDD).

[0069] Number of pulses: The multi-level approach allows independent selection of the number of pulses for each converter 20, 22. This feature provides complete control over semiconductor switching losses.

[0070] Step size: As in the hybrid multi-level approach, minimization of the OPP cost function will not guarantee that the entire converter device 36 switches only between adjacent voltage levels with the smallest possible step size.

[0071] Static balancing: In this approach, individual constraints can be set for the fundamental component of each converter. This ensures that the fundamental component of the output voltage waveform of the floating cell 28 (AFC) is zero in the steady-state and ideal case. This saves control effort in the steady-state and facilitates the application of theoretically calculated optimal switching instants for each converter.

[0072] The main difficulty with modulation schemes with controllable number of individual pulses (i.e., prior art hybrid multilevel and common OPP modulation schemes) is the occurrence of "voltage steps beyond the step size limit where the minimum step size can no longer be assumed" (non-minimum voltage steps). Therefore, it is proposed to modify the switching position pattern in order to generate non-minimum voltage steps generated by these modulation schemes, such as Figure 5 As shown, this results in a temporary voltage characteristic 56 that reduces the step size at the output voltage 46 compared to the step size at the voltage 42 of the first converter 20 .

[0073] The main idea is to decompose the large step 58 into a series of small steps 60 by a suitable switching position pattern of the series connected floating cells 28 (AFC). Note that when using the above modulation scheme, there may be Figure 5 A similar switch position mode is shown on the right.

[0074] However, due to the following reasons, Figure 5 The suggested patterns on the right differ both quantitatively and qualitatively:

[0075] 1. For the modulation schemes described previously, the timing of the pattern (i.e., the time intervals T1, T2, and T3) is predetermined by the modulation principle and cannot be modified. In contrast, the proposed pattern has a flexible timing that can be determined by the system designer. The switching time intervals T1, T2, and T3 can, for example (but not necessarily) be chosen so that the volt-seconds of the original pattern generated by the modulation remain unchanged ( Figure 5 the same shaded area in ).

[0076] 2. For the above modulation scheme, due to the modulation principle, it automatically generates Figure 5 In contrast, whenever it is deemed necessary, i.e., in the modulation scheme generated Figure 5 The proposed pattern is intentionally inserted into the modulation scheme when the pattern shown on the left is used.

[0077] Figure 6 Three implementation options (a)-(c) of a step size reduction scheme for a modulation scheme with a controllable number of individual pulses are shown. Depending on the modulation scheme used, the step size reduction scheme ( Figure 6 The block 62 in FIG. 1 can be implemented online or offline. Figure 6 (a) hybrid multi-level modulation (multi-level modulation scheme 50) or Figure 6 (b) is effective in combination with the common OPP modulation scheme 64 shown. The online step size reduction scheme delays the switching position pattern by T1 to perform the desired modification. If OPP modulation is used, this disadvantage can be overcome. In this case, the step size reduction scheme can be performed offline. Then, the online OPP modulator 66 will generate a switching position pattern that already has the minimum step size, see Figure 6 (c) In other words, the in-line OPP modulator 66 is an OPP modulator including a step size reduction.

[0078] Below we discuss some simulation results (TDD comparison) and a brief performance comparison between the hybrid multilevel approach and the multilevel common OPP. Single-level CB-PWM is not considered in this comparison because its performance in terms of TDD and static balance is worse than that of the hybrid multilevel approach. Figure 1 and Figure 2In the 3LANPC+AFC converter shown, the AFC floating capacitor voltage is 1 / 5 of the 3LANCP DC link voltage. The multi-level common OPP is calculated as described above. For the 3LANPC CB-PWM, a carrier frequency six times the fundamental frequency has been selected. Furthermore, to achieve quarter-wave symmetry and a pulse count of 3, a level-shifted carrier with an inverting configuration is used, as in the multi-level common OPP, with the upper carrier phase being π.

[0079] Figure 7 Figure 1 shows the TDD as a function of the modulation index η when a 3LNPC converter is connected in series with an AFC, with a fundamental output frequency of 50 Hz. A: CB-PWM of both converters (d1=3 and d2=19), and B: common OPP (d1=3 and d2=19). The 3LNPC reference is calculated by adding the appropriate common-mode signal to the sinusoidal reference, so that the 3LNPC output voltage has optimal harmonic distribution. The AFC reference is equal to the difference between the 3LNPC output voltage and the sinusoidal 3LNPC sinusoidal reference. In addition, a common-mode signal equal to the "min-max" of the three-phase reference is added to the reference signal of each phase to better utilize the available AFC voltage. The carrier is selected so that the resulting number of pulses of the AFC is equal to 19, the same as in the case of multi-level common OPP.

[0080] exist Figure 7 In Figure 1, the TDD of the two modulation methods is shown as a function of the modulation index. A purely inductive load with an impedance of 0.2 pu has been considered for the calculation of the TDD. It can be seen that, although the switching frequency is the same in both cases for 3LANPC and AFC, the TDD is 17 times higher than that of the common OPP. In certain modulation index ranges, it approaches a value of 27%, while in the case of the common OPP it always remains below 4%. In addition, as Figure 8 As shown in Figure 1, when using a hybrid multi-level CB-PWM, the AFC generates a significant fundamental component that must be compensated by the voltage balancing controller. This component is due to the AFC's overmodulation, and its voltage is typically lower than its CB-PWM reference voltage. With a multi-level common OPP, the AFC's fundamental component is automatically zero.

[0081] Finally, the demonstration of the performance gain of the proposed step-size reduction scheme is discussed. We assume Figure 1 and Figure 2 The topology is shown in Figure 2, where the AFC floating capacitor voltage is 1 / 5 of half the 3LANCP DC link voltage. We consider a single phase of the converter, EMC filter, cable, and motor, and compare the uncompensated 3LANPC pulses with the power consumption. Figure 5(a) The proposed voltage mode modified 3LANPC pulse is compared. Typical medium voltage IGCT and low voltage IGBT are considered for 3LANPC and AFC respectively. The waveforms obtained are shown in Figure 9 As shown, the figure shows a comparison of 3LANPC switching transitions without and with the proposed step size reduction scheme. The corresponding parameters (output voltage, load / motor voltage, EMC filter current, and EMC filter and AFC switching losses) are shown for step size reduction SSR and without step size reduction NSSR. In addition, the losses are shown for step size reduction plus switching losses. It can be seen that the overvoltage at the motor terminals can be significantly reduced from 1.37kV to 0.27kV (-80%) by the step size reduction scheme. The losses in the EMC filter resistor can be reduced from 3.1J to 1.35J (-56%). Taking into account the additional switching losses caused by the 4 additional AFC pulses, the total losses are reduced by 44%.

[0082] Reference Signs List

[0083] 10: Converter circuit

[0084] 12: Input side

[0085] 14: Input terminal

[0086] 16: Output side

[0087] 18: Output terminal

[0088] 20: First converter

[0089] 22: Second converter

[0090] 24: Capacitor element

[0091] 26: Semiconductor devices

[0092] 28: Floating unit

[0093] 30: Semiconductor devices

[0094] 32: DC intermediate circuit

[0095] 34: Capacitor element

[0096] 36: Converter device

[0097] 38: Load

[0098] 40: Control device

[0099] 42: Voltage (first converter)

[0100] 44: Voltage (Second Converter)

[0101] 46: Output voltage (at load)

[0102] 48: Sine waveform

[0103] 50: Multi-level modulation scheme

[0104] 52: First modulator block

[0105] 54: Second modulator block

[0106] 56: Transient voltage characteristics

[0107] 58: Big Leap

[0108] 60: Small step

[0109] 62: Step size reduction block

[0110] 64: OPP modulator

[0111] 66: OPP modulator, including step size reduction

[0112] SSR: Step size reduction

[0113] NSSR: No step size reduction

[0114] η: modulation index

Claims

1. A method for operating a power electronic converter device (36) for a power conversion system, The power electronic converter device (36) comprises a converter circuit (10), the converter circuit (10) comprising an input side (12) having input terminals (14), an output side (16) having at least one AC output terminal (18), a first converter (20) having a semiconductor device (26) connected to the input terminal (14), and at least one second converter (22) connected between the AC output of the first converter (20) and the AC output terminal, the second converter (22) comprising at least one floating unit (28) having a DC intermediate circuit (32) and a semiconductor device (30); wherein the first converter and the second converter are switched in a switching pattern comprising a first switching instant of the semiconductor device (26) for the first converter (20) and a second switching instant of the semiconductor device (30) for the second converter (22), such that the two converters (20, 22) generate a voltage (42, 44) having a step voltage change, and an output voltage (46) of the power electronic converter device (36) results from a superposition of the voltages (42, 44) of the two converters (20, 22); wherein the first switching instants of the switching pattern are selected such that the voltage (42) of the first converter (20) provides a fundamental voltage component of the output voltage (46); wherein the second switching instant of the switching pattern is selected such that if the step size of the first switching instant of the first converter (20) exceeds a step size limit, a compensating switching instant for the second converter (22) is included in the switching pattern, the compensating switching instant causing the voltage (44) of the second converter (22) to be reduced by the step size at the output voltage (46) compared to the step size at the voltage (42) of the first converter (20); The switching pattern includes adjacent switching instants for the second converter (22), the adjacent switching instants being adjacent to the compensating switching instants, and the directions and switching times of the adjacent switching instants being selected such that the voltage (44) of the second converter (22) maintains the fundamental voltage component of the voltage (42) of the first converter (20) unchanged and such that the second converter (22) does not generate the fundamental component of the output voltage (46).

2. The method according to claim 1, wherein the switching pattern is stored in a table of pre-calculated optimized pulse patterns; and / or The switching pattern has been optimized offline so that the first switching instant generates the fundamental voltage component and the second switching instant keeps the fundamental voltage component unchanged.

3. The method according to claim 1 or 2, wherein the switching pattern is modified on-line by including the compensating switching instant and the adjacent switching instant into a pre-calculated optimized pulse pattern.

4. The method according to claim 1 or 2, The switching times of the adjacent switching instants included therein are optimized online so that the voltage (44) of the second converter (22) maintains the fundamental voltage component of the voltage (42) of the first converter (20) unchanged.

5. The method according to claim 1 or 2, wherein the compensating switching transiently causes a double-step voltage change between a positive voltage and a negative voltage of the floating unit (28); The adjacent switching transients cause a single step voltage change between the positive voltage and zero voltage or between the negative voltage and zero voltage.

6. The method according to claim 1 or 2, wherein in order to compensate for the step size of the first switching instant of the first converter (20) exceeding the step size limit, the second switching instant comprises a single step voltage change in a first direction before the switching time of the first switching instant, and the compensating switching instant has a double step voltage change in an opposite direction at the switching time of the first switching instant.

7. The method according to claim 6, wherein the second switching instant comprises a single step voltage change in the first direction exceeding the step size limit after the switching time of the first switching instant.

8. The method according to claim 6, wherein the second switching instant comprises two single step voltage changes exceeding the step size limit at different switching times in the first direction before the switching time of the first switching instant; and / or The second switching instant comprises two single step voltage changes exceeding the step size limit in the first direction at different switching times after the switching time of the first switching instant.

9. The method according to claim 1 or 2, The compensating switching instants and the adjacent switching instants are included in a pre-calculated optimized pulse pattern by online post-processing with the aid of a multi-level modulation scheme (50).

10. The method according to claim 1 or 2, The compensating switching instant and the adjacent switching instant are included in a pre-calculated optimized pulse pattern by online post-processing with the aid of an optimized pulse pattern modulator (64).

11. The method according to claim 1 or 2, Wherein the pre-calculated switching pattern is optimized based on at least one cost function and a constraint.

12. The method according to claim 1 or 2, Wherein the switching pattern consists of an optimized pulse pattern for the first converter and the second converter, the optimized pulse pattern being based on individual cost functions and constraints.

13. A computer program product comprising a computer-executable program code portion having program code instructions configured to perform the method according to any one of claims 1 to 8 when loaded into a computer-based control device (40).

14. A computer-readable medium having stored thereon the computer program product according to claim 13.

15. A power electronic converter device (36) for a power conversion system, the power electronic converter device (36) comprising: - a converter circuit (10) comprising an input side (12) with input terminals (14), an output side (16) with at least one AC output terminal (18), a first converter (20) connected to the input terminal (14) and having a semiconductor device (26), and at least one second converter (22) connected between the AC output of the first converter (20) and the AC output terminal, the second converter (22) comprising at least one floating unit (28) with a DC intermediate circuit (32) and a semiconductor device (30); and A control device (40) for driving the semiconductor devices (26, 30) of at least one of the converters (20, 22), wherein the control device is configured to perform the method according to any one of claims 1 to 12.

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