Method and apparatus for SS / PBCH block pattern in higher frequency range

Abstract

The present disclosure relates to a pre-fifth generation (5G) or 5G communication system, which is provided for supporting a higher data rate beyond the fourth generation (4G) communication system, such as long term evolution (LTE). A method of operating a user equipment (UE) includes: receiving a synchronization signal and physical broadcast channel (SS / PBCH) block; determining a parameter set of the SS / PBCH block, wherein the parameter set includes a subcarrier spacing (SCS) and a cyclic prefix (CP) length; and, based on the parameter set, determining an SS / PBCH block mode, wherein the SS / PBCH block mode includes candidate SS / PBCH blocks mapped to time slots within a half frame and a minimum gap between adjacent candidate SS / PBCH blocks, wherein: based on determining that the SCS included in the parameter set of the SS / PBCH block is 120kHz or 240kHz, the minimum gap is 0 symbols; or, based on determining that the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz, the minimum gap is 1 symbol.

Description

Technical Field

[0001] The present disclosure generally relates to wireless communication systems, and more particularly to a synchronization signal / physical broadcast channel (SS / PBCH) block pattern in a higher frequency range in a wireless communication system. Background Art

[0002] Fifth Generation (5G) or New Radio (NR) mobile communications are gathering more and more momentum recently, with all the global technical activities of various candidate technologies from industry and academia. Candidate enablers for 5G / NR mobile communications include massive antenna technology from traditional cellular bands to high frequencies to provide beamforming gain and support increased capacity, new waveforms (e.g., new radio access technologies (RATs)) to flexibly adapt to various services / applications with different requirements, new multiple access schemes to support massive connectivity, and so on.

[0003] In order to meet the increased demand for wireless data services since the deployment of 4G communication systems, efforts have been made to develop improved 5G or pre-5G communication systems. Therefore, 5G or pre-5G communication systems are also referred to as 'super 4G networks' or 'post-LTE systems'. 5G communication systems are considered to be implemented in higher frequency (millimeter wave, mmWave) bands (e.g., 60GHz bands) to achieve higher data rates. In order to reduce the propagation loss of radio waves and increase the transmission distance, beamforming, massive multiple input multiple output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and massive antenna technology are discussed in 5G communication systems. In addition, in 5G communication systems, development of system network improvements is underway based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, device-to-device (D2D) communications, wireless backhaul, mobile networks, collaborative communications, coordinated multi-point (CoMP), receiving-end interference elimination, etc. In 5G systems, hybrid FSK and QAM modulation (FQAM) and sliding window superposition coding (SWSC) as advanced coded modulation (ACM), and filter bank multi-carrier (FBMC), non-orthogonal multiple access (NOMA) and sparse code multiple access (SCMA) as advanced access technologies have been developed.

[0004] The Internet, as a human-centered connected network where humans generate and consume information, is now evolving toward the Internet of Things (IoT), in which distributed entities (such as things) exchange and process information without human intervention. The Internet of Everything (IoE), which combines IoT technology with big data processing technology through connection with cloud servers, has emerged. Since technical elements such as "sensing technology", "wired / wireless communication and network infrastructure", "service interface technology" and "security technology" are required for IoT implementation, sensor networks, machine-to-machine (M2M) communication, machine-type communication (MTC), etc. have been recently studied. This IoT environment can provide smart Internet technology services that create new value for human life by collecting and analyzing data generated between connected things. Through the integration and combination between existing information technology (IT) and various industrial applications, IoT can be applied to various fields, including smart homes, smart buildings, smart cities, smart cars or connected cars, smart grids, healthcare, smart appliances, and advanced medical services.

[0005] In view of this, various attempts have been made to apply 5G communication systems to IoT networks. For example, technologies such as sensor networks, machine type communications (MTC), and machine-to-machine (M2M) communications can be implemented through beamforming, MIMO, and array antennas. Cloud radio access networks (RANs) as an application of the above-mentioned big data processing technology can also be regarded as an example of the fusion of 5G technology and IoT technology. Summary of the invention

[0006] Technical issues

[0007] The 5G communication system according to the present disclosure can be implemented in a higher frequency range. Therefore, an SS / PBCH block mode that can be used in a higher frequency range is required.

[0008] Technical Solution

[0009] Aspects of the present disclosure are directed to at least solving the above problems and / or disadvantages and providing at least the advantages described below. Therefore, the present disclosure provides a synchronization signal / physical broadcast channel (SS / PBCH) block pattern in a higher frequency range in a wireless communication system.

[0010] In one embodiment, a user equipment (UE) in a wireless communication system is provided. The UE includes a transceiver configured to receive an SS / PBCH block. The UE also includes a processor operably connected to the transceiver, the processor of the UE being configured to: determine a parameter set of the SS / PBCH block, wherein the parameter set includes a subcarrier spacing (SCS) and a cyclic prefix (CP) length; determine an SS / PBCH block mode based on the parameter set, wherein the SS / PBCH block mode includes candidate SS / PBCH blocks mapped to time slots within a half frame and a minimum gap between adjacent candidate SS / PBCH blocks Where: If the SCS included in the parameter set of the SS / PBCH block is 120kHz or 240kHz, then symbols; or, if the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz, then symbol.

[0011] In another embodiment, a base station (BS) in a wireless communication system is provided. The BS includes a processor configured to: determine a parameter set of an SS / PBCH block, wherein the parameter set includes an SCS and a CP length; determine an SS / PBCH block mode based on the parameter set, wherein the SS / PBCH block mode includes candidate SS / PBCH blocks mapped to time slots within a half frame and a minimum gap between adjacent candidate SS / PBCH blocks Where: If the SCS included in the parameter set of the SS / PBCH block is 120kHz or 240kHz, then symbols; or, if the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz, then symbols; and, based on the parameter set and the SS / PBCH block pattern, generating an SS / PBCH block. The BS also includes a transceiver operatively connected to the processor, the transceiver of the BS being configured to send the SS / PBCH block.

[0012] In yet another embodiment, a method of a UE in a wireless communication system, the method comprising: receiving an SS / PBCH block; determining a parameter set of the SS / PBCH block, wherein the parameter set comprises an SCS and a CP length; and determining an SS / PBCH block mode based on the parameter set, the SS / PBCH block mode comprising candidate SS / PBCH blocks mapped to time slots within a half-frame and a minimum gap between adjacent candidate SS / PBCH blocks. Wherein: based on determining whether the SCS included in the parameter set of the SS / PBCH block is 120kHz or 240kHz, symbols; or, based on determining whether the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz, symbol.

[0013] Other technical features will be readily apparent to those skilled in the art from the drawings, description and claims.

[0014] Advantageous Effects of the Invention

[0015] According to various embodiments of the present disclosure, SS / PBCH block patterns in a higher frequency range are provided. More specifically, SS / PBCH block patterns for existing parameter sets and SS / PBCH block patterns for new parameter sets are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts:

[0017] Figure 1 illustrates an example wireless network according to an embodiment of the present disclosure;

[0018] Figure 2 An example gNB according to an embodiment of the present disclosure is illustrated;

[0019] Figure 3 An example UE according to an embodiment of the present disclosure is illustrated;

[0020] Figure 4 illustrates example wireless transmit and receive paths according to the present disclosure;

[0021] Figure 5 illustrates example wireless transmit and receive paths according to the present disclosure;

[0022] Figure 6 illustrates an example SS / PBCH block composition according to an embodiment of the present disclosure;

[0023] Figure 7 illustrates an example SS / PBCH block time domain pattern in a (multiple) time slots according to an embodiment of the present disclosure;

[0024] Figure 8 illustrates an example time slot in a half-frame containing candidate SS / PBCH blocks according to an embodiment of the present disclosure;

[0025] Fig. 9 FIG. 1 illustrates an example disabling of a candidate SS / PBCH block according to an embodiment of the present disclosure;

[0026] Fig.10 illustrates an example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0027] Fig.11Another example SS / PBCH block pattern according to an embodiment of the present disclosure is illustrated;

[0028] Fig.12 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0029] FIG13A illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0030] FIG13B illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0031] Fig.14 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0032] FIG15A illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0033] FIG15B illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0034] FIG16A illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0035] FIG16B illustrates yet another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0036] Fig.17 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0037] Fig.18 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0038] Fig.19 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0039] Fig. 20 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0040] Fig.21 FIG. 2 illustrates another example SS / PBCH block pattern according to an embodiment of the present disclosure;

[0041] Fig. 22 illustrates example predefined time units within a predefined time period according to an embodiment of the present disclosure; and

[0042] Fig.23 A flowchart of a method for SS / PBCH block mode according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0043] Before carrying out the following detailed description, it may be advantageous to set forth the definitions of certain words and phrases used in this patent document.The term "coupling" and its derivatives refer to any direct or indirect communication between two or more elements, whether or not these elements are in physical contact with each other.The terms "send", "receive" and "communication" and their derivatives include both direct and indirect communication.The terms "include" and "comprise" and their derivatives mean to include without limitation.The term "or" is inclusive, meaning and / or.The phrase "associated with..." and its derivatives mean to include, be included in, interconnect with, include, be included in, be connected to, or be connected with, be coupled to, or be coupled with, can communicate with, collaborate with, interweave, juxtapose, be close to, be bound to, or be bound with, have, have...attributes, have a relationship with, or have a relationship with, etc.The term "controller" means any device, system or part thereof that controls at least one operation.Such a controller can be implemented with hardware or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. When used with a list of items, the phrase "at least one of" means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.

[0044] In addition, the various functions described below can be implemented or supported by one or more computer programs, each of which is composed of a computer-readable program code and is embodied in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, processes, functions, objects, classes, instances, related data, or a portion thereof that are suitable for implementation with a suitable computer-readable program code. The phrase "computer-readable program code" includes any type of computer code, including source code, object code, and executable code. The phrase "computer-readable medium" includes any type of medium that can be accessed by a computer, such as a read-only memory (ROM), a random access memory (RAM), a hard drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. "Non-transitory" computer-readable media does not include wired, wireless, optical, or other communication links that transmit temporary electrical signals or other signals. Non-transitory computer-readable media include media that can permanently store data and media that can store and then rewrite data, such as rewritable optical discs or erasable memory devices.

[0045] Definitions for other words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

[0046] Discussed below Figures 1 to 23 The various embodiments used to describe the principles of the present disclosure in this patent document are illustrative only and should not be construed in any way to limit the scope of the present disclosure. Those skilled in the art will appreciate that the principles of the present disclosure can be implemented in any suitably arranged system or device.

[0047] The following documents are incorporated by reference into the present disclosure as if fully set forth herein: 3GPP TS 38.211 v15.7.0, “NR; Physical channels and modulation”; 3GPP TS 38.212 v15.7.0, “NR; Multiplexing and Channel coding”; 3GPP TS 38.213 v15.7.0, “NR; Physical Layer Procedures for Control”; 3GPP TS 38.214 v15.7.0, “NR; Physical Layer Procedures for Data”; and 3GPP TS 38.321 v15.7.0, “NR; Medium Access Control (MAC) protocol specification”.

[0048] The following Figures 1 to 3 Various embodiments are described that are implemented in a wireless communication system using orthogonal frequency division multiplexing (OFDM) or orthogonal frequency division multiple access (OFDMA) communication techniques. Figures 1 to 3 The description is not meant to imply physical or architectural limitations to the manner in which different embodiments may be implemented. Different embodiments of the present disclosure may be implemented in any suitably arranged communications system.

[0049] Figure 1 An example wireless network according to an embodiment of the present disclosure is illustrated. Figure 1 The embodiment of the wireless network shown in FIG. 1 is for illustration only. Other embodiments of the wireless network 100 can be used without departing from the scope of the present disclosure.

[0050] like Figure 1As shown, the wireless network includes gNB 101 (e.g., base station, BS), gNB 102, and gNB 103. gNB 101 communicates with gNB 102 and gNB 103. gNB 101 also communicates with at least one network 130 (such as the Internet, a proprietary Internet Protocol (IP) network, or other data network).

[0051] gNB 102 provides wireless broadband access to network 130 for a first plurality of user equipment (UE) within coverage area 120 of gNB 102. The first plurality of UEs include: UE 111, which may be located in a small enterprise; UE 112, which may be located in an enterprise (E); UE 113, which may be located in a WiFi hotspot (HS); UE 114, which may be located in a first residence (R); UE 115, which may be located in a second residence (R); and UE 116, which may be a mobile device (M) such as a cellular phone, a wireless laptop, a wireless PDA, etc. gNB 103 provides wireless broadband access to network 130 for a second plurality of UEs within coverage area 125 of gNB 103. The second plurality of UEs includes UE 115 and UE 116. In some embodiments, one or more of gNBs 101-103 may communicate with each other and with UEs 111-116 using 5G / NR, LTE, LTE-A, WiMAX, WiFi, or other wireless communication technologies.

[0052] Depending on the network type, the term "base station" or "BS" may refer to any component (or set of components) configured to provide wireless access to a network, such as a transmission point (TP), a transmission reception point (TRP), an enhanced base station (eNodeB or eNB), a 5G / NR base station (gNB), a macro cell, a femto cell, a WiFi access point (AP), or other wireless enabling devices. The base station may provide wireless access according to one or more wireless communication protocols (e.g., 5G / NR 3GPP NR, Long Term Evolution (LTE), Advanced LTE (LTE-A), High Speed ​​Packet Access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc.). For convenience, the terms "BS" and "TRP" are used interchangeably in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Moreover, depending on the network type, the term "user equipment" or "UE" may refer to any component, such as a "mobile station", "user station", "remote terminal", "wireless terminal", "reception point", or "user device". For convenience, the terms "user equipment" and "UE" are used in this patent document to refer to a remote wireless device that wirelessly accesses a BS, whether the UE is a mobile device (such as a mobile phone or smartphone) or a commonly considered fixed device (such as a desktop computer or vending machine).

[0053] The dashed lines illustrate the approximate extents of coverage areas 120 and 125, which are shown as approximately circular for purposes of illustration and explanation only. It should be clearly understood that coverage areas associated with gNBs, such as coverage areas 120 and 125, may have other shapes, including irregular shapes, depending on the configuration of the gNB and variations in the radio environment associated with natural and man-made obstacles.

[0054] As described in more detail below, one or more of the UEs 111-116 include circuitry, programming, or a combination thereof for beam management and coverage enhancement for semi-persistent and configuration grant transmissions. In certain embodiments, one or more of the gNBs 101-103 include circuitry, programming, or a combination thereof for beam management and coverage enhancement for semi-persistent and configuration grant transmissions.

[0055] although Figure 1 The diagram shows an example of a wireless network, but Figure 1 Various changes may be made. For example, the wireless network can include any number of gNBs and any number of UEs in any suitable arrangement. Moreover, gNB 101 can communicate directly with any number of UEs and provide those UEs with wireless broadband access to network 130. Similarly, each gNB 102-103 can communicate directly with network 130 and provide UEs with direct wireless broadband access to network 130. In addition, gNBs 101, 102, and / or 103 can provide access to other or additional external networks, such as an external telephone network or other type of data network.

[0056] Figure 2 An example gNB 102 according to an embodiment of the present disclosure is illustrated. Figure 2 The embodiment of the gNB 102 shown in FIG. is for illustration only, and Figure 1 gNBs 101 and 103 can have the same or similar configurations. However, gNBs have a variety of configurations, and Figure 2 The scope of the present disclosure is not limited to any particular implementation of the gNB.

[0057] like Figure 2 As shown, gNB 102 includes multiple antennas 205a-205n, multiple RF transceivers 210a-210n, transmit (TX) processing circuitry 215, and receive (RX) processing circuitry 220. gNB 102 also includes a controller / processor 225, a memory 230, and a backhaul or network interface 235.

[0058] The RF transceivers 210a-210n receive incoming RF signals from the antennas 205a-205n, such as signals transmitted by UEs in the network 100. The RF transceivers 210a-210n downconvert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are sent to the RX processing circuit 220, which generates processed baseband signals by filtering, decoding and / or digitizing the baseband or IF signals. The RX processing circuit 220 sends the processed baseband signals to the controller / processor 225 for further processing.

[0059] The TX processing circuit 215 receives analog or digital data (such as voice data, network data, email, or interactive video game data) from the controller / processor 225. The TX processing circuit 215 encodes, multiplexes, and / or digitizes the outgoing baseband data to generate a processed baseband or IF signal. The RF transceivers 210a-210n receive the outgoing processed baseband or IF signals from the TX processing circuit 215 and up-convert the baseband or IF signals to RF signals that are transmitted via the antennas 205a-205n.

[0060] The controller / processor 225 may include one or more processors or other processing devices that control the overall operation of the gNB 102. For example, the controller / processor 225 may be capable of controlling the reception of forward channel signals and the transmission of reverse channel signals by the RF transceivers 210a-210n, the RX processing circuitry 220, and the TX processing circuitry 215 in accordance with well-known principles. The controller / processor 225 may also be capable of supporting additional functionality, such as more advanced wireless communication functionality. For example, the controller / processor 225 may be capable of supporting beamforming or directional routing operations, in which outgoing / incoming signals from / to multiple antennas 205a-205n are weighted differently to effectively direct the outgoing signals in a desired direction. Any of a variety of other functions may be supported in the gNB 102 by the controller / processor 225.

[0061] Controller / processor 225 is also capable of executing programs and other processes, such as an OS, that reside in memory 230. Controller / processor 225 may move data into or out of memory 230 as required by the executing process.

[0062] The controller / processor 225 is also coupled to a backhaul or network interface 235. The backhaul or network interface 235 allows the gNB 102 to communicate with other devices or systems via a backhaul connection or via a network. The interface 235 is capable of supporting communication via any suitable (multiple) wired or wireless connections. For example, when the gNB 102 is implemented as part of a cellular communication system (such as a cellular communication system supporting 5G / NR, LTE, or LTE-A), the interface 235 is capable of allowing the gNB 102 to communicate with other gNBs via a wired or wireless backhaul connection. When the gNB 102 is implemented as an access point, the interface 235 is capable of allowing the gNB 102 to communicate via a wired or wireless local area network or via a wired or wireless connection to a larger network (such as the Internet). The interface 235 includes any suitable structure that supports communication via a wired or wireless connection, such as an Ethernet or RF transceiver.

[0063] Memory 230 is coupled to controller / processor 225. A portion of memory 230 can include RAM, while another portion of memory 230 can include flash memory or other ROM.

[0064] although Figure 2 An example of a gNB 102 is shown, but the Figure 2 For example, gNB 102 can include any number of Figure 2 As a specific example, the access point can include multiple interfaces 235, and the controller / processor 225 can support routing functions to route data between different network addresses. As another specific example, although shown as including a single instance of TX processing circuitry 215 and a single instance of RX processing circuitry 220, the gNB 102 can include multiple instances of each (such as one for each RF transceiver). Furthermore, Figure 2 The various components in can be combined, further subdivided or omitted, and additional components can be added according to specific needs.

[0065] Figure 3 An example UE 116 is illustrated according to an embodiment of the disclosure. Figure 3 The embodiment of UE 116 shown in FIG. 1 is for illustration only, and Figure 1 UEs 111-115 can have the same or similar configurations. However, UEs have a variety of configurations, and Figure 3 The scope of the present disclosure is not limited to any particular implementation of the UE.

[0066] like Figure 3As shown, UE 116 includes antenna 305, radio frequency (RF) transceiver 310, TX processing circuit 315, microphone 320 and RX processing circuit 325. UE 116 also includes speaker 330, processor 340, input / output (I / O) interface (IF) 345, touch screen 350, display 355 and memory 360. Memory 360 includes operating system (OS) 361 and one or more applications 362.

[0067] RF transceiver 310 receives incoming RF signals sent by a gNB of network 100 from antenna 305. RF transceiver 310 downconverts the incoming RF signals to generate an intermediate frequency (IF) or baseband signal. The IF or baseband signal is sent to RX processing circuitry 325, which generates a processed baseband signal by filtering, decoding, and / or digitizing the baseband or IF signal. RX processing circuitry 325 sends the processed baseband signal to speaker 330 (such as for voice data) or to processor 340 (such as for web browsing data) for further processing.

[0068] The TX processing circuit 315 receives analog or digital voice data from the microphone 320, or receives other outgoing baseband data (such as network data, email, or interactive video game data) from the processor 340. The TX processing circuit 315 encodes, multiplexes, and / or digitizes the outgoing baseband data to generate a processed baseband or IF signal. The RF transceiver 310 receives the outgoing processed baseband or IF signal from the TX processing circuit 315 and up-converts the baseband or IF signal to an RF signal that is transmitted via the antenna 305.

[0069] The processor 340 may include one or more processors or other processing devices and executes the OS 361 stored in the memory 360 to control the overall operation of the UE 116. For example, the processor 340 can control the reception of forward channel signals and the transmission of reverse channel signals through the RF transceiver 310, the RX processing circuit 325, and the TX processing circuit 315 according to well-known principles. In some embodiments, the processor 340 includes at least one microprocessor or microcontroller.

[0070] The processor 340 is also capable of executing other processes and programs resident in the memory 360, such as processes for beam management. The processor 340 can move data into or out of the memory 360 as required by the processes being executed. In some embodiments, the processor 340 is configured to execute applications 362 based on the OS 361 or in response to signals received from the gNB or operator. The processor 340 is also coupled to the I / O interface 345, which provides the UE 116 with the ability to connect to other devices such as laptops and handheld computers. The I / O interface 345 is the communication path between these accessories and the processor 340.

[0071] Processor 340 is also coupled to touch screen 350 and display 355. An operator of UE 116 may enter data into UE 116 using touch screen 350. Display 355 may be a liquid crystal display, light emitting diode display, or other display capable of presenting text and / or at least limited graphics (such as from a website).

[0072] Memory 360 is coupled to processor 340. A portion of memory 360 can include random access memory (RAM), while another portion of memory 360 can include flash memory or other read-only memory (ROM).

[0073] although Figure 3 An example of UE 116 is shown, but the Figure 3 Make various changes. For example, Figure 3 The various components in can be combined, further subdivided, or omitted, and additional components can be added according to specific needs. As a specific example, processor 340 can be divided into multiple processors, such as one or more central processing units (CPUs) and one or more graphics processing units (GPUs). Moreover, although Figure 3 The UE 116 is illustrated as being configured as a mobile phone or smart phone, but the UE can be configured to operate as other types of mobile or stationary devices.

[0074] In order to meet the increased demand for wireless data services since the deployment of 4G communication systems and to realize various vertical applications, efforts have been made to develop and deploy improved 5G / NR or pre-5G / NR communication systems. Therefore, 5G / NR or pre-5G / NR communication systems are also referred to as "super 4G networks" or "post-LTE systems". 5G / NR communication systems are considered to be implemented in higher frequency (millimeter wave, mmWave) bands (e.g., 28GHz or 60GHz bands) to achieve higher data rates, or in lower frequency bands (e.g., 6GHz) to achieve robust coverage and mobility support. Various aspects of the present disclosure may also be applied to the deployment of 5G communication systems, 6G or even later versions that can use terahertz (THz) bands. In order to reduce the propagation loss of radio waves and increase the transmission distance, beamforming, massive multiple-input multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and massive antenna technology are discussed in 5G / NR communication systems.

[0075] In addition, in the 5G / NR communication system, development of system network improvements is underway based on advanced small cells, cloud radio access networks (RAN), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, mobile networks, collaborative communications, coordinated multi-point (CoMP), receiving-end interference cancellation, etc.

[0076] A communication system includes a downlink (DL) and an uplink (UL), where downlink refers to transmission from a base station or one or more transmission points to a UE, and uplink refers to transmission from a UE to a base station or one or more reception points.

[0077] The time unit for DL ​​signaling or UL signaling on a cell is called a time slot and may include one or more symbols. A symbol may also be used as an additional time unit. A frequency (or bandwidth (BW)) unit is called a resource block (RB). An RB includes multiple subcarriers (SCs). For example, a time slot may have a duration of 0.5 milliseconds or 1 millisecond, include 14 symbols, and an RB may include 12 SCs with an interval of 15 KHz or 30 KHz between SCs, and so on.

[0078] DL signals include data signals that convey information content, control signals that convey DL control information (DCI), and reference signals (RS) also known as pilot signals. The gNB sends data information or DCI through the corresponding physical DL shared channel (PDSCH) or physical DL control channel (PDCCH). PDSCH or PDCCH can be sent on a variable number of time slot symbols (including one time slot symbol). For simplicity, the DCI format that schedules PDSCH reception of the UE is called the DL DCI format, and the DCI format that schedules the physical uplink shared channel (PUSCH) transmission from the UE is called the UL DCI format.

[0079] The gNB transmits one or more of multiple types of RS including Channel State Information RS (CSI-RS) and Demodulation RS (DMRS). CSI-RS is mainly used for UE to perform measurements and provide Channel State Information (CSI) to the gNB. For channel measurement, non-zero power CSI-RS (NZP CSI-RS) resources are used. For interference measurement reporting (IMR), CSI interference measurement (CSI-IM) resources associated with zero power CSI-RS (ZP CSI-RS) configuration are used. The CSI process includes NZP CSI-RS and CSI-IM resources.

[0080] The UE can determine the CSI-RS transmission parameters through DL control signaling or high-layer signaling (such as radio resource control (RRC) signaling) from the gNB. The transmission instance of CSI-RS can be indicated by DL control signaling or configured by high-layer signaling. DMRS is only transmitted in the BW of the corresponding PDCCH or PDSCH, and the UE can use DMRS to demodulate data or control information.

[0081] Figure 4 and Figure 5 Example wireless transmit and receive paths according to the present disclosure are illustrated. In the following description, transmit path 400 may be described as being implemented in a gNB (such as gNB 102) and receive path 500 may be described as being implemented in a UE (such as UE 116). However, it is understood that receive path 500 may be implemented in a gNB and transmit path 400 may be implemented in a UE. In some embodiments, receive path 500 is configured to support codebook design and structure for a system having a 2D antenna array as described in embodiments of the present disclosure.

[0082] Figure 4The transmit path 400 shown in the figure includes a channel coding and modulation block 405, a serial to parallel (S to P) block 410, an inverse fast Fourier transform (IFFT) block of size N 415, a parallel to serial (P to S) block 420, an add cyclic prefix block 425, and an up converter (UC) 430. Figure 5 The receive path 500 shown in FIG. 5 includes a down converter (DC) 555, a remove cyclic prefix block 560, a serial to parallel (S to P) block 565, a size N fast Fourier transform (FFT) block 570, a parallel to serial (P to S) block 575, and a channel decoding and demodulation block 580.

[0083] As shown in diagram 400, the channel coding and modulation block 405 receives a set of information bits, applies coding (such as low-density parity-check (LDPC) coding), and modulates the input bits (such as using quadrature phase-shift keying (QPSK) or quadrature amplitude modulation (QAM)) to generate a sequence of frequency-domain modulation symbols.

[0084] Serial to parallel block 410 converts (such as demultiplexes) the serial modulation symbols into parallel data to generate N parallel symbol streams, where N is the IFFT / FFT size used in gNB 102 and UE 116. Size N IFFT block 415 performs IFFT operations on the N parallel symbol streams to generate a time domain output signal. Parallel to serial block 420 converts (such as multiplexes) the parallel time domain output symbols from size N IFFT block 415 to generate a serial time domain signal. Add cyclic prefix block 425 inserts a cyclic prefix into the time domain signal. Up converter 430 modulates (such as upconverts) the output of add cyclic prefix block 425 to RF frequency for transmission via a wireless channel. The signal may also be filtered at baseband before being converted to RF frequency.

[0085] The RF signal transmitted from gNB 102 reaches UE 116 after passing through the wireless channel, and an operation opposite to that at gNB 102 is performed at UE 116.

[0086] like Figure 5 As shown, the down converter 555 down-converts the received signal to the baseband frequency, and the cyclic prefix removal block 560 removes the cyclic prefix to generate a serial time domain baseband signal. The serial to parallel block 565 converts the time domain baseband signal to a parallel time domain signal. The FFT block 570 of size N performs an FFT algorithm to generate N parallel frequency domain signals. The parallel to serial block 575 converts the parallel frequency domain signals into a sequence of modulated data signals. The channel decoding and demodulation block 580 demodulates and decodes the modulation symbols to recover the original input data stream.

[0087] Each of gNBs 101-103 may implement a method similar to that for transmitting in the downlink to UEs 111-116. Figure 4 The transmission path 400 shown in FIG. 4 and may be implemented similarly to the reception from UEs 111-116 in the uplink. Figure 5 Receive path 500 is shown. Similarly, each of UEs 111-116 can implement transmit path 400 for transmitting to gNBs 101-103 in the uplink, and can implement receive path 500 for receiving from gNBs 101-103 in the downlink.

[0088] Figure 4 and Figure 5 Each of the components in may be implemented using hardware only, or a combination of hardware and software / firmware. As a specific example, Figure 4 and Figure 5 At least some of the components in can be implemented with software, while other components can be implemented by configurable hardware or a mixture of software and configurable hardware. For example, FFT block 570 and IFFT block 515 can be implemented as a configurable software algorithm, wherein the value of size N can be modified according to the implementation.

[0089] In addition, although described as using FFT and IFFT, this is illustrative only and should not be interpreted as limiting the scope of the present disclosure. Other types of transforms can be used, such as discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) functions. It will be appreciated that for DFT and IDFT functions, the value of variable N can be any integer (such as 1, 2, 3, 4, etc.), while for FFT and IFFT functions, the value of variable N can be any integer (such as 1, 2, 4, 8, 16, etc.) that is a power of 2.

[0090] although Figure 4 and Figure 5 The diagram shows an example of a wireless transmit and receive path, but Figure 4 and Figure 5 Make various changes. For example, Figure 4 and Figure 5 The various components in may be combined, further subdivided, or omitted, and additional components may be added according to specific needs. Figure 4 and Figure 5 It is intended to illustrate examples of the types of transmit and receive paths that may be used in a wireless network.Any other suitable architecture may be used to support wireless communications in a wireless network.

[0091] The present disclosure focuses on SS / PBCH block patterns in the time domain of a higher frequency range with a new set of parameters, including potential new subcarrier spacing and / or extended CP length. The content of the present disclosure includes the following embodiments and examples. In one embodiment, the SS / PBCH block pattern is determined in the time domain using examples: scaling the Rel-15 SS / PBCH block pattern; scaling and disabling the Rel-15 SS / PBCH block pattern; a new SS / PBCH block pattern using a reference SCS; a new common SS / PBCH block pattern for all supported SCSs; a new SS / PBCH block pattern for an extended CP and using a reference SCS; and, a new common SS / PBCH block pattern for an extended CP and all supported SCSs. In one embodiment, the SS / PBCH block pattern is determined for operations using shared spectrum channel access and operations not using shared spectrum channel access. In one embodiment, low latency considerations are determined for the SS / PBCH block pattern.

[0092] In New Radio (NR) Rel-15, multiple parameter sets are supported, one for each SS / PBCH block and other transmissions. Table 1 gives a summary of the supported parameter sets.

[0093] Table 1. Supported parameter sets for NR Rel-15

[0094]

Table 1

[0095]

[0096] Figure 6 An example SS / PBCH block composition 600 is illustrated according to an embodiment of the disclosure. Figure 6 The embodiment of SS / PBCH block composition 600 shown in FIG. 6 is illustrative only. In NR Rel-15, each SS / PBCH block consists of four consecutive OFDM symbols, where the center 12 RBs of the first symbol are mapped for the primary synchronization signal (PSS), the second and fourth symbols are mapped for the PBCH, and the third symbol is mapped for both the secondary synchronization signal (SSS) and the PBCH. Figure 6 An illustration of the SS / PBCH block composition is shown in Figure 1. The same SS / PBCH composition is applied to all supported carrier frequency ranges in NR, which span from 0.41 GHz to 7.125 GHz as frequency range 1 (FR1) and from 24.25 GHz to 52.6 GHz as frequency range 2 (FR2). In each RB mapped for PBCH, 3 of the 12 resource elements (REs) are mapped for the demodulation reference signal (DM-RS) of the PBCH, where the 3 REs are evenly distributed in the RB and the starting position of the first RE is based on the cell identity (ID).

[0097] For a given frequency band, NR Rel-15 supports one or two SCSs for SS / PBCH blocks, where the same SCS is applied to PSS, SSS, and PBCH (including its DM-RS). For FR1, 15kHz and / or 30kHz can be applied to SS / PBCH blocks; and for FR2, 120kHz and / or 240kHz can be applied to SS / PBCH blocks.

[0098] Figure 7 An example SS / PBCH block time domain pattern 700 in a time slot according to an embodiment of the disclosure is illustrated. Figure 7 The embodiment of the SS / PBCH block time domain pattern 700 in a time slot shown in FIG. 1 is for illustration only. NR Rel-15 also supports multiple candidate SS / PBCH blocks within a time unit of a half frame, where the time unit repeats in the time domain with a configurable period. Figure 7 The time domain pattern of the SS / PBCH block to at least one time slot is illustrated in FIG. For FR1 (701), the SS / PBCH block pattern is designed based on 15 kHz as the reference SCS; and for FR2 (702), the SS / PBCH block pattern is designed based on 60 kHz as the reference SCS.

[0099] The maximum number of candidate SS / PBCH blocks (expressed as ) is determined based on the carrier frequency range, and for FR1 and FR2 licensed spectrum, the value can be one of 4, 8, or 64 for a given carrier frequency range. Figure 8 A diagram of the time domain pattern of time slots containing candidate SS / PBCH blocks within a half-frame is shown in FIG.

[0100] Figure 8 Illustrated are example time slots in a half-frame 800 that include candidate SS / PBCH blocks according to an embodiment of the present disclosure. Figure 8 The embodiment of the time slots containing candidate SS / PBCH blocks in the half-frame 800 shown in FIG. 8 is illustrative only. For the new carrier frequency range between 52.6 GHz and 71 GHz, it is possible to support at least a new parameter set with a larger subcarrier spacing to accommodate larger phase noise and larger carrier bandwidth. When a new parameter set (e.g., including a new subcarrier spacing) is supported in NR, the SS / PBCH block pattern in the time domain needs to be enhanced to support such a new parameter set. The present disclosure details the details of the SS / PBCH block pattern for a higher frequency range, wherein the higher frequency range includes at least a carrier frequency range between 52.6 GHz and 71 GHz, and can be applied to licensed bands (e.g., not using shared spectrum channel access operation) and unlicensed bands (e.g., using shared spectrum channel access operation) in the frequency range.

[0101] Although the following exemplary description and embodiments assume OFDM or OFDMA, the present disclosure may be extended to other OFDM-based transmission waveforms or multiple access schemes, such as filtered OFDM (F-OFDM). The present disclosure encompasses several components that may be used in conjunction or in combination with one another, or may operate as standalone schemes.

[0102] In one embodiment, the SS / PBCH block pattern in the time domain within a predefined time period (e.g., half a frame) is determined based on the SS / PBCH block pattern in a predefined time unit (e.g., one time slot or several consecutive time slots), and is repeated in the time domain to constitute all candidate SS / PBCH blocks within the predefined time period. For this embodiment, the index of the first symbol of the candidate SS / PBCH block within the predefined time period is and K is the size of a predefined time unit in time slots, is the number of symbols in a slot (e.g., 14 symbols for normal CP and 12 symbols for extended CP), and S start is the set of symbols that are the first symbols of candidate SS / PBCH blocks within a predefined time unit. n is the index of a predefined time unit within a predefined time period, where n∈S index For example, in NR Rel-15, Figure 7 The SS / PBCH block pattern in the predefined time unit is shown in Figure 8 S is shown in index A collection of .

[0103] In one embodiment, at least one embodiment and / or example may be to support SS / PBCH block patterns for a given SCS in a predefined time unit, where the SCS may be, for example, in {120kHz, 240kHz, 480kHz, 960kHz}. This embodiment focuses on S start and K designs, which can be combined with a focus on S index to provide a complete design of SS / PBCH block patterns in the time domain.

[0104] In one embodiment, the predefined time unit for the SS / PBCH block pattern is relative to a reference SCS, and the mapping of the candidate SS / PBCH blocks in the predefined time unit is determined based on reserving a number of symbols in the time slot for a control resource set (CORESET) and / or hybrid automatic repeat request (HARQ) acknowledgement (ACK) transmission (including delay requirements for TX to RX switching).

[0105] In one embodiment, the predefined time unit for the SS / PBCH block pattern is determined by assuming that a minimum required number of symbols between adjacent candidate SS / PBCH blocks is reserved for beam scanning of SS / PBCH blocks, e.g. is the minimum number of symbols required for beam scanning of SS / PBCH blocks. start The spacing between adjacent elements in can be at least Where 4 is the number of symbols used for the SS / PBCH block.

[0106] In one example, the SS / PBCH block pattern in the predefined time unit remains the same as one of the SS / PBCH block patterns supported in Rel-15 and is scaled by the new parameter set. For this example, the predefined time unit is one time slot or several consecutive time slots, and the SS / PBCH block pattern in the predefined time unit follows Figure 7 An example of this is in .

[0107] In one example, for a given parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2, 8} + 14·n, where n∈S index , and S index is as described in the examples of the present disclosure. This example is shown as #1 in Table 2.

[0108] In another example, for a given parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {4, 8, 16, 20}+28·n, where n∈S index , and S index is as described in the examples of the present disclosure. This example is shown as #2 in Table 2.

[0109] In yet another example, for a given parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {8, 12, 16, 20, 32, 36, 40, 44} + 56·n, where n∈S index , and S index is as described in the examples of the present disclosure. This example is shown as #3 in Table 2.

[0110] In one example, the SS / PBCH block pattern in the predefined time unit is following the Rel-15 pattern by disabling some candidate SS / PBCH blocks.

[0111] In one example, for a given parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2}+14·n, where n∈S index , and Sindex As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with odd candidate SS / PBCH block indices (e.g., starting symbol 8) are disabled. This example is illustrated in Fig. 9 , and also as shown in #4 in Table 2.

[0112] In another example, for a given parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {8}+14·n, where n∈S index , and S index As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with even candidate SS / PBCH block indices (eg, starting symbol 2) are disabled. This example is shown as #5 in Table 2.

[0113] In yet another example, for a given parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {4, 16}+28·n, where n∈S index , and S index As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with odd candidate SS / PBCH block indices (e.g., starting symbols 8 or 20) are disabled. This example is illustrated in Fig. 9 , and also as shown in #6 in Table 2.

[0114] In yet another example, for a given parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {8, 20}+28·n, where n∈S index , and S index As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with even candidate SS / PBCH block indices (eg, starting symbols 4 or 16) are disabled. This example is shown as #7 in Table 2.

[0115] In yet another example, for a given parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {8, 16, 32, 40}+56·n, where n∈S index , and S index As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with odd candidate SS / PBCH block indices (e.g., starting symbols 12, 20, 36, or 44) are disabled. This example is illustrated in FIG. Fig. 9 , and also as shown in #8 in Table 2.

[0116] In yet another example, for a given parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {12, 20, 36, 44}+56·n, where n∈S index , and S index As described in the examples of the present disclosure. In this example, candidate SS / PBCH blocks with even candidate SS / PBCH block indices (e.g., starting symbols 8, 16, 32, or 40) are disabled. This example is shown in #9 in Table 2.

[0117] In one example, disabling candidate SS / PBCH blocks with even candidate SS / PBCH block indices or odd candidate SS / PBCH block indices may be configurable for the UE (eg, at least for the SCell or PCell).

[0118] Fig. 9 An example disabled candidate SS / PBCH block 900 is illustrated in accordance with an embodiment of the present disclosure. Fig. 9 The embodiment of disabling candidate SS / PBCH blocks 900 shown in FIG. 1 is illustrative only. In yet another example, the predefined time unit for the SS / PBCH block pattern is a time slot relative to a reference SCS, and the mapping of candidate SS / PBCH blocks in the time slot relative to all supported SCSs within the carrier frequency range is determined based on the symbol number requirement for the CORESET and the delay requirement for the TX to RX switch (e.g., aiming to receive the corresponding HARQ ACK in the same time slot).

[0119] In one example, the reference SCS may be 480 kHz. In another example, the reference SCS may be 240 kHz. In yet another example, the reference SCS may be 120 kHz.

[0120] Fig.10 An example SS / PBCH block pattern 1000 is illustrated in accordance with an embodiment of the present disclosure. Fig.10 The embodiment of the SS / PBCH block pattern 1000 shown in FIG. 1 is illustrative only. In one example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2}+14·n, where n∈S index，1 , and S index，1 is as described in the example of the present disclosure; and for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {4, 8}+28·n, where n∈ index，2 , and S index，2As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.10 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*7us (e.g., 7 symbols at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 2. This example is shown in #10 and #11 in Table 2.

[0121] In another example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3}+14·n, where n∈S index，1 , and S index，1 As described in the examples of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {6, 10} + 28·n, where n∈S index，2 , and S index，2 As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.10 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*6us (e.g., 6 symbols at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 3. This example is shown in #12 and #13 in Table 2.

[0122] In yet another example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4}+14·n, where n∈S index，1 , and S index，1 As described in the examples of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {8, 12}+28·n, where n∈S index，2 , and S index，2As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.10 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*5us (e.g., 5 symbols at 480kHz SCS and normal CP), and the maximum number of CORESET symbols relative to the reference SCS can be 4. This example is shown in #14 and #15 in Table 2.

[0123] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 5}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {2, 6, 10, 14}+28·n, where n∈S index，2 , and S index，2 As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.11 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*4us (e.g., 4 symbols at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 1. This example is shown in #16 and #17 in Table 2.

[0124] Fig.11 Another example SS / PBCH block pattern 1100 is illustrated according to an embodiment of the present disclosure. Fig.11 The embodiment of the SS / PBCH block pattern 1100 shown in FIG. 1 is for illustration only. In yet another example, there are two candidate SS / PBCH blocks mapped to time slots relative to the reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {2, 6}+14·n, where n∈S index，1 , and S index，1As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4, 8, 12, 16}+28·n, where n∈S index，2 , and S index，2 As described in the example of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960kHz, while the reference SCS in the first parameter set is 480kHz). The example is illustrated in Fig.11 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*3us (e.g., 3 symbols at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 2. This example is shown in #18 and #19 in Table 2.

[0125] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3, 7}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {6, 10, 14, 18}+28·n, where n∈S index，2 , and S index，2 is as described in the examples of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.11 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*2us (e.g., 2 symbols at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 3. This example is shown in #20 and #21 in Table 2.

[0126] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4, 8}+14·n, where n∈S index，1 , and S index，1As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {8, 12, 16, 20}+28·n, where n∈S index，2 , and S index，2 As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.11 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*1us (e.g., 1 symbol at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 4. This example is shown in #22 and #23 in Table 2.

[0127] Fig.12 Yet another example SS / PBCH block pattern 1200 according to an embodiment of the disclosure is illustrated. Fig.12 The embodiment of the SS / PBCH block pattern 1200 shown in FIG. 1 is for illustration only. In yet another example, there are two candidate SS / PBCH blocks mapped to non-contiguous symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half frame is {1, 6}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {2, 6, 12, 16}+28·n, where n∈S index，2 , and S index，2 As described in the example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (for example, the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.12 As shown in 1201 of . For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*3us (e.g., 3 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 1. This example is shown in #24 and #25 in Table 2.

[0128] In yet another example, there are two candidate SS / PBCH blocks mapped to non-consecutive symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 8}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 6, 16, 20}+28·n, where n∈S index，2 , and S index，2 is as described in the examples of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.12 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*1us (e.g., 1 symbol at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 1. This example is shown in #26 and #27 in Table 2.

[0129] In yet another example, there are two candidate SS / PBCH blocks mapped to non-contiguous symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 8}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {4, 8, 16, 20}+28·n, where n∈S index，2 , and S index，2 is as described in the examples of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set. In one example, the SCS in the second parameter set is 960kHz, while the reference SCS in the first parameter set is 480kHz. In another example, the SCS in the second parameter set is 240kHz, while the reference SCS in the first parameter set is 120kHz. This example is illustrated in Fig.12For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*1us (e.g., 1 symbol at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 2. This example is shown in #28 and #29 in Table 2.

[0130] In yet another example, there are two candidate SS / PBCH blocks mapped to non-contiguous symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2, 9}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {4, 8, 18, 22}+28·n, where n∈S index，2 , and S index，2 is as described in the examples of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.12 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.23*1us (e.g., 1 symbol at 480kHz SCS and normal CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 2. This example is shown in #30 and #31 in Table 2.

[0131] In yet another example, there are two candidate SS / PBCH blocks mapped to non-contiguous symbols in a slot relative to a reference SCS, and for a first parameter set with a normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3, 10}+14·n, where n∈S index，1 , and S index，1 As described in the example of the present disclosure, for the second parameter set with normal CP length, the index of the first symbol of the candidate SS / PBCH block within the half frame is {6, 10, 20, 24}+28·n, where n∈S index，2 , and S index，2 is as described in the examples of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.12 For this example, there is no gap for TX / RX switching and HARQ ACK, and the maximum number of symbols of CORESET relative to the reference SCS can be 3. This example is shown in #32 and #33 in Table 2.

[0132] In yet another embodiment, the predefined time unit for the SS / PBCH block pattern is a time slot of the SCS relative to the SS / PBCH block, and the SS / PBCH block pattern is common to all supported SCSs or at least one supported SCS. For this example, the mapping of candidate SS / PBCH blocks in the time slot can be determined based on the symbol number requirement for the CORESET and the delay requirement for the TX to RX switch (e.g., aiming to receive the corresponding HARQ ACK in the same time slot).

[0133] In one example, the supported SCS for the higher frequency range may be the set of {120kHz, 240kHz, 480kHz, 960kHz} or a subset thereof.

[0134] FIG. 13A illustrates another example SS / PBCH block pattern 1300 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1300 shown in FIG. 13A is for illustration only. In one example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2}+14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1301 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*7us (e.g., if 960kHz is the maximum SCS supported, it is 7 symbols under 960kHz SCS and normal CP) or 2.23*7us (e.g., if 480kHz is the maximum SCS supported, it is 7 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 2. This example is also shown in #1 in Table 3.

[0135] In another example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3}+14·n, where n∈S index , and S indexAs described in one example of the present disclosure. A diagram of this example is shown in 1302 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*6us (e.g., if 960kHz is the maximum SCS supported, it is 6 symbols under 960kHz SCS and normal CP) or 2.23*6us (e.g., if 480kHz is the maximum SCS supported, it is 6 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 3. This example is also shown in #2 in Table 3.

[0136] In yet another example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4}+14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1303 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*5us (e.g., if 960kHz is the maximum SCS supported, it is 5 symbols under 960kHz SCS and normal CP) or 2.23*5us (e.g., if 480kHz is the maximum SCS supported, it is 5 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 4. This example is also shown in #3 in Table 3.

[0137] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 5} + 14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1304 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*4us (e.g., if 960kHz is the maximum SCS supported, it is 4 symbols under 960kHz SCS and normal CP) or 2.23*4us (e.g., if 480kHz is the maximum SCS supported, it is 4 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 1. This example is also shown in #4 in Table 3.

[0138] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 6} + 14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1305 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*3us (e.g., if 960kHz is the maximum SCS supported, it is 3 symbols under 960kHz SCS and normal CP) or 2.23*3us (e.g., if 480kHz is the maximum SCS supported, it is 3 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 2. This example is also shown in #5 in Table 3.

[0139] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3, 7}+14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1306 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*2us (e.g., if 960kHz is the maximum SCS supported, it is 2 symbols under 960kHz SCS and normal CP) or 2.23*2us (e.g., if 480kHz is the maximum SCS supported, it is 2 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 3. This example is also shown in #6 in Table 3.

[0140] In yet another example, there are two candidate SS / PBCH blocks mapped to consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4, 8}+14·n, where n∈S index , and S indexAs described in one example of the present disclosure. A diagram of this example is shown in 1307 of FIG. 13A. For this example, the gap for TX / RX switching can be as large as 1.11*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and normal CP) or 2.23*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 4. This example is also described in #7 in Table 3.

[0141] FIG. 13B illustrates yet another example SS / PBCH block pattern 1350 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1350 shown in FIG. 13B is for illustration only. In yet another example, there are two candidate SS / PBCH blocks mapped to non-contiguous symbols in a slot as a predefined time unit of the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 6} + 14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1311 of FIG. 13B. For this example, the gap for TX / RX switching can be as large as 1.11*3us (e.g., if 960kHz is the maximum SCS supported, it is 3 symbols under 960kHz SCS and normal CP) or 2.23*3us (e.g., if 480kHz is the maximum SCS supported, it is 3 symbols under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 1. This example is also shown in #8 in Table 3.

[0142] In yet another example, there are two candidate SS / PBCH blocks mapped to non-consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 8}+14·n, where n∈S index , and S indexAs described in one example of the present disclosure. A diagram of this example is shown in 1312 of FIG. 13Bb. For this example, the gap for TX / RX switching can be as large as 1.11*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and normal CP) or 2.23*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 1. This example is also shown in #9 in Table 3.

[0143] In yet another example, there are two candidate SS / PBCH blocks mapped to non-consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 8}+14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1313 of FIG. 13B. For this example, the gap for TX / RX switching can be as large as 1.11*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and normal CP) or 2.23*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 2. This example is also shown in #10 in Table 3.

[0144] In yet another example, there are two candidate SS / PBCH blocks mapped to non-consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 9} + 14·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1314 of FIG. 13B. For this example, the gap for TX / RX switching can be as large as 1.11*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and normal CP) or 2.23*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and normal CP), and the maximum number of symbols of CORESET can be 2. This example is also shown in #11 in Table 3.

[0145] In yet another example, there are two candidate SS / PBCH blocks mapped to non-consecutive symbols in a slot that is a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with a normal CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3, 10} + 14·n, where n∈S index , and S index As described in one example of the present disclosure. An illustration of this example is shown in 1315 of FIG. 13B. For this example, there is no gap for TX / RX switching and HARQ ACK, and the maximum number of symbols of CORESET can be 3. This example is also shown in #12 in Table 3.

[0146] In yet another example, the predefined time unit for the SS / PBCH block pattern is a time slot relative to a reference SCS, and the mapping of candidate SS / PBCH blocks in the time slots relative to all supported SCSs within the carrier frequency range is determined based on the symbol number requirement for the CORESET and the delay requirement for TX to RX switching (e.g., aiming to receive the corresponding HARQ ACK in the same time slot).

[0147] In one example, the reference SCS may be the minimum SCS for data transmission of the carrier frequency range under consideration, for example, 120 kHz or 240 kHz or 480 kHz.

[0148] Fig.14 Yet another example SS / PBCH block pattern 1400 according to an embodiment of the disclosure is illustrated. Fig.14 The embodiment of the SS / PBCH block pattern 1400 shown in FIG. 1 is for illustration only. In one example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with an extended CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2}+12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {4, 8}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.14As shown in 1401 of . For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.6*5us (e.g., 5 symbols under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 2. This example is shown in #1 and #2 in Table 4.

[0149] In another example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with an extended CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3}+12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {6, 10}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). Fig.14 For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.6*4us (e.g., 4 symbols at 480kHz SCS and extended CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 3. This example is shown in #3 and #4 in Table 4.

[0150] In yet another example, there is a candidate SS / PBCH block mapped to a slot relative to a reference SCS, and for a first parameter set with an extended CP length, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4}+12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {8, 12}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure; and the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). This example is illustrated in Fig.14For this example, if the reference SCS is 480kHz, the gap for TX / RX switching can be as large as 2.6*3us (e.g., 3 symbols at 480kHz SCS and extended CP), and the maximum number of symbols of CORESET relative to the reference SCS can be 4. This example is shown in #5 and #6 in Table 4.

[0151] FIG. 15A illustrates another example SS / PBCH block pattern 1500 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1500 shown in FIG. 15A is for illustration only. FIG. 15B illustrates another example SS / PBCH block pattern 1550 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1550 shown in FIG. 15B is for illustration only. In yet another example, there are two candidate SS / PBCH blocks mapped to time slots relative to a reference SCS, and for a first parameter set with an extended CP length, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {1, 5}+12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with an extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half-frame is {2, 6, 10, 14}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1501 of FIG. 15A. For this example, if the reference SCS is 480 kHz, the gap for TX / RX switching can be as large as 2.6*2us (e.g., 2 symbols at 480 kHz SCS and extended CP), and the maximum number of symbols of the CORESET relative to the reference SCS can be 1. This example is shown in #7 and #8 in Table 4.

[0152] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {2, 6} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {4, 8, 12, 16}+24·n, where n∈S index，2 , and Sindex，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1502 of FIG. 15A. For this example, if the reference SCS is 480 kHz, the gap for TX / RX switching can be as large as 2.6*1us (e.g., 1 symbol at 480kHz SCS and extended CP), and the maximum number of symbols of the CORESET relative to the reference SCS can be 2. This example is shown in #9 and #10 in Table 4.

[0153] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {3, 7} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {6, 10, 14, 18}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1503 of FIG. 15A. For this example, if the reference SCS is 480 kHz, the gap for TX / RX switching can be as large as 2.6*1us (e.g., 1 symbol at 480kHz SCS and extended CP), and the maximum number of symbols of the CORESET relative to the reference SCS can be 3. This example is shown in #11 and #12 in Table 4.

[0154] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {1, 6} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {2, 6, 12, 16}+24·n, where n∈S index，2 , and S index，2As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1504 of FIG. 15A. For this example, if the reference SCS is 480 kHz, the gap for TX / RX switching can be as large as 2.6*1us (e.g., 1 symbol at 480kHz SCS and extended CP), and the maximum number of symbols of the CORESET relative to the reference SCS can be 1. This example is shown in #13 and #14 in Table 4.

[0155] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {1, 7} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {2, 6, 14, 18}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1305 of FIG. 15B. For this example, if the reference SCS is 480 kHz, the gap for TX / RX switching can be as large as 2.6*1us (e.g., 1 symbol at 480kHz SCS and extended CP), and the maximum number of symbols of the CORESET relative to the reference SCS can be 1. This example is shown in #15 and #16 in Table 4.

[0156] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {2, 8} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {4, 8, 16, 20}+24·n, where n∈S index，2 , and S index，2As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1506 of FIG. 15B. For this example, there is no gap for TX / RX switching, and the maximum number of symbols of the CORESET relative to the reference SCS can be 2. This example is shown in #17 and #18 in Table 4.

[0157] In yet another example, there are two candidate SS / PBCH blocks mapped to the time slot relative to the reference SCS, and for the first parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {2, 8} + 12·n, where n∈S index，1 , and S index，1 As described in one example of the present disclosure, for the second parameter set with extended CP length, the index of the first symbol of the candidate SS / PBCH block in the half frame is {3, 8, 15, 20}+24·n, where n∈S index，2 , and S index，2 As described in one example of the present disclosure, the SCS in the second parameter set is twice the reference SCS in the first parameter set (e.g., the SCS in the second parameter set is 960 kHz, while the reference SCS in the first parameter set is 480 kHz). An illustration of this example is shown in 1507 of FIG. 15B. This example is shown in #19 and #20 in Table 4.

[0158] In yet another embodiment, the predefined time unit for the SS / PBCH block pattern is a time slot of the SCS relative to the SS / PBCH block, and the SS / PBCH block pattern is common to all supported SCSs or at least one supported SCS. For this example, the mapping of candidate SS / PBCH blocks in the time slot can be determined based on the symbol number requirement for the CORESET and the delay requirement for the TX to RX switch (e.g., aiming to receive the corresponding HARQ ACK in the same time slot).

[0159] In one example, the supported SCS for the higher frequency range may be the set of {120kHz, 240kHz, 480kHz, 960kHz} or a subset thereof.

[0160] FIG. 16A illustrates another example SS / PBCH block pattern 1600 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1600 shown in FIG. 16A is for illustration only. In one example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with an extended CP, the index of the first symbol of the candidate SS / PBCH block within a half-frame is {2}+12·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1601 of FIG. 16A. For this example, the gap for TX / RX switching can be as large as 1.3*5us (e.g., if 960kHz is the maximum SCS supported, it is 5 symbols under 960kHz SCS and extended CP) or 2.6*5us (e.g., if 480kHz is the maximum SCS supported, it is 5 symbols under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 2. This example is shown in #21 in Table 4.

[0161] In another example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3}+12·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1602 of FIG. 16A. For this example, the gap for TX / RX switching can be as large as 1.3*4us (e.g., if 960kHz is the maximum SCS supported, it is 4 symbols under 960kHz SCS and extended CP) or 2.6*4us (e.g., if 480kHz is the maximum SCS supported, it is 4 symbols under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 3. This example is shown in #22 in Table 4.

[0162] In yet another example, there is one candidate SS / PBCH block mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4}+12·n, where n∈S index , and S indexAs described in one example of the present disclosure. A diagram of this example is shown in 1603 of FIG. 16A. For this example, the gap for TX / RX switching can be as large as 1.3*3us (e.g., if 960kHz is the maximum SCS supported, it is 3 symbols under 960kHz SCS and extended CP) or 2.6*3us (e.g., if 480kHz is the maximum SCS supported, it is 3 symbols under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 4. This example is shown in #23 in Table 4.

[0163] In yet another example, there are two candidate SS / PBCH blocks mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 5} + 12 n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1604 of FIG. 16A. For this example, the gap for TX / RX switching can be as large as 1.3*2us (e.g., if 960kHz is the maximum SCS supported, it is 2 symbols under 960kHz SCS and extended CP) or 2.6*2us (e.g., if 480kHz is the maximum SCS supported, it is 2 symbols under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 1. This example is shown in #24 in Table 4.

[0164] In yet another example, there are two candidate SS / PBCH blocks mapped to a time slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 6} + 12 n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1605 of FIG. 16A. For this example, the gap for TX / RX switching can be as large as 1.3*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and extended CP) or 2.6*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 2. This example is shown in #25 in Table 4.

[0165] FIG. 16B illustrates yet another example SS / PBCH block pattern 1650 according to an embodiment of the present disclosure. The embodiment of the SS / PBCH block pattern 1650 shown in FIG. 16B is for illustration only. In yet another example, there are two candidate SS / PBCH blocks mapped to a time slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with an extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {3, 7} + 12·n, where n∈S index , and S index As described in one example of the present disclosure. A diagram of this example is shown in 1606 of FIG. 16B. For this example, the gap for TX / RX switching can be as large as 1.3*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and extended CP) or 2.6*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 3. This example is shown in #26 in Table 4.

[0166] In yet another example, there are two candidate SS / PBCH blocks mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {4, 8}+12·n, where n∈S index , and S index As described in one example of the present disclosure. An illustration of this example is shown in 1607 of FIG. 16B. For this example, there is no gap for TX / RX switching, and the maximum number of symbols of CORESET can be 4. This example is shown as #27 in Table 4.

[0167] In yet another example, there are two candidate SS / PBCH blocks mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {1, 6} + 12 n, where n∈S index , and S indexAs described in one example of the present disclosure. A diagram of this example is shown in 1608 of FIG. 16B. For this example, the gap for TX / RX switching can be as large as 1.3*1us (e.g., if 960kHz is the maximum SCS supported, it is 1 symbol under 960kHz SCS and extended CP) or 2.6*1us (e.g., if 480kHz is the maximum SCS supported, it is 1 symbol under 480kHz SCS and extended CP), and the maximum number of symbols of CORESET can be 1. This example is shown in #28 in Table 4.

[0168] In yet another example, there are two candidate SS / PBCH blocks mapped to a slot as a predefined time unit for the SS / PBCH block pattern, and for each supported SCS with extended CP, the index of the first symbol of the candidate SS / PBCH block within the half-frame is {2, 8} + 12 n, where n∈S index , and S index As described in one example of the present disclosure. An illustration of this example is shown in 1609 of FIG. 16A. For this example, there is no gap for TX / RX switching, and the maximum number of symbols of CORESET can be 2. This example is shown as #29 in Table 4.

[0169] An example of the above-described example according to the normal CP is shown in Table 2 or Table 3, and an example of the above-described example according to the extended CP is shown in Table 4.

[0170] Table 2. Example SS / PBCH block patterns

[0171]

Table 2

[0172]

[0173] Table 3. Example SS / PBCH block patterns

[0174]

Table 3

[0175]

[0176] Table 4. Example SS / PBCH block patterns

[0177]

Table 4

[0178]

[0179]

[0180] In one embodiment, the first 4 symbols relative to the 120 kHz SCS are retained, that is, the first 4 symbols relative to the 120·2 μ kHz SCS 4·2μ symbols, and these symbols are not mapped to SS / PBCH blocks, and the last 4 symbols relative to the 120kHz SCS are reserved, that is, relative to 120·2 μ kHz SCS 4·2 μ symbols, and these symbols are not mapped for SS / PBCH blocks. There are 4·2 in a predefined time unit (e.g., 2 slots in 120kHz SCS). μ SS / PBCH blocks.

[0181] In one embodiment, the first SS / PBCH block within the predefined time unit starts at symbol #4 relative to the 120 kHz SCS, i.e., relative to 120·2 μ kHz SCS symbol #4·2 μ The last SS / PBCH block within the predefined time unit starts at 120·2 μ kHz SCS symbol #24·2 μ -4. If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #12 to #15 relative to the 120kHz SCS can be used for SS / PBCH block mapping. For example, the first half of the SS / PBCH block can be shifted to the following symbol, and the second half of the SS / PBCH block can be shifted to the previous symbol. In this example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0182]

[0183]

[0184] and

[0185] K=2·2 μ .

[0186] An example corresponding to this example is shown in Table 5, and a diagram of this example is shown in Fig.17 Shown in. Fig.17 The 1702 in This is Example 2 in Table 5.

[0187] Table 5. Example SS / PBCH block patterns

[0188]

Table 5

[0189]

[0190] Fig.17 Yet another example SS / PBCH block pattern 1700 according to an embodiment of the disclosure is illustrated. Fig.17 The embodiment of the SS / PBCH block pattern 1700 shown in FIG. 1 is for illustration only. In another example, the first SS / PBCH block within the predefined time unit starts at symbol #4 relative to the 120 kHz SCS, i.e., relative to 120·2 μ kHz SCS symbol #4·2 μ If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #12 to #15 relative to the 120kHz SCS can be used for SS / PBCH block mapping. For example, the first half of the SS / PBCH block can be shifted to the following symbol, and the second half of the SS / PBCH block can be shifted to the previous symbol. In this example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0191]

[0192] and

[0193] K=2·2 μ .

[0194] An example corresponding to this example is shown in Table 6.

[0195] Table 6. Example SS / PBCH block patterns

[0196]

Table 6

[0197]

[0198] In another example, the first 2 symbols relative to the 120kHz SCS are retained, that is, the first 2 symbols relative to 120·2 μ 2 kHz SCS 2 2 μ symbols, and these symbols are not mapped to SS / PBCH blocks, and the last 2 symbols relative to the 120kHz SCS are reserved, that is, relative to 120·2 μ 2 kHz SCS 2 2 μsymbols, and these symbols are not mapped for SS / PBCH blocks. There are 4·2 in a predefined time unit (e.g., 2 slots in 120kHz SCS). μ If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #2, #3, #12 to #15, #24, and #25 relative to the 120kHz SCS can be used for SS / PBCH block mapping.

[0199] In one example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks for 120kHz SCS (e.g., for 120kHz and / or 240kHz SCS, And for 480kHz and / or 960kHz SCS, ).

[0200]

[0201]

[0202] and

[0203] K=2·2 μ ,

[0204] Where S 1 is the starting symbol of the first SS / PBCH block within a predefined time unit and is contained in symbol #2 or #3 or #4 relative to 120kHz SCS (e.g., for 240kHz SCS, S 1 = 4, 5, 6, 7, or 8; or, for 480kHz SCS, S 1 =8, 9, ... or 16; or, for 960kHz SCS, S 1 =16, 17, ..., 32); and S 2 It is the symbol after the last symbol of the last SS / PBCH block in the predefined time unit (i.e., equivalent to S 2 -4 is the starting symbol of the last SS / PBCH block) and is contained in symbol #24 or #25 or #26 relative to 120kHz SCS (e.g., for 240kHz SCS, S 1 =48, 49, ..., 52; or, for 480kHz, S 1=96, 97, ..., 104; or, for 960kHz SCS, S 1 =192, 193, ..., 208).

[0205] An example corresponding to this example is shown in Table 7, and a diagram of this example is shown in Fig.18 Shown in. Fig.18 The 1802 in corresponds to This is Example 3 in Table 7.

[0206] Table 7. Example SS / PBCH block patterns

[0207]

Table 7

[0208]

[0209]

[0210]

[0211]

[0212] Fig.18 Yet another example SS / PBCH block pattern 1800 according to an embodiment of the disclosure is illustrated. Fig.18 The embodiment of SS / PBCH block pattern 1800 shown in FIG. 1 is for illustration only. In another embodiment, the spacing between adjacent SS / PBCH blocks may be inconsistent (e.g., may be different for a given mode), and the first one or two symbols of the slot are reserved for the CORESET.

[0213] In one example, for SCS as SS / PBCH blocks of 240 kHz, the SS / PBCH block pattern may be given by {4, 8, 16, 20, 32, 36, 44, 48}+14·4·n or equivalently by {4, 8, 16, 20}+14·2·n. In another example, for SCS as SS / PBCH blocks of 240 kHz, the SS / PBCH block pattern may be given by {4, 9, 15, 20, 32, 37, 43, 48}+14·4·n or equivalently by {4, 9, 15, 20}+14·2·n. In yet another example, for an SCS of SS / PBCH blocks of 480 kHz, the SS / PBCH block pattern may be given by {8, 12, 16, 20, 32, 36, 40, 44, 64, 68, 72, 76, 88, 92, 96, 100}+14·8·n or equivalently by {8, 12, 16, 20, 32, 36, 40, 44}+14·4·n. In yet another example, for an SCS of SS / PBCH blocks of 480 kHz, the SS / PBCH block pattern may be given by {8, 13, 18, 23, 29, 34, 39, 44, 64, 69, 74, 79, 85, 90, 95, 100}+14·8·n or equivalently by {8, 13, 18, 23, 29, 34, 39, 44}+14·4·n.

[0214] In yet another example, for SCS as SS / PBCH blocks at 960 kHz, the SS / PBCH block pattern may be or equivalently by {16, 20, 24, 28, 32, 36, 40, 44, 64, 68, 72, 76, 80, 84, 88, 92} + 14·8·n. In yet another example, for an SCS as a 960 kHz SS / PBCH block, the SS / PBCH block pattern may be given by is given by or equivalently by {16, 21, 26, 31, 36, 41, 46, 51, 57, 62, 67, 72, 77, 82, 87, 92} + 14·8·n.

[0215] In one example, the first two symbols relative to the 240kHz SCS are retained, that is, the first two symbols relative to 240·2 μ 2 kHz SCS 2 2 μ symbols, and these symbols are not mapped to SS / PBCH blocks, and the last 2 symbols relative to the 240kHz SCS are reserved, that is, relative to 240·2 μ 2 kHz SCS 2 2 μsymbols, and these symbols are not mapped for SS / PBCH blocks. There are 8·2 in a predefined time unit (e.g., 2 slots in a 240kHz SCS). μ SS / PBCH blocks. If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, then symbols other than those reserved relative to the 240kHz SCS can be used for SS / PBCH block mapping. μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 240·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0216]

[0217]

[0218] and

[0219] K=4·2 μ ,

[0220] Where S 1 is the starting symbol of the first SS / PBCH block within the predefined time unit, and S 2 is the symbol after the last symbol of the last SS / PBCH block in the predefined time unit (i.e., equivalent to s 2 -4 is the starting symbol of the last SS / PBCH block).

[0221] An example corresponding to this example is shown in Table 8, and a diagram of this example is shown in Fig.19 Shown in.

[0222] Table 8. Example SS / PBCH block patterns

[0223]

Table 8

[0224]

[0225] Fig.19 Yet another example SS / PBCH block pattern 1900 is illustrated according to an embodiment of the present disclosure. Fig.19 The embodiment of SS / PBCH block pattern 1900 shown in FIG. 1 is for illustration only. In one embodiment, the first two symbols relative to the 120 kHz SCS are retained, that is, the first two symbols relative to the 120 kHz SCS are retained. μ kHz SCS 2·2 μsymbols, and these symbols are not mapped to SS / PBCH blocks, and the last 2 symbols relative to 120kHz SCS are reserved, that is, relative to 120·2 μ kHz SCS 2·2 μ symbols, and these symbols are not mapped for SS / PBCH blocks. There are 2·2 in a predefined time unit (e.g., 1 slot in a 120kHz SCS). μ SS / PBCH blocks.

[0226] In one example, the first SS / PBCH block within the predefined time unit starts at symbol #2 relative to the 120 kHz SCS, i.e., relative to 120·2 μ kHz SCS symbol #2·2 μ The last SS / PBCH block within the predefined time unit starts at 120·2 μ kHz SCS symbol #12·2 μ -4. If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #6 to #7 relative to the 120kHz SCS can be used for SS / PBCH block mapping. For example, the first half of the SS / PBCH block can be shifted to the following symbol, and the second half of the SS / PBCH block can be shifted to the previous symbol. In this example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0227]

[0228]

[0229] and

[0230] K=2 μ .

[0231] An example corresponding to this example is shown in Table 9, and a diagram of this example is shown in Fig. 20 Shown in. Fig. 20 The 2002 in This is Example 2 in Table 9.

[0232] Table 9. Example SS / PBCH block patterns

[0233]

Table 9

[0234]

[0235] Fig. 20 Yet another example SS / PBCH block pattern 2000 according to an embodiment of the present disclosure is illustrated. Fig. 20 The embodiment of the SS / PBCH block pattern 2000 shown in FIG. 2 is for illustration only. In another example, the first SS / PBCH block within the predefined time unit starts at symbol #2 relative to the 120 kHz SCS, i.e., relative to 120·2 μ kHz SCS symbol #2·2 μ If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #6 to #7 relative to the 120kHz SCS can be used for SS / PBCH block mapping. For example, the first half of the SS / PBCH block can be shifted to the later symbol, and the second half of the SS / PBCH block can be shifted to the earlier symbol. In this example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0236]

[0237] and

[0238] K=2 μ .

[0239] An example corresponding to this example is shown in Table 10.

[0240] Table 10. Example SS / PBCH block patterns

[0241]

Table 10

[0242]

[0243] In another example, the first 2 symbols relative to the 120kHz SCS are retained, that is, the first 2 symbols relative to 120·2 μ kHz SCS 2·2 μ symbols, and these symbols are not mapped to SS / PBCH blocks, and the last symbol relative to the 120kHz SCS is reserved, that is, relative to 120·2 μ 2 kHz SCS μ symbols, and these symbols are not mapped for SS / PBCH blocks. There are 2·2 in a predefined time unit (e.g., 1 slot in a 120kHz SCS).μ SS / PBCH blocks.

[0244] In one embodiment, the first SS / PBCH block within the predefined time unit starts at symbol #2 relative to the 120 kHz SCS, i.e., relative to 120·2 μ kHz SCS symbol #2·2 μ The last SS / PBCH block within the predefined time unit starts at 120·2 μ kHz SCS symbol #S 2 -4. If the gap between two adjacent SS / PBCH blocks is at least 1 symbol relative to a certain SCS, symbols #6 to #8 relative to the 120kHz SCS can be used for SS / PBCH block mapping. For example, the first half of the SS / PBCH block can be shifted to the following symbol, and the second half of the SS / PBCH block can be shifted to the previous symbol. In this example, relative to 120·2 μ kHz SCS SS / PBCH block pattern can be expressed as follows, where is relative to 120·2 μ The minimum number of symbols required for beam scanning of SS / PBCH blocks of kHz SCS.

[0245]

[0246]

[0247] and

[0248] K=2 μ .

[0249] An example corresponding to this example is shown in Table 11, and a diagram of this example is shown in Fig.21 Shown in. Fig.21 The 2102 in corresponds to This is Example 2 in Table 11.

[0250] Table 11. Example SS / PBCH block pattern

[0251]

Table 11

[0252]

[0253]

[0254] Fig.21 Yet another example SS / PBCH block pattern 2100 according to an embodiment of the disclosure is illustrated. Fig.21The embodiment of the SS / PBCH block pattern 2100 shown in FIG. 2 is for illustration only. In one example, the first 2 symbols relative to the 240 kHz SCS are retained, that is, the first 2 symbols relative to the 240 kHz SCS are retained. μ kHz SCS 2·2 μ symbols, and these symbols are not mapped to SS / PBCH blocks, and the last 2 symbols relative to the 240kHz SCS are reserved, that is, relative to 240·2 μ kHz SCS 2·2 μ symbols, and these symbols are not mapped for SS / PBCH blocks. There are 2·2 in a predefined time unit (e.g., 1 time slot in a 240kHz SCS). μ SS / PBCH blocks.

[0255] Examples corresponding to this example are shown in Tables 12 and 13.

[0256] Table 12. Example SS / PBCH block patterns

[0257]

Table 12

[0258]

[0259] Table 13. Example SS / PBCH block patterns

[0260]

Table 13

[0261]

[0262] In one embodiment, the first two symbols relative to the 480kHz SCS are retained, that is, the first two symbols relative to the 480·2 μ kHz SCS 2·2 μ symbols, and these symbols are not mapped for SS / PBCH blocks. There are 2·2 in a predefined time unit (e.g., 1 time slot in a 480kHz SCS). μ SS / PBCH blocks.

[0263] Examples corresponding to this example are shown in Tables 14 and 15.

[0264] Table 14. Example SS / PBCH block pattern

[0265]

Table 14

[0266]

[0267] Table 15. Example SS / PBCH block pattern

[0268]

Table 15

[0269]

[0270] In one embodiment, the SS / PBCH block pattern may be enhanced in the design of a predefined time unit within a predefined time period, for example, including S index Design. Fig. 22 FIG. 1 shows a diagram of predefined time units within a predefined time period, wherein the predefined time units containing candidate SS / PBCH blocks are marked with shading, and their corresponding indexes n form a set S index The examples and embodiments of the present disclosure may be used with S start Combined with the design of K, as described in other embodiments of the present disclosure.

[0271] Fig. 22 An example predefined time unit within the predefined time period 2200 according to an embodiment of the present disclosure is illustrated. Fig. 22 The embodiment of the predefined time unit within the predefined time period 2200 shown in FIG. is for illustration only. In NR Rel-15 and Rel-16, the predefined time period for the SS / PBCH block pattern is half a frame. For NR operating from 52.6 GHz to 71 GHz, it may be necessary to extend the predefined time period so that more candidate SS / PBCH blocks can be included.

[0272] In one embodiment, the predefined time period including the SS / PBCH block can be extended to more than half a frame. For example, for operation using shared spectrum channel access, the predefined time period including the SS / PBCH block can be extended to a frame. For another example, for operation using shared spectrum channel access, the predefined time period including the SS / PBCH block can be extended to two frames.

[0273] In one embodiment, the SS / PBCH block may be transmitted within a carrier frequency range, wherein the carrier frequency range may correspond to either operation using shared spectrum channel access or operation not using shared spectrum channel access. For example, in one geographic region, the carrier frequency range may correspond to operation using shared spectrum channel access; while for another geographic region, the carrier frequency range may correspond to operation not using shared spectrum channel access.

[0274] In one example, for a given parameter set, the SS / PBCH block pattern in the time domain (e.g., including the SS / PBCH mapping pattern in the time domain with predefined time units and the occasions of the time units within a predefined duration) can be the same for operations using shared spectrum channel access and operations not using shared spectrum channel access. index The operation is the same for both the operation using the shared spectrum channel access and the operation not using the shared spectrum channel access.

[0275] In one example, the maximum number of candidate SS / PBCH blocks within a predefined time period The time slots within the predefined time period that contain the candidate SS / PBCH blocks may be the same for operations using shared spectrum channel access and operations not using shared spectrum channel access. In this regard, the time slots within the predefined time period that contain the candidate SS / PBCH blocks may also be the same for operations using shared spectrum channel access and operations not using shared spectrum channel access.

[0276] For one example, for the higher carrier frequency ranges considered in this disclosure, for both operation using shared spectrum channel access and operation not using shared spectrum channel access,

[0277] In another example, for a given parameter set, the SS / PBCH mapping pattern in the time domain with a predefined time unit may be the same for operations using shared spectrum channel access and operations not using shared spectrum channel access, but the maximum number of candidate SS / PBCH blocks within a predefined time period may be different for operations using shared spectrum channel access and operations not using shared spectrum channel access. index This is different for operations using shared spectrum channel access and operations not using shared spectrum channel access.

[0278] For example, the maximum number of candidate SS / PBCH blocks within a predefined time period for operation using shared spectrum channel access is greater than the maximum number of candidate SS / PBCH blocks within a predefined time period for operation not using shared spectrum channel access, so as to allow more transmission opportunities to accommodate shared spectrum channel access. In this regard, the time slots within the predefined time period containing candidate SS / PBCH blocks for operation not using shared spectrum channel access are a subset of the time slots within the predefined time period containing candidate SS / PBCH blocks for operation using shared spectrum channel access, and the SS / PBCH block pattern in the time domain (e.g., in one time slot or several consecutive time slots) remains the same for operation using shared spectrum channel access and operation not using shared spectrum channel access. For example, the SS / PBCH blocks within the predefined time period for operation not using shared spectrum channel access are greater than the maximum number of candidate SS / PBCH blocks within the predefined time period for operation using shared spectrum channel access. index is the S for operation using shared spectrum channel access index A subset of .

[0279] In one example, for the higher carrier frequency ranges considered in this disclosure, for operation not using shared spectrum channel access, For operations using shared spectrum channel access,

[0280] In another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For operations using shared spectrum channel access,

[0281] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For operations using shared spectrum channel access,

[0282] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For operations using shared spectrum channel access,

[0283] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For operations using shared spectrum channel access,

[0284] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For an SCS supported and using shared spectrum channel access operation, where SCS corresponds to 120·2 μ kHz SCS.

[0285] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For an SCS supported and using shared spectrum channel access operation, where SCS corresponds to 120·2 μ kHz SCS.

[0286] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For an SCS supported and using shared spectrum channel access operation, where SCS corresponds to 120·2 μ kHz SCS.

[0287] In yet another example, for the higher carrier frequency ranges considered in the present disclosure, for operation not using shared spectrum channel access, For an SCS supported and using shared spectrum channel access operation, where SCS corresponds to 120·2 μ kHz SCS.

[0288] In yet another example, for a given set of parameters, the SS / PBCH block pattern in the time domain may be different for operation using shared spectrum channel access and operation not using shared spectrum channel access.

[0289] In one example, at least for one of the supported parameter sets, one example SS / PBCH block pattern in a time domain specified in the present disclosure can be used for operations using shared spectrum channel access, and another different example SS / PBCH block pattern in a time domain specified in the present disclosure can be used for operations not using shared spectrum channel access.

[0290] In one example, both of them support a higher frequency range. For example, for at least one of the supported parameter sets, the SS / PBCH block pattern in the time domain may be the same for operations using shared spectrum channel access and operations not using shared spectrum channel access; and for at least one of the supported parameter sets, the SS / PBCH block pattern in the time domain may be different for operations using shared spectrum channel access and operations not using shared spectrum channel access.

[0291] In one embodiment, there is a latency requirement such that the span of a SS / PBCH block in the time domain cannot exceed X, where the unit of X is a predefined time unit of the SS / PBCH block pattern.

[0292] In one example, when the total duration of the candidate SS / PBCH blocks is within the predefined duration in the examples of the present disclosure, some candidate SS / PBCH blocks may be truncated to accommodate services with low latency.

[0293] In one example, for the example of one candidate SS / PBCH block in the predefined time unit for the SS / PBCH block pattern in the present disclosure, the value of n may be restricted to S index ={0, 1, ..., X-1}+Y·m, where YX is the number of predefined time units for SS / PBCH block pattern reserved for low latency services, and m=0, 1, ..., until the number of values ​​of n reaches Where |S start | is the number of candidate SS / PBCH blocks within a predefined time unit.

[0294] In one example, low latency considerations for SS / PBCH block mode may only apply to operations that do not use shared spectrum channel access.

[0295] At least one of the following examples may be used in the S described in the present disclosure: index The design of S index In the previous examples of this disclosure, it may also be referred to as S index，1 or index，2 .

[0296] In one example, for 120·2 μ kHz SS / PBCH block SCS, the number of candidate SS / PBCH blocks in a predefined time unit is represented as |S start |, and the maximum number of candidate SS / PBCH blocks in a predefined time period is expressed as but A predefined time unit contains candidate SS / PBCH blocks.

[0297] In one example, the indexes of the predefined time units may be consecutive. μ kHz SS / PBCH block SCS, |s start | and the predefined time unit duration K are as described in the example of the embodiment of the present disclosure, then S index Can be continuous, through Given.

[0298] In one example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=4·2 μ , and the predefined time unit is 2 time slots relative to the 120kHz SCS, then

[0299] In another example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=2·2 μ , and the predefined time unit is 1 time slot relative to the 120kHz SCS, then

[0300] In yet another example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=1·2 μ , and the predefined time unit is 1 time slot relative to the 120kHz SCS, then

[0301] In yet another example, for 120·2μ kHz SS / PBCH block SCS, |S start | = 4, and the predefined time unit is 2 time slots of the SCS relative to the SS / PBCH block, then

[0302] In yet another example, for 120·2 μ kHz SS / PBCH block SCS, |S start | = 2, and the predefined time unit is 1 time slot of the SCS relative to the SS / PBCH block, then

[0303] In yet another example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=1, and the predefined time unit is 1 time slot of the SCS relative to the SS / PBCH block, then

[0304] In another example, the indexes of the predefined time units may be non-contiguous. μ kHz SS / PBCH block SCS, |S start | and the predefined time unit K are as described in the example of the embodiment of the present disclosure, then S index Can be discontinuous, through S index ={0, 1, ..., 8·2 μ / K-1}+10·2 μ / K·m, where

[0305] In one example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=4·2 μ , the predefined time period is 5ms, and the predefined time unit is 2 time slots relative to 120kHz SCS, then S index ={0, 1, 2, 3}+5·m, where m=0, 1, ..., 4 / 2 μ -1.

[0306] In another example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=2·2 μ , the predefined time period is 5ms, and the predefined time unit is 1 time slot relative to the 120kHz SCS, then Sindex ={0, 1, 2, 3, 4, 5, 6, 7}+10·m, where m=0, 1, ..., 4 / 2 μ -1.

[0307] In yet another example, for 120·2 μ kHz SS / PBCH block SCS, |S start |=1·2 μ , the predefined time period is 10ms, and the predefined time unit is 1 time slot relative to the 120kHz SCS, then S index ={0, 1, 2, 3, 4, 5, 6, 7}+10·m, where m=0, 1, ..., 8 / 2 μ -1

[0308] For operations not using shared spectrum shared channel access, at least one of the examples in Table 16 and Table 17 may be supported.

[0309] Table 16. S according to the present disclosure index Example Design

[0310]

Table 16

[0311]

[0312] Table 17. S according to the present disclosure index Example Design

[0313]

Table 17

[0314]

[0315] For operations using shared spectrum shared channel access, at least one of the examples in Tables 18 to 22 may be supported.

[0316] Table 18. S according to the present disclosure index Example Design

[0317]

Table 18

[0318]

[0319] Table 19. S according to the present disclosure index Example Design

[0320]

Table 19

[0321]

[0322] Table 20. S according to the present disclosure index Example Design

[0323]

Table 20

[0324]

[0325] Table 21. S according to the present disclosure index Example Design

[0326]

Table 21

[0327]

[0328] Table 22. S according to the present disclosure index Example Design

[0329]

Table 22

[0330]

[0331] Fig.23 A flow chart of a method 2300 for SS / PBCH block mode according to an embodiment of the present disclosure is illustrated, such as may be performed by a UE (e.g., Figure 1 UE 111-116) shown in FIG. Fig.23 The embodiment of method 2300 shown in FIG. 2 is for illustration only. Fig.23 One or more of the components shown in the drawings may be implemented in dedicated circuits configured to perform the functions described, or one or more of the components may be implemented by one or more processors executing instructions to perform the functions described.

[0332] like Fig.23 As shown, method 2300 starts at step 2302. In step 2302, the UE receives a SS / PBCH block.

[0333] In step 2304, the UE determines a parameter set for the SS / PBCH block, where the parameter set includes an SCS and a CP length.

[0334] In step 2306, the UE determines an SS / PBCH block pattern based on the parameter set, the SS / PBCH block pattern including candidate SS / PBCH blocks mapped to time slots within the half-frame and a minimum gap between adjacent candidate SS / PBCH blocks. Wherein: based on determining whether the SCS included in the parameter set of the SS / PBCH block is 120kHz or 240kHz, symbols; or, based on determining whether the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz, symbol.

[0335] In one embodiment, the SS / PBCH block mode in step 2306 is determined by Given, and n∈Sindex ; S start is a set of starting symbol indices of candidate SS / PBCH blocks in multiple time slots (K); and S index is a set of indices of multiple time slots (K) within a half-frame, wherein: based on determining that the CP length included in the parameter set of the SS / PBCH block is a normal CP length, Alternatively, based on determining that the CP length included in the parameter set of the SS / PBCH block is an extended CP length,

[0336] In one embodiment, based on determining that the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz and the CP length included in the parameter set of the SS / PBCH block is a normal CP length, the SS / PBCH block mode in step 2306 is given by {2, 8}+14·n.

[0337] In one embodiment, based on determining that the SCS included in the parameter set of the SS / PBCH block is 480kHz or 960kHz and the CP length included in the parameter set of the SS / PBCH block is an extended CP length, the SS / PBCH block mode in step 2306 is given by {2, 8}+12·n.

[0338] In one embodiment, the UE determines the index set (S) in the SS / PBCH block pattern based on whether the SS / PBCH block can use the shared spectrum channel access operation. index ), where the index set (S index ) includes a first index set of SS / PBCH blocks that can be operated without using shared spectrum channel access and a second index set of SS / PBCH blocks that can be operated using shared spectrum channel access, and the first index set is a subset of the second index set.

[0339] In one embodiment, based on determining that the SCS included in the parameter set of the SS / PBCH block is 480 kHz, for the SS / PBCH block that may not use the shared spectrum channel access operation, the S index ={0, 1, .. . , 31}; or, for SS / PBCH blocks that can use shared spectrum channel access operations, S index ={0, 1, ..., 31}+40·m, where m=0, 1, 2, 3.

[0340] In one embodiment, based on determining that the SCS included in the parameter set of the SS / PBCH block is 960 kHz, for the SS / PBCH block that may not use the shared spectrum channel access operation, S index = {o, 1, ..., 31}; or, for SS / PBCH blocks that can use shared spectrum channel access operations, Sindex ={0,1,...,63}+80·m, where m=0,1.

[0341] The above flow charts illustrate example methods that can be implemented according to the principles of the present disclosure, and various changes can be made to the methods shown in the flow charts herein. For example, although shown as a series of steps, the individual steps in each figure can overlap, occur in parallel, occur in a different order, or occur multiple times. In another example, steps can be omitted or replaced with other steps.

[0342] Although the present disclosure has been described with exemplary embodiments, various changes and modifications are conceivable to those skilled in the art. The present disclosure is intended to include such changes and modifications that fall within the scope of the appended claims. Any description in this application should not be construed as implying that any particular element, step or function is an essential element that must be included in the scope of the claims. The scope of the patent subject matter is defined by the claims.

Claims

1. A terminal in a communication system, the terminal comprising: Transceiver; as well as The controller is configured as: Determine the subcarrier spacing (SCS) of the synchronization signal and physical broadcast channel (SS / PBCH) blocks, and Based on the SCS, determining an SS / PBCH block pattern associated with one or more candidate SS / PBCH blocks for the half-frame, Where SCS is 480kHz or 960kHz, and The first symbol of one or more candidate SS / PBCH blocks in the half-frame has an index {2, 9}+14·n, where n=0, 1, 2, 3, ..., 31 for a carrier frequency in the frequency range between 52600 MHz and 71000 MHz.

2. The terminal according to claim 1, in, The maximum number of candidate SS / PBCH blocks in a half-frame is 64.

3. The terminal according to claim 2, in, For operation not using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range including the frequency range between 52600 MHz and 71000 MHz.

4. The terminal according to claim 2, in, For operation using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range between 52600 MHz and 71000 MHz.

5. A base station in a communication system, the base station comprising: Transceiver; as well as The controller is configured as: Determine the subcarrier spacing (SCS) of the synchronization signal and physical broadcast channel (SS / PBCH) blocks, and Based on the SCS, determining an SS / PBCH block pattern associated with one or more candidate SS / PBCH blocks for the half-frame, Where SCS is 480kHz or 960kHz, and The first symbol of one or more candidate SS / PBCH blocks in the half-frame has an index {2, 9}+14·n, where n=0, 1, 2, 3, ..., 31 for a carrier frequency in the frequency range between 52600 MHz and 71000 MHz.

6. The base station according to claim 5, in, The maximum number of candidate SS / PBCH blocks in a half-frame is 64.

7. The base station according to claim 6, in, For operation not using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range including the frequency range between 52600 MHz and 71000 MHz.

8. The base station according to claim 6, in, For operation using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range between 52600 MHz and 71000 MHz.

9. A method performed by a terminal in a communication system, the method comprising: Determine the subcarrier spacing (SCS) of the synchronization signal and physical broadcast channel (SS / PBCH) blocks; as well as Based on the SCS, determining an SS / PBCH block pattern associated with one or more candidate SS / PBCH blocks for the half-frame, Where SCS is 480kHz or 960kHz, and The first symbol of one or more candidate SS / PBCH blocks in the half-frame has an index {2, 9}+14·n, where n=0, 1, 2, 3, ..., 31 for a carrier frequency in the frequency range between 52600 MHz and 71000 MHz.

10. The method according to claim 9, in, The maximum number of candidate SS / PBCH blocks in a half-frame is 64.

11. The method according to claim 10, in, For operation not using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range including the frequency range between 52600 MHz and 71000 MHz.

12. The method according to claim 10, in, For operation using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range between 52600 MHz and 71000 MHz.

13. A method performed by a base station in a communication system, the method comprising: Determine the subcarrier spacing (SCS) of the synchronization signal and physical broadcast channel (SS / PBCH) blocks; as well as Based on the SCS, determining an SS / PBCH block pattern associated with one or more candidate SS / PBCH blocks for the half-frame, Where SCS is 480kHz or 960kHz, and The first symbol of one or more candidate SS / PBCH blocks in the half-frame has an index {2, 9}+14·n, where n=0, 1, 2, 3, ..., 31 for a carrier frequency in the frequency range between 52600 MHz and 71000 MHz.

14. The method according to claim 13, in, The maximum number of candidate SS / PBCH blocks in a half-frame is 64.

15. The method according to claim 13, in, For operation not using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range including the frequency range between 52600 MHz and 71000 MHz, and For operation using shared spectrum channel access, the maximum number of SS / PBCH blocks transmitted in a half-frame is 64 in the frequency range between 52600 MHz and 71000 MHz.

Images