Image capturing element, ranging device and electronic device

Abstract

[Problem] To provide an imaging element, a distance measuring device, and an electronic device that can improve the resolution of a distance image while preventing the generation of electromagnetic noise. [Solution] An imaging element according to the present disclosure is provided with a signal generator configured to generate a clock signal; a plurality of flip-flops connected in cascade; a circuit block configured to supply a first signal to a single clock terminal in the plurality of flip-flops and a second signal to an input terminal of a first-stage flip-flop in the plurality of flip-flops in accordance with the clock signal; and a pixel array including pixels configured to be driven using pulse signals supplied from different stages in the plurality of flip-flops.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging element, a distance measuring device, and an electronic device. BACKGROUND

[0002] A distance measuring technology using an indirect time-of-flight (ToF) method is known. In such a distance measuring system, a sensor that detects reflected light obtained by an object reflecting light emitted from a light source at a predetermined phase and allocates charges of the light signal to different regions is used. If a sensor using an indirect ToF method is used, distance measurement can be performed based on a signal allocated to each charge accumulation region according to the phase of the incident light. In distance measurement by an indirect ToF method, a sensor in which a plurality of pixels are arranged in two dimensions is generally used. In recent years, the number of pixels mounted on the sensor has increased in order to obtain a distance image with higher resolution.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2018-117117 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In an indirect ToF method sensor, a drive signal is provided to each pixel to detect charges corresponding to incident light. In a case where the number of pixels to which the drive signal is provided increases, a drive signal with a larger current is required. In a case where the total current of the drive signal increases, electromagnetic noise generated when incident light is detected becomes large, and there is a concern that a requirement for electromagnetic compatibility (EMC) cannot be satisfied.

[0008] Therefore, the present disclosure provides an imaging element, a distance measuring device, and an electronic device capable of improving the resolution of a distance image while preventing the generation of electromagnetic noise.

[0009] SOLUTION TO THE PROBLEM

[0010] An imaging element according to an aspect of the present disclosure includes a signal generator configured to generate a clock signal; a plurality of flip-flops connected in cascade; a circuit block configured to provide a first signal to a clock terminal of each of the plurality of flip-flops and provide a second signal to an input terminal of a first stage flip-flop among the plurality of flip-flops according to the clock signal; and a pixel array including a pixel configured to be driven using a pulse signal provided from different stages among the plurality of flip-flops.

[0011] The pixel in the pixel array can include a signal taking-out unit configured to detect charges generated by photoelectric conversion if provided with the pulse signal.

[0012] The pixels in the pixel array can include a plurality of signal extraction units, and each signal extraction unit can be configured to detect charges generated at different time points.

[0013] The imaging device can further include a plurality of clock distribution circuits connected to the plurality of flip-flops of any stage at an input side and connected to the pixels in the pixel array via the driving lines at an output side.

[0014] The at least one clock distribution circuit can be in a clock tree manner.

[0015] The pixel columns or the pixel rows in the pixel array can be configured to be driven using the pulse signals provided from the plurality of flip-flops of the common stage.

[0016] The pulse signals can be configured to be provided from different stages of the plurality of flip-flops according to an area in which the pixels are arranged in the pixel array.

[0017] The imaging device can further include a multiplexer configured to select the pulse signals provided to the pixels in the pixel array.

[0018] The circuit block can be configured to output a first signal having a first frequency and output a second signal having a second frequency different from the first frequency.

[0019] The circuit block can be configured to output the first signal and the second signal synchronized with each other.

[0020] The circuit block can further include a frequency divider circuit that generates the first signal based on the clock signal.

[0021] The circuit block can be configured to output the first signal having a first frequency equal to a clock frequency of the clock signal.

[0022] The imaging device can further include a control unit configured to output a control signal to the circuit block, and the circuit block can be configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the provided control signal.

[0023] A distance measuring device according to an aspect of the disclosure can include a signal generator configured to generate a clock signal; a plurality of flip-flops connected in cascade; a circuit block configured to provide a first signal to a clock terminal of each of the plurality of flip-flops and provide a second signal to an input terminal of a first stage flip-flop among the plurality of flip-flops according to the clock signal; a pixel array including pixels configured to be driven using pulse signals provided from different stages among the plurality of flip-flops; and a signal processing unit configured to generate a distance image based on charges generated by photoelectric conversion in the pixels in the pixel array.

[0024] An electronic device according to an aspect of the present disclosure can include a signal generator configured to generate a clock signal; a plurality of flip-flops connected in cascade; a circuit block configured to provide a first signal to a clock terminal of each of the plurality of flip-flops and to provide a second signal to an input terminal of a first stage flip-flop among the plurality of flip-flops according to the clock signal; and a pixel array including a pixel configured to be driven using a pulse signal provided from different stages among the plurality of flip-flops. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a block diagram illustrating an example of an imaging device according to the present disclosure.

[0026] Figure 2 is a block diagram illustrating an example of an imaging device driving pixels in a vertical direction.

[0027] Figure 3 is a diagram illustrating an example of a configuration of a pixel in an imaging device.

[0028] Figure 4 is a diagram illustrating an example of a signal taking-out unit in a pixel.

[0029] Figure 5 is a diagram illustrating an example of an equivalent circuit of a pixel.

[0030] Figure 6 is a diagram illustrating an example of another equivalent circuit of a pixel.

[0031] Figure 7 is a diagram illustrating an example of a configuration of a distance measuring device.

[0032] Figure 8 is a diagram illustrating an example of a case where all pixels in an imaging device are simultaneously driven.

[0033] Figure 9 is a diagram illustrating an example of a pulse generator according to the present disclosure.

[0034] Figure 10 is a diagram illustrating an example of a case where pixels are driven for each column in an imaging device;

[0035] Figure 11 is a diagram illustrating an example of a case where pixels in an imaging device are driven per row.

[0036] Figure 12 is a diagram illustrating an example of a case where pixels in an imaging device are driven for each region.

[0037] Figure 13 is a diagram illustrating an example of a pulse generator according to Modification 1.

[0038] Figure 14is a diagram showing an example of a pulse generator according to Modification 2.

[0039] Figure 15 is a diagram showing an example of a configuration of an imaging element according to Modification 2.

[0040] Figure 16 is a diagram showing an example of an electronic device according to the present disclosure.

[0041] Figure 17 is a diagram showing an example of an electronic device according to the present disclosure.

[0042] Figure 18 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0043] Figure 19 is an explanatory diagram showing an example of mounting positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION

[0044] A preferred embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that in this specification and the accompanying drawings, constituent elements having substantially the same function are denoted with the same reference numeral, and repeated description thereof will be omitted.

[0045] The present disclosure is used to prevent generation of electromagnetic noise in an imaging element mounted in a distance measuring system (distance measuring device) that performs distance measurement by an indirect time-of-flight (ToF) method. The imaging element can be mounted in various electronic devices.

[0046] As an example of the distance measuring system, there is a vehicle-mounted system mounted in a vehicle and measuring a distance to an object outside the vehicle. Furthermore, the distance measuring system can be applied to a gesture recognition system that measures a distance to an object such as a user's hand and recognizes a user gesture on the basis of the measurement result, and the like. For example, an operation of a car navigation system can be performed using a result of the gesture recognition. Here, the result of the gesture recognition can be used for other purposes.

[0047] Figure 1 The block diagram of FIG. 1 shows an example of an imaging element (light receiving element) according to the present disclosure.

[0048] For example, Figure 1 The imaging element 11 in FIG. 1 is a back-illuminated sensor, and is mounted in an imaging device having a distance measuring function. Here, the imaging element 11 can be a front-illuminated sensor.

[0049] The imaging element 11 includes, for example, a pixel array unit 21 formed on a semiconductor substrate (not shown) and a peripheral circuit unit integrated on the semiconductor substrate as with the pixel array unit 21. The peripheral circuit unit includes, for example, a pixel driving unit 22, a column processing unit 23, a lead driving unit 24, and a system control unit 25.

[0050] The imaging element 11 can also include a signal processing unit 26 and a data storage unit 27. The signal processing unit 26 and the data storage unit 27 can be provided on the same substrate as the imaging element 11 or on a different substrate from the imaging element 11.

[0051] In the pixel array unit 21, for example, unit pixels are arranged in an array form. The unit pixel (hereinafter, also referred to as “pixel”) generates a charge corresponding to the amount of received light and outputs a signal according to the charge. For example, the pixels are arranged in both a row direction and a column direction of the pixel array. Here, the pixels can be formed in any two-dimensional array in the pixel array unit 21. That is, the pixel array unit 21 includes a plurality of pixels that photoelectrically convert incident light and output a signal according to a charge obtained by the photoelectric conversion.

[0052] Here, the row direction refers to the direction in which the pixels are arranged in a pixel row (i.e., in the horizontal direction). In addition, the column direction refers to the direction in which the pixels are arranged in a pixel column (i.e., in the vertical direction). The row direction corresponds to the horizontal direction in the drawing, and the column direction corresponds to the vertical direction in the drawing.

[0053] In the pixel array unit 21, a pixel drive line 28 is wired with respect to each pixel row in the row direction for the pixel array in a matrix form. In addition, two vertical signal lines 29 are wired in the column direction in each pixel column. For example, the pixel drive line 28 transmits a drive signal for performing driving when a signal is read from the pixel. Although the pixel drive line 28 is illustrated as one signal line in Figure 1 The number of signal lines is not limited to one. One end of the pixel drive line 28 is connected to an output terminal of the pixel drive unit 22 corresponding to each row.

[0054] The pixel drive unit 22 is a circuit that drives some of the pixels in the pixel array unit 21 in a predetermined order. The combination of pixels driven by the pixel drive unit 22 at each time and the order in which each pixel combination is driven are referred to as a “pixel drive mode”. The pixel drive unit 22 according to the present disclosure prevents electromagnetic noise from being generated by reducing the number of pixels simultaneously driven in the pixel array unit 21. The pixel drive unit 22 includes, for example, a shift register or an address decoder. The pixel drive unit 22 forms a drive unit that controls the operation of each pixel in the pixel array unit 21 together with a system control unit 25 that controls the pixel drive unit 22. Details of the pixel drive unit according to the present disclosure will be described later.

[0055] In an imaging element for distance measurement by indirect ToF method, the accuracy of the driving timing depends on the number of elements connected to the same control line. In a pixel array of an imaging element for distance measurement by indirect ToF method, the driving timing can be delayed due to an increase in the length of the control line in the horizontal direction. Therefore, not only the control line but also, for example, other signal lines such as the vertical signal line 29 can be used to drive the pixels. In this case, the driving signal can be output to each vertical signal line 29 from a driving unit (for example, a lead driving unit) provided separately from the pixel driving unit 22.

[0056] According to the driving control using the pixel driving unit 22, the signal output from each pixel of the pixel row is input to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the signal output from each pixel via the vertical signal line 29 and temporarily holds the pixel signal that has undergone the signal processing. The column processing unit 23 can perform at least one of a noise removal process and an analog-digital (AD) conversion process as the signal processing. Although an example of the noise removal process includes a correlated double sampling (CDS), other types of processing can be performed.

[0057] For example, the lead driving unit 24 includes a shift register, an address decoder, and the like, and sequentially selects the unit circuit corresponding to the pixel column of the column processing unit 23. By using the selective scanning of the lead driving unit 24, the pixel signal that has undergone the signal processing of each unit circuit in the column processing unit 23 is output in sequence.

[0058] The system control unit 25, for example, includes a timing generator that generates various timing signals. The system control unit 25 performs the driving control of the pixel driving unit 22, the column processing unit 23, the lead driving unit 24, and the like, based on the various timing signals generated by the timing generator.

[0059] The signal processing unit 26 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing based on the pixel signal output from the column processing unit 23. The data storage unit 27 temporarily stores data required for the signal processing in the signal processing unit 26 at the time of processing.

[0060] Figure 2 The block diagram shows an example of the imaging element according to the modification example 1. As in the example of the imaging element 1, Figure 2 In this case, as in the example of the imaging element 1, Figure 2As shown, in each pixel column, two vertical signal lines 29 can be wired in the column direction. Further, as will be described later, the pixel drive unit 22 can output a drive signal to a first pixel drive line wired in the vertical direction and a second pixel drive line wired in the horizontal direction, and drive a pixel among the pixels in the pixel array unit 21. As described above, the direction and combination of the signal lines (pixel drive lines) for driving the pixels in the pixel array unit 21 are not limited.

[0061] <Example of configuration of pixel>

[0062] An example of the configuration of a pixel provided in the pixel array unit 21 will be described below. Figure 3 An example of a pixel provided in the pixel array unit 21 is shown.

[0063] Figure 3 A cross section of one pixel 51 provided in the pixel array unit 21 is shown. The pixel 51 receives light incident from the outside, photoelectrically converts the light, and outputs a signal according to the charge obtained as a result. The pixel 51 can receive, for example, infrared light. Here, the wavelength of the electromagnetic wave received by the pixel 51 is not limited.

[0064] The pixel 51 includes, for example, a substrate 61 (semiconductor layer) and an on-chip lens 62 formed on the substrate 61. As the substrate 61, for example, a silicon substrate including a P-type semiconductor region can be used.

[0065] For example, the thickness of the substrate 61 in the z-axis direction (thickness in the direction perpendicular to the surface of the substrate 61) is set to 20 μm or less. Here, the thickness of the substrate 61 can be 20 μm or more. The thickness of the substrate 61 can be determined in accordance with the design and use of the imaging element 11.

[0066] As the substrate 61, for example, a high-resistance P-Epi substrate having a substrate concentration of about 1E+13 or less can be used. In this case, the resistance (resistivity) of the substrate 61 is, for example, 500 [Ωcm] or more.

[0067] The resistance value of the substrate 61 depends on the substrate concentration. For example, when the substrate concentration is 6.48E+12 [cm 3 ], the resistance is 2000 [Ωcm]. Further, when the substrate concentration is 1.30E+13 [cm 3 ], the resistance is 1000 [Ωcm]. When the substrate concentration is 2.59E+13 [cm 3 ], the resistance is 500 [Ωcm]. Further, when the substrate concentration is 1.30E+14 [cm 3 ], the resistance is 100 [Ωcm].

[0068] On the surface of the z-axis positive direction side of the substrate 61, that is, on the surface of the side on which light is incident on the substrate 61 from the outside (hereinafter, also referred to as an "incident surface"), an on-chip lens 62 that converges light incident from the outside and causes the light to be incident on the substrate 61 is formed.

[0069] Further, in the pixel 51, an inter-pixel light-shielding unit 63-1 and an inter-pixel light-shielding unit 63-2 for preventing color mixing between adjacent pixels are formed at the end portion of the pixel 51 on the incident surface of the substrate 61.

[0070] In this example, light from the outside is incident on the substrate 61 via the on-chip lens 62. Preferably, the light incident from the outside passes through the on-chip lens 62 and a portion of the substrate 61, and is not incident on the region of another pixel disposed adjacent to the pixel 51 in the substrate 61. In Figure 3 In the example, light incident from the outside on the on-chip lens 62 and guided into another pixel adjacent to the pixel 51 is light-shielded by the inter-pixel light-shielding unit 63-1 and the inter-pixel light-shielding unit 63-2, and is prevented from being incident on another adjacent pixel. In a case where the inter-pixel light-shielding unit 63-1 and the inter-pixel light-shielding unit 63-2 do not need to be particularly distinguished, they are also simply referred to as "inter-pixel light-shielding units 63".

[0071] Since the imaging element 11 is a back-illuminated sensor, the incident surface of the substrate 61 is the so-called back surface of the substrate 61. A wiring layer including a wiring and the like is not formed on the back surface side of the substrate 61. Further, a wiring layer in which a wiring for driving a transistor and the like formed in the pixel 51 in a stacked structure, a wiring for reading a signal from the pixel 51, and the like are formed is formed in a portion of the surface on the side opposite to the incident surface of the substrate 61.

[0072] On the surface side of the substrate 61 opposite to the incident surface, that is, on a portion inside the surface on the z-axis negative direction side, an oxide film 64, and a signal extraction unit 65-1 and a signal extraction unit 65-2 called taps are formed.

[0073] In this example, the oxide film 64 is formed in a central portion of the pixel 51 near the surface opposite to the incident surface of the substrate 61, and the signal extraction unit 65-1 and the signal extraction unit 65-2 are formed at both ends of the oxide film 64, respectively.

[0074] Here, the signal taking-out unit 65-1 includes an N+ semiconductor region 71-1, an N- semiconductor region 72-1, a P+ semiconductor region 73-1, and a P- semiconductor region 74-1. The N+ semiconductor region 71-1 is an N-type semiconductor region. The N- semiconductor region 72-1 is an N-type semiconductor region having a donor impurity concentration lower than that of the N+ semiconductor region 71-1. The P+ semiconductor region 73-1 is a P-type semiconductor region. The P- semiconductor region 74-1 is a P-type semiconductor region having an acceptor impurity concentration lower than that of the P+ semiconductor region 73-1. For example, in the case of using a silicon (Si) substrate, an element belonging to Group 5 of the periodic table, such as phosphorus (P) or arsenic (As), can be used as a donor impurity. In this case, for example, an element belonging to Group 3 of the periodic table, such as boron (B), can be used as an acceptor impurity. An element as a donor impurity is also referred to as a "donor element", and an element as an acceptor impurity is also referred to as an "acceptor element".

[0075] The N+ semiconductor region 71-1 is formed at a position of the x-axis positive direction side of the oxide film 64 near the surface of the substrate 61 opposite to the incident surface. Further, the N- semiconductor region 72-1 is formed on the z-axis positive direction side of the N+ semiconductor region 71-1 so as to cover (surround) the N+ semiconductor region 71-1.

[0076] Further, the P+ semiconductor region 73-1 is formed at a position adjacent to the N+ semiconductor region 71-1 on the x-axis positive direction side of the surface of the substrate 61 opposite to the incident surface. Further, the P- semiconductor region 74-1 is formed on the z-axis positive direction side of the P+ semiconductor region 73-1 so as to cover (surround) the P+ semiconductor region 73-1.

[0077] Note that, when the substrate 61 is viewed from a direction perpendicular to the surface of the substrate 61, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 can be formed so as to surround the outer periphery of the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center.

[0078] Similarly, the signal taking-out unit 65-2 includes an N+ semiconductor region 71-2, an N- semiconductor region 72-2, a P+ semiconductor region 73-2, and a P- semiconductor region 74-2. The N+ semiconductor region 71-2 is an N-type semiconductor region. The N- semiconductor region 72-2 is an N-type semiconductor region having a donor impurity concentration lower than that of the N+ semiconductor region 71-2. The P+ semiconductor region 73-2 is a P-type semiconductor region. The P- semiconductor region 74-2 is a P-type semiconductor region having an acceptor impurity concentration lower than that of the P+ semiconductor region 73-2.

[0079] The N+ semiconductor region 71-2 is formed at a position on the x-axis negative direction side adjacent to the oxide film 64 near the surface of the substrate 61 opposite to the incident surface. Further, the N- semiconductor region 72-2 is formed on the z-axis positive direction side of the N+ semiconductor region 71-2 so as to cover (surround) the N+ semiconductor region 71-2.

[0080] Further, the P+ semiconductor region 73-2 is formed at a position on the x-axis negative direction side adjacent to the N+ semiconductor region 71-2 near the surface of the substrate 61 opposite to the incident surface. Further, the P- semiconductor region 74-2 is formed on the z-axis positive direction side of the P+ semiconductor region 73-2 so as to cover (surround) the P+ semiconductor region 73-2.

[0081] Note that, when the substrate 61 is viewed from a direction perpendicular to the surface of the substrate 61, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 can be formed so as to surround the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 with the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 as the center.

[0082] Hereinafter, in a case where it is not necessary to particularly distinguish the signal extraction unit 65-1 and the signal extraction unit 65-2, they are also simply referred to as "signal extraction unit 65".

[0083] Further, hereinafter, in a case where it is not necessary to particularly distinguish the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, they are also simply referred to as "N+ semiconductor region 71". Further, in a case where it is not necessary to particularly distinguish the N- semiconductor region 72-1 and the N- semiconductor region 72-2, they are also simply referred to as "N- semiconductor region 72".

[0084] Further, hereinafter, in a case where it is not necessary to particularly distinguish the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, they are simply referred to as "P+ semiconductor region 73". Further, in a case where it is not necessary to particularly distinguish the P- semiconductor region 74-1 and the P- semiconductor region 74-2, they are also simply referred to as "P- semiconductor region 74".

[0085] Further, a separation portion 75-1 for separating the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 in the substrate 61 is formed between these regions using an oxide film or the like. Similarly, a separation portion 75-2 for isolating the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 is also formed between these regions using an oxide film or the like. Hereinafter, in a case where it is not necessary to particularly distinguish the separation portion 75-1 and the separation portion 75-2, they are simply referred to as "separation portion 75".

[0086] The N+ semiconductor region 71 provided in the substrate 61 functions as a charge detection unit for detecting the amount of light (the amount of signal carriers generated by photoelectric conversion using the substrate 61) incident on the pixel 51 from the outside. Note that not only the N+ semiconductor region 71 but also an N- semiconductor region 72 having a low donor impurity concentration can function as a charge detection unit. Further, the P+ semiconductor region 73 functions as a voltage application unit for applying a voltage directly to the substrate 61 to generate an electric field in the substrate 61. At this time, a majority carrier current can be injected into the substrate 61. Note that in addition to the P+ semiconductor region 73, a P- semiconductor region 74 having a low acceptor impurity concentration can function as a voltage application unit.

[0087] In the pixel 51, a floating diffusion (FD) portion (hereinafter also particularly referred to as "FD portion A") as a floating diffusion region (not shown) is directly connected to the N+ semiconductor region 71-1, and the FD portion A is further connected to the vertical signal line 29 via an amplification transistor or the like (not shown).

[0088] Similarly, another FD portion (hereinafter also particularly referred to as "FD portion B") different from the FD portion A is directly connected to the N+ semiconductor region 71-2, and the FD portion B is further connected to the vertical signal line 29 via an amplification transistor or the like (not shown). Here, the FD portion A and the FD portion B are connected to different vertical signal lines 29.

[0089] For example, in a case where the distance to an object is measured by an indirect ToF method, the object is irradiated with infrared light from an imaging device including the imaging element 11. In addition, in a case where the infrared light is reflected by the object and returns to the imaging element as reflected light, the substrate 61 of the imaging element 11 receives the incident reflected light (infrared light) and performs photoelectric conversion.

[0090] At this time, the pixel driving unit 22 drives the pixel 51. As a result, a signal according to the charge obtained by photoelectric conversion can be distributed to the FD portion A and the FD portion B. Note that as described above, the pixel 51 can not be driven by the pixel driving unit 22, but by a driving unit separately provided via the vertical signal line 29 or another control line wired in the vertical direction, the lead driving unit 24, or the like.

[0091] For example, at a certain time, the pixel driving unit 22 applies a voltage to the two P+ semiconductor regions 73 via contact or the like. For example, the pixel driving unit 22 applies a high (e.g., 1.5 V) voltage to the P+ semiconductor region 73-1, and applies a low (e.g., 0 V) voltage to the P+ semiconductor region 73-2.

[0092] Accordingly, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and a current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move in the direction of the P+ semiconductor region 73-2 and electrons move in the direction of the P+ semiconductor region 73-1.

[0093] Infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62, and the infrared light is photoelectrically converted in the substrate 61 to be converted into a pair of electrons and holes. The electrons obtained in the above state are guided in the direction of the P+ semiconductor region 73-1 due to the electric field between the P+ semiconductor regions 73, and move into the N+ semiconductor region 71-1.

[0094] In this case, the electrons generated by the photoelectric conversion serve as signal carriers (charges) for detecting a signal according to the amount of infrared light (amount of received infrared light) incident on the pixel 51.

[0095] As a result, according to the electrons that move into the N+ semiconductor region 71-1, charges are accumulated in the N+ semiconductor region 71-1. The accumulated charges are detected using the column processing unit 23 via the FD section A, the amplification transistor, the vertical signal line 29, and the like.

[0096] The charges accumulated in the N+ semiconductor region 71-1 are transferred to the FD section A directly connected to the N+ semiconductor region 71-1. Further, a signal according to the charges transferred to the FD section A is read using the column processing unit 23 via the amplification transistor and the vertical signal line 29. Further, the column processing unit 23 performs processing (for example, AD conversion processing) on the read signal, and provides the generated pixel signal as a result to the signal processing unit 26.

[0097] This pixel signal is a signal indicating the amount of charges according to the electrons detected using the N+ semiconductor region 71-1 (the amount of charges accumulated in the FD section A). That is, it can also be said that the pixel signal is a signal indicating the amount of infrared light received using the pixel 51.

[0098] Note that, as with the case of the N+ semiconductor region 71-1, a pixel signal according to the electrons detected in the N+ semiconductor region 71-2 can be used for distance measurement.

[0099] Further, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 using the pixel driving unit 22 by contact or the like, to generate an electric field in a direction opposite to the direction of the electric field generated so far in the substrate 61. Specifically, for example, a high (for example, 1.5 V) voltage is applied to the P+ semiconductor region 73-2, and a low (for example, 0 V) voltage is applied to the P+ semiconductor region 73-1.

[0100] Accordingly, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and a current flows from the P+ semiconductor region 73-2 to the P+ semiconductor region 73-1.

[0101] Infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62, and the infrared light is photoelectrically converted in the substrate 61 to generate a pair of an electron and a hole. In the above state, the generated electron is guided in the direction of the P+ semiconductor region 73-2 due to the electric field between the P+ semiconductor regions 73, and moves into the N+ semiconductor region 71-2.

[0102] As a result, a charge corresponding to the electron that moves into the N+ semiconductor region 71-2 is accumulated in the N+ semiconductor region 71-2. The accumulated charge is detected using the column processing unit 23 via the FD section B, the amplification transistor, the vertical signal line 29, and the like.

[0103] The charge accumulated in the N+ semiconductor region 71-2 is transferred to the FD section B directly connected to the N+ semiconductor region 71-2. Further, a signal according to the charge transferred to the FD section B is read using the column processing unit 23 via the amplification transistor and the vertical signal line 29. Further, the column processing unit 23 performs processing (for example, AD conversion processing) on the read signal, and provides the generated pixel signal as a result to the signal processing unit 26.

[0104] Note that, as in the case of the N+ semiconductor region 71-2, ranging can be performed using a pixel signal according to the electron detected in the N+ semiconductor region 71-1.

[0105] In this way, if pixel signals obtained by photoelectric conversion in different cycles are obtained in the same pixel 51, the signal processing unit 26 calculates distance information representing a distance to an object based on these pixel signals and outputs the distance information to a circuit of a subsequent stage. For example, the distance information can be a distance image including a distance value for each pixel.

[0106] As described above, a technique of allocating signal carriers to N+ semiconductor regions 71 different from each other and calculating distance information based on signals corresponding to the signal carriers is referred to as an "indirect ToF method".

[0107] Note that, here, an example of controlling the voltage applied to the P+ semiconductor region 73 using the pixel driving unit 22 has been described. Here, as described above, the driving unit (block) serving as the voltage application control unit that controls the voltage applied to the P+ semiconductor region 73 can be provided in the imaging element 11 separately from the pixel driving unit 22.

[0108] When the distance to the object is measured from Figure 2When observing the signal extraction unit 65 in pixel 51 along the positive Z-axis direction (perpendicular to the surface of substrate 61), for example, a method such as... Figure 3 The structure shown depicts a P+ semiconductor region 73 surrounded by an N+ semiconductor region 71. It should be noted that... Figure 3 In, corresponding to Figure 2 The constituent elements in the above are indicated by the same reference numerals and their descriptions will be omitted as appropriate.

[0109] exist Figure 4 In the example, oxide film 64 (not shown) is formed in the central portion of pixel 51. Furthermore, signal extraction unit 65 is formed in a portion offset from the center of pixel 51. Figure 3 Two signal extraction units 65 are formed in pixel 51.

[0110] Furthermore, in each signal extraction unit 65, the P+ semiconductor region 73 is formed into a rectangular shape at its center. Additionally, the periphery of the P+ semiconductor region 73 is surrounded by an N+ semiconductor region 71 with a rectangular frame shape. That is, the N+ semiconductor region 71 is formed as the periphery surrounding the P+ semiconductor region 73.

[0111] Furthermore, in pixel 51, the on-chip lens 62 is configured such that infrared light incident from the outside is concentrated in the central portion of pixel 51 (i.e., the portion indicated by arrow A11). In other words, infrared light incident from the outside onto the on-chip lens 62 is concentrated by the on-chip lens 62 at the position indicated by arrow A11, i.e. Figure 2 The position of the oxide film 64 on the positive z-axis side.

[0112] Therefore, the infrared light is focused at the position between signal extraction unit 65-1 and signal extraction unit 65-2. This prevents the infrared light from incident on pixels adjacent to pixel 51 and causing color mixing, and also prevents the infrared light from directly incident on signal extraction unit 65.

[0113] For example, if infrared light is directly incident on the signal extraction unit 65, the charge separation efficiency, the contrast between effective and ineffective taps (Cmod), and the modulation contrast will decrease.

[0114] The signal extraction unit 65 (tap) that reads the signal corresponding to the charge (electron) obtained through photoelectric conversion is called the "effective tap".

[0115] The signal extraction unit 65 (tap) that does not read the signal based on the charge obtained through photoelectric conversion, that is, the signal extraction unit 65 that is not a valid tap, is called an "invalid tap".

[0116] In the above example, the signal extraction unit 65 to which a high (e.g., 1.5 V) voltage is applied to the P+ semiconductor region 73 is an effective tap. In addition, the signal extraction unit 65 to which a low (e.g., 0 V) voltage is applied to the P+ semiconductor region 73 is an ineffective tap.

[0117] Cmod is an index indicating a percentage of charges (i.e., whether a signal according to the charges can be extracted) of charges that can be detected in the N+ semiconductor region 71 of the signal extraction unit 65 that is an effective tap, which are generated by photoelectric conversion of incident infrared light, and represents a charge separation efficiency.

[0118] Therefore, for example, when infrared light incident from the outside is incident on the region of the ineffective tap and is subjected to photoelectric conversion in the ineffective tap, electrons that are signal carriers generated by the photoelectric conversion are likely to move to the N+ semiconductor region 71 in the ineffective tap. Therefore, the charges of some of the electrons obtained by the photoelectric conversion are not detected in the N+ semiconductor region 71 in the effective tap, and Cmod (charge separation efficiency) decreases.

[0119] Therefore, in the pixel 51, infrared light is concentrated near the center portion of the pixel 51 at positions that are substantially equidistant from the two signal extraction units 65, so that it is possible to reduce the probability that infrared light incident from the outside is subjected to photoelectric conversion in the region of the ineffective tap, and it is possible to improve the charge separation efficiency. Furthermore, in the pixel 51, it is also possible to improve the modulation contrast. That is, the electrons obtained by the photoelectric conversion are easily guided to the N+ semiconductor region 71 in the effective tap.

[0120] <Example of configuration of equivalent circuit of pixel>

[0121] An example of the circuit configuration in the pixel will be described below. Figure 5 An equivalent circuit of the pixel 51 is shown.

[0122] The pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplification transistor 724A, and a selection transistor 725A corresponding to the signal extraction unit 65-1 including the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1.

[0123] Furthermore, the pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplification transistor 724B, and a selection transistor 725B corresponding to the signal extraction unit 65-2 including the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2.

[0124] The pixel driving unit 22 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of MIX0 and MIX1 is high (e.g., 1.5 V) and the other is low (e.g., 0 V). The P+ semiconductor regions 73-1 and 73-2 correspond to the voltage application units to which the first voltage or the second voltage is applied.

[0125] The N+ semiconductor regions 71-1 and 71-2 correspond to charge detection units that detect and accumulate charges generated by photoelectric conversion of light incident on the substrate 61.

[0126] If the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721A becomes conductive accordingly. As a result, the charges accumulated in the N+ semiconductor region 71-1 are transferred to the FD 722A. If the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721B becomes conductive accordingly. As a result, the charges accumulated in the N+ semiconductor region 71-2 are transferred to the FD 722B.

[0127] The FD 722A temporarily holds the charges supplied from the N+ semiconductor region 71-1. On the other hand, the FD 722B temporarily holds the charges supplied from the N+ semiconductor region 71-2. The FD 722A corresponds to the FD part A described in the description of Figure 2 On the other hand, the FD 722B corresponds to the FD part B.

[0128] If the drive signal RST supplied to the gate electrode becomes active, the reset transistor 723A becomes conductive accordingly. As a result, the potential of the FD 722A is reset to a predetermined level (reset voltage VDD). If the drive signal RST supplied to the gate electrode becomes active, the reset transistor 723B becomes conductive accordingly. As a result, the potential of the FD 722B is reset to a predetermined level (reset voltage VDD). Note that the transfer transistors 721A and 721B can be active when the reset transistors 723A and 723B are active.

[0129] The source electrode of the amplification transistor 724A is connected to the vertical signal line 29A via the selection transistor 725A. As a result, a load MOS and a source follower circuit of the constant current source circuit unit 726A connected to one end of the vertical signal line 29A are formed. The source electrode of the amplification transistor 724B is connected to the vertical signal line 29B via the selection transistor 725B. As a result, a load MOS and a source follower circuit of the constant current source circuit unit 726B connected to one end of the vertical signal line 29B are formed.

[0130] The selection transistor 725A is connected between the source electrode of the amplification transistor 724A and the vertical signal line 29A. If the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725A becomes conductive accordingly. Thus, the pixel signal output from the amplification transistor 724A is output to the vertical signal line 29A.

[0131] The selection transistor 725B is connected between the source electrode of the amplification transistor 724B and the vertical signal line 29B. If the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725B becomes conductive accordingly. Thus, the pixel signal output from the amplification transistor 724B is output to the vertical signal line 29B.

[0132] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled using, for example, the pixel drive unit 22.

[0133] Figure 6 Another equivalent circuit of the pixel 51 is shown.

[0134] In Figure 6 corresponding to the constituent elements in Figure 5 are denoted by the same reference numerals. The constituent elements denoted by the same reference numerals will not be described.

[0135] Figure 6 The equivalent circuit of the pixel 51 of Figure 5 The equivalent circuit of the pixel 51 of

[0136] Specifically, the additional capacitor 727A is connected between the transfer transistor 721A and the FD 722A via the switching transistor 728A. Further, the additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B via the switching transistor 728B.

[0137] If the drive signal FDG supplied to the gate electrode becomes active, the switching transistor 728A becomes conductive accordingly. As a result, the additional capacitor 727A is connected to the FD 722A. If the drive signal FDG supplied to the gate electrode becomes active, the switching transistor 728B becomes conductive accordingly. As a result, the additional capacitor 727B is connected to the FD 722B.

[0138] For example, at high illuminance with a large amount of incident light, the pixel driving unit 22 causes the switching transistors 728A and 728B to activate and causes the FD 722A to be connected with the additional capacitor 727A. In addition, the pixel driving unit 22 causes the FD 722B to be connected with the additional capacitor 727B. This makes it possible to accumulate more electric charges at high illuminance.

[0139] On the other hand, at low illuminance with a small amount of incident light, the pixel driving unit 22 causes the switching transistors 728A and 728B to be inactive. As a result, the additional capacitors 727A and 727B are respectively cut off from the FDs 722A and 722B.

[0140] As in the example of FIG. 8, Figure 6 by installing the additional capacitors 727 and appropriately using the additional capacitors according to the amount of incident light, a high dynamic range can be ensured. Here, as in the equivalent circuit in Figure 5 of FIG. 8, a configuration that omits the additional capacitors 727 can be used.

[0141] (Example of configuration of distance measurement module)

[0142] Figure 7 is a block diagram showing an example of a configuration of a distance measurement module that outputs distance measurement information using the imaging element 11 in Figure 1 of FIG. 8.

[0143] The distance measurement module 1000 includes a light emitting unit 1011, a light emitting control unit 1012, and a light receiving unit 1013.

[0144] The light emitting unit 1011 has a light source that emits light of a predetermined wavelength and emits irradiation light whose luminance periodically changes to irradiate an object. For example, the light emitting unit 1011 includes a light emitting diode that emits infrared light having a wavelength in the range of 780 nm to 1000 nm as a light source. The light emitting unit 1011, for example, generates irradiation light in synchronization with a rectangular wave light emitting control signal CLKp provided from the light emitting control unit 1012.

[0145] Note that, for example, a periodic signal can be used as the light emitting control signal CLKp. The periodic signal is not limited to a rectangular wave. For example, the light emitting control signal CLKp can be a sine wave.

[0146] The light emitting control unit 1012 provides the light emitting control signal CLKp to the light emitting unit 1011 and the light receiving unit 1013 to control the timing of irradiation of the irradiation light. The frequency of the light emitting control signal CLKp is, for example, 20 megahertz (MHz). Note that the frequency of the light emitting control signal CLKp is not limited to 20 megahertz (MHz) and can be set to other values such as 5 megahertz (MHz).

[0147] The light-receiving unit 1013 receives reflected light reflected from an object and calculates distance information for each pixel from the light-receiving result. Further, a distance image in which the distance to the object is represented by a gray value is generated for each pixel and the distance image is output.

[0148] As the light-receiving unit 1013, for example, the above-described imaging element 11 can be used. In a case where the imaging element 11 is used as the light-receiving unit 1013, distance information can be calculated for each pixel on the basis of the signal intensity detected by the charge detection unit (N+ semiconductor region 71) of each of the signal taking-out units 65-1 and 65-2 of each pixel 51 of the pixel array unit 21 on the basis of the light emission control signal CLKp.

[0149] As described above, Figure 1 The imaging element 11 in the above-described

[0150] Further, although an example in which an electron is used as a signal carrier has been described above, a hole generated by photoelectric conversion can be used as a signal carrier. In this case, a charge detection unit for detecting a signal carrier is formed using a P+ semiconductor region. Further, a voltage application unit for generating an electric field in a substrate is formed by an N+ semiconductor region. Further, a hole as a signal carrier can be detected in a charge detection unit provided in a signal taking-out unit.

[0151] (Example of Configuration of Imaging Element)

[0152] Figure 8 An example in which all the pixels in the imaging element are simultaneously driven is shown. Figure 8 A portion including the pixel drive unit 22A, the pixel array unit 21, and the column processing unit 23 in the above-described Figure 2 A portion including the pixel drive unit 22A, the pixel array unit 21, and the column processing unit 23 in the above-described Figure 8 The pixel drive unit 22A in the above-described includes a phase-locked loop (PLL) 31, a pulse generator 30, and a clock distribution circuit 37. Further, the column processing unit 23 includes an analog-digital converter 240.

[0153] The PLL 31 is an example of a signal generator that generates a clock signal. A case where the PLL is used as the signal generator will be described below as an example. Here, it is not obstructive to use a circuit other than the PLL as the signal generator. The pulse generator 30 is connected to a subsequent stage of the PLL 31. Further, the clock distribution circuit 37 is connected to a subsequent stage of the pulse generator 30. Figure 8The clock distribution circuit 37 in the clock array 21 distributes signals using a clock tree method. Here, a grid-based (collective drive) clock distribution circuit can be used, and the type of clock distribution circuit is not limited. The clock distribution circuit 37 has multiple output terminals. Each output terminal of the clock distribution circuit 37 is connected to a pixel column in the pixel array unit 21 via a pixel drive line 28A. Furthermore, each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via a vertical signal line 29.

[0154] A clock signal with frequency f0 output from PLL 31 is provided to pulse generator 30. Pulse generator 30 generates pulses at a predetermined period based on the clock signal with frequency f0. The pulses generated by pulse generator 30 are provided to each pixel column in pixel array unit 21 at substantially the same time via clock distribution circuit 37.

[0155] Therefore, in Figure 8 In the imaging element, all pixels in the pixel array unit 21 are driven in one phase (phase = 0 degrees). Figure 8 In the imaging element, as the number of pixels in the pixel array unit 21 increases, the total value of the driving current output from the pulse generator 30 in the pixel driving unit 22A increases. Because the change in current value becomes larger, there is concern that the electromagnetic noise generated during incident light detection will increase. Therefore, as will be described later, a pulse generator capable of generating pulses with multiple phases can be installed in the pixel driving unit 22 or the pixel driving unit 22A.

[0156] Figure 9 An example of a pulse generator according to the present invention is shown. Figure 9 The pulse generator 30A includes multiple output terminals (output terminals C1 to C4). Output terminals C1 to C4 are connected to pixel drive line 28 or pixel drive line 28A via, for example, a signal distribution circuit described later. As described later, the pulse generator 30A can output pulses from the respective signal lines with different phases. The pulse generator 30A includes circuit block 33 and flip-flops 340 to 343. Flip-flops 340 to 343 are, for example, D flip-flops including D terminals, Q terminals, and CLK terminals. The type of flip-flop used is not limited here.

[0157] Each D flip-flop includes (1) a type that latches a signal input to a D terminal at a rising edge of a signal input to a CLK terminal and (2) a type that latches a signal input to a D terminal at a falling edge of a signal input to a CLK terminal. As the flip-flops 340 to 343, either the type (1) or the type (2) can be used. Further, the flip-flop of the type (1) and the flip-flop of the type (2) can be mixed in the flip-flops 340 to 343. By mixing the different types of flip-flops, it is possible to shift the timing at which a pulse is output from each output terminal C1 to C4.

[0158] The circuit block 33 is connected to the PLL 31 via a signal line L0. Further, the circuit block 33 is connected to the system control unit 25 via a signal line L3. The circuit block 33 is connected to the D terminal of the flip-flop 340 via a signal line L2. Further, the circuit block 33 is connected to the CLK terminals of the flip-flops 340 to 343 via signal lines L1.

[0159] The circuit block 33 includes, for example, a frequency divider circuit. In this case, the frequency divider circuit of the circuit block 33 generates a signal having a frequency different from that of a clock signal to be input, based on the clock signal. The setting of the frequency divider circuit of the circuit block 33 can be changed according to a register or a voltage level of a signal line, and the like. In this case, the system control unit 25 can adjust the frequency of a signal output from the circuit block 33. Here, the configuration and the function of the circuit block 33 can be different from those described above. For example, a configuration in which the setting of the circuit block 33 is always changed by the system control unit 25 can not be employed.

[0160] In Figure 9 the plurality of flip-flops are connected in cascade. For example, the Q terminal of the flip-flop 340 is connected to the D terminal of the flip-flop 341. On the other hand, the Q terminal of the flip-flop 341 is connected to the D terminal of the flip-flop 342. The Q terminal of the flip-flop 342 is connected to the D terminal of the flip-flop 343.

[0161] Further, the Q terminal of each flip-flop is connected to a corresponding output terminal. For example, the output terminal C1 is connected to the Q terminal of the flip-flop 340. Further, the output terminal C2 is connected to the Q terminal of the flip-flop 341. The output terminal C3 is connected to the Q terminal of the flip-flop 342. The output terminal C4 is connected to the Q terminal of the flip-flop 343. Here, the Q terminals of all the flip-flops connected in cascade can not necessarily be connected to any output terminal. For example, the Q terminals of some of the flip-flops connected in cascade can be connected to any output terminal.

[0162] The operation of the pulse generator 30A will be described below.

[0163] The PLL 31 supplies a clock signal having a frequency fo to the circuit block 33 via a signal line L0. The circuit block 33 supplies a first signal having a frequency fl from a signal line LI to CLK terminals of flip-flops 340 to 343. Further, the circuit block 33 supplies a second signal having a frequency f2 to a D terminal of the flip-flop 340 via a signal line L2. The second signal is also referred to as a "modulation signal or pilot pulse".

[0164] It is assumed that the frequency fl of the first signal (first frequency) and the frequency f2 of the second signal (second frequency) are different. Hereinafter, a case where the first frequency fl is higher than the second frequency f2 will be described. Here, the second frequency f2 can be set to be higher than the first frequency fl. The circuit block 33 can output the first signal and the second signal in synchronization with each other. Here, the first signal and the second signal do not have to be in synchronization with each other.

[0165] Here, it will be described that the frequency fo of the clock signal (clock frequency) is equal to the first frequency fl. Here, the clock frequency fo generated by the signal generator can be different from the first frequency fl. For example, the circuit block 33 can convert the frequency of the clock signal using a frequency divider or the like.

[0166] As a result, pulses that have been delayed using different numbers of flip-flops are output from the output terminals Cl to C4 of the pulse generator 30A. In the case of the example of Figure 9 , the pulses are output in order through the output terminal Cl, the output terminal C2, the output terminal C3, and the output terminal C4. That is, the pulses are output at different timings from the output terminals Cl to C4 of the pulse generator 30A. Hereinafter, the difference in the timing at which the pulses are output from any of the signal lines without the pulse generator will be described using a phase (phase in the drawing).

[0167] In the pulse generator according to the present disclosure, the shift in the timing at which the pulses are output from the plurality of output terminals can be adjusted based on the first frequency fl and the second frequency f2. The phase delay Δθ caused by the second signal passing through one flip-flop is Δθ = 360 x f2 / fl. For example, in the case where fl = 2.0 GHz and f2 = 500 MHz, Δθ = 90 degrees is satisfied. In this case, as shown in Figure 9 , the pulse signals are output at phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees from the output terminals Cl, C2, C3, and C4, respectively. The values of the first frequency fl and the second frequency f2 mentioned here are merely examples. Therefore, the first frequency fl and the second frequency f2 can be set to values different from the first frequency fl and the second frequency f2.

[0168] Hereinafter, the phase of the pulse signal output from the output terminal C1 is P1, the phase of the pulse signal output from the output terminal C2 is P2, the phase of the pulse signal output from the output terminal C3 is P3, and the phase of the pulse signal output from the output terminal C4 is P4. For example, in the case where f1 = 2.0 GHz and f2 = 500 MHz as described above, P1 = 0 degrees, P2 = 90 degrees, P3 = 180 degrees, and P4 = 270 degrees are satisfied.

[0169] Note that the first frequency f1 of the first signal and the second frequency f2 of the second signal can not be fixed. For example, the circuit block 33 can change at least one of the first frequency f1 of the first signal or the second frequency f2 of the second signal based on a control signal transmitted from the system control unit 25 via the signal line L3. Thus, the pulse generator can change the frequency of the pulse signal. Further, the pulse signal can output the pulse signal related to various combinations of phases.

[0170] The pulse generator according to the present disclosure can change the frequency of the pulse signal or the combination of phases used in the pulse signal according to, for example, the object to be detected or the operation mode. For example, in the case where an object located at a relatively short distance is to be detected, the pulse frequency can be set to be high. In addition, in the case where an object located at a relatively long distance is to be detected, the pulse frequency can be set to be low. Because the pulse generator according to the present disclosure does not use an inverter chain to generate the pulse signal of multiple phases, the individual variation of the delay amount can be minimized. Further, in the pulse generator according to the present disclosure, the distortion to be generated can be minimized. For this reason, the pulse generator according to the present disclosure can also be combined with a signal generator (e.g., the PLL 31) that outputs a relatively low clock frequency.

[0171] As described above, the circuit block can be configured to output a first signal having a first frequency and output a second signal having a second frequency different from the first frequency. The circuit block can be configured to output the first signal and the second signal in synchronization with each other. Further, the circuit block can be configured to output the first signal having a first frequency equal to the clock frequency of the clock signal.

[0172] Further, the imaging element according to the present disclosure can include a control unit configured to output a control signal to the circuit block. The above-described system control unit 25 is an example of the control unit. In this case, the circuit block can be configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the provided control signal.

[0173] Figure 10 The pixel drive unit 22B in the imaging element 22 includes the PLL 31 (signal generation unit), the pulse generator 30A, and the circuit block 370. Figure 10 The imaging element in the system according to the present disclosure is the same as Figure 8The pulse generator 30 of the imaging element in the Figure 9 The pulse generator 30A in the Figure 8 The clock distribution circuit 37 of the imaging element in the Figure 10 The clock distribution circuits 371 to 374 of the

[0174] The clock distribution circuits 371 to 374 are connected to any one of the output terminals C1 to C4 of the pulse generator 30A, respectively. Thus, each of the clock distribution circuits 371 to 374 distributes any one of the signals of the phases P1 to P4. In the following description, it is assumed that the output terminal C1 is connected to the clock distribution circuit 371, the output terminal C2 is connected to the clock distribution circuit 372, the output terminal C3 is connected to the clock distribution circuit 373, and the output terminal C4 is connected to the clock distribution circuit 374. Here, the connection relationship between the output terminal and the clock distribution circuit can be different.

[0175] Each of the pixel columns in the pixel array unit 21 is connected to any one of the clock distribution circuits 371 to 374 via the pixel drive line 28A. The timing at which the pixel column in the pixel array unit 21 is driven with the pulse (the phase of the pulse signal) depends on the clock distribution circuit to which the corresponding pixel drive line 28A is connected. In the case of the example of the Figure 10 In the example of the Figure 10 In the example of the

[0176] In the pixel array unit 21 of the Figure 10 In the pixel array unit 21 of the Figure 10 In the

[0177] Each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via a vertical signal line 29. The column processing unit 23 can be connected to a lead driving unit 24 (not shown). In the case where the lead driving unit 24 is installed, the lead driving unit 24 can select a cell circuit corresponding to the pixel column of the column processing unit 23. The lead driving unit 24 can perform selective scanning on the pixel column (e.g., P1 to P4) driven in each phase. In this case, the column processing unit 23 can convert the pixel signal from an analog signal to a digital signal using an analog-digital converter 240, and output the pixel signal to the signal processing unit 26 in a subsequent stage.

[0178] The pixel signal related to the pixel column driven and read in a plurality of phases (e.g., P1 to P4) is input to the signal processing unit 26. In the signal processing unit 26, the pixel signal is subjected to various processes such as a correction process, a distance calculation process, and a distance image generation process. Figure 10 In the imaging element, a shift in the driving timing and a shift in the pixel signal reading timing occur depending on the pixel column. For this reason, the data of the pixel signal can be accumulated in a buffer memory in the signal processing unit 26 and a distance image corresponding to the entire pixel array unit 21 can be generated.

[0179] The imaging element according to the present disclosure can include a signal generator, a plurality of flip-flops connected in cascade, a circuit block, and a pixel array. The signal generator is configured to generate a clock signal. The circuit block is configured to provide a first signal to a clock terminal of each of the plurality of flip-flops and provide a second signal to an input terminal of a first stage flip-flop of the plurality of flip-flops in accordance with the clock signal. The pixel array includes pixels configured to be driven using pulse signals provided from different stages of the plurality of flip-flops. The above-described pixel array unit is an example of the pixel array. As the signal generator, for example, a PLL can be used. As the flip-flop, for example, a D flip-flop can be used. The first stage flip-flop is the above-described flip-flop 340, for example.

[0180] The pixel in the pixel array can include a signal taking-out unit configured to detect a charge generated by photoelectric conversion if provided with a pulse signal. Further, the pixel in the pixel array can include a plurality of signal taking-out units, and each signal taking-out unit can be configured to detect a charge generated at a different timing.

[0181] Further, the imaging element according to the present disclosure can further include a plurality of clock distribution circuits connected to the plurality of flip-flops of any stage on the input side and connected to the pixels in the pixel array via a driving line on the output side. At least one of the clock distribution circuits can be of a clock tree type.

[0182] Figure 10An example of an imaging element is shown, in which the driving timing (phase of the pulse signal) can be set on a per-pixel-column basis. Here, the pixels in pixel array unit 21 can be controlled with units and patterns different from these units and patterns. For example, as in Figure 11 In the example, an imaging element that sets the driving time (phase of the pulse signal) in units of pixel rows can be used.

[0183] Figure 11 The imaging element in the image corresponds to the one in the image. Figure 1 The imaging element in the image is replaced by the pixel driving unit 22C, which is the pixel driving unit 22. The pixel driving unit 22C includes a PLL 31 (signal generator), a pulse generator 30A, and a circuit block 380. In addition, the circuit block 380 includes clock distribution circuits 381 to 384. Figure 11 The clock distribution circuits 381 to 384 are in a clock tree configuration. Here, at least one of the clock distribution circuits 381 to 384 may use another method such as the grid method (collective drive method).

[0184] Clock distribution circuits 381 to 384 are connected to any one of the output terminals C1 to C4 of the pulse generator 30A. Therefore, clock distribution circuits 381-384 distribute any one of the signals with phases P1-P4. In the following description, output terminal C1 is connected to clock distribution circuit 381, output terminal C2 is connected to clock distribution circuit 382, ​​output terminal C3 is connected to clock distribution circuit 383, and output terminal C4 is connected to clock distribution circuit 384. However, the connection relationships between the output terminals and the clock distribution circuits can be different.

[0185] Each pixel row in pixel array unit 21 is connected to any one of clock distribution circuits 381 to 384 via pixel drive line 28. The timing of driving the pixel row in pixel array unit 21 with pulses (the phase of the pulse signal) depends on the clock distribution circuit to which the corresponding pixel drive line 28 is connected. Figure 11 In the example case, pixel rows connected to clock distribution circuit 381 are driven with phase P1, pixel rows connected to clock distribution circuit 382 are driven with phase P2, pixel rows connected to clock distribution circuit 383 are driven with phase P3, and pixel rows connected to clock distribution circuit 384 are driven with phase P4. Therefore, in Figure 11 In the example, pixels in the imaging element are driven in rows.

[0186] exist Figure 11In the pixel array unit 21, pixel rows driven by phase P1, pixel rows driven by phase P2, pixel rows driven by phase P3, and pixel rows driven by phase P4 are arranged in a pattern (sequentially) from top to bottom. This pattern is merely an example. Therefore, the pixel rows of the pixel array unit 21 can be driven with a pattern different from this one. It should be noted that in... Figure 11 In this example, the number of pixels included in pixel array unit 21 is 8×8=64. However, the number of pixels included in pixel array unit 21 is not limited. Therefore, a different number of pixels (e.g., more pixels) can be installed in pixel array unit 21.

[0187] Each pixel column in pixel array unit 21 is connected to column processing unit 23 via vertical signal line 29. Column processing unit 23 can be connected to lead drive unit 24 (not shown). With lead drive unit 24 installed, lead drive unit 24 can select the unit circuit corresponding to the pixel column of column processing unit 23. Lead drive unit 24 can perform selective scanning of pixel columns. In this case, column processing unit 23 can use analog-to-digital converter 240 to convert pixel signals from analog signals to digital signals, and output pixel signals to signal processing unit 26 in a subsequent stage.

[0188] Pixel signals related to the read pixel column are input to signal processing unit 26. Figure 10 In the imaging element, the offset of the driving time occurs according to the pixel row, and the offset of the pixel signal readout time occurs according to the pixel column. For this purpose, pixel signal data can be accumulated in the buffer memory in the signal processing unit 26, and a distance image corresponding to the entire pixel array unit 21 can be generated.

[0189] As described above, in the imaging element according to this disclosure, the pixel column or pixel row in the pixel array can be configured to be driven using a pulse signal provided from a common stage of multiple triggers.

[0190] exist Figure 11 An example of an imaging element in which the driving time (phase of the pulse signal) is set in units of pixel rows has already been described. Here, the pixels in pixel array unit 21 can be controlled with units and patterns different from these units and patterns. For example, as in Figure 12 In the example, an imaging element that sets the driving time (phase of the pulse signal) for each region in the pixel array unit 21 can be used.

[0191] Figure 12 The imaging elements include a pixel driving unit 22B, a pixel array unit 21A, a column processing unit 23, and a timing control unit 32. Figure 12 The configuration of the pixel driving unit 22B inFigure 10 The configuration of the pixel driving unit 22B is similar. The timing control unit 32 outputs a timing signal to the pixel driving line 28A based on the pulse signal output to the pixel driving line 28A by the clock distribution circuits 371 to 374.

[0192] For example, assume that each pixel in pixel array unit 21A includes logic circuitry (not shown) that performs calculations based on pulse signals and timing signals. Each pixel in pixel array unit 21A is driven when the output voltage level of the logic circuitry meets predetermined conditions. The driving conditions can vary depending on the pixel. For example, in pixel array unit 21A, pixels driven when the output voltage level of the logic circuitry is high and pixels driven when the output voltage level of the logic circuitry is low can be mixed. The configuration of pixel array unit 21A is similar to the configuration of pixel array unit 21 described above, except that each pixel includes logic circuitry.

[0193] Therefore, as Figure 12 As shown in the example, the driving time (phase of the pulse signal) can be set for each region of a pixel in the imaging element. Figure 12 In the example, any one of phases P1 to P4 is periodically assigned to each square region. Here, Figure 12 The allocation patterns shown are merely examples. For instance, the drive timing (phase of the pulse signal) can be set for each region with other shapes such as polygons or rings. Furthermore, there are no particular restrictions on the order in which phases are allocated to the various regions. The phase allocation order can be based on predetermined rules or it can be random.

[0194] like Figure 12 As shown, the timing control unit 32 can be connected to the system control unit 25. In this case, the timing control unit 32 can change the timing signal output to the pixel drive line 28 based on the control signal provided from the system control unit 25. Therefore, the driving timing (phase of the pulse signal) in each region of the pixel array unit 21A can be dynamically changed.

[0195] exist Figure 12 In the imaging element, the configuration of the column processing unit 23 and its subsequent stages of circuitry is similar to... Figure 10 and Figure 11 The configuration of their imaging elements is similar. It is important to note that... Figure 12 This is just one example of an imaging element, where the driving time (phase of the pulse signal) can be set for each region. Therefore, circuitry with a different configuration can be used to set the driving time (phase of the pulse signal) of pixels for each region.

[0196] As described above, the imaging element according to the invention can be configured such that, depending on the region in the pixel array in which the pixels are arranged, pulse signals are provided from different stages of a plurality of triggers.

[0197] Figure 9 A pulse generator 30A capable of generating pulses with four phases (phases P1 to P4) is shown. Here, Figure 9 The pulse generator 30A described herein is merely an example of an imaging element that can be used in an imaging element according to the present invention. For example, it can be used... Figure 13 The pulse generator 30B replaces Figure 9 The pulse generator 30A.

[0198] Figure 13 The pulse generator 30B corresponds to the pulse generator, wherein the pulse generator is as follows: Figure 9 The number of stages of the triggers connected in the cascaded configuration of pulse generator 30A increases from 4 to 8. Here, pulse generator 30B will be described focusing on the differences between it and pulse generator 30A. For example, in... Figure 9 In this circuit, the Q terminal of flip-flop 340 is connected to circuit block 33 via signal line L2. Furthermore, the Q and D terminals of the connected flip-flops are cascaded together. Additionally, circuit block 33 is connected to the CLK terminals of flip-flops 340 to 347 via signal line L1. The Q terminal of each flip-flop in pulse generator 30B is connected to a corresponding output terminal (output terminals C1 to C8). Output terminals C1 to C8 are respectively connected to pixel drive line 28 or pixel drive line 28A via different clock distribution circuits.

[0199] It should be noted that, Figure 9 and Figure 13 In the example, the Q terminals of all the cascaded flip-flops in the pulse generator are connected to any one of the output terminals. Here, the Q terminals of all the cascaded flip-flops do not necessarily need to be connected to any output terminal. For example, if only a portion of the phase of the generated pulse signal is needed, the Q terminals of some of the cascaded flip-flops can be connected to the output terminal.

[0200] Aside from an increase in the number of phases of the pulse signals to be generated, the operation of pulse generator 30B is similar to that of pulse generator 30A described above. That is, based on the first frequency f1 of the first signal output from circuit block 33 to signal line L1 and the first frequency f2 of the second signal output from circuit block 33 to signal line L2, the timing offset of the pulses output from multiple output terminals can be adjusted. For example... Figure 9As shown, the phase delay Δθ caused by the second signal passing through the first-stage trigger is Δθ = 360 × f2 / f1. Similar to the description above, it is assumed that the phases of the pulse signals output from output terminals C1 to C8 are P1 to P8, respectively.

[0201] For example, when f1 = 2.0 GHz and f2 = 250 MHz, Δθ = 45 degrees is satisfied. In this case, as... Figure 13 As shown, pulses are output from output terminals C1, C2, C3, C4, C5, C6, C7, and C8 with phases of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively. That is, in pulse generator 30B, the phases of the pulse signals are P1 = 0 degrees, P2 = 45 degrees, P3 = 90 degrees, P4 = 135 degrees, P5 = 180 degrees, P6 = 225 degrees, P7 = 270 degrees, and P8 = 315 degrees. The values ​​of the first frequency f1 and the second frequency f2 mentioned here are merely examples. Therefore, the first frequency f1 and the second frequency f2 can be set to values ​​different from the first frequency f1 and the second frequency f2.

[0202] It should be noted that Figure 13 Other components (pulse generator 30B) are similar to Figure 9 The imaging element according to this disclosure may include a pulse generator capable of generating pulses at multiple (two or more) phases (times). Therefore, the number of stages of the triggers in the pulse generator can be set to any number of two or more.

[0203] Figure 9 and Figure 13 The pulse generator includes multiple output terminals and is configured to output pulse signals with different phases from the respective output terminals. Here, the pulse generator according to this disclosure can be configured to output any one of the multiple phase pulse signals.

[0204] Figure 14 The diagram shows a pulse generator 30C with three stages of triggers and a multiplexer 36. The following will focus on... Figure 14 The pulse generator 30C and Figure 9 and Figure 13 To describe the differences between the pulse generators 30C Figure 14 The pulse generator 30C.

[0205] The multiplexer 36 includes input terminals in1 to in3. In the pulse generator 30C, the Q terminal of each flip-flop is connected to the input terminal of the multiplexer 36. That is, the Q terminal of the flip-flop 340 is connected to the input terminal in1 of the multiplexer 36 through the signal line cl. The Q terminal of the flip-flop 341 is connected to the input terminal in2 of the multiplexer 36 via the signal line c2. Note that the Q terminals of some of the plurality of flip-flops connected in cascade can be connected to the input terminals of the multiplexer 36.

[0206] The Q terminal of the flip-flop 342 is connected to the input terminal in3 of the multiplexer 36 via the signal line c3. The control terminal of the multiplexer 36 is connected to the system control unit 25 via the signal line cnt. Further, the output terminal mout of the multiplexer 36 is connected to the output terminal of the pulse generator 30C.

[0207] The multiplexer 36 selects the signal supplied from the Q terminal of any one of the flip-flops on the basis of the control signal supplied from the system control unit 25. Further, the multiplexer 36 outputs the selected signal from the output terminal mout to the circuit of the subsequent stage. That is, the pulse generator 30C is able to output the pulse signal of any one of the phases P1 to P3 in accordance with the setting of the system control unit 25. Also, in the case where the phase delay Δθ is set to 45 degrees, the above-described equation is established. Figure 14

[0208] The circuit block 33A of the pulse generator 30C includes a frequency divider circuit 35. The frequency divider circuit 35 is, for example, a single frequency divider circuit. Here, the frequency division number of the frequency divider circuit can be different from this. The frequency division number of the frequency divider circuit can be determined in accordance with the clock frequency f0 of the first signal to be generated and the first frequency fl. The input side of the frequency divider circuit 35 is connected to the PLL 31 via the signal line L0. Further, the output side of the frequency divider circuit 35 is connected to the CLK terminals of the flip-flops 340 to 342 via the signal line L1.

[0209] Thereby, the first signal having the first frequency fl which is 1 / 2 of the clock frequency f0 is supplied to the CLK terminals of the flip-flops 340 to 342 via the signal line L1. For example, in the case where the clock frequency f0 generated by the PLL 31 is 1.6 GHz, the first frequency fl of the first signal is 800 MHz. In the case where the second frequency f2 of the second signal output from the signal line L2 by the circuit block 33A is 100 MHz, the phase delay Δθ caused by the second signal passing through one stage of flip-flop is Δθ = 45 degrees. Therefore, assuming that the phase P1 is 0 degrees, the phase P2 is 45 degrees, and the phase P3 is 90 degrees. Further, the circuit block 33A can also generate the second signal in synchronization with the first signal.

[0210] ​The clock frequency f0, the first frequency f1, and the second frequency f2 described here are merely examples. Thus, signals having frequencies different from these frequencies can be used in the pulse generator according to the present application. Furthermore, as described above, the first frequency f1 of the first signal and the second frequency f2 of the second signal generated by the circuit block can not be fixed frequencies, but can be adjustable (variable) frequencies.

[0211] In this way, the imaging device according to the present disclosure can further include a multiplexer configured to select a pulse signal provided to a pixel in the pixel array. Furthermore, the circuit block can further include a frequency divider circuit that generates the first signal based on the clock signal.

[0212] Although the number of stages of the flip-flop is 3 in the example of Figure 14 , the number of stages of the flip-flop can be different from 3. For example, a pulse signal related to a plurality of phases can be generated by connecting two or more arbitrary number of flip-flops in a cascade manner. In the case where the number of stages of the flip-flop is greater than Figure 14 in the example of the flip-flop, a multiplexer having three or more input terminals can be used or a plurality of multiplexers can be installed in the pulse generator.

[0213] Figure 15 An example of an imaging device including a plurality of pulse generators 30C of Figure 14 is shown. In Figure 15 , a system control unit 25, a pixel drive unit 22C, a pixel array unit 21, and a column processing unit 23 are provided. The pixel drive unit 22C includes a PLL 31 (a signal generator), a pulse generator 30C-1, a pulse generator 30C-2, a pulse generator 30C-3, and a circuit block 370A. The pulse generators 30C-1, 30C-2, and 30C-3 correspond to the pulse generators 30C of Figure 14 . Furthermore, the circuit block 370A includes clock distribution circuits 371 to 373. Although the clock distribution circuits 371 to 373 are, for example, clock tree type circuits, the method of the clock distribution circuit is not limited.

[0214] The PLL 31 is connected to a signal line L0 of the pulse generators 30C-1, 30C-2, and 30C-3. The output terminals of the pulse generators 30C-1, 30C-2, 30C-3 are connected to any of the clock distribution circuits of the circuit block 370A. Furthermore, each pixel column in the pixel array unit 21 is connected to any of the clock distribution circuits 371 to 373 via a pixel drive line 28A. Furthermore, each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via a vertical signal line 29.

[0215] In Figure 15In the example, assume that pulse generator 30C-1 outputs a pulse signal with phase P1 = 0 degrees, pulse generator 30C-2 outputs a pulse signal with phase P2 = 45 degrees, and pulse generator 30C-3 outputs a pulse signal with phase P3 = 90 degrees. Therefore, the pixel column in the pixel array unit 21 connected to pulse generator 30C-1 via either clock distribution circuit is driven using the pulse signal with phase P2. Conversely, the pixel column in the pixel array unit 21 connected to pulse generator 30C-2 via either clock distribution circuit is driven using the pulse signal with phase P2. Furthermore, the pixel column in the pixel array unit 21 connected to pulse generator 30C-3 via either clock distribution circuit is driven using the pulse signal with phase P3.

[0216] By using Figure 15 The imaging element can dynamically change the timing of each pixel column in the driving pixel array unit 21. That is, in Figure 15 In the imaging element, the pixel columns in pixel array unit 21 can be driven using at least one of a phase pulse signal that can be generated by a corresponding pulse generator. Therefore, depending on the application, it can also be used in conjunction with... Figure 8 In the example, all pixels of pixel array unit 21 are driven at almost the same time. Furthermore, the number of phases used to drive the pixels in pixel array unit 21 can be changed during the operation of the imaging element.

[0217] exist Figure 15 In the imaging element, the driving time (phase of the pulse signal) can be set in the pixel column unit of the pixel array unit 21. Here, the unit for setting the driving time (phase of the pulse signal) is not limited to the pixel column. For example, as in... Figure 11 In the example, the driving timing (phase of the pulse signal) can be set in pixel rows. Furthermore, as in... Figure 12 In the example, the driving time (phase of the pulse signal) can be set for each region in the pixel array unit 21.

[0218] As described above, if the imaging element according to this disclosure is used, pixels in the pixel array can be driven individually at multiple times, instead of driving all pixels in the pixel array simultaneously at the same time. This minimizes the total current of the driving signal at each driving moment. Therefore, the resolution of the distance image can be improved while preventing the generation of electromagnetic noise.

[0219] (Example of electronic device configuration)

[0220] Figure 16 and Figure 17 Examples of electronic devices according to this disclosure are shown. Figure 16The configuration of the electronic device 1 is shown when viewed from the z-axis positive direction side. On the other hand, Figure 17 The configuration of the electronic device 1 is shown when viewed from the z-axis negative direction side. The electronic device 1 has, for example, a substantially flat plate shape, and includes a display unit 1a on at least one surface (here, the surface of the z-axis positive direction side). The display unit 1a can display, for example, an image of a liquid crystal, a micro LED, or an organic electroluminescence method. Here, the display method in the display unit 1a is not limited. In addition, the display unit 1a can include a touch panel and a fingerprint sensor.

[0221] The first imaging unit 110, the second imaging unit 111, the first light emitting unit 112, and the second light emitting unit 113 are mounted on the surface of the z-axis negative direction side of the electronic device 1. The first imaging unit 110 is, for example, a camera module capable of capturing a color image. The camera module includes, for example, a lens system and an imaging element that performs photoelectric conversion on light gathered by the lens system. The first light emitting unit 112 is, for example, a light source that functions as a flash for the first imaging unit 110. A white LED can be used as the first light emitting unit 112, for example. Here, the type of the light source that functions as the first light emitting unit 112 is not limited.

[0222] The second imaging unit 111 is, for example, an imaging element capable of distance measurement by an indirect ToF method. An imaging element according to the present disclosure can be mounted as the second imaging unit 111, for example. The second imaging unit 111 corresponds to, for example, the light receiving unit 1013 in the distance measurement module 1000 in Figure 7 The second light emitting unit 113 can be used as a light source for distance measurement by an indirect ToF method. The second light emitting unit 113 corresponds to, for example, the light emitting unit 1011 in the distance measurement module 1000 in Figure 7 That is, the distance measurement module 1000 in the distance measurement module 1000 in Figure 7 The distance measurement module 1000 in the distance measurement module 1000 in

[0223] The electronic device according to the present disclosure has been described above as a case where the electronic device is a smartphone or a tablet. Here, the electronic device according to the present disclosure can be other types of devices such as a game console, a car-mounted device, a PC, and a surveillance camera, for example.

[0224] The ranging device according to this disclosure may include a signal generator, a plurality of cascaded flip-flops, a circuit block, a pixel array, and a signal processing unit. The signal generator is configured to generate a clock signal. The circuit block is configured to provide a first signal to a clock terminal of each of the plurality of flip-flops according to the clock signal and to provide a second signal to an input terminal of a first-stage flip-flop among the plurality of flip-flops. The pixel array includes pixels configured to be driven using pulse signals provided from different stages of the plurality of flip-flops. The signal processing unit is configured to generate a distance image based on the charge generated in the pixels of the pixel array through photoelectric conversion.

[0225] The electronic device according to this disclosure may include a signal generator, a plurality of cascaded flip-flops, a circuit block, and a pixel array. The signal generator is configured to generate a clock signal. The circuit block is configured to provide a first signal to a clock terminal of each of the plurality of flip-flops and a second signal to an input terminal of a first-stage flip-flop among the plurality of flip-flops, according to the clock signal. The pixel array includes pixels configured to be driven using pulse signals provided from different stages of the plurality of flip-flops.

[0226] (Examples of applications involving moving objects)

[0227] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed in any type of mobile body (such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots).

[0228] Figure 18 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0229] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 18 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0230] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for a drive force generating device (such as an internal combustion engine or drive electric motor) for generating drive force for the vehicle, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, a braking device for generating braking force for the vehicle, etc.

[0231] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, hazard lights, or fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that replaces buttons can be input to the body system control unit 12020. The body system control unit 12020 receives these radio wave or signal inputs and controls the vehicle's door locking devices, power window devices, lights, etc.

[0232] The exterior information detection unit 12030 detects exterior information of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing related to people, vehicles, obstacles, signs, characters on the road surface, etc., based on the received images.

[0233] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image or an electrical signal as ranging information. In addition, the light received by imaging unit 12031 can be visible light or infrared light, which is invisible to the eye.

[0234] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or it can determine whether the driver is dozing off.

[0235] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, lane departure warning, etc.

[0236] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing coordinated control related to autonomous driving and other functions that are independent of the driver's operation.

[0237] Additionally, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030 to perform cooperative control for glare prevention, such as switching from high beam to low beam.

[0238] The audio-visual output unit 12052 sends an output signal of at least one of audio or visual information to an output device capable of visually or audibly notifying vehicle occupants or persons outside the vehicle. Figure 18 In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0239] Figure 19 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0240] exist Figure 19 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are included as imaging units 12031.

[0241] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, within the interior of vehicle 12100 at locations such as the front nose, side mirrors, rear bumper, rear door, and the upper part of the windshield. Imaging unit 12101 at the front nose and imaging unit 12105 at the upper part of the windshield primarily acquire images of objects in front of vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of objects on the sides of vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of objects behind vehicle 12100. The images of the front acquired by imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0242] It should be noted that Figure 19 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 indicates the imaging range of imaging unit 12101 located at the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located at the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, by overlaying the image data captured by imaging units 12101 to 12104, a top-view image of vehicle 12100 when viewed from above is obtained.

[0243] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0244] For example, the microcomputer 12051 obtains the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. It then extracts the three-dimensional object (specifically, the closest three-dimensional object on the vehicle 12100's travel path) traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher) as the vehicle ahead. Furthermore, the microcomputer 12051 can pre-set a safe distance in front of the vehicle and can perform automatic braking control (including automatic stop control), automatic acceleration control (including automatic start control), etc. As described above, coordinated control is possible for autonomous driving systems, such as those where the vehicle drives itself without relying on driver operation.

[0245] For example, microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as utility poles) based on distance information obtained from imaging units 12101 to 12104, extract the three-dimensional object data, and use the three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. In addition, microcomputer 12051 determines the collision risk, which represents the risk of collision with each obstacle. When the collision risk is above a set value and there is a possibility of collision, microcomputer can perform driving assistance for collision avoidance by outputting an alarm to the driver via audio speaker 12061 or display unit 12062 or by performing forced deceleration or evasive steering via drive system control unit 12010.

[0246] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian is present in the images captured by the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by using a process of extracting feature points from the captured images of the imaging units 12101 to 12104, which are infrared cameras, and a process of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether the object is a pedestrian. If the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and identifies the object as a pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay and display a square outline for emphasizing the identified pedestrian. Furthermore, the audio-visual output unit 12052 can control the display unit 12062 to display icons or other indicators of pedestrians at desired locations.

[0247] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. For example, the technology according to this disclosure can be applied to the imaging unit 12031 in the above configuration. That is, the imaging element of the present invention can be mounted on the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, the resolution of the distance image can be improved while preventing the generation of electromagnetic noise, and the functionality and safety of the vehicle 12100 can be enhanced.

[0248] It should be noted that this technology can have the following configurations.

[0249] (1) An imaging element, comprising:

[0250] The signal generator is configured to generate a clock signal;

[0251] Multiple triggers are connected in a cascaded manner;

[0252] A circuit block is configured to provide a first signal to the clock terminal of each of a plurality of flip-flops and a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops, according to a clock signal; and

[0253] A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of a plurality of triggers.

[0254] (2) The imaging element according to (1), wherein,

[0255] The pixels in the pixel array include signal extraction units configured to detect charge generated by photoelectric conversion if a pulse signal is provided.

[0256] (3) The imaging element according to (2), wherein,

[0257] The pixels in the pixel array include multiple signal extraction units, and each signal extraction unit is configured to detect the charge generated at different times.

[0258] (4) The imaging element according to any one of (1) to (3) further comprises:

[0259] Multiple clock distribution circuits are connected to multiple flip-flops at any stage on the input side and to the pixels in the pixel array via drive lines on the output side.

[0260] (5) The imaging element according to (4), wherein,

[0261] At least one clock distribution circuit is a clock tree type.

[0262] (6) The imaging element according to any one of (1) to (5), wherein,

[0263] A pixel column or a pixel row in a pixel array is configured to be driven using a pulse signal provided from a common stage of multiple triggers.

[0264] (7) The imaging element according to any one of (1) to (6), wherein,

[0265] The pulse signal is configured to be provided from different stages of multiple triggers according to the area in the pixel array where pixels are set.

[0266] (8) The imaging element according to any one of (1) to (7) further comprises:

[0267] The multiplexer is configured to select the pulse signal provided to the pixels in the pixel array.

[0268] (9) The imaging element according to any one of (1) to (8), wherein,

[0269] The circuit block is configured to output a first signal having a first frequency and a second signal having a second frequency different from the first frequency.

[0270] (10) The imaging element according to any one of (1) to (9), wherein,

[0271] The circuit block is configured to output a first signal and a second signal that are synchronized with each other.

[0272] (11) The imaging element according to any one of (1) to (10), wherein,

[0273] The circuit block also includes a frequency divider circuit that generates a first signal based on a clock signal.

[0274] (12) The imaging element according to any one of (1) to (10), wherein,

[0275] The circuit block is configured to output a first signal having a first frequency equal to the clock frequency of the clock signal.

[0276] (13) The imaging element according to any one of (1) to (12) further comprises:

[0277] The control unit is configured to output control signals to the circuit block;

[0278] The circuit block is configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the provided control signal.

[0279] (14) A ranging device, comprising:

[0280] The signal generator is configured to generate a clock signal;

[0281] Multiple triggers connected in a cascade;

[0282] The circuit block is configured to provide a first signal to the clock terminal of each of the plurality of flip-flops and a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops, according to a clock signal.

[0283] A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of a plurality of triggers; and

[0284] The signal processing unit is configured to generate a distance image based on the charge generated by photoelectric conversion in the pixels of the pixel array.

[0285] (15) An electronic device comprising:

[0286] The signal generator is configured to generate a clock signal;

[0287] Multiple triggers connected in a cascade;

[0288] A circuit block is configured to provide a first signal to the clock terminal of each of a plurality of flip-flops and a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops, according to a clock signal; and

[0289] A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of a plurality of triggers.

[0290] The aspects of this invention are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art. Furthermore, the effects of this disclosure are not limited to the details described above. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of this disclosure derived from the details defined in the claims and their equivalents.

[0291] List of icon numbers

[0292] 1. Electronic devices

[0293] 11, 11A Imaging Element

[0294] 21-pixel array unit

[0295] Pixel driving units 22, 22A, 22B

[0296] 23-column processing unit

[0297] 24-lead drive unit

[0298] 25 System Control Unit

[0299] 26 Signal Processing Units

[0300] 27 Data storage units

[0301] 30, 30A, 30B, 30C, 30C-1, 30C-2, 30C-3 Pulse Generators

[0302] 31 PLL

[0303] 32-hour control unit

[0304] 33, 33A, 370, 370A, 380 circuit blocks

[0305] 35-frequency divider circuit

[0306] 36 Multiplexers

[0307] Clock distribution circuits 37, 371, 372, 373, 374, 381, 382, ​​383, 384

[0308] 240 Analog-to-Digital Converter

[0309] Triggers 340, 341, 342, 343, 344, 345, 346, 347

[0310] 1000 ranging module

[0311] 1011 Light Emitting Unit

[0312] 1012 Light-emitting control unit

[0313] 1013 Optical receiving unit.

Claims

1. An imaging element, comprising: The signal generator is configured to generate a clock signal; Multiple triggers are connected in a cascaded manner; The circuit block is configured to provide a first signal to the clock terminal of each of the plurality of flip-flops according to the clock signal, and to provide a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops. A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of a plurality of triggers; A timing control unit is configured to output a timing signal to the pixels in the pixel array based on the pulse signal; as well as The system control unit is configured to provide control signals to the timing control unit; in, Each pixel in the pixel array includes logic circuitry configured to perform calculations based on the pulse signal and the time signal, and the pixel is configured to be driven when the level of the output voltage of the logic circuitry satisfies a condition set for the pixel. The timing control unit is configured to change the timing signal output to the pixel based on the control signal.

2. The imaging element according to claim 1, wherein, The pixels in the pixel array include a signal extraction unit configured to detect charge generated by photoelectric conversion if the pulse signal is provided.

3. The imaging element according to claim 2, wherein, The pixels in the pixel array include multiple signal extraction units, and each signal extraction unit is configured to detect charges generated at different times.

4. The imaging element according to claim 1, further comprising: Multiple clock distribution circuits are connected on the input side to any one of the multiple flip-flops and on the output side to the pixels in the pixel array via drive lines.

5. The imaging element according to claim 4, wherein, At least one of the clock distribution circuits is in a clock tree configuration.

6. The imaging element according to claim 1, wherein, A pixel column or a pixel row in the pixel array is configured to be driven using the pulse signal provided from a common stage of multiple triggers.

7. The imaging element according to claim 1, wherein, The pulse signal is configured to be provided from different levels of the plurality of triggers according to the region in the pixel array where the pixel is located.

8. The imaging element according to claim 1, further comprising: A multiplexer is configured to select the pulse signal provided to the pixels in the pixel array.

9. The imaging element according to claim 1, wherein, The circuit block is configured to output a first signal having a first frequency and to output a second signal having a second frequency different from the first frequency.

10. The imaging element according to claim 1, wherein, The circuit block is configured to output the first signal and the second signal synchronized with each other.

11. The imaging element according to claim 1, wherein, The circuit block also includes a frequency divider circuit, which generates the first signal based on the clock signal.

12. The imaging element according to claim 1, wherein, The circuit block is configured to output the first signal having a first frequency equal to the clock frequency of the clock signal.

13. The imaging element according to claim 1, further comprising: The control unit is configured to output control signals to the circuit block; The circuit block is configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the provided control signal.

14. A ranging device, comprising: The signal generator is configured to generate a clock signal; Multiple triggers are connected in a cascaded manner; The circuit block is configured to provide a first signal to the clock terminal of each of the plurality of flip-flops according to the clock signal, and to provide a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops. A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of the plurality of triggers; A timing control unit is configured to output a timing signal to the pixels in the pixel array based on the pulse signal; The system control unit is configured to provide control signals to the timing control unit; as well as The signal processing unit is configured to generate a distance image based on the charge generated by photoelectric conversion in the pixels of the pixel array; in, Each pixel in the pixel array includes logic circuitry configured to perform calculations based on the pulse signal and the time signal, and the pixel is configured to be driven when the level of the output voltage of the logic circuitry satisfies a condition set for the pixel. The timing control unit is configured to change the timing signal output to the pixel based on the control signal.

15. An electronic device, comprising: The signal generator is configured to generate a clock signal; Multiple triggers are connected in a cascaded manner; The circuit block is configured to provide a first signal to the clock terminal of each of the plurality of flip-flops according to the clock signal, and to provide a second signal to the input terminal of the first stage flip-flop of the plurality of flip-flops. A pixel array, comprising pixels configured to be driven using pulse signals provided from different stages of the plurality of triggers; A timing control unit is configured to output a timing signal to the pixels in the pixel array based on the pulse signal; as well as The system control unit is configured to provide control signals to the timing control unit; in, Each pixel in the pixel array includes logic circuitry configured to perform calculations based on the pulse signal and the time signal, and the pixel is configured to be driven when the level of the output voltage of the logic circuitry satisfies a condition set for the pixel. The timing control unit is configured to change the timing signal output to the pixel based on the control signal.

Images