Fault tolerance testing method, device, electronic equipment and storage medium

Abstract

The present invention relates to a fault tolerance test method, device, electronic device and storage medium, the method comprising: obtaining test data to be tested, copying the test data to be tested to obtain control group data to be tested; inputting the test data to be tested and the control group data to be tested into a first FPGA state machine and a second FPGA state machine respectively for flipping and direct output, obtaining first test output data and control group output data and comparing them, and determining the first output state of the first FPGA state machine according to the comparison result; when the first output state is that the first test output data and the control group output data are inconsistent, re-testing to obtain the second test output data and comparing it with the control group output data and determining the fault tolerance of the first FPGA state machine according to the second comparison result. The present invention solves the technical problems in the prior art that the cost of single particle collision tolerance experiment on the state machine is high and the experimental environment affects the experimental opportunities, resulting in few experimental opportunities.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment reliability, and in particular to a fault tolerance testing method, device, electronic equipment and storage medium. Background Art

[0002] When FPGA devices are running in space, they will face the impact of various charged particles. Microscopically, high-energy charged particles pass through semiconductor materials, lose energy along their path and release electron-hole pairs, which are prone to ionization reactions, destroying the stable electric field structure inside the semiconductor, causing the potential of sensitive areas in microelectronic devices to change significantly. Macroscopically, FPGA registers are composed of logic circuits, and the stable electric field inside the semiconductor is destroyed, resulting in local potential changes that cause abnormal changes in register values. When a single-particle flip fault occurs in the state machine register, the state machine will jump to an error state that does not match the judgment logic and execute the instructions of this state, resulting in system signal disorder, making it impossible for data signals to flow normally, and seriously affecting the operation and safety of electronic devices in space. Therefore, when designing FPGA hardware circuits running in space, it is necessary to make special fault-tolerant designs for the state machine registers to ensure that electronic devices can operate normally under the impact of charged particles.

[0003] When designing FPGA hardware circuits, state machines are commonly used to control changes in module signals. The state machine jumps in a pre-set state, which can decompose complex logic into limited simple logic, forming a complete closed-loop system. The register that represents the state machine jump state is called the state machine register. When the judgment condition in the state machine meets the jump logic, the state machine register will change, so the state machine jumps to the new state corresponding to the state machine register and executes the instructions in this state, while waiting for the next logic judgment.

[0004] In the prior art, when conducting the corresponding fault tolerance design, among various evaluation methods, the data obtained by measuring the space environment is the most accurate, but the launch cost of the spacecraft is expensive and there are few debugging opportunities. Another method, such as using a charged particle beam on the ground to irradiate a specific area of ​​the FPGA for irradiation experiments, needs to be completed in a specific laboratory. Since the design requires multiple adjustments and modifications, the cost is also high, and a single state machine register cannot be flipped directly, some interference items will appear, increasing the difficulty of analysis and even damaging the development board. Therefore, it is necessary to propose a new method for testing the fault tolerance of FPGA state machine flip faults to overcome the problems of few debugging opportunities and high costs for fault tolerance tests affected by the environment in existing evaluation methods. Summary of the invention

[0005] In view of this, it is necessary to provide a fault tolerance testing method, device, electronic device and storage medium to overcome the problem that the fault tolerance test evaluation of single particle upset in the prior art cannot meet the demand or is costly.

[0006] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a fault tolerance testing method, comprising the following steps:

[0008] Acquire test data to be tested, and copy the test data to be tested to obtain control group data to be tested;

[0009] Input the test data to be tested into the first FPGA state machine for flipping output to obtain first test output data, and input the control group data to be tested into the second FPGA state machine for direct output to obtain control group output data;

[0010] Comparing the first test output data with the control group output data, and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result;

[0011] When the first output state is that the first test output data and the control group output data are inconsistent, the test data to be tested is re-input into the first FPGA state machine for flipping output to obtain second test output data;

[0012] The second test output data is compared with the control group output data to obtain a second comparison result, and the fault tolerance status of the first FPGA state machine is determined according to the second comparison result.

[0013] In some embodiments, the step of inputting the test data to be tested into a first FPGA state machine for flipping and outputting to obtain first test output data includes:

[0014] Determine flip configuration information;

[0015] According to the flip configuration information, the test data to be tested is input into the first FPGA state machine for flip output to obtain the first test output data.

[0016] In some embodiments, the determining the flip configuration information includes:

[0017] The flip configuration information is determined to be register flip start time, register flip duration, and register bit flip information.

[0018] In some embodiments, the step of inputting the test data to be tested into the first FPGA state machine for flipping and outputting to obtain the first test output data according to the flip configuration information includes:

[0019] Converting the test data to be tested into binary test data to be tested;

[0020] Converting the register bit flip information data into binary register bit flip information data, wherein the binary register bit flip information data has a one-to-one correspondence with the bit width of the binary test data to be tested;

[0021] The binary test data to be tested is inverted according to the binary register flip information data to obtain the first test output data.

[0022] In some embodiments, comparing the first test output data with the control group output data and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result includes:

[0023] When the first comparison result is that the first test output data and the control group output data are completely identical, determining that the first output state is a normal state;

[0024] When the data and the data volume of the first test output data and the control group output data are different, determining that the first output state is data output abnormality;

[0025] When the first comparison result is that the first test output data has no data output, it is determined that the first output state is a state machine flip abnormal state.

[0026] In some embodiments, when the first output state is that the first test output data and the control group output data are inconsistent, re-inputting the test data to be tested into the first FPGA state machine for flipping output to obtain second test output data includes:

[0027] According to the first output state, resetting the flip configuration information of the first FPGA state machine to zero;

[0028] According to the reset flip configuration information, the test data to be tested is input into the first FPGA state machine to output second test output data.

[0029] In some embodiments, comparing the second test output data with the control group output data and obtaining a second comparison result, and determining the fault tolerance of the first FPGA state machine according to the second comparison result includes:

[0030] When the second comparison result is that the second test output data and the control group output data are completely identical, it is determined that the first FPGA state machine has recovered to a normal state after being affected by the flip;

[0031] When the second comparison result is that the second test output data is inconsistent with the control group output data, it is determined that the first FPGA state machine cannot recover to a normal state after being affected by the flip.

[0032] A copy module, used for obtaining the test data to be tested, and copying the test data to be tested to obtain the control group data to be tested;

[0033] A first data output module is used to input the test data to be tested into the first FPGA state machine for flipping output to obtain first test output data, and input the control group data to be tested into the second FPGA state machine for direct output to obtain control group output data;

[0034] A first output state determination module, used for comparing the first test output data with the control group output data, obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result;

[0035] A second data output module, for re-inputting the test data to be tested into the first FPGA state machine for output to obtain second test output data when the first output state is that the first test output data and the control group output data are inconsistent;

[0036] The second output state determination module is used to compare the second test output data with the control group output data, and obtain a second comparison result, and determine the fault tolerance status of the first FPGA state machine according to the second comparison result.

[0037] In a third aspect, the present invention further provides an electronic device, comprising: a processor and a memory;

[0038] The memory stores a computer-readable program executable by the processor;

[0039] When the processor executes the computer-readable program, the steps in the fault tolerance testing method described above are implemented.

[0040] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in the fault tolerance testing method as described above.

[0041] Compared with the prior art, the beneficial effects of the present invention include: firstly obtaining test data to be tested, and copying the test data to be tested to obtain control group data to be tested; then inputting the test data to be tested into a first FPGA state machine for flipping output to obtain first test output data, and inputting the control group data to be tested into a second FPGA state machine for direct output to obtain control group output data; then comparing the first test output data with the control group output data, and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result; when the first output state is that the first test output data and the control group output data are inconsistent, re-inputting the test data to be tested into the first FPGA state machine for flipping output to obtain second test output data; then comparing the second test output data with the control group output data, and obtaining a second comparison result, and determining the fault tolerance of the first FPGA state machine according to the second comparison result; by adopting a combination of software and hardware, simulating a single-particle flip fault in a state machine register in an FPGA, the effectiveness of the existing fault-tolerant technology of the test state machine is tested, and the test cost is low and is not affected by the test environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A flowchart of an embodiment of a fault tolerance testing method provided by the present invention;

[0043] Figure 2 A flowchart of an embodiment of step S102 in the fault tolerance testing method provided by the present invention;

[0044] Figure 3 A flowchart of an embodiment of step S202 in the fault tolerance testing method provided by the present invention;

[0045] Figure 4 A flowchart of an embodiment of step S103 in the fault tolerance testing method provided by the present invention;

[0046] Figure 5 A flowchart of an embodiment of step S104 in the fault tolerance testing method provided by the present invention;

[0047] Figure 6 A flowchart of an embodiment of step S105 in the fault tolerance testing method provided by the present invention;

[0048] Figure 7 A schematic diagram of an embodiment of a fault tolerance testing device provided by the present invention;

[0049] Figure 8 A schematic diagram of an operating environment of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] The fault tolerance test method, device, equipment or computer-readable storage medium involved in the present invention can be used in an FPGA state machine. The method, device, equipment or computer-readable storage medium involved in the present invention can be integrated with the above system or can be relatively independent.

[0052] This embodiment provides a fault tolerance testing method, which can be executed by an FPGA state machine device, specifically, by one or more processors of the device. Figure 1 is a flowchart of a fault tolerance testing method provided by an embodiment of the present invention, please refer to Figure 1 , the fault tolerance testing method includes the following steps:

[0053] S101, obtaining test data to be tested, and copying the test data to be tested to obtain control group data to be tested;

[0054] S102, inputting the test data to be tested into the first FPGA state machine for flipping output to obtain first test output data, and inputting the control group data to be tested into the second FPGA state machine for direct output to obtain control group output data;

[0055] S103, comparing the first test output data with the control group output data, and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result;

[0056] S104, when the first output state is that the first test output data and the control group output data are inconsistent, re-inputting the test data to be tested into the first FPGA state machine for output to obtain second test output data;

[0057] S105 . Compare the second test output data with the control group output data, obtain a second comparison result, and determine the fault tolerance status of the first FPGA state machine according to the second comparison result.

[0058] It should be noted that in step S101, the test data is sent by the upper computer, wherein the upper computer refers to a computer that can directly issue control commands, which can be any one of PC / host computer / master computer / uppercomputer, and various signal changes can be displayed on the screen.

[0059] Specifically, the test data to be tested is copied to form the control group data to be tested. The method and form of the copying are not limited, as long as the test data to be tested and the control group data to be tested can be completely consistent.

[0060] It should be noted that, in step S102, the first test output data and the control group output data are output via different modules, and the control group output data is the output data of the state machine in a normal state.

[0061] It should be noted that, in step S103, the first comparison result is obtained by the data comparison module comparing the first test output data and the control group output data one by one.

[0062] When the first output state is that the first test output data and the control group output data are inconsistent, in step S104, it means that the last flip test on the FPGA state machine was successful, causing a flip failure in the FPGA state machine, and it is necessary to analyze the fault tolerance of the FPGA state machine; specifically, the first test data to be tested is input again into the first FPGA state machine that has the fault, and the FPGA state machine is no longer flipped this time, that is, the flip configuration information is set to zero, and the fault tolerance of the FPGA state machine is judged by the second test output data.

[0063] In this embodiment, by combining hardware and software, a single-particle flip in the simulation space impacts the FPGA state machine, causing a flip failure in the state machine, and analyzing the fault tolerance of the state machine. Specifically, after the first test data passes through the state machine with an added flip control module, the output first test output data will be affected by the flip control module, and this influence may be varied; the control group test data is output through the original state machine to obtain the control group output data, wherein there is a difference between the first test output data and the control group output data, and this difference reflects the simulated single-particle flip failure.

[0064] In some embodiments, see Figure 2 , the step of inputting the test data to be tested into the first FPGA state machine for flipping output to obtain the first test output data comprises:

[0065] S201, determining flip configuration information;

[0066] S202 , input the test data to be tested into the first FPGA state machine according to the flip configuration information, perform flip output, and obtain first test output data.

[0067] It should be noted that, in this embodiment, the flip information is recorded by hardware, and when the state machine is working, the flip output is performed according to the configured flip configuration information.

[0068] In some embodiments, the determining the flip configuration information includes:

[0069] The flip configuration information is determined to be register flip start time, register flip duration, and register bit flip information.

[0070] It should be noted that the register flip start time indicates the time point from which the flip starts, that is, the start time of the single-particle impact state machine register, and the corresponding state machine register is flipped. The timer is represented by a counter. After each clock cycle, the number of the counter is increased by one to represent the time. When the data to be tested enters the test system, the timer starts timing until the data is processed. The register flip duration is the time to control the duration of the flip, that is, the duration of the simulated particle impact. The flip duration is also represented by a counter; the register bit flip information corresponds to the bit width of the state machine register, that is, it simulates the specific potential affected by the single-particle impact.

[0071] Among them, after the test system processes the data to be tested, the counter is cleared.

[0072] It should be noted that in the process of simulating a single-particle flip, due to the change in the value of the state machine register, the state machine will jump to the state corresponding to the value and execute the statements in the state, which may cause data processing disorder or even failure of the test system, that is, the test system is impacted by a single particle and fails.

[0073] In some embodiments, see Figure 3 , the step of inputting the test data to be tested into the first FPGA state machine for flipping and outputting to obtain the first test output data according to the flip configuration information includes:

[0074] S301, converting the test data to be tested into binary test data to be tested;

[0075] S302, converting the register bit flip information data into binary register bit flip information data, wherein the binary register bit flip information data has a one-to-one correspondence with the bit width of the binary test data to be tested;

[0076] S303 , inverting the binary test data to be tested according to the binary register flip information data to obtain first test output data.

[0077] In this embodiment, it should be noted that a single particle upset is a phenomenon in which a single high-energy particle in the universe is injected into the sensitive area of ​​a semiconductor device, causing the device logic state to flip. For a state machine register, the phenomenon is generally that a certain bit of the register is inverted, causing the state machine to jump to an incorrect state, resulting in failure of data transmission or processing in the lower computer, and outputting erroneous data. The flip control module added in the test system simulates a single particle flip fault and performs an inversion operation on a specified bit in the state machine register within a configured time.

[0078] Specifically, in this embodiment, the bit width of one of the state machine registers is 6 bits, so the effective bit width of the register bit flip information is also 6 bits, and the specified bit of the register is inverted according to 6 bits; in another embodiment of the present invention, when the value of the register bit flip information is 001000 bits, the third bit of the register from left to right is inverted.

[0079] In some embodiments, see Figure 4 , comparing the first test output data with the control group output data and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result, including:

[0080] S401: when the first comparison result is that the first test output data and the control group output data are completely identical, determining that the first output state is a normal state;

[0081] S402: when the data and data volume of the first test output data and the control group output data are different, determining that the first output state is data output abnormality;

[0082] S403: When the first comparison result is that the first test output data has no data output, determine that the first output state is a state machine flip abnormal state.

[0083] It should be noted that in step S401, under normal conditions, it indicates that the set flip configuration information has no effect on the corresponding state machine register, and the serial port feeds back byte data indicating this condition to the host computer, such as 8'h59, and the host computer resets the new flip configuration information for the next test.

[0084] Specifically, in this embodiment, the new flip configuration information is set as follows: register flip start time 32'h0000020a, register flip duration 16'h00b1 and register bit flip information 32'h00000004; specifically, when the first counter counts to 522, i.e. 32'h0000020a, the state machine register starts to flip, and the second counter representing the flip duration starts counting; if the value of the state machine register is 5'b00100 at this time, the next clock will flip it to 5'b00000, and execute the statement in the corresponding state of the state machine register; before the second counter counts to 177, i.e. 16'h00b1, each clock will flip the third bit from right to left of the register and execute the corresponding statement. The data output by the test project is compared in the data comparison module.

[0085] It should be noted that in step S402, in this state, it indicates that the flip configuration information set this time causes an error in the output transmission, and byte data indicating this situation, such as 8'hae, is fed back to the host computer through the serial port.

[0086] It should be noted that the serial port data is only used to inform the host computer of the status and can be changed as needed without restriction.

[0087] It should be noted that in step S403, the result shows that the flip configuration information set this time causes data errors, that is, the flip configuration information successfully simulates the system being hit by a single particle and causing a failure. The serial port feeds back byte data representing this situation to the host computer, such as 8'h5e, and the host computer resets the new flip configuration information for the next test.

[0088] It should be noted that, in step S402 and step S403, the first output state has two different manifestations, and both are flip faults of the state machine.

[0089] In some embodiments, see Figure 5 , when the first output state is that the first test output data and the control group output data are inconsistent, re-inputting the test data to be tested into the first FPGA state machine for flipping output to obtain second test output data, including:

[0090] S501. Reset the flip configuration information of the first FPGA state machine to zero according to the first output state;

[0091] S502: According to the reset flip configuration information, the test data to be tested is input into the first FPGA state machine to output second test output data.

[0092] It should be noted that when the first output state is that the first test output data and the control group output data are inconsistent, it indicates that the current test has caused a flip failure in the state machine. In order to further analyze the fault tolerance of the state machine to the current fault, the configuration information is set to 0, that is, the information that does not cause flipping is set, and then the test data to be tested is input into the state machine where the fault occurs and outputs normally, and the second test output data is obtained. The fault tolerance of the state machine to the fault is analyzed through the second output data.

[0093] In some embodiments, see Figure 6 , comparing the second test output data with the control group output data and obtaining a second comparison result, and determining the fault tolerance of the first FPGA state machine according to the second comparison result, including:

[0094] S601: When the second comparison result is that the second test output data and the control group output data are completely identical, it is determined that the first FPGA state machine has recovered to a normal state after being affected by the flip;

[0095] S602: When the second comparison result is that the second test output data is inconsistent with the control group output data, it is determined that the first FPGA state machine cannot recover to a normal state after being affected by the flip.

[0096] Under the premise of knowing the state machine failure, the next test on the state machine will obtain two results in steps S601 and S602. Among them, when the result is that the second experimental output data in step S602 is inconsistent with the output data of the control group, the state machine can be tested again. At this time, the flip configuration information is still set to 0, that is, the state machine does not flip. If the output data after the second test is consistent with the output data of the control group, it means that the state machine can return to normal after a long period of time, has a certain anti-flip ability, and has good fault tolerance. Then set new flip configuration information and perform a new test on the state machine to verify its fault tolerance to other faults; if the output data after the second test is inconsistent with the output data of the control group, it means that the state machine failure still cannot return to normal after a period of time, and multiple tests can be continued for detection until the state machine returns to normal or the number of tests reaches the set maximum number, where the number of tests is generally set to 5 times at most. It can be understood that the number of tests is not limited and can be set multiple times according to needs.

[0097] Based on the above fault tolerance testing method, the embodiment of the present invention also provides a fault tolerance testing device 700. Figure 7As shown, the device includes: a copy module 710, a first data output module 720, a first output state determination module 730, a second data output module 740, and a second output state determination module 750.

[0098] A copy module 710 is used to obtain the test data to be tested, and copy the test data to be tested to obtain the control group data to be tested;

[0099] The first data output module 720 is used to input the test data to be tested into the first FPGA state machine for flipping output to obtain first test output data, and input the control group data to be tested into the second FPGA state machine for direct output to obtain control group output data;

[0100] A first output state determination module 730, configured to compare the first test output data with the control group output data, obtain a first comparison result, and determine a first output state of the first FPGA state machine according to the first comparison result;

[0101] A second data output module 740 is used for re-inputting the test data to be tested into the first FPGA state machine for output to obtain second test output data when the first output state is that the first test output data and the control group output data are inconsistent;

[0102] The second output state determination module 750 is used to compare the second test output data with the control group output data and obtain a second comparison result, and determine the fault tolerance status of the first FPGA state machine according to the second comparison result.

[0103] In this embodiment, first, the test data to be tested is obtained, and the test data to be tested is copied to obtain the control group data to be tested; then, the test data to be tested is input into the first FPGA state machine for flipping output to obtain the first test output data, and the control group data to be tested is input into the second FPGA state machine for direct output to obtain the control group output data; then, the first test output data and the control group output data are compared, and a first comparison result is obtained, and a first output state of the first FPGA state machine is determined according to the first comparison result; when the first output state is that the first test output data and the control group output data are inconsistent, the test data to be tested is re-input into the first FPGA state machine for flipping output to obtain the second test output data; then, the second test output data and the control group output data are compared, and a second comparison result is obtained, and the fault tolerance of the first FPGA state machine is determined according to the second comparison result; by adopting a combination of software and hardware, a single-particle flip fault in the state machine register in the FPGA is simulated to test the effectiveness of the existing fault-tolerant technology of the state machine, and the test cost is low and is not affected by the test environment.

[0104] Based on the above fault tolerance test method, the embodiment of the present invention also provides a fault tolerance test electronic device, which can be a computing device such as a mobile terminal, a desktop computer, a notebook, a palm computer, and a server. Figure 8 As shown, the electronic device includes a processor 801 , a memory 802 and a display 803 . Figure 8 Only some components of the electronic device are shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0105] In some embodiments, the memory 802 may be an internal storage unit of the electronic device, such as a hard disk or memory of the electronic device. In other embodiments, the memory 802 may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory 802 may also include both an internal storage unit of the electronic device and an external storage device. The memory 802 is used to store application software and various types of data installed in the electronic device, such as program codes for installing the electronic device. The memory 802 may also be used to temporarily store data that has been output or is to be output. In one embodiment, a fault tolerance test program 804 is stored on the memory 802, and the fault tolerance test program 1000 may be executed by the processor 801, thereby implementing the test of each embodiment of the present invention.

[0106] In some embodiments, the processor 801 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run program codes or process data stored in the memory 802, such as executing a fault tolerance testing method.

[0107] In some embodiments, the display 803 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 803 is used to display information on the fault tolerance test device and to display a visual user interface. The components 801-803 of the electronic device communicate with each other via a system bus.

[0108] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method for testing fault tolerance of a state machine as described above is implemented.

[0109] Generally speaking, the computer instructions for implementing the method of the present invention can be carried by any combination of one or more computer-readable storage media. Non-transitory computer-readable storage media can include any computer-readable media except for the signal itself that is temporarily propagating.

[0110] Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device.

[0111] Computer program code for performing the operation of the present invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages, in particular, Python language suitable for neural network computing and platform frameworks based on TensorFlow, PyTorch, etc. can be used. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0112] In summary, the fault tolerance test method, device, electronic device and storage medium provided by the present invention first obtain test data to be tested, copy the test data to be tested to obtain control group data to be tested; then input the test data to be tested into the first FPGA state machine for flipping output to obtain first test output data, and input the control group data to be tested into the second FPGA state machine for direct output to obtain control group output data; then compare the first test output data with the control group output data, and obtain a first comparison result, and determine the first output state of the first FPGA state machine according to the first comparison result; when the first output state is that the first test output data and the control group output data are inconsistent, re-input the test data to be tested into the first FPGA state machine for flipping output to obtain second test output data; then compare the second test output data with the control group output data, and obtain a second comparison result, and determine the fault tolerance of the first FPGA state machine according to the second comparison result; by adopting a combination of software and hardware, a single particle flip fault in the state machine register in the FPGA is simulated to test the effectiveness of the existing fault tolerance technology of the state machine, and the test cost is low and is not affected by the test environment.

[0113] Of course, those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware (such as a processor, a controller, etc.) through a computer program, and the program can be stored in a computer-readable storage medium, and the program can include the processes of the above-mentioned method embodiments when executed. The storage medium can be a memory, a disk, an optical disk, etc.

[0114] The specific implementation of the present invention described above does not constitute a limitation on the protection scope of the present invention. Any other corresponding changes and modifications made based on the technical concept of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A fault tolerance testing method, characterized in that: The following steps are involved: Acquire test data to be tested, and copy the test data to be tested to obtain control group data to be tested; Determine flip configuration information; convert the test data to be tested into binary test data to be tested; convert register bit flip information data into binary register bit flip information data, wherein the binary register bit flip information data has a one-to-one correspondence with the bit width of the binary test data to be tested; invert the binary test data to be tested according to the binary register flip information data, and input the inverted binary test data to be tested into the first FPGA state machine for output to obtain first test output data, and input the test control group data into the second FPGA state machine for direct output to obtain control group output data; Comparing the first test output data with the control group output data, and obtaining a first comparison result, and determining a first output state of a first FPGA state machine according to the first comparison result; When the first output state is that the first test output data and the control group output data are inconsistent, the configuration information is set to 0, and the test data to be tested is re-input into the first FPGA state machine for output to obtain the second test output data; Comparing the second test output data with the control group output data, and obtaining a second comparison result; When the data output from the second test is inconsistent with the output data of the control group, the flip configuration information is set to 0 again. If the output data after the second test is consistent with the output data of the control group, it means that the state machine can return to normal after a long period of time; if the output data after the second test is inconsistent with the output data of the control group, it means that the fault of the state machine still cannot return to normal after a period of time, then continue to perform multiple tests for detection until the state machine returns to normal or the number of tests reaches the set maximum number of times.

2. The fault tolerance testing method according to claim 1, characterized in that: The determining of the flip configuration information includes: The flip configuration information is determined to be register flip start time, register flip duration, and register bit flip information.

3. The fault tolerance testing method according to claim 1, characterized in that: The step of comparing the first test output data with the control group output data and obtaining a first comparison result, and determining a first output state of the first FPGA state machine according to the first comparison result includes: When the first comparison result is that the first test output data and the control group output data are completely identical, determining that the first output state is a normal state; When the data and the data volume of the first test output data and the control group output data are different, determining that the first output state is data output abnormality; When the first comparison result is that the first test output data has no data output, it is determined that the first output state is a state machine flip abnormal state.

4. The fault tolerance testing method according to claim 3, characterized in that: When the first output state is that the first test output data and the control group output data are inconsistent, the test data to be tested is re-inputted into the first FPGA state machine for flipping output to obtain second test output data, including: According to the first output state, resetting the flip configuration information of the first FPGA state machine to zero; According to the reset flip configuration information, the test data to be tested is input into the first FPGA state machine to output second test output data.

5. The fault tolerance testing method according to claim 3, characterized in that: The step of comparing the second test output data with the control group output data and obtaining a second comparison result, and determining the fault tolerance status of the first FPGA state machine according to the second comparison result includes: When the second comparison result is that the second test output data and the control group output data are completely identical, it is determined that the first FPGA state machine has recovered to a normal state after being affected by the flip; When the second comparison result is that the second test output data is inconsistent with the control group output data, it is determined that the first FPGA state machine cannot recover to a normal state after being affected by the flip.

6. A fault tolerance testing device, characterized in that: include: A copy module, used for obtaining the test data to be tested, and copying the test data to be tested to obtain the control group data to be tested; A first data output module is used to determine the flip configuration information; convert the test data to be tested into binary test data to be tested; convert the register bit flip information data into binary register bit flip information data, wherein the binary register bit flip information data has a one-to-one correspondence with the bit width of the binary test data to be tested; invert the binary test data to be tested according to the binary register flip information data, and input the inverted binary test data to be tested into the first FPGA state machine for output to obtain the first test output data, and input the test control group data to be tested into the second FPGA state machine for direct output to obtain the control group output data; A first output state determination module, used for comparing the first test output data with the control group output data, obtaining a first comparison result, and determining a first output state of a first FPGA state machine according to the first comparison result; A second data output module, used for setting the configuration information to 0 when the first output state is that the first test output data and the control group output data are inconsistent, and re-inputting the test data to be tested into the first FPGA state machine for output to obtain second test output data; Comparing the second test output data with the control group output data, and obtaining a second comparison result; The second output state determination module is used to set the flip configuration information to 0 again when the second test data is inconsistent with the output data of the control group. If the output data after the second test is consistent with the output data of the control group, it means that the state machine can return to normal after a long period of time; if the output data after the second test is inconsistent with the output data of the control group, it means that the fault of the state machine still cannot return to normal after a period of time, then continue to perform multiple tests for detection until the state machine returns to normal or the number of tests reaches the set maximum number of times.

7. An electronic device, characterized in that: comprising a memory and a processor, wherein: The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the fault tolerance testing method described in any one of claims 1 to 5 above.

8. A computer-readable storage medium, characterized in that: Used to store computer-readable programs or instructions, which, when executed by a processor, can implement the steps of the fault tolerance testing method described in any one of claims 1 to 5 above.

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