A SHA-256 hardware optimization design method based on folding

Abstract

The present invention relates to a SHA-256 hardware optimization design method based on folding. In order to improve the operation speed of the SHA-256 algorithm circuit and increase the throughput, and reduce the chip area required by the algorithm. The present invention uses a folding method to divide the rescheduled round calculation critical path into two stages with lower delay; a 4-2 compressor is reused to replace the five-operand addition operation in the original critical path. The present invention realizes the high-speed operation and high throughput of SHA-256 hardware implementation under the condition of maintaining high efficiency, and occupies less chip area.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits and relates to a SHA-256 hardware optimization design method based on folding. Background Art

[0002] The secure hash algorithm generates a fixed-length summary from messages or programs of different lengths, giving the message a unique "fingerprint". The message summary corresponds to a unique message, and the original message cannot be deduced from the summary, so it has strong security. The secure hash function SHA was designed by the US NIST and NSA. The SHA-256 algorithm generates a 256-bit hash value, which has higher security and collision resistance than previous hash algorithms and is currently widely used in practice.

[0003] There are many methods for hardware implementation of SHA-256 algorithm, aiming to improve the algorithm's operation speed or reduce chip area and power consumption. Common optimization algorithms include pipelining, un-rolling, folding and rescheduling. The existing rescheduling method for round calculation is a SHA-256 hardware implementation method that can use a higher clock frequency. This algorithm shortens the critical path delay of the round calculation process by rescheduling the update process of the intermediate hash value, so it has a very high throughput.

[0004] The folding method is a design method for reducing circuit power consumption. This method uses the repetitiveness of some computing units on the critical path of the algorithm to "fold" the operation process between two registers into two or more operation processes of the same form, thereby maximizing the reuse of hardware resources on the circuit and reducing the chip area required for the algorithm.

[0005] In order to improve the operation speed of SHA-256 algorithm circuit and increase the throughput, a SHA-256 hardware optimization design method based on folding is proposed, which can greatly improve the operation speed while having high throughput without occupying too much chip area. Summary of the invention

[0006] The purpose of the present invention is to provide a SHA-256 hardware optimization design method based on folding.

[0007] The present invention uses a folding method to divide the rescheduled round calculation critical path into two stages with lower delays; reuses a 4-2 compressor to replace the five-operand addition operation in the original critical path. Specifically, it includes the following steps:

[0008] The folding method is used to divide the critical path of the rescheduled round calculation into two stages with lower latency:

[0009] The critical path of the SHA-256 round calculation is the update of register A. k+1 =∑ 0 (A k )+Maj(A k ,B k ,C k )+P k +S k +N k , where k is the number of rounds of calculation, A k represents the value stored in register A in the kth round of calculation; ∑ 0 (A k ) and Maj(A k ,B k ,C k ) is the result of performing a logical operation on the value in the register.

[0010] Using the folding method, the addition operation containing five operands on the critical path is divided into two stages. In the first stage, S k 、N k , P k The sum of is converted into two numbers As k and Ac k , stored in the new registers As and Ac, the second stage calculates the value stored in the new register As k ,Ac k and∑ 0 (A k )、Maj(A k +B k +C k ) and; registers S, N, and P store each round of S k 、N k and P k The value of .

[0011] The multiplexing of a 4-2 compressor to replace the five-operand addition operation in the original critical path is specifically as follows:

[0012] The addition operation on the critical path is replaced by a 4-2 compressor. In the two stages of the operation, the input of the 4-2 compressor in the first stage is S k 、N k and P k , the output is As k and Ac k ; The input of the second stage 4-2 compressor is ∑ 0 (A k )、Maj(A k +B k +C k ),As k and Ack , the output is As k+1 and Ac k+1 Four two-to-one multiplexers are used to select the input of the two-stage 4-2 compressor. Since there are only three valid input values ​​in the first stage, the fourth multiplexer selects a 0 value as input in the first stage. Registers As and Ac store As respectively. k and Ac k The values ​​of , and their sum is stored in register A in the first stage of each round.

[0013] The present invention realizes high-speed operation (clock frequency reaches 366MHz) and high throughput (1990Mbps) of SHA-256 hardware while maintaining high efficiency (the algorithm hardware efficiency of this solution is 1.86Mbps / Slice). It realizes high throughput and small chip area while greatly improving the operation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The critical path calculated for the original rescheduling plan round;

[0015] Figure 2 This is a flowchart for realizing the key path of the present invention. DETAILED DESCRIPTION

[0016] The present invention is further described below in conjunction with the accompanying drawings.

[0017] like Figure 1 As shown in , the critical path of the original rescheduling scheme round calculation has a delay equal to the sum of the delays of two CSAs and one adder. Figure 2 As shown, the critical path delay of the present invention is the sum of the delays of the multiplexer and the 4-2 compressor.

[0018] A SHA-256 hardware optimization design method based on folding is proposed. The critical path is divided into two stages using the folding method:

[0019] Registers S, N, and P store the S of each round of calculation respectively. k 、N k , P k The value of ∑ 0 To calculate ∑ 0 (A k ) logic circuit, Maj is the calculation of Maj(A k +B k +C k ) logic circuit. Register S and logic circuit ∑ 0The output of is connected to the input of multiplexer m0, the output of register N and logic circuit Maj is connected to the input of multiplexer m1, and the output of register P is connected to one input of multiplexer m2. The multiplexer implements a two-fold multiplexing method. In the first stage of the operation, m0 selects the output of register S, m1 selects the output of register N, and m2 selects the output of register P. Since there are only three operands in this stage, the fourth multiplexer m3 selects the value 0; in the second stage of the operation, m0 selects ∑ 0 output, m1 selects the output of Maj.

[0020] The multiplexing of a 4-2 compressor to replace the five-operand addition operation in the original critical path is specifically as follows:

[0021] A 4-2 compressor is used to replace the adder in the original circuit. The input of the 4-2 compressor is the output of four multiplexers m0, m1, m2 and m3, which are used to receive different input values ​​at different stages. The output of the 4-2 compressor is two registers As and Ac. Registers As and Ac store As respectively. k and Ac k The value of .

[0022] The outputs of registers As and Ac are connected to multiplexers m2 and m3 respectively. In the second stage of the operation, the input of multiplexer m2 is the output of register As, and the input of multiplexer m3 is the output of register Ac.

[0023] The scheme of combining 4-2 compressor and multiplexer adopted by the present invention realizes "folding" the key path of SHA-256 round calculation hardware circuit into two identical operations, reducing the path delay to 36% of the original scheme; the highest available clock frequency of the circuit can reach 366MHz, and the throughput is 1990Mbps. The algorithm efficiency of the circuit is 1.86Mbps / Slice. The comparison with the original scheme is shown in Table 1.

[0024] Table 1

[0025] plan Clock frequency (MHz) Throughput (Mbps) Efficiency (Mbps / Slice) Original rescheduling plan 131.76 881.1 1.82 The present invention 366 1990 1.86

Claims

1. A SHA-256 hardware optimization design method based on folding, characterized by: The folding method is used to divide the rescheduled round calculation critical path into two stages with lower latency; a 4-2 compressor is reused to replace the five-operand addition operation in the original critical path; the specific steps include: The folding method is used to divide the critical path of the rescheduled round calculation into two stages with lower latency: The critical path of the SHA-256 round calculation is the update of register A. k+1 =∑0(A k )+Maj(A k ,B k ,C k )+P k +S k +N k , where k is the number of rounds of calculation, A k represents the value stored in register A in the kth round of calculation; ∑0(A k ) and Maj(A k ,B k ,C k ) is the result of performing a logical operation on the value in the register; Using the folding method, the addition operation containing five operands on the critical path is divided into two stages. In the first stage, S k 、N k , P k The sum of is converted into two numbers As k and Ac k , stored in the new registers As and Ac, the second stage calculates the value stored in the new register As k ,Ac k and∑0(A k )、Maj(A k +B k +C k ) and; registers S, N, and P store each round of S k 、N k and P k The value of The multiplexing of a 4-2 compressor to replace the five-operand addition operation in the original critical path is specifically as follows: The addition operation on the critical path is replaced by a 4-2 compressor. In the two stages of the operation, the input of the 4-2 compressor in the first stage is S k 、N k and P k , the output is As k and Ac k ; The input of the second stage 4-2 compressor is ∑0(A k )、Maj(A k +B k +C k ),As k and Ac k , the output is As k+1 and Ac k+1 ; Four two-to-one multiplexers are used to select the input of the two-stage 4-2 compressor. Since there are only three valid input values ​​in the first stage, the fourth multiplexer selects a 0 value as input in the first stage; registers As and Ac store As respectively. k and Ac k The values ​​of , and their sum is stored in register A in the first stage of each round.

Images