Temperature-informed memory refresh

Abstract

Apparatus and techniques for temperature-informed memory refresh are described herein. Temperature data may be updated in response to a memory component write performed at an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element may be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh may be performed on the memory component element.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 201980071437.5, application date September 19, 2019, and invention name “TEMPERATURE NOTIFIED MEMORY REFRESH”.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. application serial number 16 / 138,115, filed on September 21, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0005] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to temperature informed memory refresh. Background Art

[0006] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, nonvolatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0007] In one aspect, the present disclosure relates to a memory system comprising: a memory component comprising: a non-volatile memory portion comprising a plurality of memory component elements; and a volatile memory portion; and a processing device which is communicatively coupled to the memory component when in operation, the processing device performing operations comprising: when a single memory component element of the plurality of memory component elements is turned on: storing a write temperature counter of the single memory component element on the volatile memory portion; and updating the stored write temperature counter in response to a memory component write performed on the single memory component element at an extreme temperature outside a defined temperature window; and storing the write temperature counter on the non-volatile memory portion in response to the single memory component element being turned off.

[0008] On the other hand, the present disclosure relates to a method comprising: when a single memory component element among multiple memory component elements of a non-volatile memory portion of a memory component is turned on: storing a write temperature counter of the single memory component element on the volatile memory portion of the memory component; and updating the write temperature counter in response to a memory component write performed on the single memory component element at an extreme temperature outside a defined temperature window; and storing the write temperature counter on the non-volatile memory portion in response to the single memory component element being turned off.

[0009] In yet another aspect, the present disclosure relates to a non-transitory machine-readable medium comprising instructions which, when executed by a processing device, cause the processing device to perform operations comprising: when a single memory component element among a plurality of memory component elements of a non-volatile memory portion of a memory component is turned on: storing a write temperature counter for the single memory component element on the volatile memory portion of the memory component; and updating the write temperature counter in response to a memory component write performed on the single memory component element at an extreme temperature outside a defined temperature window; and storing the write temperature counter on the non-volatile memory portion in response to the single memory component element being turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of examples and not limitation, in the accompanying figures, in which like references indicate similar elements.

[0011] Figure 1 An example of an environment including a memory component according to some embodiments of the present disclosure is described.

[0012] Figure 2 Examples of super blocks according to some embodiments of the present disclosure are described.

[0013] Figure 3 An example of block write temperature tracking in a superblock according to some embodiments of the present disclosure is described.

[0014] Figure 4 An example of a data structure for implementing temperature informed memory refresh according to some embodiments of the present disclosure is described.

[0015] Figure 5 A flow chart illustrating a method for temperature informed memory refresh according to some embodiments of the present disclosure.

[0016] Figure 6is a block diagram illustrating an example computer system within which a set of instructions may be executed for causing a machine to perform any one or more of the methodologies discussed herein according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure relate to temperature-informed memory refresh in a memory subsystem. A memory subsystem is also referred to hereinafter as a "memory component." An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Typically, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request data to be retrieved from the memory subsystem.

[0018] In order to avoid cross-temperature events with minimal device (e.g., firmware, processing, etc.) overhead to the device, an extreme write temperature counter may be maintained at the Super Block level to identify refresh candidates. When write temperatures are acceptable (e.g., possibly correlated with read temperatures), refreshes (writing to new cells) maintain data integrity and reduce RBER (e.g., via write amplification) at the expense of wear on the cells themselves. Thus, excessive refresh activity results in waste of both cell program and erase cycles and processing (e.g., resulting in a performance impact on the flash device as resources are used to perform refreshes). The extreme write temperature counter provides an efficient way to sequence elements (e.g., blocks, Super Blocks, etc.) to minimize erroneous processing events due to cross-temperature issues while minimizing the number of refreshes used.

[0019] Although tracking can be performed at the frame, page, die, or other levels, superblocks provide an attractive aggregation of memory component elements with write temperature counters attached. Although memory devices permit write and read addressing at the page level and erase addressing at the block level, there are some practical difficulties in such fine-grained solutions. These difficulties may include addressing overhead for various tasks and operations including flash translation layer (FTL) table maintenance. To address these issues, blocks are typically aggregated into a single logical entity (e.g., superblock) where data is written. Traditionally, an aggregated block includes a block from each plane in each die of a memory array in a flash memory system. This arrangement provides some performance advantages, such as parallel execution of write commands across dies.

[0020] The clustered block concept allows fewer storage units to be tracked, relieving pressure on temperature counters and FTL tables and management. This can be important in resource-limited devices such as managed memory, where the available working memory (e.g., random access memory (RAM) to hold system state) is limited. Using super blocks as the basic operating unit in memory components provides the efficient resource management discussed above with respect to clustered block units, while allowing more efficient maintenance operations (e.g., reduced latency and reduced time to perform operations) and efficient device OP.

[0021] In an example, the technology described herein includes a measure for tracking data written at extreme temperatures with minimal memory size loss. Typically, a managed memory controller writes data to an open superblock. At any given time, there is typically a limited amount of available open superblocks. The ambient temperature is measured by the memory component during writing, and at the superblock level, the memory controller maintains one or two of a high write temperature counter (HWTC) and a low write temperature counter (LWTC). In an example, for each code (data word after applying an error correction code) written at high temperature, the HWTC increments. Similarly, for each codeword written at low temperature, the LWTC increments. In an example, after closing the superblock, the HWTC and LWTC are stored in the memory component (e.g., in a memory array relative to the RAM on the device). In an example, a single counter (e.g., an extreme write temperature counter (EXWTC)) may be incremented when a high or low temperature write occurs and stored in the memory component.

[0022] In an example, the counter may be reset (e.g., initialized to zero) when a Super Block is erased or newly opened. During periods of low activity of the memory component, such as when there are no pending read or write requests, the memory component may efficiently perform maintenance operations, such as refreshes of the Super Block. Since this time may be limited, a better return on refresh activity may be achieved by sequencing the Super Blocks so that those Super Blocks with higher extreme temperature write concentrations (e.g., with higher HWTC, LWTC, or EXWTC values) are refreshed first. Thus, Super Blocks with higher concentrations of data written at high or low temperatures are refreshed when the memory component temperature is acceptable. In an example, the sequencing may include: increasing the HWTC and LWTC to achieve a single value according to which the Super Blocks are sequenced; sequencing the HWTC and then using the LWTC to sequence among Super Blocks with the same HWTC value; or vice versa (e.g., sorting the LWTC first), or sorting the EXWTC. In an example, to reduce refreshes with minimal impact, if the resulting sequencing value does not exceed a threshold, the Super Block is not refreshed. In an example, write temperatures may be maintained in memory component metadata, enabling codewords marked with extreme temperatures (eg, high or low) to be selectively garbage collected, thereby avoiding full refreshes of superblocks or other memory component elements.

[0023] Figure 1 An example of an environment 100 including a memory system 110 according to some embodiments of the present disclosure is illustrated. The environment 100 is also illustrated as including a host device 105 configured to communicate with the memory system 110 through a communication interface. The host device 105 or the memory system 110 may be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.), to support processing, communication, or control of the product 150.

[0024] Memory system 110 includes a memory system controller 115 and memory components 120, which include, for example, multiple individual dies (e.g., a stack of three-dimensional (3D) memory dies) or other media (e.g., organized as an array). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of layers, physical pages, and correspondingly increasing the density of memory components (e.g., storage devices). In an example, memory system 110 may be a discrete memory or storage device component of host device 105. In other examples, memory system 110 may be part of an integrated circuit (e.g., a system on a chip (SOC), etc.) that is stacked with or otherwise includes one or more other components of host device 105.

[0025] One or more communication interfaces may be used to transfer data between the memory system 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Memory (UFS) interface, an eMMC interface, or a USB interface. TM interface, or one or more other connectors or interfaces. Host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to memory system 110. In some examples, host 105 may be a host computer having a reference Figure 6 The machine 600 may be a machine having some or all of the components discussed above.

[0026] The memory system controller 115 may receive instructions from the host 105 and may communicate with the memory component 120 to transfer data to (e.g., write or erase) or transfer data from (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory component 120. The memory system controller 115 may include circuitry or firmware, including one or more components or integrated circuits, among other things. For example, the memory system controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory component 120 and provide a translation layer between the host 105 and the memory system 110.

[0027] The memory manager 125 may include, among other things, circuitry or firmware, such as a plurality of components or integrated circuits associated with various memory management functions. For purposes of the present description, example memory operations and management functions will be described in the context of memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such memory management functions include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with the operation of a memory component, etc.), or generate device commands for the memory controller 135 or one or more other components of the memory system 110 (e.g., to implement various memory management functions).

[0028] The memory manager 125 may update the memory component element, for example, via hardware of the illustrated example of the refresh component 113, or via Figure 6The management function of the instruction execution of an instance of the refresh component shown above. As described above, refreshing incurs costs in terms of memory component element wear and processing time, which may increase power consumption and affect the user-perceived performance by delaying the execution of host requests when processing is complete. However, also as described above, refreshing during periods of acceptable ambient temperature can provide an efficient correction for cross-temperature issues by rewriting the data at an acceptable temperature when it was initially written at an extreme temperature. Again, the extreme temperature is a temperature outside the preset temperature range of device 110, and the acceptable temperature is within that range. Thus, as defined by the preset range, the extreme temperature may be too hot or too cold. The preset range can be adjusted for different usage scenarios. For example, if the average temperature of the operating environment is higher, such as in an injection molding factory, the preset range can be set higher than for other usage scenarios. In an instance, the preset range is defined by a series of read temperatures measured at device 110 and can be adjusted over time.

[0029] To implement temperature-notified refreshing, the memory manager 125 is arranged to update a temperature counter in response to a write to the memory component 120 that is executed at an extreme temperature. Here, a write is performed on the memory component elements in the memory component 120. In an instance, the memory component write is a codeword write. A codeword is the result of encoding a piece of data with, for example, an error correction code. Generally, a codeword is the smallest unit written to the memory component, but several codewords can be grouped to write a page, block, superblock, etc. In an instance, the memory component element is a superblock. Thus, whenever a codeword is written to a memory component element, the memory manager 125 compares the ambient temperature of device 110 with the preset range to determine whether the write is at an extreme temperature. If the write is at an extreme temperature, the counter for the memory component element is updated (e.g., incremented by one) to track these writes.

[0030] In an example, the temperature counter is 20 bits. In an example, in response to the erasure of the memory component element, the temperature counter is reset to zero. Therefore, when the memory component element no longer has valid data, the counter is reset to prepare to track new extreme temperature writes, and also to avoid unnecessary refreshing of invalid data. In an example, the extreme temperature is lower than the low write temperature threshold of the memory component 110. In an example, the temperature counter includes a low temperature write counter (LWTC). In an example, the extreme temperature is higher than the high write temperature threshold of the memory component 110. In an example, the temperature counter includes a high temperature write counter (HWTC). In an example, the extreme temperature is higher than the high write temperature threshold of the memory component 110 or lower than the low write temperature threshold of the memory component 110. In an example, the temperature counter includes an extreme temperature write counter (EXWTC). In general, when it is not important to know whether the write is during an extreme high temperature or an extreme low temperature, the EXWTC is a combination of the LWTC and the HWTC.

[0031] In an example, the temperature counter is stored separately from the memory component element. This example is different from storing one or more temperature counters in the metadata of the memory element itself, for example, through some super block data (which can also be implemented). In an example, in response to turning on the memory component element, the temperature counter is stored in the volatile memory portion of the memory component 110. The volatile portion enables fast updating of the counter without undue wear on the memory unit while the counter is likely to be changing. In an example, in response to turning off the memory component element, the temperature counter is stored in the memory component 120. Here, once the memory component element is no longer written to, the counter will no longer change, thereby allowing the counter to be saved to the memory component unit without significant side effects. One or more counters may be stored in the management table 130 described below and processed similarly to other counters (e.g., bad block counts, write counts, etc.) retained for, for example, super blocks or other memory component elements.

[0032] The memory manager 125 is arranged to sort memory component elements that are sorted above other memory component elements in the memory component 120 based on the temperature counters. Here, the memory component elements having temperature counters are organized in order based on the temperature counters. In an example, the sorting includes combining the LWTC and the HWTC to form a sorting value that is compared to the sorting values ​​calculated for the other memory component elements. Where the EXWTC is used instead of, or in addition to, the LWTC and the HWTC, the combined LWTC and the HWTC have a value equal to the EXWTC.

[0033] In an example, the memory manager 125 is arranged to exclude from the ranking memory component elements having corresponding temperature counters that do not exceed a minimum temperature-based refresh threshold. Thus, for each memory manager 125 in the body to rank the memory component elements, it has a ranking value that exceeds the minimum temperature-based refresh threshold. The minimum temperature-based refresh threshold is used to reduce refreshes that have little benefit to the performance of the device 110. Thus, the minimum temperature-based refresh threshold establishes a baseline where one or more extreme temperature counters will not trigger a refresh. In an example, the minimum temperature-based refresh threshold is based on the raw bit error rate (RBER) of the memory component. For example, if the average RBER of the super block exceeds the threshold when the sum of the HWTC and LWTC counters is greater than X, then the minimum temperature-based refresh threshold is set to X. In an example, the minimum temperature-based refresh threshold is the percentage of bytes in the memory component element that are written at extreme temperatures. For example, if more than 30% of the bytes are written at extreme temperatures, then the minimum temperature-based refresh threshold is met.

[0034] The memory manager 125 is arranged to perform a refresh on the memory component elements in response to the sort. In an example, the sort is performed in response to shutting down the memory component elements. Here, shutting down refers to a state in which data is no longer written to the memory component elements. For example, the shut down state can be transformed into a different state via garbage collection. After garbage collection, the memory component elements can be called "new" and can be used for writing. In an example, the sort is performed in response to an acceptable ambient temperature measurement on the device 110. In an example, the sort is performed in response to a storage metric (e.g., less than a minimum number of free memory component elements are available) or other management functions (e.g., performing or triggering garbage collection). The refresh is performed first on the memory component element with the highest counter value, and the refresh continues until the refresh is interrupted (e.g., by a request from the host 105), or an allocation of power or time is exceeded. Therefore, in an example, to perform the refresh, the memory manager 125 is arranged to copy the contents of the memory component elements to a new memory component element (e.g., a different and ready-to-write memory component element). In an example, the copying of the contents is performed in response to a non-extreme temperature (e.g., acceptable) of the new memory component element. In an example, the copying of the content is performed in response to a low utilization period of the memory component.

[0035] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory system 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory system controller 115). For example, the management tables 130 may include information about block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more memory cell blocks coupled to the memory system controller 115. In certain examples, if the number of errors detected for one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. The management tables 130 may, among other things, maintain counts of correctable or uncorrectable bit errors. In an example, the management tables 103 may include a translation table or an L2P map.

[0036] The memory controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory system 110 coupled to the memory system controller 115. The memory operations may be based on host commands (e.g., associated with wear leveling, error detection or correction, etc.), such as received from the host 105 or generated internally by the memory manager 125.

[0037] The memory controller 135 may include an error correction code (ECC) component 140, which may include, among other things, an ECC engine, or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory system 110 coupled to the memory system controller 115. The memory system controller 115 may be configured to effectively detect and recover from error occurrences (e.g., bit errors, operational errors, etc.) associated with various operations or data storage, while maintaining the integrity of data transferred between the host 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0038] Memory component 120 may include a number of memory cells arranged in, for example, multiple devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC memory component may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory component (storing two data bits per cell (i.e., 4 programmable states)) may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but has half the required write time and doubled program / erase (P / E) cycles compared to the corresponding TLC memory component. Other examples may include other numbers or arrangements. In some examples, the memory component, or portions thereof, may selectively operate in SLC mode, or in a desired MLC mode (e.g., TLC, QLC, etc.).

[0039] In operation, data is typically written to or read from memory system 110 in pages, and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. The data transfer size of memory system 110 is typically referred to as a page; while the data transfer size of the host is typically referred to as a sector.

[0040] Although a data page may include several bytes of user data (e.g., a data payload containing several data sectors) and its corresponding metadata, the size of the page often only refers to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may include 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) and metadata corresponding to the user data in multiple bytes (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0041] Different types of memory cells or memory arrays 120 may provide different page sizes, or may require different amounts of metadata associated therewith. For example, different memory component types may have different error rates, which may result in the need for different amounts of metadata to ensure the integrity of the data page (e.g., a memory component with a higher error rate may require more bytes of error correction code data than a memory component with a lower error rate). As an example, a multi-level cell (MLC) memory flash device may have a higher error rate compared to a corresponding single-level cell (SLC) memory flash device. Thus, an MLC device may require more metadata bytes for error data compared to the corresponding SLC device.

[0042] The techniques described herein use very little system memory and very little space in the memory component 120 (e.g., memory array) to track extreme temperature writes. Because the refresh (or selective garbage collection) occurs in the background, like many error handling processes, this technique does not affect the user-perceived performance of the memory system 110. In addition, because the memory system 110 already accesses ambient temperature information, memory component 120 element refreshes, and tracks super block data (e.g., erase counts, read counts, etc.), the techniques can be integrated in the memory system controller 115 without introducing costly changes to the memory system controller 115 design.

[0043] The efficiency of the codeword and superblock counters is very high. For example, assuming 20 bytes are allocated for HWTC and LWTC respectively, 16 million codewords can be tracked for each superblock, with 5 bytes allocated for each superblock. If 20 superblocks are open at any given time, the number of bytes of limited memory of the memory system used to track the temperature counters is 20 times the 5 bytes, or 100 bytes. If the memory component 120 has 1,000 superblocks, the total RAM usage of the memory system 110 requires approximately five thousand bytes.

[0044] Figure 2 245 and 250 are both full or full width super blocks spanning all four planes of all four dies. To illustrate the block index relationship between planes and dies, Figure 2 . Some blocks in each superblock are marked in . For example, superblock 245 includes blocks 205 and 215 of planes 225 and 230, respectively. In the example, the block index cannot be restarted between planes. Therefore, even if the block indexes for 205 and 215 are the first blocks in their respective planes, the block indexes are different. However, blocks 205 and 215 have the same indexes in die 235 as blocks 210 and 220 in die 240. Therefore, the block set only needs to specify the index within a single die, and these indexes are applied across all dies to form a superblock. In the example where the block indexing restarts within the plane, the superblock can be specified by a single index and a set of planes. Moreover, as described, each superblock 245 and 250 has at most one block for a unique combination of die and plane, but other examples may include multiple blocks per plane.

[0045] Figure 3An example of block write temperature tracking in a superblock according to some embodiments of the present disclosure is described. The bottom portion of the table illustrates writes with acceptable or extreme temperatures of the memory component during the write. The top portion of the table illustrates the change in the total bytes written, and the incrementing of the LWTC and HWTC counters corresponding to those writes. In the example, HWTC and LWTC counters are maintained for each superblock. Codewords written at high ambient temperatures are sorted as high temperature counts toward the HWTC, and codewords written at low ambient temperatures are sorted as low temperature counts toward the LWTC. After closing the superblock, the HWTC and LWTC are dumped to non-volatile memory (e.g., in a memory array). The process can be repeated for each open superblock. Subsequently, using these counter values, firmware running on a memory component (e.g., a memory system controller, a memory controller, or a memory manager) can take snapshots of the percentages of superblocks written at acceptable nominal temperatures, high temperatures, and low temperatures. These values ​​can then be used to selectively refresh superblocks to prevent future read errors caused by extreme cross-temperature conditions.

[0046] Figure 4 An example of a data structure for implementing temperature-informed memory refresh according to some embodiments of the present disclosure is illustrated. The data structure includes a Super Block Identifier field 405, and for each Super Block, records the percentage of bytes written at the Extreme Temperature Field 410. As illustrated, the records are sorted by the percentage of bytes written at the Extreme Temperature Field 410. The sorting is performed when the device is at an acceptable temperature. Blocks whose percentage of (HWTC+LWTC) writes versus acceptable temperature writes exceeds a refresh threshold 415 are marked for refresh (e.g., folding). These blocks are refresh candidates 420, while the remaining blocks 425 will not have a refresh performed based on the extreme temperature counter at this time.

[0047] The memory components may have a performance and RBER distribution established, for example, during manufacturing. As described above, the RBER may be a function of high and low write temperatures. Depending on the RBER and codeword rate, the refresh threshold 415 may be configured to maintain the RBER and performance distribution of the memory components. For example, if writing more than 25% of the Super Block at extreme temperatures degrades performance, the refresh threshold 415 is set at 25%.

[0048] Figure 5 Flowchart illustrating a method 500 for temperature-informed memory refresh according to an embodiment. The operations of the method 500 are implemented in electronic hardware, such as the one described above with respect to Figure 1 (e.g., memory system controller) and below with respect to Figure 6 (e.g., circuitry) describes electronic hardware.

[0049] At operation 505, a temperature counter is updated in response to a memory component write performed at an extreme temperature. Here, the write is performed on a memory component element in the memory component. In an example, the memory component write is a codeword write. In an example, the memory component element is a superblock.

[0050] In an example, the temperature counter is 20 bits. In an example, the temperature counter is reset to zero in response to erasure of the memory component element. In an example, the extreme temperature is below a low write temperature threshold of the memory component. In an example, the temperature counter comprises a low temperature write counter (LWTC). In an example, the extreme temperature is above a high write temperature threshold of the memory component. In an example, the temperature counter comprises a high temperature write counter (HWTC).

[0051] In an example, the temperature counter is stored separately from the memory component element. In an example, the temperature counter is stored in a volatile memory portion of the memory component in response to turning on the memory component element. In an example, the temperature counter is stored in the memory component in response to turning off the memory component element.

[0052] At operation 510, the memory component element is ranked above other memory component elements in the memory component based on the temperature counter. In an example, the ranking includes combining the LWTC and the HWTC to form a ranking value that is compared to the ranking values ​​calculated for the other memory component elements. In an example, the ranking value exceeds a minimum temperature-based refresh threshold. In an example, the minimum temperature-based refresh threshold is based on a raw bit error rate (RBER) of the memory component. In an example, the minimum temperature-based refresh threshold is a percentage of bytes in the memory component element that are written at an extreme temperature.

[0053] At operation 515, a refresh is performed on the memory component element in response to the sequencing. In an example, the sequencing is performed in response to shutting down the memory component element.

[0054] In an example, performing a refresh includes copying the contents of the memory component element to a new memory component element. In an example, copying the contents is performed in response to a non-extreme temperature of the new memory component element. In an example, copying the contents is performed in response to a low utilization period of the memory component.

[0055] Figure 6A block diagram of an example machine 600 according to some embodiments of the present disclosure is illustrated, on which any one or more of the techniques (e.g., methods) discussed herein may be executed. In alternative embodiments, the machine 600 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In an example, the machine 600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. In addition, although only a single machine is shown, the term "machine" should also be deemed to include any machine collection that executes a set (or multiple sets) of instructions individually or jointly to execute any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations.

[0056] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a set) of circuits implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members may be flexible over time and with underlying hardware variability. A circuit system includes components that can perform specific tasks individually or in combination when operating. In an example, the hardware of the circuit system can be designed in an unchangeable manner to perform specific operations (e.g., hard wiring). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetic, electrically movable placement of fixed centralized particles, etc.) to encode instructions for specific operations. When connecting physical components, the basic electrical properties of the hardware components are changed, such as from an insulator to a conductor, or vice versa. Instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create circuit system components in hardware via variable connections to perform parts of specific tasks when operating. Thus, the computer-readable medium is communicatively coupled to other components of the circuit system when the device is operating. In an example, any one of the physical components can be used in more than one component in more than one circuit system. For example, under operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time.

[0057] The machine (e.g., computer system) 600 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as memory system controller 115, etc.), a main memory 604, and a static memory 606, some or all of which may communicate with each other through an interconnect (e.g., a bus) 608. The machine 600 may further include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In an example, the display unit 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The machine 600 may additionally include a storage device (e.g., a drive unit) 616, a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 600 may include an output controller 628, such as a serial (e.g., Universal Serial Bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0058] The storage device 616 may include a machine-readable medium 622 on which is stored one or more sets of data structures or instructions 624 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein (e.g., refresh component 113). The instructions 624 may also reside, completely or at least partially, within the main memory 604, within the static memory 606, or within the hardware processor 602 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, the main memory 604, the static memory 606, or the storage device 616 may constitute the machine-readable medium 622.

[0059] Although machine-readable medium 622 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 624 .

[0060] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 600 and causing the machine 600 to perform any one or more of the techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable media examples may include solid-state memory, and optical and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles, the particles having a constant (e.g., stationary) mass. Thus, the centralized machine-readable medium is a non-transitory propagating signal. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory components (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory components; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0061] Instructions 624 (e.g., software, programs, operating systems (OS), etc.) or other data are stored on storage device 621 and can be accessed by memory 604 for use by processor 602. Memory 604 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage device than storage device 621 (e.g., SSD) which is suitable for long-term storage (including when in a "shutdown" condition). Instructions 624 or data for use by a user or machine 600 are typically loaded in memory 604 for use by processor 602. When memory 604 is full, virtual space of storage device 621 can be allocated to supplement memory 604; however, because storage device 621 is typically slower than memory 604 and write speeds are typically at least twice slower than read speeds, the use of virtual memory may greatly reduce the user experience due to storage device latency (compared to memory 604, such as DRAM). In addition, the use of storage device 621 for virtual memory may greatly reduce the usable service life of storage device 621.

[0062] Compared to virtual memory, virtual memory compression (e.g. The kernel feature "ZRAM") uses portions of memory as compressed block storage to avoid paging to storage 621. Paging occurs in compressed blocks until the data must be written to storage 621. Virtual memory compression increases the available size of memory 604 while reducing wear on storage 621.

[0063] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD TM) card, etc.). MMC devices include multiple parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are often components that can be removed and separated from the host device. In contrast, eMMC TM The device is attached to the circuit board and is seen as a component of the host device, with read speeds comparable to Serial ATA-based TM (Serial Advanced Technology (AT) Attachment, or SATA) SSD devices. However, the demand for mobile device performance continues to increase in order to fully enable virtual or augmented reality devices, take advantage of increased network speeds, etc. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices, which include a controller and firmware, use a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path to communicate with a host device, further promoting higher read / write speeds.

[0064] The instructions 624 may further be transmitted or received over a communication network 626 using a transmission medium via the network interface device 620 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network called The IEEE 802.11 series of standards, known as ), IEEE 802.16 family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, and other networks. In an example, network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 626. In an example, network interface device 620 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be taken to include any intangible media capable of storing, encoding, or carrying instructions for execution by machine 600, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0065] Example 1 is a memory system for temperature-informed memory refresh, the memory system comprising: a memory component; and a processing device, which is communicatively coupled to the memory component when in operation, the processing device being used to: update a temperature counter in response to a memory component write performed at an extreme temperature, the write being performed on a memory component element in the memory component; sort the memory component element above other memory component elements in the memory component based on the temperature counter; and perform a refresh of the memory component element in response to the sorting.

[0066] In example 2, the subject matter of example 1 includes wherein the memory component element is a super block.

[0067] In example 3, the subject matter of examples 1-2 includes wherein the extreme temperature is below a low write temperature threshold of the memory component.

[0068] In example 4, the subject matter of example 3 includes, wherein the temperature counter includes a low temperature write counter (LWTC).

[0069] In example 5, the subject matter of examples 1-4 includes, wherein the extreme temperature is above a high write temperature threshold of the memory component.

[0070] In Example 6, the subject matter of Example 5 includes, wherein the temperature counter includes a high temperature write counter (HWTC).

[0071] In Example 7, the subject matter of Examples 1-6 includes, wherein to sort the memory component elements, the processing device combines a low temperature write counter (LWTC) and a high temperature write counter (HWTC) to form a sort value that is compared to sort values ​​calculated for the other memory component elements.

[0072] In Example 8, the subject matter of Example 7 includes, wherein the ranking value exceeds a minimum temperature-based refresh threshold.

[0073] In example 9, the subject matter of example 8 includes, wherein the minimum temperature-based refresh threshold is based on a raw bit error rate (RBER) of the memory component.

[0074] In Example 10, the subject matter of Examples 8-9 includes, wherein the minimum temperature-based refresh threshold is a percentage of bytes in the memory component elements written at extreme temperatures.

[0075] In Example 11, the subject matter of Examples 1-10 includes wherein the temperature counter is stored separately from the memory component element.

[0076] In Example 12, the subject matter of Example 11 includes, wherein in response to opening the memory component element, the temperature counter is stored in a volatile memory portion of the memory component.

[0077] In Example 13, the subject matter of Examples 11-12 includes, wherein in response to shutting down the memory component element, the temperature counter is stored in the memory component.

[0078] In Example 14, the subject matter of Examples 1-13 includes wherein the memory component write is a codeword write.

[0079] In example 15, the subject matter of examples 1-14 includes, wherein in response to shutting down the memory component element, the processing device performs sorting.

[0080] In Example 16, the subject matter of Examples 1-15 includes wherein the temperature counter is 20 bits.

[0081] In Example 17, the subject matter of Examples 1-16 includes, wherein in response to erasing the memory component element, the temperature counter is reset to zero.

[0082] In Example 18, the subject matter of Examples 1-17 includes, wherein to perform the refresh, the processing device copies the contents of the memory component element to a new memory component element.

[0083] In Example 19, the subject matter of Example 18 includes, wherein in response to a non-extreme temperature of the new memory component element, the processing device copies the content.

[0084] In Example 20, the subject matter of Examples 18-19 includes, wherein in response to a low utilization period of the memory component, the processing device copies the content.

[0085] Example 21 is a method for temperature-informed memory refresh, the method comprising: updating a temperature counter in response to a memory component write performed at an extreme temperature, the memory component being included in a memory system, the write being performed on a memory component element in the memory component; sorting the memory component element above other memory component elements in the memory component based on the temperature counter; and performing a refresh of the memory component element in response to the sorting.

[0086] In Example 22, the subject matter of Example 21 includes wherein the memory component element is a super block.

[0087] In Example 23, the subject matter of Examples 21-22 includes wherein the extreme temperature is below a low write temperature threshold of the memory component.

[0088] In Example 24, the subject matter of Example 23 includes, wherein the temperature counter includes a low temperature write counter (LWTC).

[0089] In Example 25, the subject matter of Examples 21-24 includes wherein the extreme temperature is above a high write temperature threshold of the memory component.

[0090] In Example 26, the subject matter of Example 25 includes, wherein the temperature counter includes a high temperature write counter (HWTC).

[0091] In Example 27, the subject matter of Examples 21-26 includes, wherein ranking the memory component elements includes combining a low temperature write counter (LWTC) and a high temperature write counter (HWTC) to form a ranking value that is compared to ranking values ​​calculated for the other memory component elements.

[0092] In Example 28, the subject matter of Example 27 includes, wherein the ranking value exceeds a minimum temperature-based refresh threshold.

[0093] In Example 29, the subject matter of Example 28 includes, wherein the minimum temperature-based refresh threshold is based on a raw bit error rate (RBER) of the memory component.

[0094] In Example 30, the subject matter of Examples 28-29 includes, wherein the minimum temperature-based refresh threshold is a percentage of bytes in the memory component elements written at extreme temperatures.

[0095] In Example 31, the subject matter of Examples 21-30 includes wherein the temperature counter is stored separately from the memory component element.

[0096] In Example 32, the subject matter of Example 31 includes, wherein in response to opening the memory component element, the temperature counter is stored in a volatile memory portion of the memory component.

[0097] In Example 33, the subject matter of Examples 31-32 includes, wherein in response to shutting down the memory component element, the temperature counter is stored in the memory component.

[0098] In Example 34, the subject matter of Examples 21-33 includes wherein the memory component write is a codeword write.

[0099] In Example 35, the subject matter of Examples 21-34 includes, wherein the sorting is performed in response to shutting down the memory component element.

[0100] In Example 36, the subject matter of Examples 21-35 includes wherein the temperature counter is 20 bits.

[0101] In Example 37, the subject matter of Examples 21-36 includes, wherein in response to erasing the memory component element, the temperature counter is reset to zero.

[0102] In Example 38, the subject matter of Examples 21-37 includes, wherein performing the refresh includes copying contents of the memory component element to a new memory component element.

[0103] In Example 39, the subject matter of Example 38 includes, wherein copying the content is performed in response to a non-extreme temperature of the new memory component element.

[0104] In Example 40, the subject matter of Examples 38-39 includes, wherein copying the content is performed in response to a low utilization period of the memory component.

[0105] Example 41 is a non-transitory machine-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations, the operations comprising: updating a temperature counter in response to a memory component write performed at an extreme temperature, the memory component being included in a memory system, the write being performed on a memory component element in the memory component; sorting the memory component element above other memory component elements in the memory component based on the temperature counter; and performing a refresh of the memory component element in response to the sorting.

[0106] In Example 42, the subject matter of Example 41 includes wherein the memory component element is a super block.

[0107] In Example 43, the subject matter of Examples 41-42 includes wherein the extreme temperature is below a low write temperature threshold of the memory component.

[0108] In Example 44, the subject matter of Example 43 includes, wherein the temperature counter includes a low temperature write counter (LWTC).

[0109] In Example 45, the subject matter of Examples 41-44 includes wherein the extreme temperature is above a high write temperature threshold of the memory component.

[0110] In Example 46, the subject matter of Example 45 includes, wherein the temperature counter includes a high temperature write counter (HWTC).

[0111] In Example 47, the subject matter of Examples 41-46 includes, wherein ranking the memory component elements includes combining a low temperature write counter (LWTC) and a high temperature write counter (HWTC) to form a ranking value that is compared to ranking values ​​calculated for the other memory component elements.

[0112] In Example 48, the subject matter of Example 47 includes, wherein the ranking value exceeds a minimum temperature-based refresh threshold.

[0113] In Example 49, the subject matter of Example 48 includes, wherein the minimum temperature-based refresh threshold is based on a raw bit error rate (RBER) of the memory component.

[0114] In Example 50, the subject matter of Examples 48-49 includes, wherein the minimum temperature-based refresh threshold is a percentage of bytes in the memory component elements written at extreme temperatures.

[0115] In Example 51, the subject matter of Examples 41-50 includes wherein the temperature counter is stored separately from the memory component element.

[0116] In Example 52, the subject matter of Example 51 includes, wherein in response to opening the memory component element, the temperature counter is stored in a volatile memory portion of the memory component.

[0117] In Example 53, the subject matter of Examples 51-52 includes, wherein in response to shutting down the memory component element, the temperature counter is stored in the memory component.

[0118] In Example 54, the subject matter of Examples 41-53 includes wherein the memory component write is a codeword write.

[0119] In Example 55, the subject matter of Examples 41-54 includes, wherein the sorting is performed in response to shutting down the memory component element.

[0120] In Example 56, the subject matter of Examples 41-55 includes wherein the temperature counter is 20 bits.

[0121] In Example 57, the subject matter of Examples 41-56 includes, wherein in response to erasing the memory component element, the temperature counter is reset to zero.

[0122] In Example 58, the subject matter of Examples 41-57 includes, wherein performing the refresh includes copying contents of the memory component element to a new memory component element.

[0123] In Example 59, the subject matter of Example 58 includes, wherein copying the content is performed in response to a non-extreme temperature of the new memory component element.

[0124] In Example 60, the subject matter of Examples 58-59 includes, wherein copying the content is performed in response to a low utilization period of the memory component.

[0125] Example 61 is a system for temperature-informed memory refresh, the system comprising: a device for updating a temperature counter in response to a memory component write performed at an extreme temperature, the memory component being included in a memory system, the write being performed on a memory component element in the memory component; a device for sorting the memory component element above other memory component elements in the memory component based on the temperature counter; and a device for performing a refresh of the memory component element in response to the sorting.

[0126] In Example 62, the subject matter of Example 61 includes wherein the memory component element is a super block.

[0127] In Example 63, the subject matter of Examples 61-62 includes wherein the extreme temperature is below a low write temperature threshold of the memory component.

[0128] In Example 64, the subject matter of Example 63 includes, wherein the temperature counter includes a low temperature write counter (LWTC).

[0129] In Example 65, the subject matter of Examples 61-64 includes wherein the extreme temperature is above a high write temperature threshold of the memory component.

[0130] In Example 66, the subject matter of Example 65 includes, wherein the temperature counter includes a high temperature write counter (HWTC).

[0131] In Example 67, the subject matter of Examples 61-66 includes wherein the means for sorting the memory component elements includes means for combining a low temperature write counter (LWTC) and a high temperature write counter (HWTC) to form a sort value that is compared to sort values ​​calculated for the other memory component elements.

[0132] In Example 68, the subject matter of Example 67 includes, wherein the ranking value exceeds a minimum temperature-based refresh threshold.

[0133] In Example 69, the subject matter of Example 68 includes, wherein the minimum temperature-based refresh threshold is based on a raw bit error rate (RBER) of the memory component.

[0134] In Example 70, the subject matter of Examples 68-69 includes, wherein the minimum temperature-based refresh threshold is a percentage of bytes in the memory component elements written at extreme temperatures.

[0135] In Example 71, the subject matter of Examples 61-70 includes wherein the temperature counter is stored separately from the memory component element.

[0136] In Example 72, the subject matter of Example 71 includes, wherein in response to opening the memory component element, the temperature counter is stored in a volatile memory portion of the memory component.

[0137] In Example 73, the subject matter of Examples 71-72 includes, wherein in response to shutting down the memory component element, the temperature counter is stored in the memory component.

[0138] In Example 74, the subject matter of Examples 61-73 includes wherein the memory component write is a codeword write.

[0139] In Example 75, the subject matter of Examples 61-74 includes, wherein the sorting is performed in response to shutting down the memory component element.

[0140] In Example 76, the subject matter of Examples 61-75 includes wherein the temperature counter is 20 bits.

[0141] In Example 77, the subject matter of Examples 61-76 includes, wherein in response to erasing the memory component element, the temperature counter is reset to zero.

[0142] In Example 78, the subject matter of Examples 61-77 includes, wherein the means for performing the refresh includes means for copying contents of the memory component element to a new memory component element.

[0143] In Example 79, the subject matter of Example 78 includes, wherein copying the content is performed in response to a non-extreme temperature of the new memory component element.

[0144] In Example 80, the subject matter of Examples 78-79 includes, wherein copying the content is performed in response to a low utilization period of the memory component.

[0145] Example 81 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-80.

[0146] Example 82 is an apparatus comprising means for implementing any of Examples 1-80.

[0147] Example 83 is a system for implementing any one of Examples 1 to 80.

[0148] Example 84 is a method for implementing any one of Examples 1 to 80.

[0149] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings show by way of illustration specific embodiments in which the present invention can be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0150] In this document, as is common in patent documents, the term "one" or "an" is used to include one or more than one, which is independent of any other examples or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to non-exclusivity, or so that unless otherwise indicated, "A or B" may include "A but not B", "B but not A" and "A and B". In the appended claims, the terms "including" and "in which" are used as concise English equivalents of the corresponding terms "comprising" and "wherein". In addition, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles or processes that include elements other than those listed after this term in the claims are still considered to be within the scope of the claims. In addition, in the following claims, the terms "first", "second", and "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0151] The terms "wafer" and "substrate" are used herein to refer generally to any structure on which an integrated circuit is formed, and also to these structures during the various stages of integrated circuit fabrication. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the various embodiments is limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0152] Various embodiments according to the present disclosure and described herein include memories utilizing vertical structures of memory cells (e.g., memory strings of memory cells). As used herein, directional adjectives will be employed relative to the surface of a substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of a vertical structure will be considered to be the end closest to the substrate surface, and a top end of a vertical structure will be considered to be the end farthest from the substrate surface).

[0153] As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, perpendicular, etc. may refer to relative orientations, and are not intended to require strict adherence to specific geometric properties unless otherwise indicated. For example, as used herein, a vertical structure need not be exactly perpendicular to the surface of a substrate, but may instead be substantially perpendicular to the surface of a substrate, and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0154] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a given state is referred to herein as "programming" and may include writing to or erasing from a memory cell (e.g., a memory cell may be programmed to an erased state).

[0155] It should be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or coupled to another element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. If two elements are shown in the drawings as being connected by a line, the two elements may be coupled or directly coupled unless otherwise indicated.

[0156] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used by those of ordinary skill in the art after consulting the above description. The abstract is submitted with the following understanding: it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above specific embodiments, various features can be grouped together to simplify the present disclosure. This situation should not be interpreted as expecting that unrequired public features are necessary for any claim. In fact, the subject matter of the present invention may be less than all the features of the specific disclosed embodiments. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim exists independently as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined by reference to the attached claims and the full scope of equivalents granted by the claims.

Claims

1. A memory system, wherein include: A memory component comprising: a non-volatile memory portion including a plurality of memory component elements; and a volatile memory portion; and a processing device operatively communicatively coupled to the memory component, the processing device performing operations including: When a single memory component element of the plurality of memory component elements is turned on: storing a write temperature counter for the individual memory component elements on the volatile memory portion; and updating the stored write temperature counter in response to a memory component write being performed on the single memory component element at an extreme temperature outside of a defined temperature window; and In response to the single memory component element being turned off, the write temperature counter is stored on the non-volatile memory portion.

2. The memory system of claim 1 , wherein storing the write temperature counter of the single memory component element on the volatile memory portion comprises at least one of: storing a low temperature write counter (LWTC) on the volatile memory portion or storing a high temperature write counter (HWTC) on the volatile memory portion.

3. The memory system of claim 1 , wherein the stored write temperature counter is updated in response to the memory component write being performed on the single memory component element at the extreme temperature outside of the defined temperature window include: At least one of a low temperature write counter LWTC on the volatile memory portion or a high temperature write counter HWTC on the volatile memory portion is updated.

4. The memory system of claim 1, wherein the operation include: A refresh is performed on the single memory component element based on the write temperature counter.

5. The memory system of claim 4, wherein performing the refresh comprises copying the contents of the single memory component element to a new memory component element.

6. The memory system of claim 5, wherein the copying is performed in response to a non-extreme temperature of the new memory component element.

7. The memory system of claim 4, wherein the operation include: Generating a ranking value for the single memory component element based at least on the write temperature counter, performing a refresh on the single memory component element based on the write temperature counter comprises: The single memory component element is selected to be refreshed based on the ranking value.

8. The memory system of claim 7, wherein the ranking value of the single memory component element is generated based at least on the write temperature counter include: The low temperature write counter LWTC and the high temperature write counter HWTC are combined to generate the ranking value.

9. The memory system of claim 7, wherein the single memory component element to be refreshed is selected based on the ranking value. include: The ranking value of the single memory component element is compared to one or more ranking values ​​generated for other memory component elements of the plurality of memory component elements.

10. The memory system according to claim 1, in, The plurality of memory component elements include a plurality of memory cells.

11. A method, wherein include: When a single memory component element of the plurality of memory component elements of the non-volatile memory portion of the memory component is turned on: storing a write temperature counter for the individual memory component elements on a volatile memory portion of the memory component; and updating the write temperature counter in response to a memory component write being performed on the single memory component element at an extreme temperature outside of a defined temperature window; as well as In response to the single memory component element being shut down, the write temperature counter is stored on the non-volatile memory portion.

12. The method of claim 11 , wherein storing the write temperature counter of the single memory component element on the volatile memory portion comprises at least one of storing a low temperature write counter (LWTC) on the volatile memory portion or storing a high temperature write counter (HWTC) on the volatile memory portion.

13. The method of claim 11, wherein the write temperature counter is updated in response to the memory component write being performed on the single memory component element at the extreme temperature outside of the defined temperature window include: At least one of a low temperature write counter LWTC on the volatile memory portion or a high temperature write counter HWTC on the volatile memory portion is updated.

14. The method according to claim 11, wherein include: A refresh is performed on the single memory component element based on the write temperature counter.

15. The method of claim 14, wherein performing the refresh comprises copying the contents of the single memory component element to a new memory component element.

16. The method of claim 15, wherein the copying is performed in response to a non-extreme temperature of the new memory component element.

17. The method according to claim 14, wherein include: Generating a ranking value for the single memory component element based at least on the write temperature counter, performing a refresh on the single memory component element based on the write temperature counter comprises: The single memory component element is selected to be refreshed based on the ranking value.

18. The method of claim 17, wherein the ranking value of the single memory component element is generated based at least on the write temperature counter include: The low temperature write counter LWTC and the high temperature write counter HWTC are combined to generate the ranking value.

19. The method of claim 17, wherein the single memory component element to be refreshed is selected based on the ranking value include: The ranking value of the single memory component element is compared to one or more ranking values ​​generated for other memory component elements of the plurality of memory component elements.

20. A non-transitory machine-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: When a single memory component element of the plurality of memory component elements of the non-volatile memory portion of the memory component is turned on: storing a write temperature counter of the individual memory component elements on a volatile memory portion of the memory component ； and updating the write temperature counter in response to a memory component write being performed on the single memory component element at an extreme temperature outside of a defined temperature window; as well as In response to the single memory component element being shut down, the write temperature counter is stored on the non-volatile memory portion.

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