Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a fin; a gate structure disposed on the fin; a doped region disposed on a side of the fin; a contact disposed on the doped region; and a conductive cap disposed on the contact, wherein the conductive cap includes germanium copper.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 172,415, filed February 10, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, particularly to a semiconductor device having a resistance-reducing element and a method for manufacturing the semiconductor device having a resistance-reducing element. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To meet increasingly demanding computing performance requirements, the size of semiconductor components continues to shrink. However, this shrinkage leads to various problems in the manufacturing process, and these problems are constantly evolving into different scenarios. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure disposed on the fin; a doped region disposed on one side of the fin; a contact disposed on the doped region; and a conductive capping layer disposed on the contact; wherein the conductive capping layer comprises copper germanide.

[0006] In embodiments of this disclosure, the semiconductor element further includes a first dielectric layer disposed on the gate structure, wherein the vertical level of the top surface of the contact is located above the vertical level of the top surface of the first dielectric layer.

[0007] In embodiments of this disclosure, the semiconductor element further includes a contact gap wall disposed on one side of the contact and located between the first dielectric layer and the doped region.

[0008] In embodiments of this disclosure, the vertical layer containing the top surface of the doped region is located above the top surface of the fin.

[0009] In embodiments of this disclosure, the gate structure includes a gate dielectric layer disposed on the fin; a gate conductive layer disposed on the gate dielectric layer; and a gate fill layer disposed on the gate conductive layer.

[0010] In embodiments of this disclosure, the semiconductor device further includes a bottom conductive layer disposed between the contact and the doped region, wherein the bottom conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0011] In embodiments of this disclosure, the semiconductor element further includes a buried insulating layer located beneath the fin.

[0012] In embodiments of this disclosure, the semiconductor device further includes a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on the gate structure and the second dielectric layer being disposed on the first dielectric layer, wherein the contact is disposed along the first dielectric layer and the second dielectric layer and protrudes from the top surface of the second dielectric layer.

[0013] In embodiments of this disclosure, the contact includes a lower portion disposed on the doped region and below the first dielectric layer; a middle portion disposed on the lower portion and along the first dielectric layer; and an upper portion disposed on the middle portion and along the second dielectric layer, protruding from the top surface of the second dielectric layer; wherein the conductive capping layer is disposed on the upper portion.

[0014] In embodiments of this disclosure, the width of the lower portion is greater than the width of the middle portion.

[0015] In embodiments of this disclosure, the width of the upper portion is greater than the width of the middle portion.

[0016] In embodiments of this disclosure, the width of the upper part is greater than the width of the lower part.

[0017] Another aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure disposed on the fin; a doped region disposed on one side of the fin; a contact disposed on the doped region; and a top conductive layer disposed on the contact; wherein the top conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0018] In embodiments of this disclosure, the semiconductor device further includes a barrier layer located between the contact and the gate structure, and between the contact and the doped region.

[0019] In embodiments of this disclosure, the semiconductor device further includes a first dielectric layer and a barrier spacer. The first dielectric layer is located on the gate structure, the contact and the barrier layer are disposed along the first dielectric layer and protrude from the top surface of the first dielectric layer, and the barrier spacer is disposed on one side of the barrier layer and the top surface of the first dielectric layer.

[0020] In embodiments of this disclosure, the semiconductor device further includes a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on the gate structure and the second dielectric layer being disposed on the first dielectric layer, wherein the contact includes: a lower portion disposed on the doped region and located below the first dielectric layer; a middle portion located on the lower portion and disposed along the first dielectric layer; and an upper portion located on the middle portion and disposed along the second dielectric layer, and protruding from the top surface of the second dielectric layer; wherein the top conductive layer is located on the upper portion.

[0021] In embodiments of this disclosure, the semiconductor device further includes a barrier layer and a barrier gap wall, wherein the barrier layer is disposed between the lower portion and the middle portion, and between the middle portion and the first dielectric layer, and is located on one side surface of the upper portion, and the barrier gap wall is located on one side surface of the barrier layer and the top surface of the second dielectric layer.

[0022] In embodiments of this disclosure, the semiconductor device further includes a bottom conductive layer disposed between the lower portion and the doped region, wherein the bottom conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0023] Another aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure disposed on the fin; a first dielectric layer disposed on the gate structure; a doped region disposed on one side of the fin; and a contact comprising: a lower portion disposed on the doped region and located below the first dielectric layer; a middle portion disposed on the lower portion and along the first dielectric layer; an upper portion disposed on the middle portion; and an insulating layer disposed on the first dielectric layer and adjacent to the upper portion.

[0024] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising forming a gate structure on a fin; forming a doped region on one side of the fin; forming a contact on the doped region; and forming a conductive capping layer on the contact; wherein the conductive capping layer comprises copper germanide.

[0025] Since the semiconductor device design disclosed herein utilizes copper germanide to form a conductive capping layer, it can reduce the contact resistance of the semiconductor device, thereby effectively improving the performance of the semiconductor device and reducing the energy consumption of the semiconductor device.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 7 These are schematic cross-sectional views of the fabrication process of a semiconductor device according to embodiments of the present disclosure.

[0030] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0031] Figures 9 to 15 These are schematic cross-sectional views illustrating the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0032] Figures 16 to 19 These are schematic cross-sectional views illustrating the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0033] Figure 20 and 21 These are schematic cross-sectional views illustrating the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0034] Figure 22 This is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0035] Figures 23 to 30 These are schematic cross-sectional views illustrating the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0036] Figures 31 to 33 These are schematic cross-sectional views of semiconductor devices according to several embodiments of the present disclosure.

[0037] The reference numerals in the attached figures are explained as follows:

[0038] 1A: Semiconductor components

[0039] 1B: Semiconductor components

[0040] 1C: Semiconductor components

[0041] 1D: Semiconductor components

[0042] 1E: Semiconductor components

[0043] 1F: Semiconductor components

[0044] 1G: Semiconductor components

[0045] 1H: Semiconductor components

[0046] 10: Method

[0047] 20: Method

[0048] 30: Method

[0049] 101: Contact element

[0050] 101S: Side View

[0051] 101TS: Top Surface

[0052] 101-1: Lower part

[0053] 101-3: Middle Section

[0054] 101-5: Upper part

[0055] 101-5S: Side View

[0056] 103: Conductive coating

[0057] 105: Barrier Layer

[0058] 105TS: Top surface

[0059] 107: Top conductive layer

[0060] 109: Barrier Spacer

[0061] 111: Bottom conductive layer

[0062] 113: Insulation layer

[0063] 200: Gate structure

[0064] 200S: Side View

[0065] 200TS: Top surface

[0066] 201: Gate dielectric layer

[0067] 201TS: Top Surface

[0068] 203: Gate conductive layer

[0069] 203TS: Top Surface

[0070] 205: Gate filler layer

[0071] 205TS: Top surface

[0072] 207: Gate spacer wall

[0073] 207TS: Top Surface

[0074] 301: Doped region

[0075] 301TS: Top surface

[0076] 401: Substrate

[0077] 403: Fins

[0078] 403S: Side View

[0079] 403TS: Top surface

[0080] 405: Intergate dielectric layer

[0081] 407: Contact gap wall

[0082] 501: First dielectric layer

[0083] 501TS: Top Surface

[0084] 503: Second dielectric layer

[0085] 503TS: Top Surface

[0086] 601: First photomask layer

[0087] 601O: First Opening

[0088] 603: Second photomask layer

[0089] 603O: Second opening

[0090] 605: Third photomask layer

[0091] 605O: Third opening

[0092] 607: Fourth photomask layer

[0093] 607O: Fourth opening

[0094] 609: Fifth photomask layer

[0095] 609O: The Fifth Opening

[0096] 611: Space

[0097] 701: Semiconductor Materials

[0098] 703: Sacrificial Material

[0099] 703TS: Top Surface

[0100] 705: Insulating materials

[0101] W1: Width

[0102] W2: Width

[0103] W3: Width

[0104] W4: Width

[0105] W5: Width

[0106] W7: Width

[0107] W8: Width

[0108] W9: Width

[0109] W10: Width Detailed Implementation

[0110] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0111] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0112] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0113] In this disclosure, a semiconductor element generally refers to an element that can function by utilizing the properties of a semiconductor, and electro-optical elements, light-emitting display elements, semiconductor circuits and electronic elements are all included in the category of semiconductor elements.

[0114] It should be noted that in the description of this disclosure, "above" corresponds to the direction pointed to by arrow Z, and "below" corresponds to the opposite direction pointed to by arrow Z.

[0115] Figure 1 This is a flowchart of a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 7 These are schematic cross-sectional views of the fabrication process of semiconductor element 1A according to embodiments of the present disclosure.

[0116] Please refer to Figure 1 and Figure 2 In step S11, a plurality of fins 403 may be formed on the substrate 401, a plurality of gate structures 200 may be formed on the fins 403, and a plurality of doped regions 301 may be formed between adjacent pairs of gate structures 200.

[0117] like Figure 2 As shown, substrate 401 may comprise bulk silicon or another suitable substrate material, such as bulk semiconductor. In one embodiment, substrate 401 may comprise silicon material. Specific embodiments of silicon-containing materials suitable for substrate 401 may include, but are not limited to, silicon, silicon-germanium, carbon-doped silicon-germanium, silicon-germanium carbide, carbon-doped silicon, silicon carbide, and multilayer structures of the aforementioned materials. Although silicon is the primary semiconductor material used in wafer manufacturing, in some embodiments, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon-germanium, cadmium telluride, zinc selenide, germanium-tin, etc.

[0118] like Figure 2 As shown, multiple fins 403 can be formed on the substrate 401 and spaced apart from each other. In one embodiment, the fins 403 can be formed by recessing a portion of the substrate 401. In other words, the fins 403 can be formed of the same material as the substrate 401. In one embodiment, the fins 403 can be formed by a subsequent patterning process, by depositing a semiconductor layer. The semiconductor layer can comprise, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors, or group II-VI compound semiconductors, or combinations thereof. It should be noted that the fins 403 comprise three fins 403, but the number is not limited to this. For example, the number of fins 403 can be less than three or more than three.

[0119] like Figure 2As shown, multiple gate structures 200 can be formed on the fin 403 respectively and spaced apart from each other. For ease of explanation, this disclosure uses only one gate structure 200 as an example. Specifically, a dummy gate structure (not shown) can be formed on the fin 403. Multiple gate spacer walls 207 can be formed on both sides of the dummy gate structure. A selective etching process can be used to remove the dummy gate structure and form a gate opening (not shown) in the place where the dummy gate structure was previously occupied. The gate structure 200 can be formed in the gate opening. The gate structure 200 can include a gate dielectric layer 201, a gate conductive layer 203, and a gate fill layer 205.

[0120] Please refer to Figure 2 The gate dielectric layer 201 may have a U-shaped cross-sectional profile and may be formed on the fin 403. The gate dielectric layer 201 may have a thickness between about 0.5 nanometers (nm) and about 5.0 nm. In one embodiment, the thickness of the gate dielectric layer 201 may be between about 0.5 nm and 2.5 nm. The gate dielectric layer 201 may be formed of, for example, a high-k dielectric material, such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminate, or combinations thereof.

[0121] Specifically, the gate dielectric layer 201 may be made of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or combinations thereof. In other embodiments, the gate dielectric layer 201 may be a multilayer structure comprising, for example, a layer of silicon oxide and another layer of high-k dielectric material.

[0122] Please refer to Figure 2 The gate conductive layer 203 can be conformally formed on the gate dielectric layer 201. The gate conductive layer 203 can have a U-shaped cross-sectional profile. The thickness of the gate conductive layer 203 can be between about 10 angstroms and about 200 angstroms. The top surface 203TS of the gate conductive layer 203 can be substantially coplanar with the top surface 201TS of the gate dielectric layer 201.

[0123] In one embodiment, the gate conductive layer 203 may include a capping layer (not shown) conformally formed on the gate dielectric layer 201, and one or more work function adjustment layers (not shown) conformally formed on the capping layer. In one embodiment, the capping layer may include a first sublayer (not shown) on the gate dielectric layer 201 and a second sublayer (not shown) on the first sublayer. The first sublayer may be formed using titanium nitride through processes such as atomic layer deposition and chemical vapor deposition, and the second sublayer may be formed using tantalum nitride through processes such as atomic layer deposition and chemical vapor deposition.

[0124] In one embodiment, the work function adjustment layer can be formed of, for example, a p-type work function metal material and an n-type work function metal material. The p-type work function material may contain components such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, or combinations thereof. The n-type metal material may contain components such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or combinations thereof. The work function adjustment layer can be formed using atomic layer deposition, chemical vapor deposition, etc. The work function adjustment layer can set the threshold voltage (Vt) of the semiconductor element 1A to a predetermined value. In one embodiment, the work function adjustment layer has a dual purpose: threshold voltage Vt setting and gate conductor.

[0125] like Figure 2 As shown, the gate filling layer 205 can be formed on the gate conductive layer 203 to completely fill the gate opening. The top surface 205TS of the gate filling layer 205 can be substantially coplanar with the top surface 203TS of the gate conductive layer 203 and the top surface 201TS of the gate dielectric layer 201. The top surface 201TS of the gate dielectric layer 201, the top surface 203TS of the gate conductive layer 203, and the top surface 205TS of the gate filling layer 205 together constitute the top surface 200TS of the gate structure 200.

[0126] The gate filling layer 205 can be made of, for example, tungsten, aluminum, cobalt, ruthenium, gold, silver, titanium, platinum, or a combination thereof, and can be formed by chemical vapor deposition, physical vapor deposition, electroplating, thermal or electron beam evaporation, or a combination thereof.

[0127] In one embodiment, a gate interface layer (not shown) may be formed between the gate dielectric layer 201 and the fin 403. The gate interface layer may be formed of an oxide and may be formed by processes such as thermal oxidation, atomic layer deposition, or chemical vapor deposition. For example, the gate interface layer may be silicon oxide. In one embodiment, the thickness of the gate interface layer may be between approximately 8 angstroms and 10 angstroms. The gate interface layer may facilitate the formation of the gate dielectric layer 201 during the fabrication of the semiconductor device 1A.

[0128] Please refer to Figure 2 Multiple doped regions 301 can be formed respectively on the side surfaces 403S of the fin 403 and between adjacent pairs of gate structures 200. For ease of explanation, this disclosure uses only one doped region 301 as an example. The top surface 301TS of the doped region 301 can be disposed at a vertical level, located above the top surface 403TS of the fin 403 and below the vertical level of the top surface 200TS of the gate structure 200. The doped region 301 can be formed by epitaxial growth processes, such as rapid thermochemical vapor deposition, low-energy plasma deposition, ultra-high vacuum chemical vapor deposition, atmospheric pressure chemical vapor deposition, or molecular beam epitaxy. In one embodiment, the epitaxial material for the n-type device can include silicon, silicon carbide, phosphorus-doped silicon-carbon, phosphorus-doped silicon-germanium, silicon phosphide, phosphorus-doped silicon-germanium-tin, etc. The epitaxial material for the p-type device can include silicon-germanium, boron-doped silicon-germanium, germanium, boron-doped germanium, germanium-tin, boron-doped germanium-tin, or boron-doped III-V compound materials.

[0129] In one embodiment, a suitable precursor can be used to in-situ incorporate the dopant. The dopant concentration of the doped region 301 can be approximately 1E19 atoms / cm³. 3 Up to approximately 1E21 atoms / cm 3 Between. It should be noted that the term "in situ" means that the dopant used to determine the conductivity type of the doped layer is introduced during a process step such as epitaxial deposition to form the doped layer. The term "conductivity type" refers to the p-type or n-type doped region.

[0130] In one embodiment, an epitaxial pre-cleaning process can be used to remove the thin layer of oxide material on the sidewalls 403S of the fin 403. The epitaxial pre-cleaning process can be a plasma-assisted dry etching process, which involves simultaneously exposing the semiconductor material to plasma byproducts of hydrogen, nitrogen trifluoride (NF3), and ammonia (NH3) or performing wet etching using a solution containing hydrofluoric acid.

[0131] Please refer to Figure 2 Gate spacer walls 207 can be formed on the side surfaces 200S of the gate structure 200, adjacent to the doped region 301. The top surface 207TS of the gate spacer wall 207 can be substantially coplanar with the top surface 200TS of the gate structure 200. The width of the gate spacer wall 207 can be between approximately 3 nm and approximately 10 nm. The gate spacer wall 207 can be formed of, for example, silicon nitride, silicon carbide boron nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, etc.

[0132] like Figure 2As shown, multiple inter-gate dielectric layers 405 can be formed on the doped region 301 respectively and located between adjacent pairs of gate structures 200. For ease of explanation, this disclosure uses only one inter-gate dielectric layer 405 as an example. This inter-gate dielectric layer 405 can be opposite to the gate structure 200, and the gate spacer 207 is located between them. The inter-gate dielectric layer 405 can be formed of, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, or a combination thereof.

[0133] Please refer to Figure 1 , Figure 3 and Figure 4 In step S13, a first dielectric layer 501 may be formed on the gate structure 200, and a second dielectric layer 503 may be formed on the first dielectric layer 501, and a first opening 601O may be further formed to expose the doped region 301.

[0134] like Figure 3 As shown, a first dielectric layer 501 can be formed on the gate structure 200, the gate spacer 207, and the inter-gate dielectric layer 405. The first dielectric layer 501 can have a thickness between about 3 nm and about 10 nm or 5 nm, or between about 100 nm and 100 nm. The first dielectric layer 501 can be formed by any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In one embodiment, the first dielectric layer 501 can be formed of, for example, silicon nitride, silicon boron carbon nitride, silicon carbon nitride, or silicon carbon oxide. In one embodiment, the first dielectric layer 501 can be made of, for example, silicon oxide, borosilicate glass, undoped silicon glass, silicon fluoride glass, low-k dielectric materials, silicon nitride, silicon oxynitride, silicon carbon boron nitride, silicon carbon nitride, or silicon carbon nitride.

[0135] Please refer to Figure 3 A second dielectric layer 503 may be formed on the first dielectric layer 501. The second dielectric layer 503 may have a thickness between about 10 nm and about 30 nm. The second dielectric layer 503 may be formed by any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In one embodiment, the second dielectric layer 503 may be formed of a material that is etch-selective towards the first dielectric layer 501. In one embodiment, the second dielectric layer 503 may be formed of an oxide such as silicon oxide.

[0136] like Figure 3 As shown, a first photomask layer 601 can be formed on the second dielectric layer 503. In one embodiment, the first photomask layer 601 may be a photoresist layer. In another embodiment, the first photomask layer 601 may include a rigid mask layer on the second dielectric layer 503 and a photoresist layer on the rigid mask layer. The first photomask layer 601 may be patterned to form the first opening 601O.

[0137] like Figure 4 As shown, portions of the second dielectric layer 503, the first dielectric layer 501, and the inter-gate dielectric layer 405 can be removed by an etching process to form the first opening 601O. In other words, the first opening 601O can be formed along the second dielectric layer 503, the first dielectric layer 501, and the inter-gate dielectric layer 405. The doped region 301 can be exposed through the first opening 601O. The width W1 of the first opening 601O can be smaller than the width W2 of the doped region 301. The inter-gate dielectric layer 405 can be divided by the first opening 601O to form a contact gap wall 407 adjacent to the gate gap wall 207. The first photomask layer 601 can be removed after the first opening 601O is formed.

[0138] Please refer to Figure 1 and Figure 5 In step S15, a plurality of contacts 101 may be formed in the first opening 601O.

[0139] like Figure 5 As shown, conductive materials, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof, can be deposited into the first opening 601O via a deposition process. Following deposition, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming the contact 101. Specifically, the contact 101 can be electrically connected to the doped region 301. A contact gap wall 407 can be disposed on the side surface 101S of the contact 101 and located between the first dielectric layer 501 and the doped region 301 to electrically isolate the contact 101 from the gate structure 200.

[0140] Please refer to Figure 1 and Figure 6 In step S17, the second dielectric layer 503 can be recessed to expose the side surface 101S and top surface of the contact 101. Figure 6As shown, the top surface 503TS of the second dielectric layer 503 can be recessed by an etching process. During the etching process, the etching rate ratio of the second dielectric layer 503 to the contact 101 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. After the etching process, the upper part of the side surface 101S of the contact 101 protrudes from the top surface 503TS of the second dielectric layer 503. In other words, the vertical level of the top surface 101TS of the contact 101 is located above the vertical level of the top surface 503TS of the second dielectric layer 503.

[0141] Please refer to Figure 1 and Figure 7 In step S19, multiple conductive capping layers 103 may be formed on the contact 101. For ease of explanation, this disclosure uses only one conductive capping layer 103 as an example. Figure 7 As shown, a conductive capping layer 103 can be formed on the top surface 101TS of the contact 101, on the upper part of the side surface 101S of the contact 101, and on the second dielectric layer 503. The conductive capping layer 103 can be formed of, for example, copper germanide. In one embodiment, the conductive capping layer 103 can be formed by, for example, sputtering, electron beam thermal evaporation, vapor-solid reaction, or epitaxial growth. In this embodiment, the conductive capping layer 103 formed by epitaxial growth is a preferred option for providing lower resistivity.

[0142] The conductive capping layer 103, formed of copper germanide with high thermal stability, low bulk resistivity, and diffusion barrier properties, can reduce the contact resistance between the contact 101 and the conductive component to be electrically connected to the contact 101. The conductive capping layer 103 can be referred to as a resistance-reducing element.

[0143] In one embodiment, one of the dielectric layers may be omitted. For example, the second dielectric layer 503 may be omitted. The contact 101 may protrude from the top surface 501TS of the first dielectric layer 501. A conductive capping layer 103 may be formed on the top surface 101TS of the contact 101, on the upper portion of the side surface 101S of the contact 101, and on the first dielectric layer 501. In another embodiment, the first dielectric layer 501 may be omitted.

[0144] Figure 8 This is a method 20 for manufacturing a semiconductor element 1B according to another embodiment of the present disclosure. Figures 9 to 15 These are schematic cross-sectional views illustrating the fabrication process of a semiconductor device according to another embodiment of this disclosure. Please refer to... Figure 8 and Figure 9In step S21, a plurality of fins 403 may be formed on a substrate 401. A plurality of gate structures 200 may be formed on the fins 403, and a plurality of doped regions 301 may be formed between adjacent pairs of such gate structures 200, and a dielectric etching process is performed to expose the doped regions 301.

[0145] like Figure 9 As shown, it can be done by... Figure 2 The intermediate semiconductor device is manufactured using a similar process to that described in the embodiment. Gate-to-gate dielectric layer 405 (e.g.) Figure 2 (As shown) can be removed after the dielectric etching process. During the dielectric etching process, the etching rate ratio of the inter-gate dielectric layer 405 to the gate spacer 207 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. During the dielectric etching process, the etching rate ratio of the inter-gate dielectric layer 405 to the gate structure 200 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. During the dielectric etching process, the etching rate ratio of the inter-gate dielectric layer 405 to the doped region 301 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. After the dielectric etching process, corner etch of the gate spacer 207 may occur.

[0146] Please refer to Figure 8 and Figure 10 In step S23, the lower portion 101-1 of the contact 101 is formed on the doped region 301. For example... Figure 10 As shown, contact material can be deposited to overfill. Figure 9 The intermediate semiconductor element is shown. A planarization process, such as chemical mechanical polishing, can then be performed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming the lower portion 101-1 of the contact 101. This planarization process may "over-polish" to remove portions of the gate spacer 207 with etched angles. The lower portion 101-1 of the contact 101 may be disposed opposite to the gate structure 200, with the gate spacer 207 located between them. It should be noted that, with... Figure 7 In contrast, no contact gap wall is provided on the side of the contact element 101.

[0147] Please refer to Figures 11 to 13 In step S25, a first dielectric layer 501 may be formed on the gate structure 200, a second dielectric layer 503 may be formed on the first dielectric layer 501, a second opening 603O may be formed along the first dielectric layer 501, and a third opening 605O may be formed along the second dielectric layer 503. Figure 11As shown, a first dielectric layer 501 can be formed on the gate structure 200, on the gate spacer 207, and on the lower portion 101-1 of the contact 101. The first dielectric layer 501 can have a thickness between about 3 nm and about 10 nm, or about 5 nm. The first dielectric layer 501 can be formed by any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In one embodiment, the first dielectric layer 501 can be formed of, for example, silicon nitride, silicon boron carbon nitride, silicon carbon nitride, or silicon carbon oxide. In another embodiment, the first dielectric layer 501 can be made of, for example, silicon oxide, borosilicate glass, undoped silicon glass, silicon fluoride glass, low-k dielectric materials, silicon nitride, silicon oxynitride, silicon carbon boron nitride, silicon carbon nitride, or silicon carbon nitride.

[0148] like Figure 11 As shown, a second dielectric layer 503 can be formed on the first dielectric layer 501. The second dielectric layer 503 may have a thickness between about 10 nm and about 30 nm. The second dielectric layer 503 can be formed by any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In one embodiment, the second dielectric layer 503 may be formed of a material that has etch selectivity for the first dielectric layer 501. In one embodiment, the second dielectric layer 503 may be formed of an oxide such as silicon oxide.

[0149] Please refer to Figure 11 A second photomask layer 603 may be formed on the second dielectric layer 503. In one embodiment, the second photomask layer 603 may be a photoresist layer. In another embodiment, the second photomask layer 603 may include a hard mask layer on the second dielectric layer 503 and a photoresist layer on the hard mask layer. The second photomask layer 603 may have a pattern of a second opening 603O.

[0150] Please refer to Figure 12 A portion of the second dielectric layer 503 and a portion of the first dielectric layer 501 can be removed by a first etching process to form the second opening 603O. During this stage, the second opening 603O can be formed along the second dielectric layer 503 and the first dielectric layer 501. The second opening 603O is used to expose the lower portion 101-1 of the contact 101, and the width W3 of the second opening 603O can be smaller than the width W4 of the lower portion 101-1 of the contact 101. The second photomask layer 603 can be removed after the second opening 603O is formed.

[0151] Please refer to Figure 12 A third photomask layer 605 can be formed on the second dielectric layer 503. In one embodiment, the third photomask layer 605 may be a photoresist layer. In another embodiment, the third photomask layer 605 may include a hard mask layer on the second dielectric layer 503 and a photoresist layer on the hard mask layer. The third photomask layer 605 may have a pattern of a third opening 605O.

[0152] Please refer to Figure 13 A portion of the second dielectric layer 503 can be removed by a second etching process to form the third opening 605O. The third opening 605O widens along the second dielectric layer 503 from the second opening 603O. The width W5 of the third opening 605O may be greater than the width W3 of the second opening 603O. In one embodiment, the width W5 of the third opening 605O may be equal to or greater than the width W4 of the lower portion 101-1 of the contact 101.

[0153] Please refer to Figure 8 , 14 In step S27, the middle portion 101-3 of the contact 101 can be formed in the second opening 603O, the upper portion 101-5 of the contact 101 can be formed in the third opening 605O, and a conductive cover layer 103 can be formed on the upper portion 101-5.

[0154] like Figure 14 As shown, conductive materials, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof, can be deposited into the second opening 603O and the third opening 605O via a deposition process. After deposition, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, thereby providing a substantially flat surface for subsequent processing steps, and simultaneously forming the middle portion 101-3 of the contact 101 in the second opening 603O and the upper portion 101-5 of the contact 101 in the third opening 605O.

[0155] The width (or size) of contact 101 is relatively critical to the overall structure. If the width of contact 101 relative to the doped region 301 is too small, although it will not cause a short circuit in the gate structure 200, it may result in very high contact resistance. If the width of contact 101 relative to the doped region 301 is too large, although the contact resistance will be low, it may still cause a short circuit in the gate structure 200. Figure 14 As shown, the width W8 of the upper portion 101-5 can be greater than the width W7 of the middle portion 101-3. In one embodiment, the width W8 of the upper portion 101-5 can be equal to or greater than the width W4 of the lower portion 101-1. In this embodiment, the wider width of the lower portion 101-1 and the wider width of the upper portion 101-5 can reduce the contact resistance by increasing the contact area. At the same time, the narrower width of the middle portion 101-3 can avoid increasing the possibility of a short circuit in the gate structure 200. Therefore, the total contact resistance of the semiconductor element 1B having the contact 101 structure of this disclosure can be reduced.

[0156] like Figure 15As shown, the top surface 503TS of the second dielectric layer 503 can be recessed through an etching process. After the etching process, the upper portion of the side 101-5S of the upper part 101-5 can protrude from the top surface 503TS of the second dielectric layer 503. In other words, the vertical level of the top surface 101-5TS of the upper part 101-5 is located above the vertical level of the top surface 503TS of the second dielectric layer 503.

[0157] like Figure 15 As shown, the conductive capping layer 103 can be formed on the top surface 101-5TS of the upper portion 101-5, on the portion above the side surface 101-5S of the upper portion 101-5, and on the second dielectric layer 503. The conductive capping layer 103 can be formed, for example, copper germanide. In one embodiment, the conductive capping layer 103 can be formed by, for example, sputtering, electron beam thermal evaporation, vapor-solid reaction, or epitaxial growth. In this embodiment, the conductive capping layer 103 formed by epitaxial growth is a preferred option for providing a lower resistivity.

[0158] The conductive capping layer 103, formed of copper germanide with high thermal stability, low bulk resistivity and diffusion barrier properties, can reduce the contact resistance between the upper part 101-5 of the contact 101 and the conductive component to be electrically connected to the contact 101.

[0159] Please refer to Figures 16 to 19 These are schematic cross-sectional views of the fabrication process of a semiconductor element 1C according to another embodiment of the present disclosure.

[0160] like Figure 16 As shown, it can be done by... Figures 1 to 10 The intermediate semiconductor device is fabricated using a similar process to that described in the embodiment. A barrier material can be conformally formed in the first opening 601O and on the top surface 503TS of the second dielectric layer 503. This barrier material can be, for example, titanium, titanium nitride, platinum, nickel, or a combination thereof. In this embodiment, the barrier material can be titanium. Subsequently, a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof can be deposited into the first opening 601O using a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming the contact 101, thus fabricating the barrier material into a barrier layer 105.

[0161] like Figure 17As shown, the top surface 503TS of the second dielectric layer 503 can be recessed by an etching process. During etching, the etching rate ratio of the second dielectric layer 503 to the contact 101 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. During etching, the etching rate ratio of the second dielectric layer 503 to the barrier layer 105 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After etching, the upper portion of the contact 101 and the upper portion of the barrier layer 105 protrude from the top surface 503TS of the second dielectric layer 503.

[0162] like Figure 18 As shown, a layer made of semiconductor material 701 can be conformally formed to cover the top surface 503TS of the second dielectric layer 503, the upper portion of the contact 101, and the upper portion of the barrier layer 105. Semiconductor material 701 can be, for example, silicon or germanium. In this embodiment, semiconductor material 701 can be silicon.

[0163] Please refer to Figure 19 Further heat treatment can be performed. During heat treatment, the metal atoms of the contact 101 and the barrier layer 105 can chemically react with the silicon atoms of the semiconductor material 701 layer to form a top conductive layer 107 on the contact 101 and barrier spacers 109 on the side surfaces 105S and top surface 105TS of the barrier layer 105. The top conductive layer 107 and barrier spacers 109 may comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The heat treatment can be a dynamic surface annealing process. After heat treatment, a cleaning process can be performed to remove unreacted semiconductor material 701. The cleaning process can be, for example, wet etching using potassium hydroxide. The top conductive layer 107 and barrier spacers 109 can reduce the contact resistance of the contact 101. In other words, the top conductive layer 107 and barrier spacers 109 can be referred to as resistance-reducing elements.

[0164] In one embodiment, one of the dielectric layers may be omitted. For example, the second dielectric layer 503 may be omitted. A contact 101 may protrude from the top surface 501TS of the first dielectric layer 501. A top conductive layer 107 may be formed on the top surface 101TS of the contact 101, while a barrier spacer 109 may be formed on the upper portion of the side surface 105S of the barrier layer 105 and on the first dielectric layer 501. In another embodiment, the first dielectric layer 501 may be omitted.

[0165] Figure 20 and 21 These are schematic cross-sectional views of the fabrication process of a semiconductor element 1D according to another embodiment of the present disclosure.

[0166] like Figure 20 As shown, it can be done by... Figure 18 and 19 The intermediate semiconductor device is fabricated using a similar process to that described in the embodiments. A barrier material can be conformally formed in the second opening 603O and the third opening 605O, and on the top surface 503TS of the second dielectric layer 503. This barrier material can be, for example, titanium, titanium nitride, platinum, nickel, or a combination thereof. Subsequently, a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum nitrides, or combinations thereof can be deposited into the second opening 603O and the third opening 605O by a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming the middle portion 101-3 and the upper portion 101-5 of the contact 101, and fabricating the barrier material into a barrier layer 105. For ease of illustration, this disclosure uses only one barrier layer 105 as an example.

[0167] like Figure 20 As shown, the barrier layer 105 can be formed between the lower part 101-1 and the middle part 101-3, between the first dielectric layer 501 and the middle part 101-3, between the first dielectric layer 501 and the upper part 101-5, and on the side 101-5S of the upper part 101-5.

[0168] Please refer to Figure 21 Similar to Figures 17 to 19 The steps shown can be used to form the top conductive layer 107 and the barrier spacer 109. The top conductive layer 107 can be formed on the top surface 101-5TS of the upper portion 101-5 respectively. The barrier spacer 109 can be formed on the side surface 105S of the barrier layer 105, on the top surface 105TS of the barrier layer 105, and on the top surface 503TS of the second dielectric layer 503.

[0169] Figure 22 This is a flowchart of a method 30 for manufacturing a semiconductor element 1E according to another embodiment of the present disclosure. Figures 23 to 30 These are schematic cross-sectional views of the fabrication process of a semiconductor element 1E according to another embodiment of the present disclosure.

[0170] Please refer to Figure 22 and Figure 23 In step S31, a plurality of fins 403 may be formed on the substrate 401, a plurality of gate structures 200 may be formed on the fins 403, a plurality of doped regions 301 may be formed between adjacent pairs of gate structures 200, and a first dielectric layer 501 may be formed on the gate structures 200.

[0171] like Figure 23 As shown, it can be achieved through... Figure 2 and Figure 3 A similar process is used to form the gate structure 200, gate spacer 207, doped region 301, substrate 401, fin 403, inter-gate dielectric layer 405, and first dielectric layer 501. A fourth photomask layer 607 may be formed on the first dielectric layer 501 and patterned to form a fourth opening 607O.

[0172] Please refer to Figures 22 to 25 In step S33, the fourth opening 607O is formed to expose the doped region 301. A sacrificial material layer 703 is formed on the first dielectric layer 501 to fill the fourth opening 607O.

[0173] Please refer to Figure 23 and Figure 24 A portion of the first dielectric layer 501 and a portion of the inter-gate dielectric layer 405 can be removed by an etching process to form the fourth opening 607O. In other words, the fourth opening 607O can be formed along the first dielectric layer 501 and the inter-gate dielectric layer 405. The doped region 301 can be exposed through the fourth opening 607O. The inter-gate dielectric layer 405 can be divided by the fourth opening 607O, forming a contact spacer wall 407 adjacent to the gate spacer wall 207. The fourth photomask layer 607 can be removed after the fourth opening 607O is formed.

[0174] like Figure 25 As shown, the sacrificial material layer 703 can be deposited on Figure 24 On the intermediate semiconductor element shown, a planarization process, such as chemical mechanical polishing, can be used to provide a flat surface for subsequent processing steps. A fifth photomask layer 609 can be formed on the sacrificial material layer 703 and patterned to form a fifth opening 609O.

[0175] In one embodiment, the sacrificial material 703 may be, for example, a doped oxide, such as borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorinated silicate glass, carbon-doped silicon oxide, etc. Compared to undoped oxides, doped oxides can exhibit a faster etching rate when etched by vaporized hydrogen fluoride. This may be due to the lower density characteristics of undoped oxides. Alternatively, in one embodiment, the sacrificial material 703 may be formed from, for example, a thermally decomposable polymer or a thermally degradable polymer. When exposed to a temperature exceeding the decomposition temperature of the thermally decomposable polymer or the degradation temperature of the thermally degradable polymer, the thermally decomposable polymer or the thermally degradable polymer decomposes or degrades into a gaseous state.

[0176] Please refer to Figure 22 and Figures 25 to 28In step S35, a plurality of fifth openings 609O may be formed to expose the first dielectric layer 501, and a plurality of insulating layers 113 may be formed in the fifth openings 609O.

[0177] like Figure 25 and 26 As shown, a portion of the sacrificial material layer 703 can be removed by an etching process to form the fifth opening 609O. A portion of the first dielectric layer 501 can be exposed through the fifth opening 609O. The fifth photomask layer 609 can be removed after the fifth opening 609O is formed.

[0178] like Figure 27 As shown, a layer made of insulating material 705 may be formed on the sacrificial material layer 703 and fill the fifth opening 609O. In one embodiment, the insulating material 705 may be, for example, an undoped oxide, such as silicon oxide or undoped silicon glass. Alternatively, in one embodiment, the insulating material 705 may be, for example, silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, undoped silicon dioxide glass, borosilicate glass, phosphosilicate glass, borosilicate-phosphosilicate glass, silicon fluoride glass, carbon-doped silicon oxide, or a combination thereof.

[0179] like Figure 28 As shown, planarization processes such as chemical mechanical polishing can be performed until the top surface 703TS of the sacrificial material layer 703 is exposed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming the insulating layer 113.

[0180] Please refer to Figure 22 and Figure 29 In step S37, space 611 can be formed by removing the sacrificial material layer 703.

[0181] like Figure 29 As shown, the sacrificial material layer 703 can be removed, and space 611 can be formed in situ. In other words, space 611 can be formed in the location previously occupied by sacrificial material layer 703, and doped region 301 can be exposed through space 611.

[0182] In one embodiment, vaporized hydrogen fluoride can be used to remove the sacrificial material layer 703 to form the space 611. Due to the density difference between the sacrificial material 703 (doped oxide) and the insulating layer 113 (undoped oxide), the hydrogen fluoride vapor has a higher etching rate on the doped oxide; therefore, the sacrificial material layer 703 can be removed by vaporized hydrogen fluoride, while the insulating layer 113 can be retained.

[0183] Alternatively, in one embodiment, a heat treatment is applied to remove the sacrificial material layer 703 comprising a thermally decomposable or thermally degradable polymer. The heat treatment temperature can be from about 300°C to about 450°C. Preferably, the heating process temperature can be from about 350°C to about 420°C.

[0184] Please refer to Figure 22 and Figure 30 In step S39, a plurality of contact elements 101 are formed in space 611.

[0185] like Figure 30 As shown, conductive materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof can be deposited into space 611 via a deposition process. Following deposition, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 113TS of the insulating layer 113 is exposed to remove excess material, thereby providing a flat surface for subsequent processing steps and simultaneously forming contacts 101. Contacts 101 can be electrically coupled to the doped region 301.

[0186] For ease of explanation, this disclosure uses only one contact 101 as an example. Contact 101 may include a lower portion 101-1, a middle portion 101-3, and an upper portion 101-5. The lower portion 101-1 may be formed on the doped region 301, below the first dielectric layer 501, and between a plurality of contact gap walls 407. The middle portion 101-3 may be formed on the lower portion 101-1 and disposed along the first dielectric layer 501. The upper portion 101-5 may be formed on the middle portion 101-3 and between a corresponding pair of adjacent insulating layers 113. The width W10 of the upper portion 101-5 may be greater than the width W9 of the middle portion 101-3. The wider upper portion 101-5 increases the contact area, thereby reducing the contact resistance.

[0187] Figures 31 to 33 These are schematic cross-sectional views of semiconductor elements 1F, 1G, and 1H, respectively, according to several embodiments of the present disclosure.

[0188] like Figure 31 As shown, semiconductor element 1F can have the same characteristics as... Figure 30 Similar structure to the embodiments. In Figure 31 As shown Figure 7Identical or similar components are labeled with the same component designation, and redundant descriptions are omitted. Semiconductor element 1F may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed between the contact 101 and the doped region 301, and may be formed of, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The thickness of the bottom conductive layer 111 may be between approximately 2 nm and approximately 20 nm. The bottom conductive layer 111 can reduce the contact resistance between the contact 101 and the doped region 301.

[0189] like Figure 32 As shown, semiconductor element 1G can have the same characteristics as... Figure 7 Similar structure to the embodiment. In Figure 31 As shown Figure 7 Identical or similar components are labeled with the same component designation, and redundant descriptions are omitted. Semiconductor element 1G may include a buried insulating layer 409 disposed beneath fin 403. In other words, the buried insulating layer 409 may be disposed between fin 403 and substrate 401. The buried insulating layer 409 may be formed of a crystalline or amorphous dielectric material, such as oxides and / or nitrides. Furthermore, the buried insulating layer 409 may be a dielectric oxide such as silicon oxide. In another embodiment, the buried insulating layer 409 may be a dielectric nitride such as silicon nitride or boron nitride. In yet another embodiment, the buried insulating layer 409 may comprise a stack of dielectric oxides and dielectric nitrides, for example, silicon oxide and silicon nitride or boron nitride stacked in any order. The buried insulating layer 409 may have a thickness between about 10 nm and 200 nm. The buried insulating layer 409 may eliminate leakage current between gate structures 200 and reduce parasitic capacitance associated with doped regions 301.

[0190] like Figure 33 As shown, semiconductor element 1H may have the same characteristics as... Figure 33 Similar structure to the embodiment. In Figure 33 As shown Figure 21 Identical or similar components are labeled with the same component designation, and redundant descriptions are omitted. Semiconductor element 1H may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed between the lower portion 101-1 of contact 101 and the doped region 301, and may be formed of, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The thickness of the bottom conductive layer 111 may be between approximately 2 nm and approximately 20 nm, and the bottom conductive layer 111 can reduce the contact resistance between the lower portion 101-1 of contact 101 and the doped region 301.

[0191] One aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure located on the fin; a doped region located on one side of the fin; a contact located on the doped region; and a conductive capping layer located on the contact; wherein the conductive capping layer comprises copper germanide.

[0192] Another aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure on the fin; a doped region on one side of the fin; a contact on the doped region; and a top conductive layer on the contact; wherein the top conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0193] Another aspect of this disclosure provides a semiconductor device comprising a fin; a gate structure on the fin; a first dielectric layer on the gate structure; a doped region on one side of the fin; a contact comprising a lower portion disposed on the doped region and below the first dielectric layer, an intermediate portion disposed on the lower portion and along the first dielectric layer, and an upper portion disposed on the intermediate portion; and an insulating layer disposed on the first dielectric layer and adjacent to the upper portion.

[0194] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a gate structure on a fin; forming a doped region on one side of the fin; forming a contact on the doped region; and forming a conductive capping layer on the contact, wherein the conductive capping layer comprises copper germanide.

[0195] Due to the design of the semiconductor device disclosed herein, the conductive capping layer 103 formed of copper germanide can reduce the contact resistance of the semiconductor device 1A. Therefore, the performance of the semiconductor device 1A can be improved, and the energy consumption of the semiconductor device 1A can be reduced.

[0196] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0197] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a fin; a gate structure disposed on the fin; a doped region disposed on a side of the fin; a contact disposed on the doped region; a top conductive layer disposed on the contact; a barrier layer located between the contact and the gate structure and between the contact and the doped region; and a first dielectric layer and a barrier spacer, wherein the first dielectric layer is located on the gate structure, the contact and the barrier layer are disposed along the first dielectric layer and protrude above a top surface of the first dielectric layer, and the barrier spacer is disposed on a side of the barrier layer and the top surface of the first dielectric layer; wherein the top conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

2. A semiconductor device, comprising: a fin; a gate structure disposed on the fin; a doped region disposed on a side of the fin; a contact disposed on the doped region; a top conductive layer disposed on the contact; a first dielectric layer disposed on the gate structure and a second dielectric layer disposed on the first dielectric layer, wherein the contact comprises: a lower portion disposed on the doped region and located below the first dielectric layer; an intermediate portion located on the lower portion and disposed along the first dielectric layer; an upper portion located on the intermediate portion and disposed along the second dielectric layer and protruding above a top surface of the second dielectric layer; and a barrier layer and a barrier spacer, wherein the barrier layer is disposed between the lower portion and the intermediate portion, between the intermediate portion and the first dielectric layer, and on a side of the upper portion, and the barrier spacer is located on a side of the barrier layer and the top surface of the second dielectric layer; wherein the top conductive layer is located on the upper portion.

3. The semiconductor device of claim 2, further comprising a bottom conductive layer disposed between the lower portion and the doped region, wherein the bottom conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. ​ ​

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