Display substrate and display device thereof

Abstract

The present disclosure relates to a display substrate, comprising: a substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a first wiring area, the first wiring area comprising a first sub-wiring area arranged in a first direction away from the display area; a first conductive layer on the substrate; a first dielectric layer on the first conductive layer; a second conductive layer on the first dielectric layer; a second dielectric layer on the second conductive layer; a third conductive layer on the second dielectric layer; a third dielectric layer as a planarization layer on the third conductive layer; a fourth conductive layer on the third dielectric layer. A fourth wiring is electrically connected to a third wiring. A normal projection of the fourth wiring on the substrate at least partially overlaps a normal projection of the third wiring on the substrate.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of display technology, and more specifically, to a display substrate and a display device thereof. Background Technology

[0002] In recent years, with the further development of technology and industry, organic light-emitting diode (OLED) display panels have been widely used in products such as mobile phones, wearable devices, and computers.

[0003] Public content

[0004] Embodiments of this disclosure provide a display substrate. The display substrate includes: a substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first wiring area, the first wiring area including a first sub-wiring area disposed along a first direction away from the display area; a first conductive layer located on the substrate, the first conductive layer including a first portion located in the peripheral area, the first portion of the first conductive layer including a first wiring in the first wiring area; a first dielectric layer located on the first conductive layer; a second conductive layer located on the first dielectric layer, the second conductive layer including a first portion located in the peripheral area, wherein the first portion of the second conductive layer includes a second wiring in the first wiring area, the first wiring and the second wiring being spaced apart from each other along a direction parallel to the substrate; a second dielectric layer located on the second conductive layer; a third conductive layer located on the second dielectric layer, the third conductive layer including a first portion located in the peripheral area, wherein the first portion of the third conductive layer includes a third wiring in the first wiring area; a third dielectric layer located on the third conductive layer as a planarization layer; and a fourth conductive layer located on the third dielectric layer, the fourth conductive layer including a first portion located in the peripheral area, the first portion of the fourth conductive layer including a fourth wiring in the first sub-wiring area. The fourth wiring is electrically connected to the third wiring. The orthographic projection of the fourth wiring on the substrate at least partially overlaps with the orthographic projection of the third wiring on the substrate.

[0005] In embodiments of this disclosure, the third dielectric layer includes a first via located in the first sub-wiring area, exposing the third wiring. The fourth wiring is connected to the third wiring via the first via.

[0006] In embodiments of this disclosure, the third wiring and the fourth wiring constitute a first power signal line.

[0007] In embodiments of this disclosure, the first via includes a first array of first sub-vias and a second array of second sub-vias. The first and second sub-vias are configured such that at least one first sub-via is surrounded by a second sub-via that is closest to the first sub-via, and at least one second sub-via is surrounded by a first sub-via that is closest to the second sub-via.

[0008] In embodiments of this disclosure, at least one first sub-via is located at the center of the shape enclosed by the second sub-via that is closest to the first sub-via. At least one second sub-via is located at the center of the shape enclosed by the first sub-via that is closest to the second sub-via.

[0009] In embodiments of this disclosure, the cross-sectional shape of the first via along a plane parallel to the substrate includes a truncated square.

[0010] In an embodiment of this disclosure, the side length of the truncated square is 11 μm.

[0011] In embodiments of this disclosure, the first portion of the fourth conductive layer includes a second via exposing the third dielectric layer.

[0012] In embodiments of this disclosure, the second via includes a first array of third sub-vias and a second array of fourth sub-vias. The third and fourth sub-vias are configured such that at least one third sub-via is surrounded by the fourth sub-via closest to the third sub-via, and at least one fourth sub-via is surrounded by the third sub-via closest to the fourth sub-via.

[0013] In embodiments of this disclosure, at least one of the third sub-vias is located at the center of the shape enclosed by the fourth sub-via that is closest to the third sub-via. At least one of the fourth sub-vias is located at the center of the shape enclosed by the third sub-via that is closest to the fourth sub-via.

[0014] In embodiments of this disclosure, the cross-sectional shape of the second via along a plane parallel to the substrate includes a square.

[0015] In an embodiment of this disclosure, the side length of the square is 16 μm.

[0016] In embodiments of this disclosure, each of the first vias is located at the center of the shape enclosed by the second via that is closest to the first via. Each of the second vias is located at the center of the shape enclosed by the first via that is closest to the second via.

[0017] In embodiments of this disclosure, the spacing between the first via and the second via is 6.5 μm in the first direction. In a second direction parallel to the substrate and perpendicular to the first direction, the spacing between the first via and the second via is 16.5 μm.

[0018] In embodiments of this disclosure, the display substrate further includes a thin-film transistor located in the display area. The thin-film transistor includes an active layer on the substrate, a gate insulating layer on the active layer, and a gate on the gate insulating layer. The first conductive layer further includes a second portion located in the display area. The second portion of the first conductive layer includes the gate of the thin-film transistor. The third conductive layer further includes a second portion located in the display area. The second portion of the third conductive layer includes the source / drain electrode of the thin-film transistor. The source / drain electrode is connected to the source / drain region of the active layer through the first dielectric layer, the second dielectric layer, and the gate insulating layer.

[0019] In embodiments of this disclosure, the fourth conductive layer further includes a second portion located in the display area. The second portion of the fourth conductive layer extends through the third dielectric layer and is connected to the source / drain electrodes of the thin-film transistor.

[0020] In embodiments of this disclosure, the display substrate further includes a fourth dielectric layer serving as a planarization layer located on the fourth conductive layer; and an encapsulation layer located on the fourth dielectric layer.

[0021] In embodiments of this disclosure, the display substrate further includes a light-emitting device located in the display area and between the fourth dielectric layer and the encapsulation layer. The light-emitting device includes an anode, a light-emitting layer, and a cathode sequentially disposed along a direction perpendicular to the substrate. The anode is located between the fourth dielectric layer and the encapsulation layer. The anode is connected to a second portion of the fourth conductive layer via a via in the fourth dielectric layer. The display substrate further includes a pixel definition layer located between the fourth dielectric layer and the encapsulation layer, defining a light-emitting area. The pixel definition layer has an opening exposing the anode.

[0022] In embodiments of this disclosure, the first wiring area further includes a second sub-wiring area located on the side of the first sub-wiring area away from the display area. The display substrate further includes a dam located in the second sub-wiring area, the dam including a first dam portion and a second dam portion sequentially spaced apart along a direction away from the display area. The first dam portion includes the fourth dielectric layer and the pixel definition layer. The second dam portion includes the third dielectric layer, the fourth dielectric layer, and the pixel definition layer.

[0023] In embodiments of this disclosure, the peripheral region further includes a bent region and a second wiring region sequentially disposed along a first direction away from the display area on the side of the first wiring region away from the display area. The bent region has an opening exposing the substrate through the gate insulating layer, the first dielectric layer, and the second dielectric layer, and a planarization layer covering the opening. The planarization layer includes at least one of the third dielectric layer and the fourth dielectric layer. The second wiring region includes the gate insulating layer, the first dielectric layer, the second dielectric layer, the third conductive layer, the fourth conductive layer, and the fourth dielectric layer sequentially disposed on the substrate along a direction perpendicular to the substrate.

[0024] In embodiments of this disclosure, the display substrate further includes a second power signal line located in the peripheral region and surrounding the display area and the first power signal line. The second power signal line includes at least one of a portion of the third conductive layer located in the peripheral region and a portion of the fourth conductive layer located in the peripheral region. The first power signal line is configured to provide a first voltage. The second power signal line is configured to provide a second voltage. The first voltage is higher than the second voltage.

[0025] In embodiments of this disclosure, the display substrate further includes a passivation layer located between the third conductive layer and the third dielectric layer. The passivation layer is conformal.

[0026] In embodiments of this disclosure, the orthographic projection of the first wiring on the substrate at least partially overlaps with the orthographic projections of the first via and the second via on the substrate. Similarly, the orthographic projection of the second wiring on the substrate at least partially overlaps with the orthographic projections of the first via and the second via on the substrate.

[0027] In embodiments of this disclosure, the encapsulation layer sequentially covers the first sub-wiring area and the dam in a direction parallel to the substrate and away from the display area. At least a portion of the edge of the encapsulation layer lies within the second sub-wiring area.

[0028] In embodiments of this disclosure, the first power signal line further includes portions located in the second sub-wiring area, the bending area, and the second wiring area that are disposed in the same layer as the third conductive layer and / or the fourth conductive layer.

[0029] Embodiments of this disclosure also provide a display device. The display device includes the display substrate described above.

[0030] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application. Attached Figure Description

[0031] The accompanying drawings described herein are for illustrative purposes only, and do not represent all possible implementations, and are not intended to limit the scope of this application, wherein:

[0032] Figure 1 A partial cross-sectional schematic diagram of the peripheral area of ​​a display substrate is shown.

[0033] Figure 2 A plan view of a display substrate according to an embodiment of the present disclosure is shown.

[0034] Figure 3 The following is illustrated according to an embodiment of the present disclosure. Figure 2 The diagram shows a cross-section of the display substrate taken by line aa'.

[0035] Figure 4 A schematic planar arrangement of a first via according to an embodiment of the present disclosure is shown.

[0036] Figure 5 A schematic planar arrangement of a second via according to an embodiment of the present disclosure is shown.

[0037] Figure 6 A schematic planar arrangement of a first via and a second via according to an embodiment of the present disclosure is shown.

[0038] Figure 7 An embodiment according to this disclosure is shown. Figure 2 A magnified planar schematic diagram of part bb' in the diagram.

[0039] Figure 8 An embodiment according to this disclosure is shown. Figure 2 A magnified planar schematic diagram of part cc' in the diagram.

[0040] Figure 9 A plan view of a display device according to an embodiment of the present disclosure is shown.

[0041] Throughout the various views of these accompanying drawings, corresponding reference numerals indicate the respective parts or features. Detailed Implementation

[0042] First, it should be noted that, unless explicitly stated otherwise in the context, the singular form of the words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “comprising” and “or” should be interpreted as including unless otherwise stated herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0043] Additionally, it should be noted that when describing the elements and embodiments thereof in this application, the articles “a,” “an,” “the,” and “the” are intended to indicate the presence of one or more elements; unless otherwise stated, “multiple” means two or more; the terms “comprising,” “including,” “containing,” and “including” are intended to be inclusive and indicate that additional elements may exist besides those listed; the terms “first,” “second,” “third,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order of formation.

[0044] Furthermore, it should be noted that in the description of this disclosure, the terms "above," "on top," "below," "under," "top," "bottom," "between," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must include a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure. In addition, when an element or layer is referred to as being "above" another element or layer, it can be directly on the other element or layer, or there may be intermediate elements or layers; similarly, when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element or layer, or there may be at least one intermediate element or layer; when an element or layer is referred to as being "between" two elements or two layers, it can be the only element or layer between the two elements or two layers, or there may be more than one intermediate element or layer.

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings.

[0046] Currently, due to the increasing pixels per inch (PPI) of display substrates, the wiring in the peripheral areas of the substrates is becoming more numerous and complex. Consequently, the overlay film in the wiring area is extremely uneven. In this situation, when using chemical vapor deposition (CVD) films for encapsulation, the CVD film serving as the overlay film is highly susceptible to poor contact with the underlying film, leading to various encapsulation defects. It should be understood that the underlying film refers to a single or multiple layers formed before the overlay film.

[0047] Specifically, Figure 1 A partial cross-sectional schematic diagram of the peripheral region of a display substrate is shown. For example... Figure 1 As shown, the display substrate includes a substrate 100, a first wiring 131 and a second wiring 151 located on the substrate 100, an encapsulation layer (including a CVD film layer) 250 located on the first wiring 131 and the second wiring 151, and a stacked structure 20 located between the first wiring 131 and the second wiring 151 and the encapsulation layer 250. Each film layer included in the stacked structure 20 is conformal. It should be noted that "conformal" here means that the surface shape of the formed film layer is consistent with or approximately the same as the surface shape of the structure beneath the film layer. Because there are many wirings in the peripheral area and their arrangement is complex, the spacing between, for example, the first wiring 131 and the second wiring 151 is small. Therefore, when the encapsulation layer 250 is formed, poor contact between the encapsulation layer 250 and the underlying film layer (e.g., the stacked structure 20) is likely to occur at location A. For example, the portion of the encapsulation layer 250 at location A does not contact the underlying film layer. This further leads to encapsulation defects.

[0048] Embodiments of this disclosure provide a display substrate that can improve the flatness of wiring in the peripheral area and significantly avoid poor contact between the encapsulation layer and the underlying film layer in the peripheral area, so as to ensure good contact between the encapsulation layer and the underlying film layer, thereby avoiding encapsulation defects and improving product yield.

[0049] Figure 2 A plan view of a display substrate according to an embodiment of the present disclosure is shown. (As shown) Figure 2 As shown, the display substrate 10 may include a substrate 100. The substrate 100 may include a display area AA and a peripheral area surrounding the display area AA. The display substrate 10 may also include a dam 300 located on the substrate 100 and in the peripheral area surrounding the display area AA.

[0050] Figure 2 Other parts shown in the document will be referenced. Figure 3 A description will be provided. Additionally, references will be made. Figure 3The display substrate of the present disclosure is further described.

[0051] It is important to note that Figure 2 and Figure 3 The drawing dimensions and the distances between the shown areas or components are for illustrative purposes only and are exemplary. Those skilled in the art should understand that in practical applications, dimensions, spacing, etc., can be adjusted according to requirements and product design.

[0052] Figure 3 The following is illustrated according to an embodiment of the present disclosure. Figure 2 The diagram shows a cross-section of the display substrate taken by line aa'. Figure 3 As shown, the display substrate 10 may include a substrate 100. As described above, the substrate 100 may include a display area AA and a peripheral area surrounding the display area AA. In embodiments of this disclosure, the peripheral area may include a first wiring area BB. As an example, the first wiring area BB may be, for example, a first fanout area.

[0053] In an exemplary embodiment of this disclosure, the first wiring area BB may include a first sub-wiring area BB' and a second sub-wiring area BB sequentially disposed along a first direction X away from the display area AA.

[0054] In embodiments of this disclosure, the display substrate 10 may further include a first conductive layer 130 located on the substrate 100. The first conductive layer 130 may include a first portion 131 located in a peripheral region. As an example, the first portion 131 of the first conductive layer 130 may include a first wiring (also indicated by reference numeral 131) located in a first wiring region BB.

[0055] In embodiments of this disclosure, the display substrate 10 may further include a first dielectric layer 140 located on the first conductive layer 130. In exemplary embodiments of this disclosure, the first dielectric layer 140 may be conformal. As an example, the first dielectric layer 140 may include an inorganic layer.

[0056] In embodiments of this disclosure, the display substrate 10 may further include a second conductive layer 150 located on the first dielectric layer 140. The second conductive layer 150 may include a first portion 151 located in the peripheral region. As an example, the first portion 151 of the second conductive layer 150 may include a second wiring (also indicated by reference numeral 151) located in the first wiring region BB.

[0057] In embodiments of this disclosure, the first wiring 131 and the second wiring 151 are spaced apart from each other along a direction parallel to the substrate 100 (e.g., a first direction X).

[0058] In embodiments of this disclosure, the display substrate 10 may further include a second dielectric layer 160 located on the second conductive layer 150. In exemplary embodiments of this disclosure, the second dielectric layer 160 may be conformal. As an example, the second dielectric layer 160 may include an interlayer dielectric layer. For instance, the second dielectric layer 160 may include an inorganic layer.

[0059] In embodiments of this disclosure, the display substrate 10 may further include a third conductive layer 170 located on the second dielectric layer 160. The third conductive layer 170 may include a first portion 171 located in the peripheral region. As an example, the first portion 171 of the third conductive layer 170 may include a third wiring (also indicated by reference numeral 171) located in the first wiring region BB.

[0060] In embodiments of this disclosure, the display substrate 10 may further include a third dielectric layer 180 serving as a planarization layer located on the third conductive layer 170. In embodiments of this disclosure, providing the third dielectric layer 180 improves the flatness of wiring within the peripheral region of the display substrate 10. More specifically, because, for example, the spacing between the first wiring 131 and the second wiring 151 is small and the overlay layer is conformal, the resulting structure has an uneven surface. Conversely, by providing the third dielectric layer 180 as a planarization layer over the first wiring 131 and the second wiring 151, embodiments of this disclosure achieve a structural surface with improved flatness, facilitating effective contact between subsequent encapsulation layers and the underlying structure, thereby improving the encapsulation effect.

[0061] In embodiments of this disclosure, the display substrate 10 may further include a fourth conductive layer 190 located on the third dielectric layer 180. The fourth conductive layer 190 may include a first portion 191 located in a peripheral region. As an example, the first portion 191 of the fourth conductive layer 190 may include a fourth wiring (also indicated by reference numeral 191) located in a first sub-wiring region BB'. In an exemplary embodiment of this disclosure, the fourth wiring 191 may be electrically connected to the third wiring 171. In an exemplary embodiment of this disclosure, the orthographic projection of the fourth wiring 191 on the substrate 100 at least partially overlaps with the orthographic projection of the third wiring 171 on the substrate 100.

[0062] In embodiments of this disclosure, the display substrate 10 may further include a fourth dielectric layer 200 as a planarization layer located on the fourth conductive layer 190. As an example, the fourth dielectric layer 200 may include an organic layer.

[0063] In embodiments of this disclosure, the display substrate 10 may further include an encapsulation layer 250 located on the fourth dielectric layer 200. As an example, the encapsulation layer 250 may be a film layer formed by chemical vapor deposition.

[0064] In embodiments of this disclosure, the third dielectric layer 170 may include a first via H1 located in the first sub-wiring region BB' to expose the third wiring 171. Further, the fourth wiring 191 may be connected to the third wiring 171 via the first via H1. Thus, the wiring formed by the connection of the third wiring 171 and the fourth wiring 191 has low resistance, thereby exhibiting better electrical performance.

[0065] In embodiments of this disclosure, the first via H1 may also penetrate the passivation layer (not shown).

[0066] In an exemplary embodiment of this disclosure, the third wiring 171 and the fourth wiring 191 may constitute at least a portion of the first power signal line VDD (e.g., Figure 2 (As shown).

[0067] In other exemplary embodiments of this disclosure, reference is made to Figure 2 and 3 Within the first sub-routing area BB', at least a portion of the first power signal line VDD may be constituted by the third wiring 171 and the fourth wiring 191. Within the second sub-routing area BB' (described later) of the first wiring area BB, at least a portion of the first power signal line VDD may be constituted by the third wiring 171.

[0068] The following is for reference. Figure 4 Describe an example arrangement of the first via H1. It should be understood that... Figure 4 The illustrations are only partial schematic diagrams and are merely exemplary in order to clearly illustrate the embodiments of this disclosure, and should not be regarded as limiting this disclosure.

[0069] Figure 4 A schematic planar arrangement of a first via according to an embodiment of the present disclosure is shown. Figure 4 As shown, in embodiments of this disclosure, the first via H1 may include a first array of first sub-vias H1' and a second array of second sub-vias H1'". In exemplary embodiments of this disclosure, the first sub-vias H1' and the second sub-vias H1' may be configured such that at least one first sub-via H1' may be surrounded by the second sub-via H1' that is closest to the first sub-via H1', ​​and at least one second sub-via H1' may be surrounded by the first sub-via H1' that is closest to the second sub-via H1'.

[0070] In an exemplary embodiment of this disclosure, at least one first sub-via H1' may be located at the center of the shape (e.g., the shape may be a square) enclosed by the second sub-via H1” that is closest to the first sub-via H1'. At least one second sub-via H1” may be located at the center of the shape (e.g., the shape may be a square) enclosed by the first sub-via H1' that is closest to the second sub-via H1”.

[0071] In the embodiments of this disclosure, the above-described settings of the positions of the first and second sub-vias can meet the flatness requirements of the upper coating layer and facilitate electrical contact between the third wiring 171 and the fourth wiring 191. It should be understood that those skilled in the art can set the distribution density and size of the first and second sub-vias according to needs, such as flatness requirements and electrical characteristic requirements, and this disclosure does not impose specific limitations herein.

[0072] In an exemplary embodiment of this disclosure, the cross-sectional shape of the first via H1 along a plane parallel to the substrate 100 may include, for example, a truncated square, such as... Figure 4 As shown.

[0073] In an exemplary embodiment of this disclosure, the side length d1 of the truncated square can be 11 μm. It should be noted that this side length refers to the side length of the square before it is truncated.

[0074] It should be noted that, Figure 4 The dimensions of the sub-vias and the spacing between them shown are merely exemplary to clearly illustrate embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. It will be understood that the spacing between the sub-vias may be shown as larger or smaller.

[0075] Refer again Figure 3 In embodiments of this disclosure, the first portion 191 of the fourth conductive layer 190 may include a second via H2 exposing the third dielectric layer 180. In embodiments of this disclosure, the second via H2 is used to drain gas remaining in the third dielectric layer 180 during its formation, which would otherwise damage the structural layers of the display substrate, for example, causing peeling or detachment between the first portion 191 of the fourth conductive layer 190 and the underlying film layer.

[0076] In an exemplary embodiment of this disclosure, the third wiring 171 and the fourth wiring 191 may constitute at least a portion of the first power signal line VDD (e.g., Figure 2 (As shown). In an exemplary embodiment of this disclosure, the orthographic projection of the second via H2 on the substrate 100 at least partially overlaps with the orthographic projection of the first power signal line VDD on the substrate 100.

[0077] The following is for reference. Figure 5 Describe an example arrangement of the second via H2. It should be understood that... Figure 5 The illustrations are only partial schematic diagrams and are merely exemplary in order to clearly illustrate the embodiments of this disclosure, and should not be regarded as limiting this disclosure.

[0078] Figure 5 A schematic planar arrangement of a second via according to an embodiment of the present disclosure is shown. Figure 5As shown, in embodiments of this disclosure, the second via H2 may include a first array of third sub-vias H2' and a second array of fourth sub-vias H2'". In exemplary embodiments of this disclosure, the third sub-vias H2' and the fourth sub-vias H2' may be configured such that at least one third sub-via H2' may be surrounded by the fourth sub-via H2' that is closest to it, and at least one fourth sub-via H2' may be surrounded by the third sub-via H2' that is closest to it.

[0079] In an exemplary embodiment of this disclosure, at least one third sub-via H2' may be located at the center of the shape (e.g., the shape may be a square) enclosed by the fourth sub-via H2” that is closest to the third sub-via H2'. At least one fourth sub-via H2” may be located at the center of the shape (e.g., the shape may be a square) enclosed by the third sub-via H2' that is closest to the fourth sub-via H2”.

[0080] In the embodiments of this disclosure, the above-described arrangement of the positions of the third and fourth sub-vias can achieve good electrical effects, such as reducing the resistance of the fourth wiring 191. It should be understood that those skilled in the art can adjust the distribution density and size of the third and fourth sub-vias as needed, such as electrical characteristic requirements, and this disclosure does not impose specific limitations therein.

[0081] In an exemplary embodiment of this disclosure, the cross-sectional shape of the second via H2 along a plane parallel to the substrate 100 may include, for example, a square, such as... Figure 5 As shown.

[0082] In an exemplary embodiment of this disclosure, the side length d2 of the square can be 16 μm.

[0083] It should be noted that, Figure 5 The dimensions of the sub-vias and the spacing between them shown are merely exemplary to clearly illustrate embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. It is understood that the spacing between the sub-vias may be shown as larger or smaller. Furthermore, it should be understood that the shapes of the sub-vias shown in the figures are approximate and are merely exemplary. For example, when a sub-via is designed as a square, due to limitations in actual manufacturing processes, the shape of the sub-via obtained after the actual manufacturing process may have a chamfered shape (e.g., the included angle between the side lengths is less than or greater than 90 degrees).

[0084] The following is for reference. Figure 6 Describe an example arrangement of the first via H1 and the second via H2. It should be understood that... Figure 6 The illustrations are only partial schematic diagrams and are merely exemplary in order to clearly illustrate the embodiments of this disclosure, and should not be regarded as limiting this disclosure.

[0085] Figure 6 A schematic planar arrangement of a first via and a second via according to an embodiment of the present disclosure is shown. Figure 6 As shown, in an exemplary embodiment of this disclosure, at least one first via H1 may be located at the center of the shape enclosed by the second via H2 that is closest to the first via H1. At least one second via H2 may be located at the center of the shape enclosed by the first via H1 that is closest to the second via H2. This arrangement allows for sufficient venting of the portion of the third dielectric layer 180 located between the first vias H1.

[0086] In the embodiments of this disclosure, the positional relationship between the first and second vias, as described above, facilitates the removal of moisture contained in the third dielectric layer 180 during the fabrication process, thereby achieving a higher yield. As an example, the second via H2 can be positioned at the center of the shape enclosed by the surrounding first vias H1, as disclosed in the embodiments of this disclosure, to ensure complete removal of moisture from the third dielectric layer 180. It should be understood that, on the one hand, those skilled in the art can design the position, distribution density, and size of the first via H1 according to actual needs, such as flatness requirements and electrical characteristic requirements; on the other hand, those skilled in the art can design the position, distribution density, and size of the second via H2 according to actual needs, such as moisture removal requirements and the planar arrangement of the first via H1, and this disclosure does not impose specific limitations herein.

[0087] In an exemplary embodiment of this disclosure, the distance d3 between the first via H1 and the second via H2 in the first direction X can be, for example, 6.5 μm. In the second direction Y, which is parallel to the substrate 100 and perpendicular to the first direction X, the distance d4 between the first via H1 and the second via H2 can be, for example, 16.5 μm.

[0088] The following description is referenced again. Figure 3 In embodiments of this disclosure, the display substrate 10 may further include a thin-film transistor (TFT) located in the display area AA. In exemplary embodiments of this disclosure, the thin-film transistor (TFT) may include an active layer 110 located on the substrate 100, a gate insulating layer 120 located on the active layer 110, and a gate 132' located on the gate insulating layer 120.

[0089] In embodiments of this disclosure, the first conductive layer 130 may further include a second portion 132 located in the display area AA. In an exemplary embodiment of this disclosure, the second portion 132 of the first conductive layer 130 may include the gate 132' of a thin-film transistor (TFT). In an exemplary embodiment of this disclosure, the second portion 132 of the first conductive layer 130 may further include a first electrode 132 of a capacitor.

[0090] In embodiments of this disclosure, the second conductive layer 150 may further include a second portion 152 located in the display area AA. As an example, the second portion 152 of the second conductive layer 150 may include the second electrode of the aforementioned capacitor (also indicated by reference numeral 152).

[0091] It should be understood that the capacitors described above can be configured similarly to those in conventional pixel driving circuits. Other descriptions of the capacitors, as are known in the art, will not be repeated here.

[0092] In embodiments of this disclosure, the third conductive layer 170 may further include a second portion 172 located in the display area AA. In an exemplary embodiment of this disclosure, the second portion 172 of the third conductive layer 170 may include the source / drain electrodes of the thin-film transistor TFT (also indicated by reference numeral 172). In an exemplary embodiment of this disclosure, the source / drain electrodes 172 may be connected to the source / drain region of the active layer 110 in sequence through the second dielectric layer 160, the first dielectric layer 140, and the gate insulating layer 120.

[0093] In embodiments of this disclosure, the fourth conductive layer 190 may further include a second portion 192 located in the display area AA. In an exemplary embodiment of this disclosure, the second portion 192 of the fourth conductive layer 190 passes through the third dielectric layer 180 and is connected to the source / drain electrode 172 of the thin-film transistor TFT. As an example, the second portion 192 of the fourth conductive layer 190 may be used as a power signal line to control the operation of the thin-film transistor. For example, the power signal line may input a high voltage or a low voltage.

[0094] In embodiments of this disclosure, the display substrate 10 may further include a light-emitting device (OLED) located in the display area AA and between the fourth dielectric layer 200 and the encapsulation layer 250. In exemplary embodiments of this disclosure, the OLED may include an anode 210, a light-emitting layer 230, and a cathode 240 sequentially disposed along a third direction Z perpendicular to the substrate 100. Specifically, the anode 210 may be located between the fourth dielectric layer 200 and the encapsulation layer 250. Further, the anode 210 may be connected to a second portion 192 of the fourth conductive layer 190 via a third via H3 in the fourth dielectric layer 200.

[0095] In embodiments of this disclosure, the display substrate 10 may further include a pixel definition layer 220 defining a light-emitting region located between the fourth dielectric layer 200 and the encapsulation layer 250. In exemplary embodiments of this disclosure, the pixel definition layer 220 may have an opening O1 exposing the anode 210 of the light-emitting device OLED.

[0096] refer to Figure 2-3In embodiments of this disclosure, the display substrate 10 may further include a dam 300 located in the second sub-wiring area BB". Specifically, the dam 300 surrounds the display area AA. The dam 300 can, for example, prevent water and oxygen from entering the display area AA.

[0097] In embodiments of this disclosure, reference is made to Figure 3 In a direction parallel to the substrate 100 and away from the display area AA (e.g., the X direction), the encapsulation layer 250 may sequentially cover the first sub-wiring area BB' and the dam 300, and at least a portion of the edge of the encapsulation layer 250 may be located within the second sub-wiring area BB'".

[0098] Continue to refer to Figure 3 In an exemplary embodiment of this disclosure, the dam 300 may include at least a first dam portion 300' and a second dam portion 300 arranged sequentially at intervals along a first direction X away from the display area AA.

[0099] In an exemplary embodiment of this disclosure, the first dam portion 300' may include a fourth dielectric layer 200 and a pixel definition layer 220. Specifically, the first dam portion 300' may, for example, include a portion 201 of the fourth dielectric layer 200 located in the second sub-wiring area BB” and a portion 221 of the pixel definition layer 220 located in the second sub-wiring area BB”. Figure 3 As shown, a portion 221 of the pixel definition layer 220 can cover a portion of the first portion 171 of the third conductive layer 170 and a portion 201 of the fourth dielectric layer 200.

[0100] In an exemplary embodiment of this disclosure, the second dam portion 300" may include a third dielectric layer 180, a fourth dielectric layer 200, and a pixel definition layer 220. Specifically, the second dam portion 300" may, for example, include portion 181 of the third dielectric layer 180 located in the second sub-wiring area BB", portion 202 of the fourth dielectric layer 200 located in the second sub-wiring area BB", and portion 222 of the pixel definition layer 220 located in the second sub-wiring area BB". Figure 3 As shown, a portion 202 of the fourth dielectric layer 200 can cover the first portion 171 of the third conductive layer 170 and a portion 181 of the third dielectric layer. A portion 222 of the pixel definition layer 220 can cover the first portion 171 of the third conductive layer 170 and a portion 202 of the fourth dielectric layer 200.

[0101] It should be understood that the membrane layers and their stacking relationship in the first dam portion 300' and the second dam portion 300" are merely exemplary. For example, the first dam portion 300' and the second dam portion 300" may contain more or fewer membrane layers. Optionally, the dam 300 may, for example, contain only either the first dam portion 300' or the second dam portion 300" . It is understood that Figure 3The illustrations are intended to clearly illustrate the embodiments of this disclosure and should not be considered as limiting the scope of this disclosure.

[0102] Continue to refer to Figure 2-3 In embodiments of this disclosure, the peripheral region of the display substrate 10 may further include a bending region CC and a second wiring region DD sequentially disposed along a first direction X away from the display region AA on the side of the first wiring region BB that is away from the display region AA. As an example, the second wiring region DD may be, for example, a second fan-out region.

[0103] refer to Figure 3 In an exemplary embodiment of this disclosure, the bending region CC may have an opening O2 through the gate insulating layer 120, the first dielectric layer 180, and the second dielectric layer 200, in the exposed substrate 100, and a planarization layer 260 covering the opening O2. For example, as Figure 3 As shown, the planarization layer 260 may also cover the first portion 171 of the third conductive layer 170 and the second dielectric layer 160.

[0104] In an exemplary embodiment of this disclosure, the planarization layer 260 may include at least one of a third dielectric layer 180 and a fourth dielectric layer 200. More specifically, the planarization layer 260 may include at least one of a portion of the third dielectric layer 180 located in the bending region CC and a portion of the fourth dielectric layer 200 located in the bending region CC.

[0105] In an exemplary embodiment of this disclosure, the second wiring region DD may include a gate insulating layer 120, a first dielectric layer 140, a second dielectric layer 160, a third conductive layer 170, a fourth conductive layer 190, and a fourth dielectric layer 200 disposed sequentially along a third direction Z perpendicular to the substrate 100.

[0106] More specifically, in an exemplary embodiment of this disclosure, the second wiring region DD may include a portion of the gate insulating layer 120 located in the second wiring region DD, a portion of the first dielectric layer 140 located in the second wiring region DD, a portion of the second dielectric layer 160 located in the second wiring region DD, a third portion 173 of the third conductive layer 170 located in the second wiring region DD, a third portion 193 of the fourth conductive layer 190 located in the second wiring region DD, and a portion 203 of the fourth dielectric layer 200 located in the second wiring region DD.

[0107] Continue to refer to Figure 2 In embodiments of this disclosure, the display substrate 10 may further include a second power signal line VSS located in the peripheral area and surrounding the display area AA and the first power signal line VDD.

[0108] In an exemplary embodiment of this disclosure, the second power signal line VSS may further include at least one of a portion of the third conductive layer 170 located in the peripheral region and a portion of the fourth conductive layer 190 located in the peripheral region.

[0109] In an exemplary embodiment of this disclosure, a first power signal line VDD can be configured to provide a first voltage. A second power signal line VSS can be configured to provide a second voltage. As an example, the first voltage may be higher than the second voltage. It should be noted that "high" and "low" here refer only to the relative magnitude relationship between the input voltages.

[0110] In embodiments of this disclosure, optionally, the first power signal line VDD may further include portions located in the second sub-wiring area BB", the bend area CC, and the second wiring area DD that are disposed on the same layer as the third conductive layer 170 and / or the fourth conductive layer 190. For a description of "disposed on the same layer," please refer to the corresponding description above, and it will not be repeated here.

[0111] As an example, the first power signal line VDD may further include portions located in the second sub-wiring area BB", the bend area CC and the second wiring area DD that are disposed on the same layer as the third conductive layer 170.

[0112] As another example, the first power signal line VDD may further include portions located in the second sub-wiring area BB", the bend area CC and the second wiring area DD that are disposed on the same layer as the fourth conductive layer 190.

[0113] As another example, the first power signal line VDD may further include portions located in the second sub-wiring area BB", the bend area CC, and the second wiring area DD that are disposed on the same layer as the third conductive layer 170 and the fourth conductive layer 190. In this case, the corresponding portions disposed on the same layer as the third conductive layer 170 and the corresponding portions disposed on the same layer as the fourth conductive layer 190 may be electrically connected via vias to provide the required electrical performance.

[0114] In embodiments of this disclosure, the display substrate 10 may further include a passivation layer (not shown) located between the third conductive layer 170 and the third dielectric layer 180. In exemplary embodiments of this disclosure, the passivation layer may be conformal. As an example, the passivation layer may include an inorganic layer. It should be understood that forming a passivation layer on the third conductive layer 170 can prevent the precipitation of materials constituting the third conductive layer 170, such as metals, thereby ensuring product quality.

[0115] The following will refer to Figure 7-8 describe Figure 2 Details of parts bb' and parts cc'.

[0116] Figure 7An embodiment according to this disclosure is shown. Figure 2 A magnified planar schematic diagram of part of bb'. (Reference) Figure 2 and Figure 7 , Figure 7 This shows a partial planar layout of the peripheral area of ​​the display substrate 10. More specifically, Figure 7 The diagram shows a partial planar layout of the first wiring area BB in the peripheral area of ​​the display substrate 10.

[0117] In an exemplary embodiment of this disclosure, at least a portion of the first power signal line VDD may span the region where the third dielectric layer 180 is disposed. For example, at least a portion of the first power signal line VDD may be located between the boundary 180' of the third dielectric layer 180 near the display area AA and the boundary 180” of the third dielectric layer 180 away from the display area AA.

[0118] In exemplary embodiments of this disclosure, reference is made to Figure 7 The first wiring 131 and the second wiring 151 can cross the boundary 180' of the third dielectric layer 180.

[0119] In an exemplary embodiment of this disclosure, the first wiring 131 and the second wiring 151 may also span portions of the first via H1 and the second via H2.

[0120] In exemplary embodiments of this disclosure, reference is made to Figure 2-3 7. The orthographic projection of the first wiring 131 on the substrate 100 may at least partially overlap with the orthographic projections of the first via H1 and the second via H2 on the substrate 100.

[0121] In an exemplary embodiment of this disclosure, the orthographic projection of the second wiring 151 on the substrate 100 may at least partially overlap with the orthographic projections of the first via H1 and the second via H2 on the substrate 100.

[0122] In an exemplary embodiment of this disclosure, the first wiring 131 can be electrically connected to a data line in the display area. As an example, the data line can be disposed in the same layer as the source / drain electrode 172 of the thin-film transistor (TFT). For example, the first wiring 131 can be electrically connected to the data line via vias in the first dielectric layer 140 and the second dielectric layer 160. Here, "disposed in the same layer" means formed by the same film layer in the same step. It should be noted that "same film layer" in the embodiments of this disclosure can refer to a film layer located on the same structural layer. Alternatively, for example, film layers at the same level can be film layers formed using the same film deposition process for forming a specific pattern. Then, the desired layer structure can be formed by patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process can include multiple exposure, development, or etching processes. Additionally, as an example, the specific pattern in the formed layer structure can be continuous or discontinuous. As other examples, these specific patterns can be at different heights or have different thicknesses.

[0123] In an exemplary embodiment of this disclosure, the second wiring 151 may be electrically connected to a data line in the display area. Similarly, as an example, the data line may be disposed on the same layer as the source / drain electrode 172 of the thin-film transistor TFT. For example, the second wiring 151 may be electrically connected to the data line via a via in the second dielectric layer 160.

[0124] It should be noted that the various aspects of the data cable mentioned above are well known to those skilled in the art and will not be repeated here.

[0125] In an exemplary embodiment of this disclosure, the second power signal line VSS may cross the boundary 180” of the third dielectric layer 180 away from the display area AA. Furthermore, the second power signal line VSS may partially surround portions of the first power signal line VDD and the first via H1 and the second via H2.

[0126] Figure 8 An embodiment according to this disclosure is shown. Figure 2 A magnified planar schematic diagram of part cc' in the image. (Reference) Figure 2 and Figure 8 , Figure 8 This shows a partial planar layout of the peripheral area of ​​the display substrate 10. More specifically, Figure 8 The diagram shows a partial planar layout of the first wiring area BB in the peripheral area of ​​the display substrate 10.

[0127] and Figure 7 The positional relationship shown is similar, and the first power signal line VDD can cross a portion of the first via H1 and the second via H2.

[0128] Furthermore, in exemplary embodiments of this disclosure, from Figure 8As can be seen, the first power signal line VDD may also have a portion that does not cross the first via H1 and the second via H2. That is, the first power signal line VDD may have a portion extending from the boundary 180” of the third dielectric layer 180 away from the display area AA.

[0129] In an exemplary embodiment of this disclosure, the first power signal line VDD and the second power signal line VSS may extend beyond the dam 300 in a direction away from the display area AA.

[0130] In an exemplary embodiment of this disclosure, the boundary 250' of the encapsulation layer 250 is located on the side of the dam 300 away from the display area AA.

[0131] In an exemplary embodiment of this disclosure, the first power signal line VDD and the second power signal line VSS may extend beyond the boundary 250' of the encapsulation layer 250 in a direction away from the display area AA.

[0132] In embodiments of this disclosure, a display device is also provided. This display device may include the display substrate described above.

[0133] Figure 9 A plan view of a display device according to an embodiment of the present disclosure is shown. Figure 9 As shown, the display device 1 may include a display substrate 10.

[0134] In exemplary embodiments of this disclosure, the display device 1 may be, for example, an OLED display device. Other examples include, the display device 1 may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, navigator, wearable device, e-book reader, etc.

[0135] The foregoing description of embodiments has been provided for illustrative and descriptive purposes. It is not intended to be exhaustive or limiting of the present application. Various elements or features of a particular embodiment are generally not limited to that particular embodiment; however, these elements and features are interchangeable and can be used in chosen embodiments where appropriate, even if not specifically shown or described. Changes are also possible in many ways. Such changes should not be considered as departing from the present application, and all such modifications are included within the scope of this application.

Claims

1. A display substrate, comprising: A substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first wiring area, the first wiring area including a first sub-wiring area disposed along a first direction away from the display area; A first conductive layer located on the substrate, the first conductive layer including a first portion located in the peripheral region, the first portion of the first conductive layer including a first wiring in the first wiring region; A first dielectric layer located on the first conductive layer; A second conductive layer is located on the first dielectric layer, the second conductive layer including a first portion located in the peripheral region, wherein the first portion of the second conductive layer includes a second wiring in the first wiring region, and the first wiring and the second wiring are spaced apart from each other in a direction parallel to the substrate; The second dielectric layer is located on the second conductive layer; A third conductive layer is located on the second dielectric layer, the third conductive layer including a first portion located in the peripheral region, wherein the first portion of the third conductive layer includes a third wiring in the first wiring region; A third dielectric layer, serving as a planarization layer, is located on the third conductive layer; A fourth conductive layer is located on the third dielectric layer, the fourth conductive layer including a first portion located in the peripheral region, the first portion of the fourth conductive layer including a fourth wiring in the first sub-wiring region. The fourth wiring is electrically connected to the third wiring, and the orthographic projection of the fourth wiring on the substrate at least partially overlaps with the orthographic projection of the third wiring on the substrate. The third dielectric layer includes a first via located in the first sub-wiring area, exposing the third wiring, and the fourth wiring is connected to the third wiring via the first via. The first via includes a first array of first sub-vias and a second array of second sub-vias. The first sub-vias and the second sub-vias are configured such that at least one first sub-via is surrounded by the second sub-via that is closest to the first sub-via, and at least one second sub-via is surrounded by the first sub-via that is closest to the second sub-via.

2. The display substrate according to claim 1, wherein, The third wiring and the fourth wiring constitute the first power signal line.

3. The display substrate according to claim 1, wherein, At least one of the first sub-vias is located at the center of the shape enclosed by the second sub-vias that are closest to the first sub-via, and at least one of the second sub-vias is located at the center of the shape enclosed by the first sub-vias that are closest to the second sub-via.

4. The display substrate according to any one of claims 1-3, wherein, The cross-sectional shape of the first via along a plane parallel to the substrate includes a truncated square.

5. The display substrate according to claim 4, wherein, The side length of the truncated square is 11 μm.

6. The display substrate according to claim 1, wherein, The first portion of the fourth conductive layer includes a second via that exposes the third dielectric layer.

7. The display substrate according to claim 6, wherein, The second via includes a first array of third sub-vias and a second array of fourth sub-vias, wherein the third sub-vias and the fourth sub-vias are configured such that at least one of the third sub-vias is surrounded by the fourth sub-via that is closest to the third sub-via, and at least one of the fourth sub-vias is surrounded by the third sub-via that is closest to the fourth sub-via.

8. The display substrate according to claim 7, wherein, At least one of the third sub-vias is located at the center of the shape enclosed by the fourth sub-via that is closest to the third sub-via, and at least one of the fourth sub-vias is located at the center of the shape enclosed by the third sub-via that is closest to the fourth sub-via.

9. The display substrate according to any one of claims 6-8, wherein, The cross-sectional shape of the second via along a plane parallel to the substrate includes a square.

10. The display substrate according to claim 9, wherein, The side length of the square is 16 μm.

11. The display substrate according to claim 6, wherein, At least one of the first vias is located at the center of the shape enclosed by the second via closest to the first via, and at least one of the second vias is located at the center of the shape enclosed by the first via closest to the second via.

12. The display substrate according to claim 11, wherein, In the first direction, the distance between the first via and the second via is 6.5 μm. In a second direction parallel to the substrate and perpendicular to the first direction, the distance between the first via and the second via is 16.5 μm.

13. The display substrate according to claim 1, further comprising a thin-film transistor located in the display area, the thin-film transistor comprising an active layer on the substrate, a gate insulating layer on the active layer, and a gate on the gate insulating layer. in, The first conductive layer further includes a second portion located in the display area, the second portion of the first conductive layer including the gate of the thin-film transistor. The third conductive layer further includes a second portion located in the display area, the second portion of the third conductive layer including the source / drain electrode of the thin film transistor, the source / drain electrode passing through the first dielectric layer, the second dielectric layer and the gate insulating layer and connected to the source / drain region of the active layer.

14. The display substrate according to claim 13, wherein, The fourth conductive layer further includes a second portion located in the display area, the second portion of the fourth conductive layer passing through the third dielectric layer and connected to the source / drain electrode of the thin-film transistor.

15. The display substrate according to claim 14, further comprising a fourth dielectric layer as a planarization layer located on the fourth conductive layer; and An encapsulation layer located on the fourth dielectric layer.

16. The display substrate according to claim 15, further comprising a light-emitting device located in the display area and between the fourth dielectric layer and the encapsulation layer, the light-emitting device comprising an anode, a light-emitting layer, and a cathode sequentially disposed along a direction perpendicular to the substrate, wherein, The anode is located between the fourth dielectric layer and the encapsulation layer, and the anode is connected to the second portion of the fourth conductive layer via a via in the fourth dielectric layer. The display substrate further includes a pixel definition layer located between the fourth dielectric layer and the encapsulation layer, defining a light-emitting area, the pixel definition layer having an opening that exposes the anode.

17. The display substrate according to claim 16, wherein, The first wiring area also includes a second sub-wiring area located on the side of the first sub-wiring area away from the display area. The display substrate further includes a dam located in the second sub-wiring area, the dam comprising a first dam portion and a second dam portion arranged sequentially at intervals along a direction away from the display area. The first dam portion includes the fourth dielectric layer and the pixel definition layer. The second dam portion includes the third dielectric layer, the fourth dielectric layer, and the pixel definition layer.

18. The display substrate according to claim 16 or 17, wherein, The peripheral area also includes a bend area and a second wiring area sequentially arranged along the first direction away from the display area on the side of the first wiring area away from the display area. The bending region has an opening exposing the substrate through the gate insulating layer, the first dielectric layer, and the second dielectric layer, and a planarization layer covering the opening, the planarization layer comprising at least one of the third dielectric layer and the fourth dielectric layer. The second wiring region includes the gate insulating layer, the first dielectric layer, the second dielectric layer, the third conductive layer, the fourth conductive layer, and the fourth dielectric layer, which are sequentially disposed on the substrate in a direction perpendicular to the substrate.

19. The display substrate according to claim 2, further comprising a second power signal line located in the peripheral area and surrounding the display area and the first power signal line. The second power signal line includes at least one of the portion of the third conductive layer located in the peripheral region and the portion of the fourth conductive layer located in the peripheral region. in, The first power signal line is configured to provide a first voltage, and the second power signal line is configured to provide a second voltage, wherein the first voltage is higher than the second voltage.

20. The display substrate according to claim 1, further comprising a passivation layer located between the third conductive layer and the third dielectric layer.

21. The display substrate according to claim 6, wherein, The orthographic projection of the first wiring on the substrate at least partially overlaps with the orthographic projections of the first via and the second via on the substrate, and the orthographic projection of the second wiring on the substrate at least partially overlaps with the orthographic projections of the first via and the second via on the substrate.

22. The display substrate according to claim 17, wherein, In a direction parallel to the substrate and away from the display area, the encapsulation layer sequentially covers the first sub-wiring area and the dam, and at least a portion of the edge of the encapsulation layer is located within the second sub-wiring area.

23. The display substrate according to claim 19, wherein, The first wiring area further includes a second sub-wiring area located on the side of the first sub-wiring area away from the display area, and the peripheral area further includes a bending area and a second wiring area sequentially arranged along the first direction away from the display area on the side of the first wiring area away from the display area. The first power signal line further includes a portion located in the second sub-wiring area, the bending area and the second wiring area that is disposed in the same layer as the third conductive layer and / or the fourth conductive layer.

24. A display device comprising a display substrate according to any one of claims 1 to 23.

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