Processor, page table prefetching method, and electronic device

Abstract

A processor, a page table prefetching method, and an electronic device. The processor includes a system memory management unit, a page table prefetching controller, and at least one address request unit. Each address request unit is configured to send at least one target request, and each target request includes a target virtual address. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The system memory management unit is configured to receive the target requests sent by each address request unit to obtain multiple target virtual addresses, and perform address translation on the multiple target virtual addresses to obtain physical addresses. The page table prefetching controller is configured to determine whether to perform a prefetch operation for the Kth-level page table based on the current target virtual address according to the multiple target virtual addresses, where 1 ≤ K < N and K is an integer. This processor can selectively prefetch page tables.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor, a page table prefetching method, and an electronic device. Background Art

[0002] In the field of computer technology, programmers can use any virtual address (VA) within the range specified by the system to write programs. When the central processing unit (CPU) executes an application program, the address used is the virtual address. When allocating memory to a process, it is necessary to map the virtual address to the physical address (PA), and the physical address is the actual physical memory access address. Distinguishing between virtual addresses and physical addresses and using them separately has become the mainstream trend in the industry. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a processor, including a system storage management unit, a page table prefetch controller, and at least one address request unit. Among them, the at least one address request unit is communicatively connected to the system storage management unit, and the page table prefetch controller is communicatively connected to the system storage management unit; each address request unit is configured to send at least one target request, and each target request includes a target virtual address, the target virtual address includes multiple address segments, the multiple address segments include a first address segment to an Nth address segment, N is an integer greater than 1, and the first address segment to the Nth address segment are respectively used to query the first-level page table to the Nth-level page table; the system storage management unit is configured to receive the target requests sent by each address request unit to obtain multiple target virtual addresses, and perform address conversion on the multiple target virtual addresses, so as to obtain multiple physical addresses respectively corresponding to the multiple target virtual addresses; the page table prefetch controller is configured to determine whether to perform a prefetch operation on the Kth-level page table based on the current target virtual address according to the multiple target virtual addresses, where 1 ≤ K < N and K is an integer.

[0004] For example, in the processor provided in an embodiment of the present disclosure, the processor only includes one address request unit, and the page table prefetch controller is located within the address request unit.

[0005] For example, in the processor provided in an embodiment of the present disclosure, the page table prefetch controller is located within the system storage management unit.

[0006] For example, in the processor provided in one embodiment of the present disclosure, whether to perform a prefetch operation on the K-th level page table based on the current target virtual address is determined according to the multiple target virtual addresses, including: determining whether there is regularity in the respective K-th level page tables respectively contained in the multiple target virtual addresses; in response to the existence of regularity in the respective K-th level page tables, determining to perform a prefetch operation on the K-th level page table based on the current target virtual address.

[0007] For example, in a processor provided by an embodiment of the present disclosure, the regularity includes: each K-th level page table is continuous in sequence, or each K-th level page table has an interval smaller than a first preset threshold.

[0008] For example, in the processor provided in one embodiment of the present disclosure, when there is regularity in each K-th level page table, when K≥2, the first level page table to the K-1th level page table corresponding to the first address segment to the K-1th address segment respectively contained in the multiple target virtual addresses are respectively the same.

[0009] For example, in the processor provided in one embodiment of the present disclosure, the page table prefetch controller is also configured to generate prefetch indication information in response to determining to perform a prefetch operation on the K-th level page table based on the current target virtual address, and send the prefetch indication information to the system storage management unit.

[0010] For example, in a processor provided in an embodiment of the present disclosure, the prefetch indication information includes flag information and number information. When the flag information is a valid value, it indicates that a prefetch operation needs to be performed on the K-th level page table. When the flag information is an invalid value, it indicates that a prefetch operation is not performed on the K-th level page table. The number information indicates the number of the K-th level page tables that need to be prefetched.

[0011] For example, in the processor provided in an embodiment of the present disclosure, the system storage management unit is further configured to receive the prefetch indication information, and in response to the flag information being a valid value, perform a prefetch operation on the K-th level page table according to the number information.

[0012] For example, in a processor provided by an embodiment of the present disclosure, the system memory management unit includes a translation lookaside buffer, which is configured to determine whether there is a hit page table during address translation, and to store a pre-fetched K-th level page table.

[0013] For example, in a processor provided by an embodiment of the present disclosure, the number of pre-fetched K-th level page tables is greater than or equal to the difference between the number of the plurality of target virtual addresses and 1.

[0014] For example, in the processor provided by an embodiment of the present disclosure, the system memory management unit further includes an address buffer, and the address buffer is configured to store the multiple target virtual addresses received by the system memory management unit.

[0015] For example, in the processor provided by an embodiment of the present disclosure, the page table prefetch controller is further configured to determine, according to the multiple target virtual addresses, whether to perform a prefetch operation on the Nth level page table based on the current target virtual address.

[0016] For example, in the processor provided in one embodiment of the present disclosure, whether to perform a prefetch operation on the N-th level page table based on the current target virtual address is determined according to the multiple target virtual addresses, including: determining whether there is regularity in the respective N-th level page tables respectively contained in the multiple target virtual addresses; in response to the existence of regularity in the respective N-th level page tables, determining to perform a prefetch operation on the N-th level page table based on the current target virtual address.

[0017] For example, in a processor provided by an embodiment of the present disclosure, the regularity includes: each N-th level page table is continuous in sequence, or each N-th level page table has an interval smaller than a second preset threshold.

[0018] For example, in the processor provided in one embodiment of the present disclosure, when there is regularity in each N-th level page table, the first level page table to the N-1th level page table corresponding to the first address segment to the N-1th address segment respectively contained in the multiple target virtual addresses are respectively the same.

[0019] At least one embodiment of the present disclosure further provides a page table prefetching method for use in a processor provided by any embodiment of the present disclosure, wherein the method comprises: determining, based on the multiple target virtual addresses, whether to perform a prefetching operation on the K-th level page table based on the current target virtual address.

[0020] For example, the method provided by an embodiment of the present disclosure further includes: determining, according to the multiple target virtual addresses, whether to perform a prefetch operation on the Nth level page table based on the current target virtual address.

[0021] At least one embodiment of the present disclosure further provides an electronic device, comprising the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] Figure 1 A diagram showing the basic working principle of a system storage management unit;

[0024] Figure 2 A schematic block diagram of a processor provided for some embodiments of the present disclosure;

[0025] Figure 3 A flowchart of a page table prefetch controller in a processor according to some embodiments of the present disclosure determining whether to perform a prefetch operation on a K-th level page table;

[0026] Figure 4 A flowchart of a page table prefetch controller in a processor according to some embodiments of the present disclosure determining whether to perform a prefetch operation on an N-th level page table;

[0027] Figure 5 A schematic diagram of the structure of a processor provided in some embodiments of the present disclosure;

[0028] Figure 6 A schematic structural diagram of another processor provided in some embodiments of the present disclosure;

[0029] Figure 7 A schematic flow chart of a page table prefetching method provided in some embodiments of the present disclosure;

[0030] Figure 8 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0031] Figure 9 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] The System Memory Management Unit (SMMU) is widely used in various System on Chips (SoCs). It is primarily used to translate virtual addresses into physical addresses, that is, to convert virtual addresses into corresponding physical addresses. To achieve a single virtual-to-physical address translation, the SMMU must repeatedly access the memory (e.g., DDR) to read the page table used for the translation. This time-consuming process results in a long virtual-to-physical address translation, thus reducing SoC performance.

[0035] To improve the efficiency of address translation, a cache is typically integrated within the SMMU. The cache integrated within the SMMU is called a Translation Lookaside Buffer (TLB), also known as a page table cache or a translation bypass cache. The TLB is a type of CPU cache used by the SMMU to improve the speed of translating virtual addresses to physical addresses. The TLB typically has a fixed number of slots for storing tag page table entries that map virtual addresses to physical addresses. The search key is the virtual address, and the search result is the physical address. If the requested virtual address exists in the TLB, a very fast match is generated, and the resulting physical address can then be used to access the memory. If the requested virtual address is not in the TLB, the tag page table is used to translate the virtual address to the physical address, which requires multiple reads of the DDR and takes a long time.

[0036] Figure 1 This is a basic working principle diagram of a system storage management unit. Figure 1As shown, a pre-designed circuit function module applied to an application-specific integrated circuit (ASIC) or a field-programmable logic device (FPGA) or other applicable scenarios is called an intellectual property core (IP core), or also referred to as an IP. The IP can be any logic block or functional block used in an ASIC or FPGA or other applicable scenarios, such as a filter, a memory controller, an interface program, etc., and the embodiments of the present disclosure are not limited to this. Since the IP needs to use an address when implementing its preset function and will issue a request for the address, in the description of this article, the IP can also be referred to as an address request unit.

[0037] In step 1, the IP sends out the virtual address for the operation. After receiving the virtual address, the SMMU begins to convert it. For example, the SMMU first searches its internal TLB. If the TLB hits, it can directly output the converted physical address based on the hit page table. If the TLB does not hit, as shown in step 2, the SMMU needs to read the page table from the DDR. After reading back the page table, the SMMU converts the virtual address into a physical address based on the content of the page table and outputs it. At the same time, the read-back page table is also cached in the TLB. If the SMMU receives the virtual address later, it can directly hit the TLB and directly convert the virtual address into a physical address for output. Finally, as shown in step 3, the SMMU sends out the translated physical address, thereby performing the corresponding operation.

[0038] Solutions to improve address translation efficiency typically focus on increasing the TLB hit rate. There are two common approaches to increasing the probability of a page table hit in the TLB during virtual-to-physical address translation.

[0039] One approach is to increase the capacity of the SMMU's internal TLB. Increasing the TLB capacity allows it to store more page tables, increasing the probability of a page table hit in the TLB during virtual-to-physical address translation, thereby improving virtual-to-physical address translation efficiency. However, this approach significantly increases chip area and power consumption, ultimately increasing chip cost. Therefore, increasing TLB capacity is subject to certain limitations.

[0040] Another way is to prefetch adjacent page tables into the TLB. That is, after a virtual address arrives, when fetching the page table corresponding to the virtual address, the page table corresponding to the adjacent address (marked as VA1) of the virtual address is also fetched into the TLB. When subsequent operations on VA1 are received, the TLB can be directly hit, thereby increasing the hit rate of subsequent virtual address to physical address conversion. This method will increase the hit rate of the TLB to a certain extent, but prefetching page tables will occupy the space of the TLB. Since the total space of the TLB is limited, each time the SMMU fetches a page table from the DDR, some page tables will be prefetched, and these prefetched page tables will occupy the space of the TLB. Therefore, when the TLB resources are tense, the prefetched page tables will kick other page tables out of the TLB, which will affect the efficiency of address conversion and result in an insignificant improvement in the TLB hit efficiency. Therefore, this method is rather blind, and the effect of this page table prefetching method on improving the conversion efficiency is limited.

[0041] At least one embodiment of the present disclosure provides a processor, a page table prefetch method, and an electronic device. The processor can selectively prefetch page tables, avoiding blindness, reducing the storage space occupied by invalid page tables inside the translation lookaside buffer, improving the hit probability, and reducing the bus congestion caused by a large number of prefetched page tables, reducing the occupation of bus resources, and the additional hardware overhead required is small.

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0043] At least one embodiment of the present disclosure provides a processor, which includes a system storage management unit, a page table prefetch controller, and at least one address request unit. At least one address request unit is communicatively connected to the system storage management unit, and the page table prefetch controller is communicatively connected to the system storage management unit. Each address request unit is configured to send at least one target request, and each target request includes a target virtual address. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query the first-level page table to the Nth-level page table. The system storage management unit is configured to receive the target requests sent by each address request unit to obtain multiple target virtual addresses, and perform address conversion on the multiple target virtual addresses to obtain multiple physical addresses respectively corresponding to the multiple target virtual addresses. The page table prefetch controller is configured to determine whether to perform a prefetch operation on the Kth-level page table based on the current target virtual address according to the multiple target virtual addresses, where 1 ≤ K < N and K is an integer.

[0044] Figure 2 A schematic block diagram of a processor provided for some embodiments of the present disclosure. As Figure 2As shown, in some embodiments, the processor 100 includes a system memory management unit 110 , a page table prefetch controller 120 , and at least one address request unit 130 .

[0045] For example, at least one address request unit 130 is communicatively connected to the system storage management unit 110. For example, in some examples, when the processor 100 includes multiple address request units 130, all address request units 130 are communicatively connected to the system storage management unit 110, that is, multiple address request units 130 are commonly connected to the same system storage management unit 110. For example, a pre-designed circuit function module applied to an application-specific integrated circuit (ASIC) or a field programmable logic device (FPGA) or other applicable scenarios is called an intellectual property core (IP core), or also referred to as an IP, and the address request unit 130 can be an intellectual property core. The address request unit 130 can be any logic block or functional block used in an ASIC or FPGA or other applicable scenarios, such as a filter, a memory controller, an interface program, etc., and the embodiments of the present disclosure are not limited to this.

[0046] Each address request unit 130 is configured to send at least one target request. The target request can be any request that is compatible with the function of the address request unit 130, such as a read request, a write request, a delete request, a reply request, or any other type of request, which is not limited in the embodiments of the present disclosure.

[0047] For example, each target request includes a target virtual address, that is, the virtual address required to be used in the operation corresponding to the target request is called the target virtual address. For example, the target virtual address is a virtual address that needs to be converted, such as a virtual address carried by certain requests or instructions. The SMMU needs to convert the target virtual address into a corresponding physical address in order to execute the corresponding request or instruction. For example, in some examples, the target virtual address can be the storage address of the data to be obtained in a read request, or the storage address of the target location to be written in a write request, or the address to be used in other types of requests, and the embodiments of the present disclosure are not limited to this.

[0048] For example, the target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query the first-level page table to the Nth-level page table, that is, the first address segment is used to query the first-level page table, the second address segment is used to query the second-level page table, and so on, the Nth address segment is used to query the Nth-level page table.

[0049] Performing a virtual address to physical address translation usually requires querying multi-level page tables, and querying different-level page tables depends on different bits (bits) of the virtual address. For example, in some examples, assume that the bit width of a certain virtual address is 36 bits, and the virtual address is, for example, 0xaa_bb_cc_000. "aa" is used for addressing the first-level page table, and "aa" is the first address segment; "bb" is used for addressing the second-level page table, and "bb" is the second address segment; "cc" is used for addressing the third-level page table, and "cc" is the third address segment. The page table granularity is 4KB. In this example, N = 3, the SMMU is divided into three-level page tables, and by performing three page table queries, the corresponding physical address can be obtained finally.

[0050] It should be noted that in the embodiments of the present disclosure, the number of bits of the virtual address is not limited to 36 bits, and can also be any other number of bits. The address segment division method and representation method of the virtual address are not limited, and this can be determined according to actual needs. The page table is not limited to being divided into three levels, and can also be any other number of levels. For a detailed description of multi-level page table addressing, reference can be made to the conventional design, which will not be elaborated here. The value of N is not limited and can be any integer greater than 1, which can be determined according to the number of levels of the page table.

[0051] For example, the system memory management unit 110 is configured to receive target requests sent by each address request unit 130 to obtain multiple target virtual addresses, and perform address translation on the multiple target virtual addresses to obtain multiple physical addresses respectively corresponding to the multiple target virtual addresses. For example, the system memory management unit 110 can sequentially perform conversions on each target virtual address one by one, thereby obtaining the corresponding physical addresses one by one. The manner in which the system memory management unit 110 performs address translation can refer to Figure 1 the described manner, which will not be elaborated here.

[0052] For example, the page table prefetch controller 120 is communicatively connected to the system memory management unit 110. The page table prefetch controller 120 is configured to determine whether to perform a prefetch operation for the K-level page table based on the current target virtual address according to multiple target virtual addresses, where 1 ≤ K < N and K is an integer. It should be noted that since K < N, the K-level page table is not the N-level page table, that is, the K-level page table is not the last-level page table. The K-level page table is used to continue querying the next-level page table, and the physical address cannot be directly obtained from the K-level page table.

[0053] For example, the current target virtual address refers to the target virtual address currently undergoing address translation among the multiple target virtual addresses. When performing a page table query for the Kth address segment in the current target virtual address, the page table prefetch controller 120 may determine whether to perform a prefetch operation for the Kth level page table based on the multiple target virtual addresses. That is, when obtaining the Kth level page table corresponding to the Kth address segment in the current target virtual address, it may determine whether to prefetch other Kth level page tables.

[0054] For example, in some examples, the system memory management unit 110 includes a translation lookaside buffer 111. The translation lookaside buffer 111 is configured to determine whether there is a hit page table during address translation and store the pre-fetched K-th level page table. The translation lookaside buffer 111 may be the aforementioned TLB.

[0055] For example, in some examples, the processor 100 includes only one address request unit 130, that is, the number of address request units 130 in the processor 100 is 1. In this case, the page table prefetch controller 120 may be located in the address request unit 130. For example, in other examples, the page table prefetch controller 120 is located in the system memory management unit 110, in which case the number of address request units 130 may be one or more.

[0056] Figure 3 A flowchart of a page table prefetch controller in a processor according to some embodiments of the present disclosure determining whether to perform a prefetch operation on a K-th level page table. For example, the page table prefetch controller 120 determines whether to perform a prefetch operation on a K-th level page table based on a current target virtual address according to multiple target virtual addresses. The specific determination method of the page table prefetch controller 120 includes the following operations: Figure 3 shown.

[0057] Step S11: determining whether there is regularity in each K-th level page table included in the plurality of target virtual addresses;

[0058] Step S12: In response to the regularity of each K-th level page table, determine to perform a prefetch operation on the K-th level page table based on the current target virtual address.

[0059] For example, in step S11, whether there is regularity among the K-th level page tables may include: the K-th level page tables are continuous in sequence, or the K-th level page tables have an interval less than a first preset threshold. For example, the first preset threshold can be any value, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this. Of course, regularity is not limited to the above-mentioned method, and can also be other types of regularities, such as continuity with intervals, conformity to a functional relationship, and a multiple relationship. As long as the K-th level page tables respectively contained in each target virtual address are predictable, it can be considered that there is regularity.

[0060] For example, in some examples, when there is regularity among the K-th level page tables, when K ≥ 2, the first-level page tables to the K-1-th level page tables corresponding to the first address segments to the K-1-th address segments respectively contained in the multiple target virtual addresses are respectively the same, which ensures that the high bits of the virtual address where the address segment used for querying the first-level page table to the K-1-th level page table is located are consistent with the high bits of the virtual address where the address segment corresponding to the prefetched page table is located. Of course, in other examples, the first-level page tables to the K-1-th level page tables corresponding to the first address segment to the K-1-th address segment may also be different, and the embodiments of the present disclosure are not limited to this.

[0061] For example, in step S12, if there is a regularity among the K-th level page tables, it is determined to perform a prefetch operation on the K-th level page table based on the current target virtual address. That is, due to the regularity, when obtaining the K-th level page table of the current target virtual address, at least one other K-th level page table different from the K-th level page table is prefetched at the same time. The prefetched K-th level page table may be a page table required by other target virtual addresses during address translation.

[0062] For example, the page table prefetch controller 120 is further configured to generate prefetch indication information in response to determining to perform a prefetch operation on the K-th level page table based on the current target virtual address, and send the prefetch indication information to the system memory management unit 110 .

[0063] For example, the prefetch indication information includes flag information and number information. The flag information is used to indicate whether the page table needs to be prefetched. When the flag information is a valid value (for example, 1), it indicates that a prefetch operation needs to be performed on the K-th level page table. When the flag information is an invalid value (for example, 0), it indicates that no prefetch operation is performed on the K-th level page table. The number information indicates the number of K-th level page tables that need to be prefetched. For example, the number information can be any value such as 1, 2, 3, 5, etc., and the embodiments of the present disclosure are not limited to this. Moreover, the number information is only valid when the flag information is a valid value. For example, the size of the number information (for example, the number of bits) can be determined according to actual needs.

[0064] The system storage management unit 110 determines whether to prefetch page tables and how many page tables to prefetch based on the prefetch indication information. For example, in some examples, the flag information is 1 and the number information is 2, and the system storage management unit 110 determines that it is necessary to prefetch page tables and prefetch two page tables. For example, in other examples, the flag information is 0 and the number information is 2, and the system storage management unit 110 determines that it is not necessary to prefetch page tables. In this case, since the flag information is 0, the number information is meaningless even if it is 2.

[0065] For example, the system storage management unit 110 is further configured to receive prefetch indication information, and in response to the flag information being a valid value, perform a prefetch operation on the K-th level page table according to the number information. When the received flag information is a valid value, it indicates that a prefetch operation on the K-th level page table is required, so the system storage management unit 110 performs a prefetch operation according to the number information. For example, in some examples, the value of the number information is 3, and the number of K-th level page tables prefetched by the system storage management unit 110 is 3, that is, when obtaining the originally required K-th level page table, 3 other K-th level page tables (for example, 3 consecutive K-th level page tables) are prefetched.

[0066] For example, in some examples, the number of pre-obtained K-th level page tables is greater than or equal to the difference between the number of multiple target virtual addresses and 1. For example, if the system storage management unit 110 currently receives 5 target virtual addresses and is performing address translation for a certain target virtual address, then the number of pre-obtained K-th level page tables is greater than or equal to 4, thereby making the remaining 4 target virtual addresses hit in the translation lookaside buffer 111 as much as possible during the address translation process, thereby improving the efficiency of address translation. Of course, the embodiments of the present disclosure are not limited to this, and the number of pre-obtained K-th level page tables is not limited to satisfying the above relationship, and may not satisfy the above relationship. This can be determined according to actual needs, for example, according to the regular characteristics between multiple target virtual addresses.

[0067] For example, in some examples, when the page table prefetch controller 120 is located within the system memory management unit 110, the system memory management unit 110 further includes an address buffer, and the address buffer is configured to store multiple target virtual addresses received by the system memory management unit 110, thereby facilitating the page table prefetch controller 120 to determine whether to perform page table prefetching based on the multiple target virtual addresses. For example, the larger the storage space of the address buffer, the more virtual addresses that can be stored, the stronger the adaptive page table fetching capability of the page table prefetch controller 120, and the more "intelligent" its decision-making. For example, in some examples, the storage space of the address buffer does not need to be set too large, for example, it can be able to cache about 20 virtual addresses, thereby not resulting in an excessive increase in chip area and power consumption.

[0068] For example, the page table prefetch controller 120 is further configured to determine, according to the multiple target virtual addresses, whether to perform a prefetch operation on the Nth level page table (ie, the last level page table) based on the current target virtual address.

[0069] Figure 4 The following is a flow chart of a page table prefetch controller in a processor according to some embodiments of the present disclosure determining whether to perform a prefetch operation on the Nth level page table. The specific determination method of the page table prefetch controller 120 includes the following operations: Figure 4 shown.

[0070] Step S21: determining whether there is regularity in each of the N-th level page tables included in the plurality of target virtual addresses;

[0071] Step S22: In response to the regularity of each N-th level page table, determine to perform a prefetch operation on the N-th level page table based on the current target virtual address.

[0072] For example, in step S21, whether there is regularity among the N-th level page tables may include: the N-th level page tables are continuous in sequence, or the N-th level page tables have an interval less than a second preset threshold. For example, the second preset threshold can be any value, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this. Of course, regularity is not limited to the above-mentioned method, and can also be other types of regularities, such as continuity with intervals, conformity to a functional relationship, and a multiple relationship. As long as the N-th level page tables respectively contained in each target virtual address are predictable, it can be considered that there is regularity.

[0073] For example, in some examples, when there is regularity among the N-th level page tables, the first to N-1th level page tables corresponding to the first to N-1th address segments respectively contained in the multiple target virtual addresses are respectively the same, which ensures that the high bits of the virtual address where the address segment used for querying the first to N-1th level page tables is located are consistent with the high bits of the virtual address where the address segment corresponding to the prefetched page table is located. Of course, in other examples, the first to N-1th level page tables corresponding to the first to N-1th address segments may also be different, and the embodiments of the present disclosure are not limited to this.

[0074] For example, in step S22, if there is a regularity among the N-th level page tables, it is determined to perform a prefetch operation on the N-th level page table based on the current target virtual address. That is, when obtaining the N-th level page table of the current target virtual address, at least one other N-th level page table different from the N-th level page table is prefetched at the same time. The prefetched N-th level page table may be a page table required by other target virtual addresses during address translation.

[0075] It should be noted that in the embodiments of the present disclosure, the prefetched page table can be the K-th level page table (not the last level page table) or the N-th level page table (the last level page table), that is, the prefetched page table can be any level page table, thereby improving the ability and adaptability of the prefetched page table.

[0076] In the processor provided by the embodiment of the present disclosure, when performing page table prefetching, the adjacent page tables are not directly prefetched back, but it is necessary to make a judgment before determining whether to prefetch the page tables and how many page tables to prefetch. Therefore, by making a judgment to determine whether to prefetch the page tables and how many page tables to prefetch, and passing the prefetch indication information of whether to prefetch the page tables and how many page tables to prefetch to the system storage management unit, the system storage management unit can selectively make the operation of whether to prefetch the page tables. As a result, the effectiveness of the prefetched page tables is higher, the probability of being hit in the subsequent address conversion operation is higher, and it has a strong pertinence.

[0077] Furthermore, by determining whether to perform a prefetch operation on the K-th level page table or the N-th level page table based on multiple target virtual addresses, the K-th level page table or the N-th level page table can be prefetched purposefully, avoiding blindness and reducing the storage space occupied by invalid page tables within the translation lookaside buffer. If it is determined that the K-th level page table or the N-th level page table is to be prefetched, the prefetched K-th level page table or the N-th level page table will be stored in the translation lookaside buffer, and when processing the subsequent address conversion operation of the target virtual address, the hit probability can be increased. Furthermore, due to the selective prefetching of the K-th level page table or the N-th level page table, the number of prefetched page tables can be reduced, thereby reducing bus congestion caused by a large number of prefetched page tables and reducing the occupancy of bus resources, and this can be achieved with only a small increase in hardware overhead.

[0078] Figure 5 A schematic diagram of the structure of a processor provided in some embodiments of the present disclosure is provided. Figure 5 An example is shown in which the page table prefetch controller 120 is located within the address request unit 130 .

[0079] like Figure 5 As shown, the page table prefetch controller 120 is represented by Prefetch_ctrl, the address request unit 130 is represented by IP, and the system memory management unit 110 is represented by SMMU.

[0080] Prefetch_ctrl is set in the IP. Prefetch_ctrl can determine whether to prefetch the page table based on a series of virtual addresses VA that the IP is about to send to the SMMU, and provide the prefetch indication information to the SMMU. For example, the prefetch indication information output by Prefetch_ctrl includes two signals, namely the flag information Prefetch_flag and the number information Prefetch_cnt. The flag information Prefetch_flag is used to indicate whether the virtual address needs to prefetch the page table. When the flag information Prefetch_flag is a valid value (for example, 1), it indicates that the page table needs to be prefetched. When the flag information Prefetch_flag is an invalid value (for example, 0), it indicates that no prefetching is required. The number information Prefetch_cnt indicates the number of page tables that need to be prefetched. This signal is only valid when the flag information Prefetch_flag is a valid value. In the process of converting the virtual address VA into the physical address PA, the SMMU knows whether the page table needs to be prefetched and how many page tables need to be prefetched based on the indication information of these two signals. For example, the pre-fetched page table may be a K-th level page table (not the last level page table) or an N-th level page table (the last level page table). That is, the pre-fetched page table may be a page table of any level.

[0081] For example, when the IP sends a virtual address to the SMMU, the IP is the active initiator of the virtual address. Therefore, when a series of virtual addresses are sent, the Prefetch_ctrl set inside the IP can perceive the relationship between these virtual addresses. Here, the relationship between virtual addresses can refer to the following situations. The first situation is whether these virtual addresses are in the same address range (this address range corresponds to the same page table); the second situation is whether these virtual addresses are in adjacent address ranges (the page tables corresponding to these adjacent address ranges are also adjacent); the third situation is how many adjacent address ranges these virtual addresses are in. Of course, the above situations are only examples, which do not constitute a limitation to the embodiments of the present disclosure.

[0082] For example, in some examples, assuming the page table granularity is 4KB, the IP needs to issue five virtual addresses VA0 through VA4 over a period of time. Their values ​​are VA0: 0x8020_0000, VA1: 0x8020_0100, VA2: 0x8020_1000, VA3: 0x8020_3000, and VA4: 0x8020_7000. These five virtual addresses exhibit the following regularity: VA0 and VA1 are in the same 4KB interval and correspond to the same page table; the page table corresponding to VA2 is adjacent to the page table corresponding to VA0; VA3 differs from VA0 by three page table granularities; and VA4 differs from VA0 by seven page table granularities. Therefore, when the IP sends VA0, its internal Prefetch_ctrl function can detect this regularity among the five virtual addresses and determine whether to perform a page table prefetch (in this case, a prefetch is required).

[0083] Therefore, when the IP sends VA0 to the SMMU, the information on whether page table prefetching is needed can also be passed to the SMMU. The information on whether page table prefetching is needed is indicated by prefetch indication information, which is generated by Prefetch_ctrl set in the IP. For example, the prefetch indication information output by Prefetch_ctrl includes two signals, namely the flag information Prefetch_flag and the number information Prefetch_cnt. The SMMU knows whether the page table needs to be prefetched and how many page tables need to be prefetched based on the flag information Prefetch_flag and the number information Prefetch_cnt, and performs the corresponding prefetch operation. In this example, during the conversion process for VA0, when the SMMU fetches the page table, it can retrieve all 7 adjacent page tables. Then, when the IP subsequently sends VA1 to VA4 to the SMMU, it can directly hit the corresponding page table.

[0084] For example, in other examples, still in Figure 5In the processor architecture shown, assuming the page table granularity is 4KB, the IP must issue five virtual addresses, VA0 through VA4, over a period of time. Their values ​​are VA0: 0x8020_0000, VA1: 0x8020_0100, VA2: 0x8020_0200, VA3: 0x8020_0300, and VA4: 0x8020_0400. These five virtual addresses are within the same 4KB range and correspond to the same page table. Therefore, when the IP sends VA0, the Prefetch_ctrl function within it can detect the regularity between these five virtual addresses and determine whether to perform a page table prefetch (in this case, no prefetch is required). Therefore, when the IP sends VA0 to the SMMU, it can also pass information about whether a page table prefetch is required. During the conversion process for VA0, SMMU only needs to retrieve the corresponding page table without pre-fetching other page tables. When IP subsequently sends VA1 to VA4 to SMMU, it can directly hit the same page table.

[0085] Figure 6 A schematic diagram of the structure of another processor provided in some embodiments of the present disclosure is provided. Figure 6 An example is shown in which the page table prefetch controller 120 is located within the system memory management unit 110 .

[0086] like Figure 6 As shown, the page table prefetch controller 120 is represented by Adaptive_Prefetch, the system memory management unit 110 is represented by SMMU, and the four address request units 130 are represented by IP0, IP1, IP2, and IP3 respectively. For example, the address request units IP0, IP1, IP2, and IP3 are connected to the SMMU signals via the Network on Chip (NOC), and the address request units IP0, IP1, IP2, and IP3 share a set of SMMUs.

[0087] Adaptive_Prefetch is set inside the SMMU. Adaptive_Prefetch can determine whether to prefetch the page table based on a series of virtual addresses VA received by the SMMU and generate prefetch indication information. This prefetch indication information can be passed to the SMMU (the SMMU performs the prefetch operation) or to the DDR (when the DDR has the corresponding processing function, the DDR can receive the prefetch indication information). Similarly, the prefetch indication information generated by Adaptive_Prefetch includes two signals, namely the flag information Prefetch_flag and the number information Prefetch_cnt. For the description of the flag information Prefetch_flag and the number information Prefetch_cnt, please refer to the above content and will not be repeated here. The SMMU knows whether to prefetch the page table and how many page tables to prefetch based on the indication information of these two signals. For example, the prefetched page table can be the K-th level page table (not the last level page table) or the N-th level page table (the last level page table), that is, the prefetched page table can be any level page table.

[0088] For example, in order to make the adaptive page table fetching capability of Adaptive_Prefetch stronger, a large enough cache space can be reserved inside the SMMU to store the received virtual address operations. Figure 6 As shown, when Adaptive_Prefetch is located within the SMMU, the SMMU also includes an address buffer configured to store virtual addresses (or corresponding virtual address operations) received by the SMMU. For example, the address buffer is represented by VA_buffer. The larger the storage space of VA_buffer, the more virtual addresses it can store, the stronger the adaptive page table fetching capability of Adaptive_Prefetch, and the more "intelligent" its decision-making. For example, in some examples, the storage space of VA_buffer does not need to be too large, for example, it can cache about 20 virtual addresses, thereby not causing an excessive increase in chip area and power consumption.

[0089] exist Figure 6 In the example shown, since the page table prefetch controller (Adaptive_Prefetch) is set inside the SMMU, it helps to improve development efficiency, reduce development workload, and facilitate unified processing by the SMMU.

[0090] For example, in order to save resources, multiple IPs (IP0, IP1, IP2, IP3) share a set of SMMUs. Multiple IPs send a series of virtual addresses to the SMMU over a period of time. After these virtual addresses arrive at the SMMU, they are cached in the VA_buffer of the SMMU, waiting for the SMMU to retrieve the page table and translate these virtual addresses. These virtual addresses are cached inside the SMMU at the same time for a period of time, so Adaptive_Prefetch can parse the relationship between these virtual addresses. Here, the relationship between virtual addresses can refer to the following situations. The first situation is whether these virtual addresses are in the same address range (this address range corresponds to the same page table); the second situation is whether these virtual addresses are in adjacent address ranges (the page tables corresponding to these adjacent address ranges are also adjacent); the third situation is how many adjacent address ranges these virtual addresses are in. Of course, the above situations are only examples, which do not constitute a limitation to the embodiments of the present disclosure.

[0091] It should be noted that the above Figure 5 The examples described in this article also apply to determining whether and how many page tables need to be prefetched. Figure 6 The processor architecture shown here differs only in that the multiple virtual addresses used as the basis for the decision have already been sent to the SMMU and cached in the VA_buffer. For example, when multiple virtual addresses are VA0 to VA4, when performing the address translation operation for VA0, the regularity between VA0 to VA4 can be analyzed to determine whether to perform page table prefetching.

[0092] It should be noted that in the embodiments of the present disclosure, the system memory management unit 110, the translation lookaside buffer 111, the page table prefetch controller 120, and the address request unit 130 can be hardware, software, firmware, or any feasible combination thereof, and can be implemented using any architecture, and can be an intellectual property core (IPC), a dedicated or general-purpose circuit, chip, or device, etc., or a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of the system memory management unit 110, the translation lookaside buffer 111, the page table prefetch controller 120, and the address request unit 130.

[0093] It should be noted that Figure 2 、 Figure 5 、 Figure 6The processor structure shown is exemplary and non-restrictive. The processor may include other components and structures as needed, and the embodiments of the present disclosure are not limited thereto. The processor may be any type of chip or circuit with processing capabilities, such as a CPU, a graphics processing unit (GPU), or a general-purpose computing on graphics processing unit (GPGPU), and the embodiments of the present disclosure are not limited thereto.

[0094] The processor provided by the embodiment of the present disclosure can selectively pre-fetch the page table, which can effectively reduce the number of times the page table is read from the memory.

[0095] For example, in some examples, assuming that address translation is required for four virtual addresses and the page table is a four-level structure, i.e., including the first-level page table to the fourth-level page table, in a conventional address translation operation, assuming a miss in the TLB, 16 (i.e., 4+4+4+4) DDR reads are required to complete the translation of these four virtual addresses.

[0096] In the processor provided by the embodiment of the present disclosure, if the first-level page table is regular and can be pre-fetched, when executing the conversion of the first virtual address, the first-level page tables corresponding to the next three virtual addresses are pre-fetched. Then, the next three virtual addresses can directly hit the first-level page table in the TLB during the conversion process, without having to read the corresponding first-level page table in the DDR. Therefore, 13 (i.e., 4+3+3+3) DDR reads are required to complete the conversion of these four virtual addresses.

[0097] If the second-level page table is regular and can be pre-fetched, when executing the conversion of the first virtual address, the second-level page tables corresponding to the next three virtual addresses are pre-fetched. Then, the next three virtual addresses can directly hit the second-level page table in the TLB during the conversion process, without having to read the corresponding second-level page table from the DDR. Therefore, 10 (i.e., 4+2+2+2) DDR reads are required to complete the conversion of these four virtual addresses.

[0098] If the third-level page table is regular and can be pre-fetched, when executing the conversion of the first virtual address, the third-level page tables corresponding to the next three virtual addresses are pre-fetched. Then, the next three virtual addresses can directly hit the third-level page table in the TLB during the conversion process, without having to read the corresponding third-level page table in the DDR. Therefore, 7 (i.e., 4+1+1+1) DDR reads are required to complete the conversion of these 4 virtual addresses.

[0099] If the fourth-level page table is regular and can be pre-fetched, when executing the conversion of the first virtual address, the fourth-level page tables corresponding to the next three virtual addresses are pre-fetched. Then, the next three virtual addresses can directly hit the fourth-level page table in the TLB during the conversion process, without having to read the corresponding fourth-level page table in the DDR. Therefore, four (i.e., 4+0+0+0) DDR reads are required to complete the conversion of these four virtual addresses.

[0100] It can be seen from this that the processor provided by the embodiment of the present disclosure can selectively prefetch any level of page table, effectively reducing the number of times the page table is read from the memory, increasing the hit probability, and improving the efficiency of address conversion.

[0101] At least one embodiment of the present disclosure further provides a page table prefetching method. This method selectively prefetches page tables, avoiding blindness, reducing the storage space occupied by invalid page tables within the translation lookaside buffer, improving the hit probability, and reducing bus congestion caused by a large number of prefetched page tables, thereby reducing bus resource usage and requiring minimal additional hardware overhead.

[0102] Figure 7 A flow chart of a page table prefetching method provided in some embodiments of the present disclosure is provided. The page table prefetching method is used to provide a processor in some embodiments of the present disclosure. Figure 7 As shown, the page table prefetching method includes step S10.

[0103] Step S10: determining, according to the plurality of target virtual addresses, whether to perform a prefetch operation on the K-th level page table based on the current target virtual address.

[0104] For example, in some examples, the page table prefetching method further includes step S20.

[0105] Step S20 : ​​determining, according to the plurality of target virtual addresses, whether to perform a prefetch operation on the Nth level page table based on the current target virtual address.

[0106] For example, steps S10 and S20 may be performed by a page table prefetch controller in a processor. However, the embodiments of the present disclosure are not limited thereto, and may also be performed by the page table prefetch controller in cooperation with other components in the processor. For detailed descriptions and technical effects of steps S10 and S20, reference may be made to the above description of the processor, and will not be repeated here.

[0107] It should be noted that, in the embodiment of the present disclosure, the page table prefetching method may further include more or fewer steps, and the execution order of the steps is not limited, which may be determined according to actual needs.

[0108] At least one embodiment of the present disclosure further provides an electronic device that can selectively prefetch page tables, thereby avoiding blindness, reducing the storage space occupied by invalid page tables within the translation lookaside buffer, improving the hit probability, and reducing bus congestion caused by a large number of prefetched page tables, thereby reducing bus resource usage and requiring minimal additional hardware overhead.

[0109] Figure 8 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 8 As shown, in some embodiments, the electronic device 200 includes a processor 210, which is a processor provided by any embodiment of the present disclosure, for example, Figure 2 The processor 100 shown, Figure 5 The processor shown or Figure 6 The electronic device 200 may be any device with computing capabilities, such as a computer, a server, a smart phone, a tablet computer, etc., and the embodiments of the present disclosure are not limited thereto.

[0110] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. Figure 9 As shown, the electronic device 300 includes a processor provided by any embodiment of the present disclosure, and the electronic device 300 is suitable for implementing the page table prefetching method provided by the embodiment of the present disclosure. The electronic device 300 can be a terminal device or a server. It should be noted that Figure 9 The electronic device 300 shown is only an example and does not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0111] like Figure 9 As shown, the electronic device 300 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 31, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 32 or a program loaded from a storage device 38 to a random access memory (RAM) 33. For example, the processing device 31 may be a processor provided by any embodiment of the present disclosure, such as Figure 2 The processor 100 shown, Figure 5 The processor shown or Figure 6 The processor shown. Various programs and data required for the operation of the electronic device 300 are also stored in the RAM 33. The processing device 31, the ROM 32 and the RAM 33 are connected to each other via a bus 34. An input / output (I / O) interface 35 is also connected to the bus 34.

[0112] Typically, the following devices may be connected to the I / O interface 35: an input device 36 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 37 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 38 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 39. The communication device 39 may allow the electronic device 300 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 9 The electronic device 300 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 300 may instead implement or possess more or fewer devices.

[0113] For detailed description and technical effects of the electronic device 200 / 300, please refer to the above description of the processor, which will not be repeated here.

[0114] There are a few points to note:

[0115] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0116] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0117] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A processor, comprising a system storage management unit, a page table prefetch controller, and at least one address request unit, wherein, the at least one address request unit is communicatively connected to the system storage management unit, and the page table prefetch controller is communicatively connected to the system storage management unit; each address request unit is configured to send at least one target request, each target request includes a target virtual address, the target virtual address includes multiple address segments, the multiple address segments include a first address segment to an Nth address segment, N is an integer greater than 1, and the first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table; the system storage management unit is configured to receive the target requests sent by each address request unit to obtain multiple target virtual addresses, and perform address conversion on the multiple target virtual addresses, so as to obtain multiple physical addresses respectively corresponding to the multiple target virtual addresses; the page table prefetch controller is configured to determine whether to perform a prefetch operation for the Kth-level page table based on the current target virtual address according to the multiple target virtual addresses, where 1 ≤ K < N and K is an integer; wherein, determining whether to perform a prefetch operation for the Kth-level page table based on the current target virtual address according to the multiple target virtual addresses includes: judging whether there is regularity in each Kth-level page table included in the multiple target virtual addresses; in response to the existence of regularity in each Kth-level page table, determining to perform a prefetch operation for the Kth-level page table based on the current target virtual address.

2. The processor according to claim 1, wherein: The processor only includes one address request unit, and the page table prefetch controller is located within the address request unit.

3. The processor according to claim 1, wherein: The page table prefetch controller is located within the system storage management unit.

4. The processor according to claim 1, wherein: The regularity includes: each Kth-level page table is consecutive in sequence, or each Kth-level page table has an interval less than a first preset threshold.

5. The processor according to claim 1, wherein: In the case where there is regularity in each Kth-level page table, when K ≥ 2, the first-level page table to the (K - 1)th-level page table corresponding to the first address segment to the (K - 1)th address segment included in the multiple target virtual addresses are respectively the same. The processor according to claim 1 , wherein: The page table prefetch controller is further configured to generate prefetch indication information in response to determining to perform a prefetch operation for the Kth-level page table based on the current target virtual address, and send the prefetch indication information to the system storage management unit.

7. The processor according to claim 6, wherein: The prefetch indication information includes flag information and number information, when the flag information is a valid value, it indicates that a prefetch operation for the Kth-level page table needs to be performed, and when the flag information is an invalid value, it indicates that a prefetch operation for the Kth-level page table is not performed, the number information indicates the number of the Kth-level page tables to be prefetched.

8. The processor according to claim 7, wherein: The system storage management unit is further configured to receive the prefetch indication information, and in response to the flag information being a valid value, perform a prefetch operation for the Kth-level page table according to the number information.

9. The processor according to claim 8, wherein: The system storage management unit includes a translation lookaside buffer, the translation lookaside buffer is configured to judge whether there is a hit page table during the address conversion process, and store the prefetched Kth-level page table.

10. The processor according to claim 8, wherein: The number of the pre-fetched K-th level page tables is greater than or equal to a difference between the number of the plurality of target virtual addresses and 1.

11. The processor according to claim 3, wherein: The system memory management unit further includes an address buffer configured to store the plurality of target virtual addresses received by the system memory management unit.

12. The processor of claim 1, wherein: The page table prefetch controller is further configured to determine, according to the multiple target virtual addresses, whether to perform a prefetch operation on the Nth level page table based on a current target virtual address.

13. The processor of claim 12, wherein: Determining, according to the multiple target virtual addresses, whether to perform a prefetch operation on the Nth level page table based on the current target virtual address includes: Determining whether there is regularity in each of the N-th level page tables respectively included in the plurality of target virtual addresses; In response to regularity among the N-th level page tables, it is determined to perform a prefetch operation on the N-th level page table based on the current target virtual address.

14. The processor of claim 13, wherein: The regularity includes: each N-th level page table is continuous in sequence, or each N-th level page table has an interval smaller than a second preset threshold.

15. The processor of claim 13, wherein: In the case where there is regularity among the N-th level page tables, the first level page table to the N-1-th level page table corresponding to the first address segment to the N-1-th address segment respectively included in the multiple target virtual addresses are respectively the same.

16. A page table prefetching method, used in the processor according to any one of claims 1 to 15, wherein: The method comprises: Determining, according to the multiple target virtual addresses, whether to perform a prefetch operation on the K-th level page table based on the current target virtual address; Wherein, judging whether to perform a prefetch operation on the K-th level page table based on the current target virtual address according to the multiple target virtual addresses includes: Determining whether there is regularity in each K-th level page table respectively included in the plurality of target virtual addresses; In response to the regularity of each K-th level page table, it is determined to perform a prefetch operation on the K-th level page table based on the current target virtual address.

17. The method according to claim 16, further comprising: It is determined according to the multiple target virtual addresses whether to perform a prefetch operation on the Nth level page table based on the current target virtual address.

18. An electronic device comprising the processor according to any one of claims 1 to 15.

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