A packaging method, a packaging structure and an electronic device

Abstract

The application relates to the technical field of semiconductor packaging, in particular to a packaging method, a packaging structure and electronic equipment. The method comprises the following steps: obtaining a to-be-packaged substrate; the to-be-packaged substrate comprises a high-resistance silicon substrate; the high-resistance silicon substrate has a packaging surface, and the packaging surface is provided with a solder point; the solder point is provided with a surface oxidation layer 7 far away from the surface of the high-resistance silicon substrate; an impedance adjustment layer is made on the packaging surface; the impedance adjustment layer is used for reducing the surface resistivity of the high-resistance silicon substrate; and the surface oxidation layer 7 is etched and removed to obtain a packaging structure. According to the packaging method, the impedance adjustment layer is arranged on the packaging surface of the substrate, the impedance adjustment layer can reduce the resistivity of the surface layer of the high-resistance silicon substrate, the self-bias voltage during radio frequency etching is improved, and therefore the surface oxidation layer 7 of the solder point can be completely removed. The method can reduce the requirement of the high-resistance silicon packaging process on etching equipment, the high-resistance silicon packaging process can be adapted to an existing silicon wafer packaging process production line, and therefore the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a packaging method, a packaging structure and an electronic device. BACKGROUND

[0002] Integrated Passive Device (IPD) technology can integrate discrete passive devices inside a substrate to improve device Q value and system integration. High-resistance substrates have good radio frequency characteristics, and high-resistance silicon IPD technology can produce inductors with a Q value of up to 70 or more. High-resistance silicon IPD is based on thin film technology and has characteristics such as high precision and high integration, and can reduce the size of passive devices by an order of magnitude. At the same time, it can take advantage of mature silicon process platforms to facilitate mass production and reduce costs. In addition, high-resistance silicon IPD technology is compatible with Through Silicon Via (TSV) technology and can achieve three-dimensional laminated packaging. Analysis shows that high-resistance silicon IPD technology has broad application prospects in system integration.

[0003] High-resistance silicon IPD involves copper bumping process when packaging. Copper bumping process refers to the process of making copper-tin bumps on the surface of a chip after the substrate circuit is processed. It provides "point connection" between chips and between chips and substrates. When performing copper bumping process, the surface oxide layer on the solder joint surface needs to be removed by plasma etching to ensure the reliability of the connection between the copper bump and the wafer. Currently, most plasma etching equipment is radio frequency plasma etching equipment. However, when high-resistance silicon wafers are subjected to radio frequency etching, the radio frequency self-bias voltage is low, which cannot completely remove the surface oxide layer on the solder joint surface, affecting the conductivity of the copper bump and the chip. SUMMARY

[0004] The present application provides a packaging method, a packaging structure and an electronic device. By setting an impedance adjustment layer on the packaging surface of the substrate, the impedance of the high-resistance silicon substrate surface is reduced to improve the radio frequency self-bias voltage during radio frequency etching, so that the surface oxide layer on the solder joint surface can be completely removed.

[0005] In a first aspect, the embodiments of the present application disclose a packaging method, comprising:

[0006] obtaining a substrate to be packaged; the substrate to be packaged comprises a high-resistance silicon substrate; the high-resistance silicon substrate has a packaging surface, and the packaging surface is provided with a solder joint; the solder joint has a surface oxide layer away from the surface of the high-resistance silicon substrate;

[0007] making an impedance adjustment layer on the packaging surface; the impedance adjustment layer is used to reduce the surface resistivity of the high-resistance silicon substrate;

[0008] etching the surface oxide layer to obtain a packaging structure.

[0009] Further, the resistivity of the impedance adjustment layer is less than the resistivity of the high-resistance silicon substrate.

[0010] Further, the material of the impedance adjustment layer is polyimide.

[0011] Further, the thickness of the impedance adjustment layer is 5-10 μm.

[0012] Further, the method of manufacturing the impedance adjustment layer on the packaging surface comprises:

[0013] coating a polyimide photoresist layer on the packaging surface;

[0014] performing a patterning process on the polyimide photoresist layer;

[0015] curing the polyimide photoresist layer after the patterning process to obtain the impedance adjustment layer.

[0016] Further, after the etching of the surface oxide layer to obtain a packaging structure, the method further comprises:

[0017] manufacturing a metal electrode on the surface of the solder joint after the surface oxide layer is removed.

[0018] Further, the method of manufacturing a metal electrode on the surface of the solder joint after the surface oxide layer is removed comprises:

[0019] manufacturing a metal connecting layer on the surface of the solder joint after the surface oxide layer is removed;

[0020] manufacturing the metal electrode on the metal connecting layer.

[0021] Further, the material of the metal connecting layer is titanium or a composite of titanium and copper.

[0022] In a second aspect, the embodiments of the present application disclose a packaging structure, which is obtained by the packaging method as described above.

[0023] In a third aspect, the embodiments of the present application disclose an electronic device, which comprises the packaging structure as described above.

[0024] By using the above technical solutions, the packaging method, the packaging structure and the electronic device have the following beneficial effects:

[0025] This packaging method, when packaging a substrate with a high-resistivity silicon substrate, involves setting an impedance adjustment layer on the packaging surface of the substrate. This impedance adjustment layer reduces the impedance of the high-resistivity silicon substrate surface, thereby increasing the self-bias voltage during radio frequency etching, and thus completely removing the oxide layer on the solder joint surface. This method reduces the requirements of etching equipment for high-resistivity silicon packaging processes, making them compatible with existing silicon wafer packaging production lines, thereby reducing production costs. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating an encapsulation method provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the structure of a packaging substrate provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a packaging structure provided in an embodiment of this application.

[0030] The following is supplementary explanation of the attached figures:

[0031] 1-High-resistivity silicon substrate; 2-Protective layer; 3-Impedance adjustment layer; 4-Solder joint; 5-Metallic connection layer; 6-Copper bump; 7-Surface oxide layer. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] The terms "one embodiment" or "an embodiment” as may be used herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the application. The appearances of the phrase "in one embodiment” or "in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are the various embodiments referred to necessarily be all directed to the same application. Furthermore, the terms "a" or "an", as may be used herein, mean "one or more”. The terms "first”, "second”, "third”, etc. as may be used herein and having "their ordinary and customary meanings" could be used to modify a wide variety of concepts in different contexts; however, the meanings of these terms in particular contexts can be intended to be different, and are specifically associated herein. By way of example, the term "a first” could signify the first of a number of concepts or a specific instance of the concept, and the term "a second” could signify the second of the number of concepts or a specific instance of the concept. The context can in some cases make it clear which of the number of concepts is meant, and in other cases the intended context can not be apparent. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including” when used herein, specify the presence of stated features, integers, steps, operations, objects, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, objects, and / or components.

[0034] The high-resistance silicon wafer has a high resistance, and the resistivity reaches 2000 Ω Ω cm. The high-resistance silicon wafer causes great challenges to the existing silicon wafer level packaging production line due to its high resistance. The high-resistance silicon wafer has a relatively high resistance, and actual tests show that the etching self-bias is low during the radio frequency etching for removing the surface oxide layer of the solder joint, and is only about half of that of the ordinary silicon wafer. Moreover, the high-resistance silicon wafer has a low etching amount and a process interruption during the radio frequency etching. Limited by the existing etching equipment, the radio frequency etching cannot completely remove the surface oxide layer of the solder joint, so that the adhesion and conductivity of the copper bump prepared on the surface of the solder joint and the solder joint are low in the subsequent copper bump process, thereby affecting the conduction performance of the copper bump and the chip, and affecting the reliability of the product.

[0035] Therefore, the application provides a packaging method, which makes a resistance adjusting layer on the surface of the high-resistance silicon wafer to reduce the surface resistance of the high-resistance silicon wafer, so as to improve the self-bias during the radio frequency etching, and thus the surface oxide layer of the solder joint can be completely removed.

[0036] Figure 1 A flowchart of a packaging method provided by the application is shown in FIG. 1, which includes the following steps. Figure 1

[0037] S101: obtaining a substrate to be packaged; the substrate to be packaged includes a high-resistance silicon substrate; the high-resistance silicon substrate has a packaging surface, and the packaging surface is provided with a solder joint; the solder joint has a surface oxide layer far from the surface of the high-resistance silicon substrate.

[0038] ​In this embodiment, the substrate to be packaged can be a semi-finished product obtained during the IPD production process, which is processed based on a high-resistivity silicon substrate. The substrate to be packaged can be prepared through relevant processing techniques or can be directly obtained from the market. The preparation method of the substrate to be packaged is not the focus of this embodiment and will not be elaborated upon here.

[0039] In the embodiments of this application, Figure 2 This is a schematic diagram of the structure of a packaging substrate provided in an embodiment of this application, such as... Figure 2 As shown, the substrate to be packaged includes a high-resistivity silicon substrate 1. Generally, a protective layer 2 is disposed on the surface of the high-resistivity silicon substrate 1 to protect it. The protective layer 2 can be made of nitride, oxide, or a composite of nitride and nitride, such as silicon nitride, silicon oxide, or a composite of silicon nitride and silicon oxide. The high-resistivity silicon substrate 1 has two opposing surfaces, one of which is the packaging surface. Pads are disposed on this packaging surface, and the pads include multiple solder joints 4. The surface of the solder joints 4 has a surface oxide layer 7, which to some extent protects the structure of the solder joints 4. However, when packaging the substrate to be packaged with the high-resistivity silicon substrate, the surface oxide layer 7 needs to be removed to ensure the reliable connection between the copper bumps and the solder joints 4.

[0040] S103: An impedance adjustment layer is fabricated on the package surface; the impedance adjustment layer is used to reduce the surface resistivity of the high-resistivity silicon substrate.

[0041] In this embodiment, the surface oxide layer 7 of the solder joint 4 is removed by etching using an RF etching apparatus. The RF etching apparatus etches the surface oxide layer 7 by generating RF plasma. The etching efficiency of the RF etching apparatus is related to the RF self-bias voltage of the RF plasma. To a certain extent, the higher the RF self-bias voltage, the higher the etching efficiency of the RF etching apparatus. For most semiconductor manufacturing manufacturers, their RF facilities and equipment are adapted to ordinary silicon wafer packaging processes, but it is difficult to process high-resistivity silicon wafers. This application adjusts the surface resistivity of the high-resistivity silicon substrate 1 by fabricating an impedance adjustment layer 3 on the packaging surface of the high-resistivity silicon substrate 1, so that the high-resistivity silicon substrate 1 can be adapted to existing silicon wafer packaging equipment.

[0042] In this embodiment, the resistivity of the impedance adjustment layer 3 is lower than the resistivity of the high-resistivity silicon substrate 1. Optionally, the resistivity of the impedance adjustment layer 3 is 10⁻⁶. -5The impedance adjustment layer 3 can be made of metal or non-metal materials. To reduce costs, the impedance adjustment layer 3 can be made of low-cost photoresist materials, such as polyimide or SU8. The photoresist material can reduce the surface resistivity of the high-resistivity silicon substrate 1, thereby increasing the RF self-bias voltage during RF etching. Furthermore, the photoresist material is flexible and can provide a buffering effect in later stages of the high-resistivity silicon processing, improving chip stability. Optionally, the thickness of the impedance adjustment layer 3 can be 5μm-10μm. The specific thickness can be determined based on the selected material.

[0043] In this embodiment, when fabricating the impedance adjustment layer 3, an impedance adjustment layer 3 covering the entire surface can be first fabricated on the package surface and the surface oxide layer 7. Then, through processes such as exposure and development, the impedance adjustment layer on the solder joint is removed, forming an opening in the impedance adjustment layer, thereby exposing the surface oxide layer 7 of the solder joint, so that the surface oxide layer 7 can be etched by the etching equipment. In some embodiments, when fabricating the impedance adjustment layer 3, a mask can also be first fabricated above the solder joint, and then an impedance adjustment layer covering the entire surface can be fabricated on the package surface and the mask surface. Then, the mask is removed, forming an opening in the impedance adjustment layer, thereby exposing the surface oxide layer 7 of the solder joint.

[0044] As an optional implementation, the following describes the fabrication method of the impedance adjustment layer 3 using polyimide as an example. The fabrication method of the impedance adjustment layer 3 using other materials can refer to this implementation. A polyimide film can be formed on the packaging surface by coating polyimide photoresist onto a high-resistivity silicon substrate 1, and then cured by heating to form the impedance adjustment layer. The cured polyimide is flexible and resistant to high temperatures and acids / alkalis. Polyimide, as an impedance adjustment layer, can protect the solder joint structure. When using polyimide to fabricate the impedance adjustment layer 3, firstly, polyimide photoresist is coated onto the packaging surface and the surface oxide layer 7 to form a polyimide film. The coating method can be spin-coating. Then, the polyimide film is patterned, and the patterned polyimide film is cured to obtain the impedance adjustment layer 3. Specifically, after coating a layer of photoresist onto the packaging surface of the high-resistivity silicon substrate 1 and the surface oxide layer 7, the pattern on the photomask is transferred onto the photoresist of the high-resistivity silicon substrate 1 using an exposure machine. The soluble portions of the exposed photoresist are then dissolved in a developer; this process is called photoresist development, which mainly involves accurately copying the pattern from the photomask onto the photoresist. Finally, it is cured in an oxygen-free curing oven to form an impedance adjustment layer 3 on the package surface.

[0045] S105: Etch to remove the surface oxide layer 7 to obtain the encapsulation structure.

[0046] In the embodiment of the present application, after the impedance adjustment layer 3 is made on the packaging surface, the surface oxidation layer 7 is etched to remove the surface oxidation layer 7 on the soldering point 4, and the packaging structure is obtained. Specifically, the to-be-packaged substrate with the impedance adjustment layer 3 is placed in the etching cavity of the radio frequency etching equipment to perform the operation, and the radio frequency self-bias voltage data of the etching is tested. After the impedance adjustment layer is made on the packaging surface, it is found through actual testing that the radio frequency self-bias voltage data of the high-resistance silicon substrate 1 with the impedance adjustment layer 3 is normal, which can meet the etching requirement, so that the etching equipment can normally etch the surface oxidation layer of the soldering point 4.

[0047] In the embodiment of the present application, after the surface oxidation layer 7 on the soldering point 4 is etched and removed, the surface of the soldering point 4 after the surface oxidation layer 7 is removed is used to make a metal electrode. That is, the copper bump 6 is made on the surface of the soldering point 4. Specifically, the metal connection layer 5 is made on the surface of the soldering point 4 after the surface oxidation layer 7 is removed, and the metal electrode is made on the metal connection layer 5. Optionally, the metal connection layer 5 is a titanium layer or a composite metal layer of a titanium layer and a copper layer. The titanium layer can improve the bonding force of copper and the high-resistance silicon substrate 1, play the role of an adhesive layer, and effectively prevent the mutual diffusion between the material of the bump 4 and aluminum and silicon, avoid the formation of an undesirable intermetallic compound, and play the role of a diffusion barrier layer. The copper layer is made on the titanium layer, and the copper layer can serve as an electroplating seed layer to play the role of electrical conduction.

[0048] As an optional implementation, the surface oxidation layer 7 on the soldering point 4 is etched and removed to ensure the adhesion and conductivity of the metal connection layer 5 and the soldering point 4, and then the gluing, photo, electroplating and etching processes and other manufacturing technologies are used to make the copper bump on the surface of the chip to ensure the conductivity of the surface of the soldering point 4 and increase the reliability of the product. Specifically, the high-resistance silicon substrate 1 with the impedance adjustment layer 3 is pretreated before electroplating. In order to obtain a clean and fresh metal surface, increase the hydrophilicity and bonding force, and prepare for obtaining a high-quality plated layer, the surface oxidation layer 7 of the soldering point 4 is etched by plasma. Then the metal connection layer 5 is made on the surface of the impedance adjustment layer 3 and the surface of the soldering point 4. Optionally, the method for making the metal connection layer 5 includes but is not limited to magnetron sputtering, electroplating, evaporation, deposition and other methods. Then the entire sputtered metal connection layer 5 is removed by using chemical reagents, and only the metal connection layer 5 at the soldering point 4 is reserved. Finally, after reflow soldering, the copper bump 6 on the soldering point 4 is obtained.

[0049] In some embodiments, after the copper bump 6 process is completed, the packaging structure is further subjected to a thinning process. Specifically, a protective film is attached to one side of the packaging surface, the front surface of the chip is protected, and then the packaging structure is placed on a grinding machine table to thin the thick sheet to a target thickness. Finally, the protective film is removed, and the thinned wafer is obtained.

[0050] In some embodiments, after the process of the copper bump 6 is completed, the package structure is further subjected to a scribing process. Specifically, a scribing film is attached to the surface of the high-resistance silicon substrate 1 away from the package surface, and then the whole wafer is cut into single chips by a scribing machine using a scribing knife.

[0051] In some embodiments, after the process of the copper bump 6 is completed, the package structure is further subjected to a flip-chip (FC) process. Specifically, a chip flip tool picks up a die from the high-resistance silicon substrate 1 wafer and flips it by 180 degrees to be attached to a substrate pad, and through reflow, the bumps of the chip are welded to the substrate pad.

[0052] In the embodiments of the present application, the high-resistance silicon substrate 1 after packaging usually needs to be subjected to a reliability experiment to verify the product reliability and related parameters, so as to ensure that the product test data meets the requirements in all aspects. The reliability experiment includes high-low temperature test. As an optional implementation, the specific test process is as follows: the high-low temperature test temperature parameter range is -65℃-150℃, and the chip is impacted by a predetermined number of times by a cold and hot impact test machine. Optionally, the predetermined number of times is 1000cys. Referring to the operation standard book of the cold and hot impact test machine, a plurality of good chips after pre-treatment are placed on the grid disc in the cold and hot impact box, the experimental parameters are set to -65℃ / 150℃, 1000cys, the temperature is rapidly increased from -65℃ to 150℃, the temperature is increased to 150℃ in 5min, maintained for 10min, then the temperature is decreased from 150℃ to room temperature in 5min, and then the temperature is decreased from room temperature to -65℃ in 5min, and maintained for 10min. The chip undergoes the high-low temperature process and is cycled 1000 times. Generally, in the high-low temperature test, the high-resistance silicon wafer often has a structure delamination problem, and after a layer of impedance adjustment layer 3 is made on the package surface of the high-resistance silicon substrate 1, the impedance adjustment layer can act as a buffer layer to suppress the internal stress of the high-resistance silicon wafer, so that the structure delamination problem of the high-resistance silicon wafer in the high-low temperature experiment is improved, and the chip reliability of the high-resistance silicon is improved.

[0053] The embodiments of the present application provide a package structure, which is packaged by the packaging method as described above.

[0054] In the embodiments of the present application, the package structure is prepared by the packaging method. Figure 3 A structure diagram of a package structure provided by the embodiments of the present application is shown in Figure 3As shown, the packaging structure includes a high-resistance silicon substrate 1, the high-resistance silicon substrate 1 is provided with a solder pad, the solder pad includes a plurality of solder joints 4. The surface of the high-resistance silicon substrate 1 is further provided with a protective layer 2, the protective layer 2 has a protective layer 2 opening for exposing the solder joint 4 from the protective layer 2. The protective layer 2 is provided with an impedance adjustment layer 3, and optionally, the thickness of the impedance adjustment layer 3 is 5-10 μm. The impedance adjustment layer 3 is used to adjust the surface resistivity of the high-resistance silicon substrate 1, and can improve the radio frequency self-bias when the radio frequency etching equipment etches the high-resistance silicon substrate 1. The impedance adjustment layer 3 is provided with an impedance adjustment layer 3 opening for exposing the solder joint 4 from the protective layer 2. The solder joint 4 is provided with a copper bump 6 for electrical connection with other chip structures.

[0055] The embodiment of the present application provides an electronic device, and the electronic device includes the packaging structure as described above.

[0056] In the embodiment of the present application, the electronic device is a device with integrated passive devices, and the integrated passive device is a high-resistance silicon integrated passive device, that is, the integrated passive device includes the packaging structure as described above.

[0057] The packaging method, packaging structure and electronic device provided by the embodiment of the present application cover an impedance adjustment layer on the surface of the high-resistance silicon substrate, which ensures etching of the solder joint surface oxide layer 7, improves the adhesion of the copper bump layer and the solder joint, ensures the conductive performance of the copper bump and the chip, improves the reliability of the chip, realizes packaging of the high-resistance silicon wafer, and increases the buffering effect in the later process procedure, and improves the stability of the chip. In addition, the high-resistance silicon substrate is provided with an impedance adjustment layer in the packaging structure, which can solve the problem of structure delamination of the high-resistance silicon wafer in the high-low temperature experiment of the chip, and improve the reliability of the high-resistance silicon chip.

[0058] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging method, characterized by, The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device.

2. The packaging method according to claim 1, characterized in that, The application relates to an encapsulation method and encapsulation structure of an electronic device.

3. The packaging method according to claim 2, characterized in that, The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device.

4. The packaging method of claim 1, wherein, The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device.

5. The packaging method according to claim 4, characterized in that, The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device.

6. The packaging method according to claim 5, wherein, The application relates to an encapsulation method and encapsulation structure of an electronic device.

7. A package structure, characterized by, The application relates to an encapsulation method and encapsulation structure of an electronic device.

8. An electronic device, comprising: The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsulation structure of an electronic device. The application relates to an encapsulation method and encapsapsulation

Images