Memory structure and method for forming the same

Abstract

A memory structure and a method for forming the same, wherein the memory structure comprises: a substrate, the substrate comprising a first region and a second region; a floating gate structure located on the second region, and an erase gate structure located on the floating gate structure; a first doped region located within the substrate; a source region located within the first doped region; a source polysilicon layer located on the first region, the source polysilicon layer in contact with the source region; a source polysilicon layer located on the first region; a wordline gate channel region located in the second region; and a wordline gate structure located on the second region. Because the source region is directly connected via the metallized source polysilicon layer, the parasitic resistance of the source region can be significantly reduced. Furthermore, the thickness of the wordline gate oxide layer of the wordline gate structure can be significantly reduced, thereby improving the control of the wordline gate layer over the underlying channel, effectively reducing the wordline voltage during read operations, reducing the risk of read crosstalk, and reducing device size.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be primarily categorized into three types: analog circuits, digital circuits, and mixed analog / digital circuits. Memory is a key component of digital circuits. Within this category, flash memory (Flash Memory) has seen particularly rapid growth in recent years. Its key features include its ability to retain stored information for long periods without power, high integration density, fast storage speeds, and ease of erasure and rewriting. Consequently, it has found widespread application in a variety of fields, including microcomputers and automated control.

[0003] Flash memory is divided into two types: stacked gate flash memory and split gate flash memory. Stacked gate flash memory has a floating gate and a control gate located above the floating gate. Stacked gate flash memory is subject to over-erase issues. Unlike stacked gate flash memory, split gate flash memory has a word line on one side of the floating gate that serves as an erase gate. Split gate flash memory effectively avoids the over-erase effect.

[0004] However, the performance of existing split-gate flash memories is poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the performance of the memory.

[0006] To solve the above problems, the present invention provides a memory structure, comprising: a substrate, the substrate comprising a first region and second regions located on both sides of the first region, and the first region is adjacent to the second region; a floating gate structure located on the second region, and an erase gate structure located on the floating gate structure; a first doped region located in the substrate, the first doped region being located in a portion of the second region and spanning the first region, the first doped region having first ions; a source region located in the first doped region, the source region having second ions, the first ions and the second ions having different electrical types; a source polysilicon layer located on the first region, the source polysilicon layer being in contact with the source region; a word line gate channel region located in the second region; a word line gate structure located in the second region, the word line gate structure being located on one side of the floating gate structure and the erase gate structure, the word line gate structure comprising a word line gate oxide layer and a word line gate layer located on the word line gate oxide layer.

[0007] Optionally, the floating gate structure includes: a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

[0008] Optionally, the erase gate structure includes: an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

[0009] Optionally, the erase gate dielectric layer is a single-layer structure or a multi-layer structure.

[0010] Optionally, when the erase gate dielectric layer is a multi-layer structure, the erase gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0011] Optionally, the erase gate structure further includes: a compensation erase gate layer located on a sidewall of the erase gate layer.

[0012] Optionally, the method further includes: a second sidewall spacer located on the sidewalls of the erase gate structure and the floating gate structure, wherein the second sidewall spacer is located on the first region.

[0013] Optionally, there are third ions in the word line gate channel region, and the third ions are of the same electrical type as the first ions.

[0014] Optionally, the material of the source polysilicon layer includes: polysilicon.

[0015] Optionally, the method further includes: a third sidewall spacer located on the sidewalls of the erase gate structure and the floating gate structure, wherein the third sidewall spacer is located on the second region.

[0016] Optionally, the material of the word line gate layer includes: polysilicon.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a memory structure, comprising: providing a substrate, the substrate comprising a first region and a second region located on both sides of the first region, and the first region is adjacent to the second region; forming a floating gate structure and an erase gate structure located on the floating gate structure on the second region; forming a first doped region in the substrate, the first doped region being located in part of the second region and spanning the first region, the first doped region having a first ion; forming a source region in the first doped region, the source region having a second ion, the first ion and the second ion having a different electrical type; forming a source polysilicon layer on the first region, the source polysilicon layer being in contact with the source region; forming a word line gate channel region in the second region; forming a word line gate structure on the second region, the word line gate structure being located on one side of the floating gate structure and the erase gate structure, the word line gate structure comprising a word line gate oxide layer, and a word line gate layer located on the word line gate oxide layer.

[0018] Optionally, the method for forming a floating gate structure on the second region and an erase gate structure located on the floating gate structure includes: forming a floating gate structure material film on the substrate; forming an erase gate structure material film on the floating gate structure material film; forming a first mask layer on the erase gate structure material film, wherein the first mask layer has a mask opening that exposes a portion of the top surface of the erase gate structure material film; forming a first sidewall on the sidewall of the mask opening; using the first mask layer and the first sidewall as a mask, etching the erase gate structure material film and the floating gate structure material film until the surface of the substrate is exposed, thereby forming an initial erase gate structure and an initial floating gate structure; after forming the initial erase gate structure and the initial floating gate structure, removing the first mask layer; using the first sidewall as a mask, etching the initial erase gate structure and the initial floating gate structure until the surface of the substrate is exposed, thereby forming the erase gate structure and the floating gate structure.

[0019] Optionally, the floating gate structure material film includes: a floating gate dielectric material film, and a floating gate material film located on the floating gate dielectric material film.

[0020] Optionally, the erase gate structure material film includes: an erase gate dielectric material film, and an erase gate material film located on the erase gate dielectric material film.

[0021] Optionally, the erase gate dielectric material film is a single-layer structure or a multi-layer structure.

[0022] Optionally, when the erase gate dielectric material film is a multi-layer structure, the erase gate dielectric material film includes: a first silicon oxide film, a silicon nitride film located on the first silicon oxide film, and a second silicon oxide film located on the silicon nitride film.

[0023] Optionally, the method for forming the initial erase gate structure includes: using the first mask layer and the first side wall as a mask, etching the erase gate material film, the second silicon oxide film and the silicon nitride film until the surface of the first silicon oxide film is exposed; forming a compensation erase gate layer on the exposed side walls of the erase gate material film, the second silicon oxide film and the silicon nitride film; after forming the compensation erase gate layer, using the first mask layer, the first side wall and the compensation erase gate layer as a mask, etching the first silicon oxide film until the surface of the floating gate structure material film is exposed, thereby forming the initial erase gate structure.

[0024] Optionally, the method for forming the first doped region includes: before forming the first sidewall spacer, using the first mask layer as a mask, performing the first ion implantation process on the substrate to form the first doped region.

[0025] Optionally, after forming the initial erase gate structure and the initial floating gate structure, the method further includes: forming a second spacer on sidewalls of the initial erase gate structure and the initial floating gate structure, wherein the second spacer is located on the first region.

[0026] Optionally, the method for forming the source region includes: using the first mask layer, the first sidewall and the second sidewall as masks, performing the second ion implantation process on the first region to form the source region, and the source region is located in the first doping region.

[0027] Optionally, the method for forming the word line gate channel region includes: using the first side wall and the source polysilicon layer as a mask, performing a third ion implantation process on the second region to form the word line gate channel region, wherein the third ion has the same electrical type as the first ion.

[0028] Optionally, after forming the erase gate structure and the floating gate structure, the method further includes: forming a third spacer on the sidewalls of the erase gate structure, the floating gate structure and the first spacer, wherein the third spacer is located on the second region.

[0029] Optionally, the material of the word line gate layer includes: polysilicon.

[0030] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0031] In the memory structure of the technical solution of the present invention, since the source region is not connected to the non-metallized substrate in the vertical direction, but is directly connected to the metallized source polysilicon layer, the parasitic resistance of the source region can be greatly reduced. Due to the special erase gate structure, the word line gate structure does not need to withstand high voltage during the erase, write and read operations. Therefore, the thickness of the word line gate oxide layer of the word line gate structure can be greatly reduced, which improves the control of the word line gate layer on the underlying channel, effectively reduces the word line voltage during the read operation, and reduces the risk of read crosstalk. At the same time, the reduction in the thickness of the word line gate oxide layer of the word line gate structure can also effectively reduce the size of the device structure. In addition, since the sidewalls of the floating gate structure can be coupled with the source region, there is no need to increase the coupling rate by increasing the lateral size of the floating gate structure, further reducing the size of the device structure.

[0032] In the method for forming a memory structure of the technical solution of the present invention, since the source region is not connected to the non-metallized substrate in the vertical direction, but is directly connected to the metallized source polysilicon layer, the parasitic resistance of the source region can be greatly reduced, and the vertical and horizontal grid ACT pattern can be avoided, thereby reducing the process difficulty. Due to the special erase gate structure, the word line gate structure does not need to withstand high voltage during the erase and write operations, so the thickness of the word line gate oxide layer of the word line gate structure can be greatly reduced, which improves the control of the word line gate layer on the underlying channel, effectively reduces the word line voltage during the read operation, and reduces the risk of read crosstalk. At the same time, the reduction in the thickness of the word line gate oxide layer of the word line gate structure can also effectively reduce the size of the device structure. In addition, since the sidewalls of the floating gate structure can be coupled with the source region, there is no need to increase the lateral size of the floating gate structure to increase the coupling rate, further reducing the size of the device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a cross-sectional schematic diagram of a flash memory;

[0034] Figures 2 to 14 It is a schematic structural diagram of each step of the memory structure and its formation method in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] As described in the background art, the performance of existing split-gate flash memories is relatively poor, which will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a cross-sectional diagram of a flash memory.

[0037] Please refer to Figure 1 A flash memory comprises: a substrate 100, wherein the substrate 100 includes an erase area A and a floating gate area B, wherein the floating gate area B is adjacent to the erase area A and is located on both sides of the erase area A; an erase gate structure 130 located on the erase area A; floating gate structures 120 respectively located on the floating gate areas B; a word line gate structure 140 located on one side of the floating gate structure 120, wherein the floating gate structure 120 is located between the erase gate structure 130 and the word line gate structure 140; a source region 110 located in the erase area A; and a bit line structure 150 located in the substrate 100, wherein the bit line structure 150 is located on one side of the word line gate structure 140.

[0038] To increase the coupling voltage between the source region 110 and the floating gate structure 120 during programming, one method is to increase the coupling area between the floating gate structure 120 and the source region 110, thereby improving the coupling ratio between the floating gate structure 120 and the source region 110. During programming, due to the high coupling ratio, a higher coupling voltage is generated on the floating gate structure 120, and more hot electrons are attracted to the floating gate structure 120, thereby enabling programming of the floating gate structure 120.

[0039] However, in the aforementioned flash memory structure, the floating gate channel region occupies approximately half the size of the floating gate structure 120; the floating gate structure 120 located above the source region 110 is used for voltage coupling. To ensure a higher voltage on the floating gate structure 120 during programming, the overlapping region between the source region 110 and the floating gate structure 120 must be large, resulting in a larger overall flash memory size, which is inconsistent with the trend of miniaturization of semiconductor devices. Furthermore, the source region 110 is connected to the substrate 200 through a longitudinal, unmetallized structure, resulting in a relatively high parasitic resistance in the source region 110.

[0040] Based on this, the present invention provides a memory structure and method for forming the same. Because the source region is connected directly through the metalized source polysilicon layer rather than through the vertical, unmetallized substrate, this significantly reduces the parasitic resistance of the source region, while also avoiding the vertical and horizontal grid-like ACT pattern and lowering the process complexity. Furthermore, the thickness of the wordline gate oxide layer in the wordline gate structure can be significantly reduced, improving the wordline gate layer's control over the underlying channel, effectively lowering the wordline voltage during read operations, reducing the risk of read crosstalk, and reducing device size.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 2 to 14 It is a schematic structural diagram of each step of the memory structure and its formation method in an embodiment of the present invention.

[0043] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 includes a first region A and second regions B located on both sides of the first region A, and the first region A and the second region B are adjacent to each other.

[0044] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0045] After providing the substrate 200, the process further includes: forming a floating gate structure on the second region B and an erase gate structure on the floating gate structure; forming a first doped region in the substrate 200, the first doped region being located in a portion of the second region B and spanning the first region A, the first doped region having first ions; forming a source region in the first doped region, the source region having second ions, the first ions and the second ions having different electrical types; and forming a source polysilicon layer on the first region A. For the specific formation process, please refer to Figures 3 to 11 .

[0046] Please refer to Figure 3 , forming a floating gate structure material film 201 on the substrate 200 ; and forming an erase gate structure material film 202 on the floating gate structure material film 201 .

[0047] In this embodiment, the floating gate structure material film 201 is used to provide material for the subsequent formation of the floating gate structure; the erase gate structure material film 202 is used to provide material for the subsequent formation of the erase gate structure.

[0048] In this embodiment, the floating gate structure material film 201 includes: a floating gate dielectric material film, and a floating gate material film (not labeled) located on the floating gate dielectric material film.

[0049] The floating gate dielectric material film may be made of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon oxynitride. In this embodiment, the floating gate dielectric material film is made of silicon oxide.

[0050] In this embodiment, the floating gate material film is made of polysilicon.

[0051] In this embodiment, the thickness of the floating gate dielectric material film is 90 angstroms; the thickness of the floating gate material film is 300 angstroms.

[0052] In this embodiment, the erase gate structure material film 202 includes: an erase gate dielectric material film and an erase gate material film (not labeled) located on the erase gate dielectric material film.

[0053] The erase gate dielectric material film has a single-layer structure or a multi-layer structure. In this embodiment, the erase gate dielectric material film has a multi-layer structure, and the erase gate dielectric material film includes: a first silicon oxide film, a silicon nitride film located on the first silicon oxide film, and a second silicon oxide film located on the silicon nitride film.

[0054] In this embodiment, the erase gate material film is made of polysilicon.

[0055] In this embodiment, the thickness of the first silicon oxide film is 120 angstroms; the thickness of the silicon nitride film is 60 angstroms; the thickness of the second silicon oxide film is 300 angstroms; and the thickness of the erase gate material film is 300 angstroms.

[0056] Please refer to Figure 4 A first mask layer 203 is formed on the erase gate structure material film 202 , wherein the first mask layer 203 has a mask opening 204 exposing a portion of the top surface of the erase gate structure material film 202 .

[0057] In this embodiment, the first mask layer 203 is used to define the position and size of the doped region to be formed subsequently.

[0058] In this embodiment, the material of the first mask layer 203 is silicon nitride.

[0059] Please refer to Figure 5 The first mask layer 203 is used as a mask, and the substrate 200 is implanted with first ions to form the first doped region 205 .

[0060] In this embodiment, the first doped region 205 is located in a portion of the second region B and spans the first region A.

[0061] In this embodiment, the first ions are P-type ions.

[0062] Please refer to Figure 6 After forming the first doping region 205 , a first sidewall spacer 206 is formed on the sidewall of the mask opening 204 .

[0063] In this embodiment, the first spacer 206 is used to define the position and size of the floating gate structure and the erase gate structure to be formed later.

[0064] In this embodiment, the material of the first sidewall spacer 206 is different from the material of the first mask layer 203 ; the material of the first sidewall spacer 206 is silicon oxide.

[0065] Please refer to Figure 7 Using the first mask layer 203 and the first sidewall 206 as masks, the erase gate structure material film 202 and the floating gate structure material film 201 are etched until the surface of the substrate 200 is exposed, thereby forming an initial erase gate structure 207 and an initial floating gate structure 208.

[0066] In this embodiment, the method for forming the initial erase gate structure 207 includes: using the first mask layer 203 and the first side wall 206 as a mask, etching the erase gate material film, the second silicon oxide film and the silicon nitride film until the surface of the first silicon oxide film is exposed; forming a compensation erase gate layer 209 on the exposed side walls of the erase gate material film, the second silicon oxide film and the silicon nitride film; after forming the compensation erase gate layer 209, using the first mask layer 203, the first side wall 206 and the compensation erase gate layer 209 as a mask, etching the first silicon oxide film until the surface of the floating gate structure material film 201 is exposed, thereby forming the initial erase gate structure 207.

[0067] Please refer to Figure 8 After forming the initial erase gate structure 207 and the initial floating gate structure 208 , a second spacer 210 is formed on the sidewalls of the initial erase gate structure 207 and the initial floating gate structure 208 , and the second spacer 210 is located on the first region A.

[0068] In this embodiment, the second sidewall spacer 210 is made of silicon oxide.

[0069] Please refer to Figure 9 After forming the second side wall 210, the first mask layer 203, the first side wall 206 and the second side wall 210 are used as masks to perform second ion implantation on the first region A to form a source region 211 in the first region A. The electrical type of the second ions is different from that of the first ions.

[0070] In this embodiment, the source region 211 is located in the first doping region 205 .

[0071] In this embodiment, the second ions are N ions.

[0072] In this embodiment, the electrical types of the second ions and the first ions are different, and therefore, a PN junction is formed at the interface between the source region 211 and the first doping region 205 .

[0073] Please refer to Figure 10 After forming the source region 211 , a source polysilicon layer 212 is formed on the first region A.

[0074] In this embodiment, the method for forming the source polysilicon layer 212 includes: forming a first doped region conductive material layer (not shown) on the first region A, the first mask layer 203 and the first sidewall 206; and planarizing the source and drain conductive material layer until the top surface of the first mask layer 203 and the first sidewall 206 is exposed to form the source polysilicon layer 212.

[0075] In this embodiment, the source polysilicon layer 212 is in contact with the source region 211 .

[0076] In this embodiment, the source polysilicon layer 212 is made of polysilicon.

[0077] In this embodiment, the formation process of the first doping region conductive material layer adopts an epitaxial growth process.

[0078] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0079] Please continue to refer to Figure 10 After forming the source polysilicon layer 212 , the method further includes: oxidizing the top surface of the source polysilicon layer 212 to form a protective layer 213 .

[0080] Please refer to Figure 11 After forming the source polysilicon layer 212, the first mask layer 203 is removed; using the first sidewall 206 as a mask, the initial erase gate structure 207 and the initial floating gate structure 208 are etched until the surface of the substrate 200 is exposed, thereby forming the erase gate structure 214 and the floating gate structure 215.

[0081] In this embodiment, the N-type doped source region 211 partially overlaps with the floating gate structure 215 in the channel direction, so that the high voltage of the source region 211 can be coupled to the floating gate structure 215 during programming operation.

[0082] Please refer to Figure 12 After forming the erase gate structure 214 and the floating gate structure 215 , a word line gate channel region 216 is formed in the second region B.

[0083] In this embodiment, the method for forming the word line gate channel region 216 includes: using the first sidewall 206 and the source polysilicon layer 212 as a mask, performing a third ion implantation process on the second region B to form the word line gate channel region 216, wherein the third ion has the same electrical type as the first ion.

[0084] In this embodiment, the third ions are P-type ions.

[0085] Please refer to Figure 13 After forming the erase gate structure 214 and the floating gate structure 215 , the method further includes: forming a third sidewall spacer 217 on the sidewalls of the erase gate structure 214 , the floating gate structure 215 and the first sidewall spacer 206 , wherein the third sidewall spacer 217 is located on the second region B.

[0086] In this embodiment, the third sidewall spacer 217 is made of silicon oxide.

[0087] Please refer to Figure 14 After forming the word line gate channel region 216, a word line gate structure 218 is formed on the second region B. The word line gate structure 218 is located on one side of the floating gate structure 215 and the erase gate structure 214. The word line gate structure 218 includes a word line gate oxide layer 218a and a word line gate layer 218b located on the word line gate oxide layer 2018a.

[0088] In this embodiment, the source region 211 is connected directly through the metalized source polysilicon layer 212 rather than through the vertical, unmetallized substrate 200. This significantly reduces the parasitic resistance of the source region 211 and avoids a vertical and horizontal grid-like ACT pattern, thus reducing process complexity. Due to the dedicated erase gate structure 214, the wordline gate structure 218 does not need to withstand high voltage during erase, write, or read operations. Therefore, the thickness of the wordline gate oxide layer 218a of the wordline gate structure 218 can be significantly reduced, improving the control of the wordline gate layer 218b over the underlying channel. This effectively reduces the wordline voltage during read operations and mitigates the risk of read crosstalk. Furthermore, the reduced thickness of the wordline gate oxide layer 218a of the wordline gate structure 218 also effectively reduces the size of the device structure. Furthermore, because the sidewalls of the floating gate structure 215 can be coupled to the source region 211, there is no need to increase the lateral dimensions of the floating gate structure 215 to increase the coupling ratio, further reducing the size of the device structure.

[0089] In this embodiment, the word line gate layer 218b is made of polysilicon.

[0090] Please continue to refer to Figure 14 After forming the word line gate structure 218, a fourth sidewall 219 is formed on the sidewall of the word line gate structure 218; using the word line gate structure 218 and the fourth sidewall 219 as a mask, fourth ions are injected into the second region B to form a second doped region 220 in the word line gate channel region 216.

[0091] In this embodiment, the fourth ion and the third ion have different electrical types, and the fourth ion is an N-type ion.

[0092] Correspondingly, an embodiment of the present invention further provides a memory structure, please continue to refer to Figure 14, comprising: a substrate 200, the substrate 200 comprising a first region A, and second regions B located on both sides of the first region A, wherein the first region A is adjacent to the second region B; a floating gate structure 215 located on the second region B, and an erase gate structure 214 located on the floating gate structure 215; a first doped region 205 located in the substrate 200, the first doped region 205 being located in a portion of the second region B and spanning the first region A, the first doped region having first ions; a source region 211 located in the first doped region 205, the source region 211 having a first ion; It has a second ion, and the electrical type of the first ion is different from that of the second ion; a source polysilicon layer 212 located on the first region A, and the source polysilicon layer 212 is in contact with the source region 211; a word line gate channel region 216 located in the second region B; a word line gate structure 218 located on the second region B, and the word line gate structure 218 is located on one side of the floating gate structure 215 and the erase gate structure 214, and the word line gate structure 218 includes a word line gate oxide layer 218a, and a word line gate layer 218b located on the word line gate oxide layer 2018a.

[0093] In this embodiment, since the source region 211 is not connected to the unmetallized substrate 200 vertically, but directly connected to the metallized source polysilicon layer 212, the parasitic resistance of the source region 211 can be significantly reduced. Due to the presence of a dedicated erase gate structure 214, the wordline gate structure 218 does not need to withstand high voltage during erase, write, or read operations. Therefore, the thickness of the wordline gate oxide layer 218a of the wordline gate structure 218 can be significantly reduced, improving the control of the wordline gate layer 218b over the underlying channel, effectively reducing the wordline voltage during read operations and mitigating the risk of read crosstalk. Furthermore, the reduced thickness of the wordline gate oxide layer 218a of the wordline gate structure 218 can also effectively reduce the size of the device structure. Furthermore, since the sidewalls of the floating gate structure 215 can be coupled to the source region 211, there is no need to increase the lateral dimensions of the floating gate structure 215 to increase the coupling ratio, further reducing the size of the device structure.

[0094] In this embodiment, the floating gate structure 215 includes a floating gate dielectric layer and a floating gate layer (not shown) located on the floating gate dielectric layer.

[0095] In this embodiment, the erase gate structure 214 includes an erase gate dielectric layer and an erase gate layer (not shown) located on the erase gate dielectric layer.

[0096] The erase gate dielectric layer is a single-layer structure or a multi-layer structure. In this embodiment, the erase gate dielectric layer is a multi-layer structure, and the erase gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0097] In this embodiment, the erase gate structure 214 further includes a compensation erase gate layer 209 located on the sidewall of the erase gate layer.

[0098] In this embodiment, the structure further includes: a second spacer 210 located on the sidewalls of the erase gate structure 214 and the floating gate structure 215 , and the second spacer 210 is located on the first region A.

[0099] In this embodiment, the first doping region 205 has first ions therein. The memory structure further includes a source region 211 located in the first region A. The source region 211 has second ions therein. The second ions are of a different electrical type from the first ions.

[0100] In this embodiment, the word line gate channel region 216 has third ions in it. The third ions have the same electrical type as the first ions.

[0101] In this embodiment, the source polysilicon layer 212 is made of polysilicon.

[0102] In this embodiment, the structure further includes: a third spacer 217 located on the sidewalls of the erase gate structure 214 and the floating gate structure 215 , and the third spacer 217 is located on the second region B.

[0103] In this embodiment, the word line gate layer 218b is made of polysilicon.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: a substrate comprising a first region and second regions located on both sides of the first region, wherein the first region is adjacent to the second region; a floating gate structure located on the second region, and an erase gate structure located on the floating gate structure; a first doped region located in the substrate, the first doped region being located in a portion of the second region and spanning the first region, and having first ions therein; a source region located in the first doping region, wherein the source region has second ions, and the first ions and the second ions are of different electrical types; a source polysilicon layer located on the first region, wherein the source polysilicon layer is in contact with the source region; a word line gate channel region located in the second region; A word line gate structure is located on the second region, the word line gate structure is located on one side of the floating gate structure and the erase gate structure, and the word line gate structure includes a word line gate oxide layer and a word line gate layer located on the word line gate oxide layer.

2. The memory structure according to claim 1, wherein: The floating gate structure includes: a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

3. The memory structure according to claim 1, wherein: The erase gate structure includes an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

4. The memory structure according to claim 3, wherein: The erase gate dielectric layer is a single-layer structure or a multi-layer structure.

5. The memory structure according to claim 4, wherein: When the erase gate dielectric layer is a multi-layer structure, the erase gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

6. The memory structure according to claim 4, wherein: The erase gate structure further includes a compensation erase gate layer located on a sidewall of the erase gate layer.

7. The memory structure according to claim 1, wherein: Also includes: A second spacer is located on the sidewalls of the erase gate structure and the floating gate structure, and the second spacer is located on the first region.

8. The memory structure according to claim 1, wherein: There are third ions in the word line gate channel region, and the third ions are of the same electrical type as the first ions.

9. The memory structure according to claim 1, wherein: The material of the source polysilicon layer includes: polysilicon.

10. The memory structure according to claim 1, wherein: Also includes: A third spacer is located on the sidewalls of the erase gate structure and the floating gate structure, and the third spacer is located on the second region.

11. The memory structure according to claim 1, wherein: The material of the word line gate layer includes: polysilicon.

12. A method for forming a memory structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and second regions located on both sides of the first region, wherein the first region is adjacent to the second region; forming a floating gate structure and an erase gate structure on the second region; forming a first doped region in the substrate, wherein the first doped region is located in a portion of the second region and spans the first region, and the first doped region has first ions; forming a source region in the first doping region, wherein the source region has second ions, and the first ions and the second ions are of different electrical types; forming a source polysilicon layer on the first region, wherein the source polysilicon layer is in contact with the source region; forming a word line gate channel region in the second region; A word line gate structure is formed on the second region. The word line gate structure is located on one side of the floating gate structure and the erase gate structure. The word line gate structure includes a word line gate oxide layer and a word line gate layer located on the word line gate oxide layer.

13. The method for forming a memory structure according to claim 12, wherein: The method for forming a floating gate structure on the second region and an erase gate structure located on the floating gate structure includes: forming a floating gate structure material film on the substrate; forming an erase gate structure material film on the floating gate structure material film; forming a first mask layer on the erase gate structure material film, wherein the first mask layer has a mask opening exposing a portion of the top surface of the erase gate structure material film; forming a first sidewall on the sidewall of the mask opening; using the first mask layer and the first sidewall as a mask, etching the erase gate structure material film and the floating gate structure material film until the surface of the substrate is exposed, thereby forming an initial erase gate structure and an initial floating gate structure; after forming the initial erase gate structure and the initial floating gate structure, removing the first mask layer; using the first sidewall as a mask, etching the initial erase gate structure and the initial floating gate structure until the surface of the substrate is exposed, thereby forming the erase gate structure and the floating gate structure.

14. The method for forming a memory structure according to claim 13, wherein: The floating gate structure material film includes: a floating gate dielectric material film and a floating gate material film located on the floating gate dielectric material film.

15. The method for forming a memory structure according to claim 13, wherein: The erase gate structure material film includes: an erase gate dielectric material film and an erase gate material film located on the erase gate dielectric material film.

16. The method for forming a memory structure according to claim 15, wherein: The erase gate dielectric material film is a single-layer structure or a multi-layer structure.

17. The method for forming a memory structure according to claim 16, wherein: When the erase gate dielectric material film is a multi-layer structure, the erase gate dielectric material film includes: a first silicon oxide film, a silicon nitride film located on the first silicon oxide film, and a second silicon oxide film located on the silicon nitride film.

18. The method for forming a memory structure according to claim 17, wherein: The method for forming the initial erase gate structure includes: using the first mask layer and the first side wall as a mask, etching the erase gate material film, the second silicon oxide film and the silicon nitride film until the surface of the first silicon oxide film is exposed; forming a compensation erase gate layer on the exposed side walls of the erase gate material film, the second silicon oxide film and the silicon nitride film; after forming the compensation erase gate layer, using the first mask layer, the first side wall and the compensation erase gate layer as a mask, etching the first silicon oxide film until the surface of the floating gate structure material film is exposed, thereby forming the initial erase gate structure.

19. The method for forming a memory structure according to claim 13, wherein: The method for forming the first doping region includes: before forming the first sidewall spacer, using the first mask layer as a mask, performing the first ion implantation process on the substrate to form the first doping region.

20. The method for forming a memory structure according to claim 19, wherein: After forming the initial erase gate structure and the initial floating gate structure, the method further includes: forming a second spacer on sidewalls of the initial erase gate structure and the initial floating gate structure, wherein the second spacer is located on the first region.

21. The method for forming a memory structure according to claim 20, wherein: The method for forming the source region includes: using the first mask layer, the first sidewall and the second sidewall as masks, performing the second ion implantation process on the first region to form the source region, wherein the source region is located in the first doping region.

22. The method for forming a memory structure according to claim 19, wherein: The method for forming the word line gate channel region includes: using the first sidewall and the source polysilicon layer as masks, performing a third ion implantation process on the second region to form the word line gate channel region, wherein the third ions have the same electrical type as the first ions.

23. The method for forming a memory structure according to claim 13, wherein: After forming the erase gate structure and the floating gate structure, the method further includes forming a third spacer on the sidewalls of the erase gate structure, the floating gate structure and the first spacer, wherein the third spacer is located on the second region.

24. The method for forming a memory structure according to claim 13, wherein: The material of the word line gate layer includes: polysilicon.

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