An organic field effect transistor and a method for manufacturing the same

Abstract

The application discloses an organic field effect transistor and a preparation method thereof. The preparation method comprises the following steps: preparing a nanoscale channel array on the surface of a substrate, then preparing a gate electrode on the surface, and then preparing a dielectric layer on the surface of the gate electrode; performing hydrophobic treatment on the surface of the dielectric layer, then preparing an organic semiconductor nanowire array layer on the surface of the dielectric layer through physical vapor deposition, and finally preparing a source electrode and a drain electrode on the surface of the organic semiconductor nanowire array layer. Through the method, the directional and ordered growth of nanowires in the organic semiconductor nanowire array can be effectively controlled, and then the subsequent preparation of the source electrode and the drain electrode can be facilitated. The overall manufacturing process is simple, easy to operate and high in production efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor device technology, in particular to an organic field effect transistor and a preparation method thereof. BACKGROUND

[0002] A field effect transistor (FET) is a voltage-controlled device with high input impedance and large power gain. The FET is a new generation of amplification element developed on the basis of the principle of a triode, which has three electrodes, namely a gate electrode, a source electrode and a drain electrode. The working principle of the FET is to form a conductive channel on the surface of the oxide layer and the semiconductor by adjusting the gate voltage, and to form a switching characteristic by applying an external voltage between the source and the drain.

[0003] Generally, the semiconductor layer of an organic field effect transistor (OFET) is an organic semiconductor thin film. However, due to the combination of the excellent properties of organic molecules (such as molecular diversity, high carrier transport efficiency, excellent heat resistance, high-efficiency photoelectric emission capability and high quantum efficiency) and the unique effects induced by the nanowire structure (such as mechanical flexibility, excellent surface-to-volume ratio and one-dimensional electron transport characteristics), the OFET made by carefully selecting different nanowire structures can realize various functions and provide high-density expandable inheritance possibilities. Therefore, in recent years, the OFET based on the organic semiconductor nanowire structure has attracted special attention.

[0004] At present, the conventional preparation method of the OFET based on the organic semiconductor nanowire is to form a plurality of nanowires on a substrate by physical vapor deposition of an organic semiconductor powder material, and then to add source and drain electrodes to the single nanowire, the double nanowire and the cross nanowire to obtain the target transistor. However, in the above method, the nanowires cannot be grown in an ordered manner, and the grown nanowires are too disordered, which increases the workload in the process of adding the source and drain electrodes, and even requires the use of a probe to pick out and transfer the nanowires to another substrate, which is complex and tedious. SUMMARY

[0005] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes an organic field effect transistor and a preparation method thereof, wherein the nanowires are grown in an ordered manner, the operation is simple and easy to implement, and the production efficiency is high.

[0006] In a first aspect, the present application provides a preparation method of an organic field effect transistor, comprising the following steps:

[0007] S1, preparing a nanoscale channel array on the surface of a substrate;

[0008] S2, preparing a gate electrode on the surface;

[0009] S3, preparing a dielectric layer on the surface of the gate electrode;

[0010] S4, performing hydrophobic treatment on the surface of the dielectric layer, and then preparing an organic semiconductor nanowire array layer on the surface of the dielectric layer by physical vapor deposition;

[0011] S5, preparing a source electrode and a drain electrode on the surface of the organic semiconductor nanowire array layer.

[0012] According to the method for preparing the organic field effect transistor provided by the embodiment of the present application, at least the following beneficial effects are achieved: the method prepares a nanoscale channel array on the surface of a substrate, and then sequentially prepares a gate electrode and a dielectric layer thereon. The prepared gate electrode and dielectric layer reproduce the nanoscale channel array structure on the surface of the substrate. When an organic semiconductor nanowire array layer is prepared on the dielectric layer, the growth orientation of the organic semiconductor nanowire in the physical vapor deposition process can be effectively controlled through the nanoscale channel array structure, so that a self-parallel arranged organic semiconductor nanowire array is obtained, the directional and ordered growth of the nanowire is realized, and the subsequent preparation of the source and drain electrodes is facilitated. The overall manufacturing process is simple, easy to operate, and high in production efficiency. The problem that the nanowires grown by the conventional OFET manufacturing method have no unified orientation and face difficulties in the preparation of the source and drain electrodes can be solved.

[0013] In some embodiments of the present application, the gate electrode in step S2 comprises at least two sub-gate electrodes. The gate electrode comprising at least two sub-gate electrodes is prepared on the surface of the substrate having the nanoscale channel array, and then the dielectric layer and the organic semiconductor nanowire array layer are sequentially prepared on the surface of each sub-gate electrode, and the source electrode and the drain electrode are prepared on the surface of the organic semiconductor nanowire array layer. Therefore, multiple organic field effect transistors can be quickly prepared on the substrate at the same time, which is beneficial to realize industrialized batch production and improve the production efficiency.

[0014] In some embodiments of the present application, the sub-gate electrodes are arranged in an array. By using the array arrangement, an array of organic field effect transistors can be prepared, the regular, ordered and rapid production of the organic field effect transistors can be realized, the production efficiency is improved, and the product failure rate can be reduced. Therefore, the problem that the conventional OFET preparation method can only prepare a single device and cannot form an OFET array can be solved.

[0015] In some embodiments of the present application, in step S2, the gate electrode template is prepared on the surface by means of the first mask through photolithography technology, and then the gate electrode is prepared on the gate electrode template by vacuum evaporation plating. Specifically, a photoresist layer can be first coated on the surface of the substrate with nanoscale channel array, and then photolithography is performed by means of the mask with through holes corresponding to the target sub-gate pattern to form a gate electrode template with the target gate electrode pattern, and then the gate electrode is prepared on the gate electrode template by vacuum evaporation plating. Considering that if the template based on photolithography technology is used for magnetron sputtering or plasma enhancement, the photoresist will be damaged, and the precision of silk screen printing, printing and spin coating is too low, the gate electrode template is prepared by photolithography technology, and then the gate electrode is prepared on the gate electrode template by vacuum evaporation plating, so that the production precision can be ensured. Moreover, the gate electrode is prepared by means of the mask, and then different sizes of gate electrodes can be prepared by adjusting the size of the through holes of the mask to prepare organic field effect transistors with different sizes. The pressure in the vacuum evaporation plating process is generally controlled to be not more than 5x10 -4 Pa, otherwise the quality of the plated gate electrode film will be affected. In addition, after the gate electrode template is prepared by photolithography technology, the sample generally needs to be subjected to plasma cleaning to remove the residual photoresist, so as not to affect the subsequent plating. Specifically, the sample can be placed in a PLASMA instrument for treatment.

[0016] In some embodiments of the present application, in step S5, the source electrode template and the drain electrode template are prepared on the surface of the organic semiconductor nanowire array layer by means of the second mask through photolithography technology, and then the source electrode and the drain electrode are prepared on the source electrode template and the drain electrode template respectively by vacuum evaporation plating. The second mask has through holes corresponding to the source electrode and the drain electrode pattern, and the second mask used for preparing the source electrode and the drain electrode is matched with the first mask used for preparing the gate electrode, so as to ensure the matching of the electrodes. Thus, the gate electrode, the source electrode and the drain electrode can be uniformly positioned and prepared by photolithography technology, which can be used for manufacturing OFET array, solves the manufacturing problem of OEFT array based on organic semiconductor nanowire, and the production precision of photolithography technology is high, so that the electrode distance error can be controlled in the micron level, which is beneficial to realize large-scale, large-area and high-precision production. Similar to the preparation of the gate electrode, after the source electrode template and the drain electrode template are prepared by photolithography technology, the residual photoresist generally needs to be removed by plasma cleaning before the corresponding electrodes are prepared on the film.

[0017] In some embodiments of the present application, in step S3, the medium layer is prepared by atomic layer deposition. The medium layer prepared by atomic layer deposition can be flat and uniform on the substrate.

[0018] In some embodiments of the present application, the total thickness of the gate electrode and the dielectric layer is less than 100 nm, and the thickness refers to the height along the direction perpendicular to the bonding surface of the gate electrode and the substrate. It can be understood that the distance between the surface with the nanoscale channel array and the organic semiconductor nanowire array layer is less than 100 nm, i.e., the total thickness of the layer prepared before depositing the organic semiconductor nanowire array layer on the substrate surface is less than 100 nm. The inventors have determined through repeated experiments that controlling the thickness can ensure the effective guided growth of the nanoscale channel array to the organic semiconductor nanowire, otherwise the growth of the organic nanowire cannot be effectively guided, and the nanowire grows in a disorderly manner. Specifically, the thickness of the gate electrode can be controlled to be 30-50 nm, and the thickness of the dielectric layer can be controlled to be 50-70 nm, based on the total thickness of the gate electrode and the dielectric layer being less than 100 nm. In addition, the thickness of the source electrode and the drain electrode is generally controlled to be 100-200 nm.

[0019] In some embodiments of the present application, in step S1, the substrate is M-surface sapphire; and a nanoscale channel array is formed on the surface of the M-surface sapphire by annealing treatment. The annealing temperature can be controlled to be 1400-1600 ℃, and the annealing time can be controlled to be 9-10 h. In addition, before the annealing treatment of the M-surface sapphire, the M-surface sapphire can be cleaned to remove surface oil stains; after the annealing treatment, the annealed sapphire substrate is cleaned again, and then dried. The cleaning can be ultrasonic cleaning with cleaning liquids such as acetone, ethanol, and deionized water, and the drying can be performed by blowing dry nitrogen.

[0020] In step S4, the hydrophobic treatment can use organosilicon glue solution such as polysiloxane and octadecyltrichlorosilane (OTS) as the hydrophobic agent. The surface is treated by hydrophobic modification to ensure the directional growth effect of the organic semiconductor nanowire, otherwise, if the substrate is not treated by hydrophobic treatment, the organic semiconductor nanowire will not grow into a guided array. The physical vapor deposition can be performed by vacuum evaporation. The source region temperature of the physical vapor deposition can be controlled to be 440 ℃-480 ℃, preferably 440 ℃-460 ℃; and the growth region temperature can be controlled to be 240 ℃-280 ℃, preferably 240 ℃-250 ℃. In addition, the physical vapor deposition is generally performed in an inert atmosphere, which can be nitrogen, helium, and other inert atmospheres. Specifically, the source region and the growth region are first heated to the predetermined temperature and stabilized, and then the semiconductor material is sent to the source region.

[0021] In some embodiments of the present application, the material of the gate electrode, the source electrode and the drain electrode is independently selected from gold; the material of the dielectric layer is selected from aluminum oxide; and the material of the organic semiconductor nanowire array layer is selected from metal phthalocyanine, such as copper phthalocyanine, zinc phthalocyanine, etc. According to the gold half-contact principle, gold is the most suitable material for the electrode. The material of the dielectric layer is selected from aluminum oxide because the aluminum oxide prepared by atomic layer deposition (ALD) is dense enough and has a large dielectric constant. If silicon dioxide is used, the silicon dioxide prepared by ALD is relatively fluffy, and the conductive dielectric constant of the silicon dioxide with the same thickness is not as good as that of aluminum oxide.

[0022] In a second aspect of the present application, a kind of organic field effect transistor is provided, which is prepared by any one of the preparation methods of organic field effect transistor proposed in the first aspect of the present application. Specifically, the organic field effect transistor can include substrate, gate electrode, dielectric layer and organic semiconductor nanowire array layer arranged in turn from bottom to top, the surface of organic nanowire array layer is connected with source electrode and drain electrode;The surface of the substrate combined with the gate electrode has a nanoscale channel array, and the nanowire array on the organic semiconductor nanowire array layer corresponds to the nanoscale channel array on the surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0023] The present application will be further described below in combination with the drawings and examples, in which:

[0024] Figure 1 It is a scanning electron microscope microstructure diagram of nanoscale channel array on M face sapphire substrate in example 1;

[0025] Figure 2 It is an optical microscope diagram of the first mask used in the preparation process of gate electrode in example 1;

[0026] Figure 3 It is an optical microscope diagram of the sample obtained after evaporating gate electrode and depositing dielectric layer on the surface of the substrate in example 1;

[0027] Figure 4 It is Figure 3 It is an optical microscope diagram of the sample surface growth preparation of copper phthalocyanine nanowire array layer;

[0028] Figure 5 It is an optical microscope diagram of the second mask used in the preparation process of source electrode and drain electrode in example 1;

[0029] Figure 6 , Figure 7 It is an optical microscope diagram of the organic field effect transistor prepared in example 1 under different magnifications;

[0030] Figure 8Output volt-ampere characteristic curve of an effective field effect transistor in the organic field effect transistor array prepared in Example 1;

[0031] Figure 9 Transfer characteristic curve of an effective field effect transistor in the organic field effect transistor array prepared in Example 1;

[0032] Figure 10 Optical microscope image of the organic field effect transistor prepared in Comparative Example 1.

[0033] Figure 11 Optical microscope image of the organic semiconductor nanowire layer prepared on the substrate in Comparative Example 2. DETAILED DESCRIPTION

[0034] The concept and technical effects of the present application will be described in detail below in combination with examples, so as to fully understand the purpose, features and effects of the present application. Obviously, the described examples are only a part of the examples of the present application, but not all the examples. Based on the examples of the present application, other examples obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0035] Example 1

[0036] An organic field effect transistor was prepared in this example, which specifically included the following steps:

[0037] S1, preparing a nanoscale channel array on the surface of a substrate.

[0038] Specifically, a single crystal M-surface sapphire wafer with a size of 1×1 cm 2 was taken as the substrate, which was put into acetone, and the surface oil stains were removed by ultrasonic cleaning agent. Then, the surface was dried by dry nitrogen, and residual acetone solvent was removed by ethanol. The surface was dried by nitrogen, and then cleaned by deionized water to remove the organic solvent on the surface. The surface was dried by nitrogen, and the cleaned substrate was put into a high-temperature box furnace, which was raised to 1600℃ at a speed of 10℃, and kept at 1600℃ for 10h. Then, the furnace was cooled to room temperature. The surface of the treated M-surface sapphire substrate produced a nanoscale channel array, the scanning electron microscope image of which is shown in Figure 1 .

[0039] S2, preparing a gate electrode on the surface of the substrate treated in step S1.

[0040] Specifically, the M-plane sapphire substrate after the S1 step is placed on a spin coater, 50 μL of NR-9 photoresist is dropped onto the surface of the substrate by using a pipette, the acceleration is 100 rpm / s, the speed is maintained at 500 rpm / s for 10 s, the acceleration is 1000 rpm / s, the speed is maintained at 3000 rpm / s for 40 s, the sample is placed on a baking coater, and is cured at 150°C for 1 min, then the cured sample is placed on a photoetching platform, and is exposed to light for 6 s by using the first mask shown in FIG. 6, and is placed on a heating platform and hardened at 100°C for 1 min, then is immersed in a developing solution for 20 s, is washed with deionized water after being taken out, and is dried by blowing nitrogen, and a gate electrode template with a gate electrode pattern is prepared on the substrate. Figure 2 The spin coater is a KW-4C of Sadekaisi Company, the baking coater is a SC-H-II of Sadekaisi Company, the heating platform is a C-MAG HS 7 of IKA Company, and the photoetching machine is a URE-2000 / 35L type ultraviolet deep photoetching machine of the Institute of Optics and Electronics, Chinese Academy of Sciences.

[0041] The substrate with the gate electrode template is placed in a PLAMA instrument, and is treated at a power of 100 W for 30 s, the instrument is a PT-2S of Sanwoda, then high vacuum evaporation film plating is performed by using a PD-400 instrument of Pudixuanyuan, specifically, a 35 nm gold film layer is evaporated on the surface of the gate electrode template at a speed of 5×10 -4 Pa under the action of a voltage of 5 V, and the gold film layer is used as a gate electrode. The sample is immersed in acetone for 0.5 h, and is subjected to a photoresist removing treatment, and a patterned gate electrode with a plurality of sub-gate electrodes is obtained.

[0042] S3, a dielectric layer is prepared on the surface of the gate electrode.

[0043] Specifically, the sample obtained in the step S2 is washed with alcohol and dried by blowing nitrogen, a 50 nm aluminum oxide film is deposited on the surface of each sub-gate electrode by atomic layer deposition (ALD) as a dielectric layer, and the optical microscope image of the obtained sample is shown in FIG. 8. Figure 3 As shown in FIG. 8, Figure 2 and Figure 3 the pattern directions of the sub-gate electrodes may be inconsistent, which may be caused by rotating the mask or the sample when observing the sample during the preparation. Figure 2

[0044] S4, the surface of the dielectric layer is subjected to a hydrophobic treatment, and then an organic semiconductor nanowire array layer is prepared thereon by physical vapor deposition.

[0045] ​Specifically, the medium layer on the sample obtained in step S3 is adsorbed on the organic silicone glue polysiloxane for 2 h for surface hydrophobic modification treatment. Then, 0.010 g of copper phthalocyanine (CuPc) medicine powder (produced by Alfa Aesar Company, purity 99%) is put into a quartz boat of a push sample rod; the sample after the hydrophobic modification treatment is put into the quartz boat, with the layer of the medium layer facing upwards, and is put into a growth zone of a TF1200-60 double-temperature-zone tube furnace produced by MICRO-X Company. The temperature of the source zone of the double-temperature-zone tube furnace is set as follows: the initial temperature of the source zone is set to 20°C, is raised to 440°C within 30 min, the raising rate is 15°C / min, and is kept at 440°C for 120 min. The temperature of the growth zone of the double-temperature-zone tube furnace is set as follows: the initial temperature of the growth zone is set to 20°C, is raised to 240°C within 30 min, the raising rate is 7°C / min, and is kept at 240°C for 120 min. The double-temperature-zone tube furnace is started, and the tube furnace is pumped to vacuum, the air in the tube furnace is exhausted, nitrogen gas is introduced into the tube furnace at a constant flow rate of 50 sccm, and the pressure in the tube furnace is adjusted to 10 mbar; after the temperature of the source zone and the growth zone is raised to 440°C and 240°C respectively and is stabilized, the push sample rod containing the CuPc powder is pushed into the source zone, the distance between the CuPc powder and the sapphire substrate is 16 cm, and is kept at the above temperature for 120 min. After the double-temperature-zone tube furnace is stopped, the quartz boat containing the CuPc powder of the push sample rod is pulled out of the source zone, nitrogen gas is continuously introduced, and after the temperature is reduced to room temperature, the M-surface sapphire substrate sample is taken out, the surface of the medium layer on the M-surface sapphire substrate sample is grown with a directed organic molecule nanowire array (i.e., a copper phthalocyanine nanowire array), and a copper phthalocyanine nanowire array layer is formed, and the optical microscope image of the copper phthalocyanine nanowire array layer is as shown in FIG. 2. Figure 4 Figure 4 Figure 3 The pattern direction is inconsistent with the direction of observation and photographing due to rotation of the sample during observation and photographing.

[0046] S5, source and drain electrodes are prepared on the surface of the semiconductor nanowire array layer.

[0047] Firstly, the sample obtained in step S3 is put into a PLASMA instrument for 1 min of hydrophilic treatment, wherein the PLASMA instrument is a PT-5S of Triwold.

[0048] ​​Then, the patterning and etching of the source electrode and the drain electrode on the surface of the organic semiconductor nanowire array layer of the sample are performed. Specifically, the sample is placed on a spin coater, 50 μL of NR-9 photoresist is dropped on one side of the surface of the semiconductor nanowire array layer of the sample by using a pipette, the sample is accelerated at an acceleration of 100 rpm / s, maintained at 500 rpm / s for 10 s, and then accelerated at an acceleration of 1000 rpm / s, maintained at 2000 rpm / s for 40 s; then the sample is placed on a photoresist curing machine and cured at 150°C for 1 min; the cured sample is placed on a photoetching table and exposed for 20 s by using a second mask plate with through holes corresponding to the pattern of the source electrode and the drain electrode as shown in FIG. 8B; the exposed sample is taken to a heating table and baked at 100°C for 1 min, then immersed in a developing solution for 20 s, taken out, washed with deionized water, and dried with nitrogen, to obtain a source electrode template and a drain electrode template with patterns corresponding to the source electrode and the drain electrode. Figure 5

[0049] Finally, the above sample is placed in a PLAMA instrument and treated at a power of 100 W for 30 s, and then a gold film of 160 nm is evaporated on the source electrode template and the drain electrode template by using a PD-400 instrument of Pudite Vacuum, to obtain the source electrode and the drain electrode, wherein the pressure is 5 x 10 -4 Pa and the speed is 0.5 A / s. Then, the sample is immersed in acetone for 0.5 h for photoresist removal, to obtain a product, an organic field effect transistor, and the optical microscope image thereof is as shown in FIG. 9B. Figure 6 Figure 7

[0050] According to the above preparation method, in combination with Figures 2 to 6 It can be known that, in the embodiment, the through holes in the first mask plate used for the preparation of the gate electrode are arranged in an array, and the second mask plate used for the preparation of the source electrode and the drain electrode is matched with the first mask plate used for the preparation of the gate electrode and arranged in an array, and thus a plurality of organic field effect transistors arranged in an array, i.e., an organic field effect transistor array, is finally obtained. Therefore, by using the above matched mask plates with through holes arranged in an array, an organic field effect transistor array can be prepared, so that the regular, ordered and rapid production of organic field effect transistors is realized, and the production efficiency is improved; and the product failure rate can be reduced by using the method. Of course, in other embodiments, the through holes of the mask plate can also be designed not to be arranged in an array; the number of the through holes on the mask plate can be designed according to the needs; or the mask plate can also be cancelled, and a single organic field effect transistor can be directly prepared on the substrate. In addition, in other embodiments, other methods (such as magnetron sputtering, plasma enhanced chemical vapor deposition, etc.) can also be used to prepare the gate electrode, the source electrode and the drain electrode.

[0051] ​​​Take the above prepared organic field effect transistor array, an effective field effect transistor, using Jiheli 2612B carries on the test of output characteristic curve and transfer characteristic curve, the output volt-ampere characteristic curve as shown in Figure 7 , the transfer characteristic curve as shown in Figure 8 . From Figure 7 and Figure 8 , it can be seen that as the gate voltage increases from 0v to 8v, the source-drain current decreases or even turns off, the switching characteristics of the field effect transistor are remarkable, showing the performance of PMOS, which is consistent with the material performance.

[0052] Comparative Example 1

[0053] This comparative example prepared an organic field effect transistor, the difference between this comparative example and Example 1 is that in the preparation process of the gate electrode, a 50nm gold film layer is evaporated on the surface of the gate electrode template as the gate electrode. The other operations are the same as Example 1. The optical microscope image of the finally prepared organic field effect transistor is shown in Figure 10 , compared with Figure 7 , the organic field effect transistor prepared in Example 1 and Figure 9 , the organic field effect transistor prepared in Comparative Example 1. From Figure 7 , it can be seen that there are several nanowires in the area above the gate electrode connecting the source electrode and the drain electrode together; and from Figure 10 , it can be seen that the nanowires above the gate electrode are in disorder and cannot effectively connect the electrodes together.

[0054] Comparative Example 2

[0055] The difference between this comparative example and Example 1 is that in step S4, the dielectric layer is not subjected to hydrophobic treatment, but an organic semiconductor nanowire layer is prepared thereon by physical vapor deposition, and the specific operations of steps S1-S3 are the same as Example 1. The optical microscope image of the organic semiconductor nanowire layer prepared on the substrate is shown in Figure 11 , and from Figure 11 , it can be seen that if the surface of the substrate is not subjected to hydrophobic treatment, the organic semiconductor nanowire will not grow into a guided array.

[0056] The above examples only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as limiting the scope of the patent of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application.

Claims

1. A method for producing an organic field effect transistor, characterized by, The method comprises the following steps: S1, preparing a nanoscale channel array on the surface of a substrate; S2, preparing a gate electrode on the surface of the substrate after step S1; S3, preparing a dielectric layer on the surface of the gate electrode; the total thickness of the gate electrode and the dielectric layer is less than 100 nm, the thickness of the gate electrode is 30-50 nm, and the thickness of the dielectric layer is 50-70 nm; S4, performing hydrophobic treatment on the surface of the dielectric layer, and then preparing an organic semiconductor nanowire array layer on the surface of the dielectric layer by physical vapor deposition; S5, preparing a source electrode and a drain electrode on the surface of the organic semiconductor nanowire array layer.

2. The method of claim 1, wherein the organic field effect transistor is prepared by a process comprising: In step S2, the gate electrode comprises at least two sub-gate electrodes.

3. The method of claim 2, wherein the step of forming the organic field effect transistor is performed by a process selected from the group consisting of a vacuum deposition process, a spin coating process, a Langmuir-Blodgett process, a printing process, and a combination thereof. The sub-gate electrodes are arranged in an array.

4. The method of claim 2, wherein the step of forming the organic field effect transistor is performed by a process selected from the group consisting of a vacuum deposition process, a spin coating process, a Langmuir-Blodgett process, a printing process, and a combination thereof. In step S2, the gate electrode is prepared on the surface of the substrate after step S1 by means of a first mask through a photolithography technique, and then the gate electrode is prepared on the gate electrode template by vacuum evaporation plating.

5. The method of claim 4, wherein the step of forming the organic field effect transistor is performed by a process selected from the group consisting of a vacuum deposition process, a spin coating process, a Langmuir-Blodgett process, a printing process, and a combination thereof. In step S5, the source electrode template and the drain electrode template are prepared on the surface of the organic semiconductor nanowire array layer by means of a second mask through a photolithography technique, and then the source electrode and the drain electrode are prepared on the source electrode template and the drain electrode template respectively by vacuum evaporation plating.

6. The method of claim 5, wherein the step of forming the organic field effect transistor is performed by a process selected from the group consisting of a vacuum deposition process, a spin coating process, a Langmuir-Blodgett process, a printing process, and a combination thereof. In step S3, the dielectric layer is prepared by atomic layer deposition.

7. The method of claim 1, wherein the organic field effect transistor is prepared by a process comprising: In step S1, the substrate is M-surface sapphire; the nanoscale channel array is formed on the surface of the M-surface sapphire by annealing treatment.

8. The method of claim 1 to 7, wherein The materials of the gate electrode, the source electrode and the drain electrode are independently selected from gold; the material of the dielectric layer is selected from aluminum oxide; and the material of the organic semiconductor nanowire array layer is selected from metal phthalocyanine.

9. An organic field effect transistor, characterized by The organic field effect transistor is prepared by the method of any one of claims 1-8.

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