Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a nitride semiconductor layer stack (100) formed on a substrate (10), a source electrode (104), a drain electrode (105), and a gate electrode (106) formed on the nitride semiconductor layer stack (100), and a surface protective film (110) covering the nitride semiconductor layer stack (100). The nitride semiconductor layer stack (100) includes a first nitride semiconductor layer (101) formed on the substrate (10) and a second nitride semiconductor layer (102) formed on the first nitride semiconductor layer (101) and having a different composition from the first nitride semiconductor layer (101). The surface protective film (110) includes a first insulating film (111) formed so as to be in contact with the gate electrode (106), and a second insulating film (112) formed so as to be adjacent to the first insulating film (111) and having a higher carbon concentration than the first insulating film (111).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Semiconductor devices using nitride semiconductor materials, particularly gallium nitride (GaN), are attracting attention as amplifying elements and power switching elements that operate at high frequencies and high outputs. In addition, high electron mobility transistors (HEMTs) utilizing two-dimensional electron gas (2DEG), metal semiconductor field effect transistors (MESFETs), metal insulator semiconductor field effect transistors (MISFETs), metal oxide semiconductor field effect transistors (MOSFETs), and thin-film transistors (TFTs) are semiconductor devices suitable for amplification in high frequency bands such as microwaves and millimeter waves, and research is being actively pursued. Furthermore, in nitride semiconductors, there are also ternary or higher mixed crystal semiconductors that contain any of GaN, indium nitride (InN), and aluminum nitride (AIN) in addition to the three binary compound semiconductor materials of GaN, InN, and AIN. As nitride semiconductors composed of three or more elements, there are, for example, AIGaN, InGaN, InAIN, InAlGaN, and the like.

[0003] In HEMTs using nitride semiconductors, there are problems such as the occurrence of gate leakage current and current collapse, and from the viewpoint of ensuring high performance and high reliability, it is strongly desired that these problems be solved once and for all. HEMTs have a high electron concentration uniformly in the element region, so the gate leakage current is inherently large, and thus it is difficult to obtain a high withstand voltage. For example, in an AIGaN / GaN-based HEMT in which the Al composition ratio is 25% or less, the concentration of 2DEG becomes 1 x 10 13 / cm 2 At the above times, it is essentially difficult to prevent gate leakage. In addition, even in the operation of the HEMT, an electric field is concentrated near the gate electrode, and the gate leakage increases. Thus, the advantages of the nitride semiconductor device, which can perform high output operation, are impaired.

[0004] As a method of suppressing the gate leakage current of the HEMT using a nitride semiconductor, there are, for example, a method of adjusting the 2DEG concentration by control of the nitride semiconductor epitaxial layer, a method of increasing the gate resistance by making the configuration of the gate electrode an insulating gate type (MIS type or MOS type) in which an insulating film is present between the gate electrode and the nitride semiconductor, rather than a configuration in which the metal gate electrode and the nitride semiconductor are in Schottky junction, a method of introducing a field plate electrode that relaxes the electric field, and the like. In addition, various techniques for reducing the gate leakage current and current collapse of a nitride semiconductor device have been proposed (for example, Patent Documents 1 to 4).

[0005] Prior Art Documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2005-286135

[0007] Patent Document 2: Japanese Patent Application Publication No. 2006-261252

[0008] Patent Document 3: Japanese Patent Application Publication No. 2012-234984

[0009] Patent Document 4: Japanese Patent Application Publication No. 2007-048866 SUMMARY

[0010] As described above, in a semiconductor device using a nitride semiconductor, it is an important issue to suppress the occurrence of the gate leakage current and the current collapse.

[0011] The present disclosure was made to solve this issue, and aims to provide a nitride semiconductor device and a manufacturing method thereof, which can suppress the occurrence of the gate leakage current and the current collapse.

[0012] The semiconductor device according to the present disclosure includes a substrate, a nitride semiconductor stacked structure formed on the substrate, a source electrode and a drain electrode formed on the nitride semiconductor stacked structure, a gate electrode formed on the nitride semiconductor stacked structure between the source electrode and the drain electrode, and a surface protective film covering the nitride semiconductor stacked structure. The nitride semiconductor stacked structure includes a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The second nitride semiconductor layer has a different composition from the first nitride semiconductor layer. A two-dimensional electron gas is formed at a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer. The surface protective film includes a first insulating film formed on the nitride semiconductor stacked structure so as to be in contact with the gate electrode, and a second insulating film formed on the nitride semiconductor stacked structure so as to be adjacent to the first insulating film. The second insulating film has a higher carbon concentration than the first insulating film.

[0013] According to the semiconductor device according to the present disclosure, by making the carbon concentration in the surface protective film covering the nitride semiconductor stacked structure have a gradient toward the source electrode or the drain electrode from the center of the gate electrode, gate leakage current and current collapse are suppressed.

[0014] The objects, features, schemes, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 1.

[0016] Figure 2 is a plan view schematically showing an example of a structure of a semiconductor device according to Embodiment 1.

[0017] Figure 3 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 2.

[0018] Figure 4 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 3.

[0019] Figure 5 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 4.

[0020] Figure 6 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 4.

[0021] Figure 7FIG. 1 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 1.

[0022] Figure 8 FIG. 2 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 2.

[0023] Figure 9 FIG. 3 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 3.

[0024] Figure 10 FIG. 4 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 4.

[0025] Figure 11 FIG. 5 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 5.

[0026] Figure 12 FIG. 6 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 6.

[0027] Figure 13 FIG. 7 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 7.

[0028] Figure 14 FIG. 8 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 8.

[0029] Figure 15 FIG. 9 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 9.

[0030] Figure 16 FIG. 10 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 10.

[0031] Figure 17 FIG. 11 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to a combination of Embodiments 1, 2, 3, 5, 6, 7, 9, and 10.

[0032] Figure 18 FIG. 12 is a flow chart showing an example of a manufacturing method of a semiconductor device according to Embodiment 11.

[0033] Figure 19 FIG. 13 is a flow chart showing an example of a manufacturing method of a semiconductor device according to Embodiment 12.

[0034] (Symbol Explanation)

[0035] 10: substrate; 100: nitride semiconductor layered structure; 101: 1st nitride semiconductor layer; 102: 2nd nitride semiconductor layer; 103: injection region; 104: source electrode; 104a: source field plate; 105: drain electrode; 106: gate electrode; 106a: gate field plate; 107: cap layer; 110: surface protective film; 111: 1st insulating film; 112: 2nd insulating film; 113: 3rd insulating film; 114: 4th insulating film; 115: 5th insulating film; 121: element region; 122: separation region. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments will be described with reference to the accompanying drawings. In addition, the drawings schematically show structures, and sometimes, structures are appropriately omitted or simplified for the convenience of explanation. In addition, the size and the positional relationship of the illustrated constituent elements are not necessarily accurate, and can be appropriately changed. In addition, in the drawings other than cross-sectional views (plan views, etc.), sometimes, hatching is added for the convenience of explanation. In addition, the same symbols are attached to the same constituent elements in a plurality of drawings. Therefore, sometimes, repeated explanation is omitted with respect to the same constituent elements.

[0037] In the following description, words indicating relative positions, directions, such as "upper", "lower", "left", "right", "side", "bottom", "top", "back", etc. are used, but these words are used for the convenience of explanation, and are not necessarily consistent with the positions, directions at the time of actual use of the semiconductor device.

[0038] <Embodiment 1>

[0039] Figure 1 and Figure 2 is a drawing schematically showing an example of the structure of the semiconductor device according to Embodiment 1, Figure 1 is a cross-sectional view of the semiconductor device, Figure 2 is a plan view of the semiconductor device. As Figure 1 and Figure 2 shown, the semiconductor device according to Embodiment 1 is formed using a substrate 10. On the substrate 10, a nitride semiconductor layered structure 100 is formed, which includes a 1st nitride semiconductor layer 101 and a 2nd nitride semiconductor layer 102 formed thereon. The compositions of the 1st nitride semiconductor layer 101 and the 2nd nitride semiconductor layer 102 are different from each other, and a two-dimensional electron gas (2DEG) occurs in a hetero interface of the 1st nitride semiconductor layer 101 and the 2nd nitride semiconductor layer 102.

[0040] On the nitride semiconductor stacked structure 100, the source electrode 104 and the drain electrode 105 are formed at intervals from each other, and the gate electrode 106 is formed in a region between the source electrode 104 and the drain electrode 105. In Embodiment 1, the source electrode 104, the drain electrode 105, and the gate electrode 106 are all in contact with the upper surface of the second nitride semiconductor layer 102. In addition, an injection region 103 in which an n-type impurity is added is formed in a surface layer portion of a region of a part of the nitride semiconductor stacked structure 100, and the source electrode 104 and the drain electrode 105 are formed on the injection region 103, respectively.

[0041] On the upper surface of the nitride semiconductor stacked structure 100, a region in which the source electrode 104, the drain electrode 105, and the gate electrode 106 are formed is covered with a surface protective film 110. The surface protective film 110 includes a first insulating film 111 formed so as to be in contact with the gate electrode 106, and a second insulating film 112 formed so as to be adjacent to the first insulating film 111. The carbon concentration in the first insulating film 111 is lower than the carbon concentration in the second insulating film 112.

[0042] Here, the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102 are each formed by epitaxial growth. As a combination of materials of the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102, for example, GaN and AlGaN, GaN and InGaN, GaN and InAlN, GaN and AlN, AlGaN and AlN, AlGaN and AlGaN, or the like is considered. In Embodiment 1, the first nitride semiconductor layer 101 is provided as GaN, and the second nitride semiconductor layer 102 is provided as AlGaN.

[0043] The material of the substrate 10 can not be a nitride semiconductor, and for example, diamond, graphene, silicon (Si), germanium (Ge), gallium arsenide (GaAs), silicon carbide (SiC), indium phosphide (InP), zinc oxide (ZnO), zinc selenide (ZnSe), gallium oxide (Ga2O3), or the like can be used. In addition, as the material of the substrate 10, a compound semiconductor material of three or more, such as IGZO, or the like can be used. Furthermore, the composition ratio of the above-described compound material can not be 1:1.

[0044] In Embodiment 1, the nitride semiconductor stacked structure 100 is provided as a two-layer structure composed of the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102, but the nitride semiconductor stacked structure 100 can be composed of three or more nitride semiconductors. In addition, the nitride semiconductor stacked structure 100 can include a fine stacked structure or a quantum structure of several tens of angstroms, such as a superlattice layer structure or an interface migration layer, or a three-dimensional structure, or the like.

[0045] AsFigure 2 As shown, the semiconductor device of Embodiment 1 is divided into an element region 121 in which a horizontal semiconductor element that causes current to flow in the in-plane direction of the second nitride semiconductor layer 102 is formed, and a separation region 122 that surrounds the element region 121. The semiconductor element can be any of a HEMT, a MESFET, a MISFET, a MOSFET, a TFT, and is here a HEMT. That is, the semiconductor device of Embodiment 1 has a HEMT having a stacked structure of GaN and AlGaN, a so-called "AlGaN / GaN-HEMT".

[0046] In addition, in Embodiment 1, Si is used as the n-type impurity added to the injection region 103. However, the n-type impurity added to the injection region 103 is not limited to Si, and can be another material (O, Ge, N hole, etc.) that forms an n-type impurity level in a nitride semiconductor. In addition, if the source electrode 104 and the drain electrode 105 form an ohmic contact with the two-dimensional electron gas that occurs in the heterojunction interface of the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102, the injection region 103 can also be omitted.

[0047] Furthermore, the semiconductor device of Embodiment 1 can also have a source pad, a drain pad, a gate pad, a wiring electrode, an interlayer insulating film, a via, a through via hole, a via metal, an air bridge, a back electrode, a recess region, and the like, in addition to the elements shown in Figure 1 and Figure 2 .

[0048] In addition, various variations are also considered in the structure of the HEMT. For example, Figure 1 and Figure 2 The HEMT shown in

[0049] The surface protective film 110 assumes the functions of inertization of the surface level of the AlGaN of the second nitride semiconductor layer 102, control of the surface charge state, water resistance, humidity resistance, gas barrier, and the like. As the material of the first insulating film 111 and the second insulating film 112 that constitute the surface protective film 110, for example, silicon nitride (SiN x ), aluminum nitride (AlN), silicon dioxide (SiO x), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), magnesium oxide (MgO), tantalum oxide (TaO x ), titanium oxide (TiO x ), calcium oxide (CaO), lanthanum oxide (LaO x ), strontium oxide (SrO x ), yttrium oxide (YO x ), gadolinium oxide (GdO x ), and the like. In addition, as the material of the first insulating film 111 and the second insulating film 112, a compound material of AlTiO, ZrSiO, AlSiO, HfSiO x , or the like having three or more components can be used. The composition of the compound material can not be 1:1. In Embodiment 1, as the material of the first insulating film 111 and the second insulating film 112, AlO x .

[0050] Here, the effect of the semiconductor device according to Embodiment 1 will be described. It is considered that carbon in the surface protective film 110 forms a charge trap or a fixed charge, or affects the interface state density of the interface between the nitride semiconductor stacked structure 100 and the surface protective film 110. Generally, the charge trap or the interface state is particularly significant in a region where an electric field is strongly applied, i.e., a region near an electrode. In the semiconductor device of Embodiment 1, the surface protective film 110 covering the nitride semiconductor stacked structure 100 includes the first insulating film 111 formed near the gate electrode 106 and having a relatively low carbon concentration, and the second insulating film 112 provided adjacent to the first insulating film 111 and having a relatively high carbon concentration. Therefore, the carbon concentration in the surface protective film 110 has a gradient toward the source electrode 104 or the drain electrode 105 centering on the gate electrode 106, and thus the electric field near the gate electrode 106 is relaxed. As a result, in the nitride semiconductor stacked structure 100 near the gate electrode 106, a low interface state density and a low trap density can be achieved, and gate leakage current and current collapse deeply associated with any defect level existing in the surface of the nitride semiconductor stacked structure 100, the interface between the nitride semiconductor stacked structure 100 and the surface protective film 110, or the vicinity thereof are suppressed.

[0051] In addition, in a case where a strong local electric field is applied to the vicinity of the gate electrode 106 and the drain electrode 105 in the operation of the HEMT, sometimes hot electrons and hot holes are trapped (fall into traps) by any defect levels present in the inside or surface of the nitride semiconductor stacked structure 100, the interface between the nitride semiconductor stacked structure 100 and the surface protective film 110, or the vicinity thereof, or new electrically active defect levels are generated. If the time until the trapped charges are extracted (escape from the traps) is long, the state of current collapse continues for a long time, which adversely affects the reliability of the semiconductor device. In the semiconductor device of Embodiment 1, the carbon concentration of the second insulating film 112 adjacent to the first insulating film 111 is high, so the extraction of the charges trapped by the above-mentioned levels is performed as soon as possible. As a result, the current recovery time from the current collapse can be accelerated to more than twice as fast as in the conventional semiconductor device. Thus, even if the current collapse occurs, the state thereof is prevented from continuing for a long time, which contributes to the improvement of the reliability of the semiconductor device.

[0052] The carbon concentration in the surface protective film 110 (AlO x film) can also be controlled by introducing carbon from the outside after the formation of the AlO x film by an annealing treatment in a CO2 environment or the like.

[0053] In addition, in a case where the AlO x film is formed by a chemical vapor deposition (CVD) method typified by an atomic layer deposition (ALD) method, carbon in the AlO x film remains in the inside of the AlO x film as an unreacted product during the CVD method. Thus, the amount of carbon (carbon concentration) remaining in the AlO x film can be said to depend strongly on the film formation conditions. For example, if the film formation temperature of the AlO x film is made to be 200°C or higher, the carbon concentration in the AlO x film tends to be lower than when the film formation temperature is made to be 200°C or lower. In addition, if the oxidizing agent used in the film formation of the AlO x film is O2 plasma, the carbon concentration in the AlO x film tends to be higher than when the oxidizing agent is O3. However, each of these techniques has advantages and disadvantages, for example, if the film formation temperature is lowered in order to increase the carbon concentration in the AlO x film, problems such as the remaining of unreacted products other than carbon impurities or the difficulty in the formation of a dense film can occur. In addition, if the oxidizing agent is changed in order to increase the carbon concentration in the AlO xWhen the carbon concentration in the film is reduced by using an O2 plasma, the O2 plasma causes plasma-induced damage to the nitride semiconductor layer, which can result in deterioration of the electrical properties.

[0054] On the other hand, in a case where the AlO x film is formed by the ALD method, when DMAH (dimethylaluminum hydride, Al(CH3)2H) is used as an organometallic precursor material at the time of film formation, the carbon concentration can be reduced by about 50% in the evaluation by the SIMS method (Secondary Ion Mass Spectroscopy) compared to the case where TMA (trimethylaluminum, Al(CH3)3) is used. TMA is an organometallic compound in which three methyl groups (CH3) are bonded to one aluminum atom, and, in contrast, DMAH has a structure in which two methyl groups and one hydrogen atom are bonded to one aluminum atom. Therefore, DMAH is an organometallic precursor material that is excellent in film formability and can greatly reduce the carbon that remains inside the AlO x film.

[0055] By using the film formation techniques and the post-film formation treatments such as CO2 annealing shown above, respectively, the carbon concentration in the AlO x film can be controlled, and by using these techniques, the carbon concentration of each of the first insulating film 111 and the second insulating film 112 of the surface protective film 110 can be set to a desired value.

[0056] However, hot electrons and hot holes that are accelerated by the application of a high voltage are captured by any defect levels present in the interior or surface of the nitride semiconductor layer stack structure 100, the interface between the nitride semiconductor layer stack structure 100 and the surface protective film 110, or the vicinity thereof, and current collapse occurs. When the hot electrons and hot holes are captured by these levels, the potential generated by the captured electrons functions as a virtual electrode. In the lower portion of the virtual electrode, the channel becomes narrow, so the access resistance increases, and as a result, the on-resistance of the semiconductor device increases, and the drain current decreases. As a method of suppressing current collapse, there are methods such as a method of reducing the density of the capture levels of the above-described electrons and holes, a method of introducing a field plate electrode in order to prevent the generation of a localized high electric field, and the like. In the former method, the suppression can be greatly performed by the selection of the material and the film formation method of the surface protective film 110, so the control of the surface charge state is particularly important.

[0057] In addition, when hot electrons, hot holes are injected into the inside or surface of the nitride semiconductor stacked structure 100, the interface or the vicinity of the interface of the nitride semiconductor stacked structure 100 and the surface protective film 110, a new electron, hole capturing level is generated, and thus, deterioration of electrical characteristics, i.e., reduction in reliability becomes a problem. Even if a new level is not generated, in a case where an electron or a hole is captured by a level deeper in energy, or an electron or a hole is captured by a level having a large capturing cross section, the time until the charge is released and the semiconductor device returns to a stable state becomes long (for example, sometimes extremely long for several minutes to several hours, further several days to several weeks, etc.), and sometimes, reduction in reliability is caused. The semiconductor device of Embodiment 1 can also cope with such a problem.

[0058] <Embodiment 2>

[0059] Figure 3 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to Embodiment 2. As shown in Figure 3 In Embodiment 2, the surface protective film 110 includes the first insulating film 111 which is in contact with the gate electrode 106, the second insulating film 112 which is adjacent to the first insulating film 111, and the third insulating film 113 which is adjacent to the second insulating film 112. The carbon concentration in the second insulating film 112 is higher than the carbon concentration in the first insulating film 111, and the carbon concentration in the third insulating film 113 is higher than the carbon concentration in the second insulating film 112. That is, the surface protective film 110 of Embodiment 2 is composed of three kinds of insulating films having different carbon concentrations, respectively, the three kinds of insulating films are arranged in the in-plane direction (the direction from the gate electrode 106 toward the source electrode 104 or the drain electrode 105), and the carbon concentrations of the three kinds of insulating films are lower as closer to the gate electrode 106 in a manner that the carbon concentrations have a gradient in the in-plane direction.

[0060] In Embodiment 2, the kinds of the insulating films which constitute the surface protective film 110 are not limited to three, and there can be three or more kinds. That is, the surface protective film 110 can be composed of three or more kinds of insulating films having different carbon concentrations, respectively, in which case, the three or more kinds of insulating films are arranged in the in-plane direction, and the carbon concentrations of the three or more kinds of insulating films are lower as closer to the gate electrode 106 in a manner that the carbon concentrations have a gradient in the in-plane direction.

[0061] According to the structure of the semiconductor device according to Embodiment 2, the gradient of the carbon concentration in the surface protective film 110 becomes a smoother gradation than Embodiment 1, and thus, the electric field relaxation can be more seamlessly achieved, and the current collapse can be suppressed. In particular, the extraction (escape from the trap) of the captured charge can be performed at a higher speed than Embodiment 1.

[0062] <Embodiment 3>

[0063] Figure 4 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 3. As shown in Figure 4 , in Embodiment 3, a part of the gate electrode 106 protrudes toward the drain electrode 105 and extends over the surface protective film 110, constituting a field plate 106a which overlaps the nitride semiconductor layer stack 100 with the surface protective film 110 interposed therebetween. Hereinafter, the field plate 106a which is a part of the gate electrode 106 will be referred to as a "gate field plate 106a".

[0064] The front end of the gate field plate 106a is preferably located on the first insulating film 111 where the carbon concentration is low, but the gate field plate 106a can extend onto the second insulating film 112.

[0065] According to the semiconductor device of Embodiment 3, the gate field plate 106a moderates the electric field applied to the end portion of the gate electrode 106, so that the current collapse can be further reduced as compared with Embodiment 1.

[0066] However, when the parasitic capacitance formed by the gate field plate 106a becomes large, the high frequency characteristics of the semiconductor device are adversely affected, so that the voltage resistance improvement and the current collapse suppression obtained by the gate field plate 106a and the high frequency characteristics are in a trade-off relationship. Therefore, the design values of the length of the gate field plate 106a and the distance between the gate field plate 106a and the nitride semiconductor layer stack 100 are extremely important.

[0067] <Embodiment 4>

[0068] Figure 5 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 4. As shown in Figure 5 , in Embodiment 4, a part of the source electrode 104 protrudes toward the drain electrode 105 and extends over the surface protective film 110, constituting a field plate 104a which overlaps the nitride semiconductor layer stack 100 with the surface protective film 110 interposed therebetween. Hereinafter, the field plate 104a which is a part of the source electrode 104 will be referred to as a "source field plate 104a".

[0069] The shape of the source field plate 104a is not particularly restricted. In the example shown in Figure 5 , the source electrode 104 and the source field plate 104a are connected in a cross-sectional view, but the source field plate 104a can be, for example, as shown in Figure 6 , island-shaped in a cross-sectional view. Figure 6 The source field plate 104a of Figure 6 is connected to the source electrode 104 in a portion not shown. That is, Figure 6 A part of the source field plate 104a of Figure 6 extends in the depth direction of

[0070] According to the semiconductor device of Embodiment 4, the source field plate 104a at the same potential as the source electrode 104 moderates the potential distribution applied to the end portion of the gate electrode 106 and the access region between the gate electrode 106 and the drain electrode 105, so the effect of electric field moderation can be expected.

[0071] If the source field plate 104a of Embodiment 4 and the gate field plate 106a of Embodiment 3 are combined, the electric field moderation can be further promoted, and the current collapse can be reduced. In addition, the source field plate 104a has the effect of reducing the capacitance (C gd ) between the gate electrode 106 and the drain electrode 105, so it also contributes to the improvement of the gain in the high-frequency characteristics. However, the source field plate 104a increases the capacitance (C gs ) between the gate electrode 106 and the source electrode 104 and the capacitance (C ds ) between the drain electrode 105 and the source electrode 104, so there is a possibility that the above effects cancel out. Therefore, the design of the length of the source field plate 104a, the distance between the source field plate 104a and the nitride semiconductor layer stack 100, and the distance between the source field plate 104a and the gate electrode 106 and the gate field plate 106a is extremely important.

[0072] <Embodiment 5>

[0073] Figure 7 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to Embodiment 5. As shown in FIG. 17, in Embodiment 5, the surface protective film 110 is formed so as to cover the entire periphery of the gate electrode 106. The first insulating film 111 covers the entire periphery of the gate electrode 106, and the second insulating film 112 is adjacent to the first insulating film 111 at least in the in-plane direction. The second insulating film 112 can be formed so as to cover the entire periphery of the gate electrode 106, or can be formed so as to be adjacent to the first insulating film 111 only in the in-plane direction without covering the upper side of the gate electrode 106. Figure 7

[0074] According to the semiconductor device according to Embodiment 5, the surface protective film 110 covers the gate electrode 106, so the effect of protecting the gate electrode 106 from electrical and mechanical disturbances can be obtained. As a specific example of the electrical disturbance, there is an electrostatic discharge phenomenon called ESD (Electro Static Discharge). ESD causes malfunction and damage of semiconductor devices and electronic components, so countermeasures are important. In the structure of Embodiment 5, the surface protective film 110 can prevent the application of ESD to the gate electrode 106, and can prevent malfunction and element damage. Figure 7

[0075] ​​In addition, it is also considered that due to application of continuous operation or the like electrical stress to the semiconductor device via the electrode, the electrical stress causes the reverse piezoelectric effect, stress is concentrated to the end portion or the like of the gate electrode 106, and a crack or a dent is generated to cause physical destruction. This is a phenomenon that significantly occurs in a nitride semiconductor heterojunction structure having piezoelectricity, and greatly affects the reliability of the semiconductor device. In Embodiment 5, even in a case where the electrical stress is applied, the surface protection film 110 covering the gate electrode 106 disperses the stress, and generation of a crack or a dent can be prevented. As a result, it is possible to expect improvement in the reliability of the semiconductor device.

[0076] <Embodiment 6>

[0077] Figure 8 and Figure 9 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to Embodiment 6. In Figure 8 , the cross-sectional shape of the gate electrode 106 having the gate field plate 106a is a T-letter shape. In Figure 9 , the cross-sectional shape of the gate electrode 106 having the gate field plate 106a is a Y-letter shape.

[0078] Further, in Embodiment 6, it is characterized that the shape of the gate electrode 106 having the gate field plate 106a is Figure 8 and Figure 9 The gate field plate 106a of the gate electrode 106 can be either away from the surface protection film 110 or in contact with the surface protection film 110. In addition, the cross-sectional shape of the gate electrode 106 can be any T-letter shape or Y-letter shape as long as the effect described below is obtained. In addition, in Figure 8 and Figure 9 , the gate field plate 106a is provided on both sides of the gate electrode 106, but can be a Γ-letter shape in which the gate field plate 106a is provided on only one side (for example, the drain electrode 105 side) of the gate electrode 106.

[0079] In Embodiment 6, the gate electrode 106 is formed so as to have a portion embedded in an opening formed in a part of the first insulating film 111 after the surface protection film 110 is formed. The opening provided in the surface protection film 110 can be formed, for example, by a dry etching or wet etching method, an electrochemical method, or the like, and the width of the opening is equivalent to the gate length. In addition, the gate electrode 106 can be formed, for example, by a sputtering method, an evaporation method, a coating method, or the like.

[0080] Regarding the mutual conductance g in the field effect transistor m , the gate width W, the gate length L, the electron mobility μ, and the gate capacitance C g, gate-source voltage V gs , threshold voltage V th , is expressed as g m = (W / L) μC g (V gs -V th ). Therefore, in order to increase the transconductance g m , it is effective to increase the W / L ratio, increase C g , and increase μ.

[0081] In the semiconductor device of Embodiment 6, the gate length can be adjusted according to the width of the opening of the first insulating film 111 in which a part of the gate electrode 106 is embedded, and thus the gate length can be shortened. Therefore, the transconductance can be increased, and contribution to the increase in gain at the time of high-frequency operation can be made. In addition, the effect of the electric field relaxation based on the gate field plate 106a described in Embodiment 3 can also be obtained.

[0082] <Embodiment 7>

[0083] Figure 10 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to Embodiment 7. As shown in Figure 10 , in Embodiment 7, the nitride semiconductor layered structure 100 includes a cap layer 107 composed of a nitride semiconductor having a composition different from that of the second nitride semiconductor layer 102 on the second nitride semiconductor layer 102. Therefore, the source electrode 104, the drain electrode 105, the gate electrode 106, and the surface protective film 110 are formed on the cap layer 107.

[0084] The cap layer 107 is formed on the second nitride semiconductor layer 102 by epitaxial growth. In Embodiment 7, the cap layer 107 composed of GaN is used. The cap layer 107 can be n-type GaN or can be composed of another nitride semiconductor.

[0085] In the semiconductor device of Embodiment 7, a Schottky structure of the gate electrode 106 is formed between the cap layer 107. The growth of the cap layer 107 composed of GaN has a tendency to homogenize and planarize the alloy composition, which can effectively suppress the unevenness of the surface of the second nitride semiconductor layer 102 composed of AlGaN. Furthermore, a higher height of the Schottky barrier than that of the second nitride semiconductor layer 102 can be obtained, and thus an effect of suppressing the gate leakage current at the time of reverse bias can also be obtained. In addition, it is considered that the cap layer 107 has an effect of stabilizing the surface charge state of the nitride semiconductor layered structure 100, and an effect of further suppressing the occurrence of current collapse can also be expected.

[0086] <Embodiment 8>

[0087] In Figures 1 to 10In the embodiment, the gate structure is a dissimilar joint of metal and semiconductor, i.e., a Schottky contact type, and in the present embodiment, the feature is that it is an MIS type or an MOS type in which an insulating film is interposed to the gate structure.

[0088] Figure 11 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to Embodiment 8. As shown in Figure 11 In Embodiment 8, the gate electrode 106 is formed on the surface protective film 110. That is, the surface protective film 110 is present between the gate electrode 106 and the nitride semiconductor layered structure 100. The semiconductor device of such a structure is generally referred to as a transistor of a planar type MIS type or MOS type.

[0089] In Figure 11 , the gate electrode 106 is in contact with only the first insulating film 111 among the first and second insulating films 111 and 112, but can be in contact with both the first and second insulating films 111 and 112.

[0090] Further, as shown in Figure 12 , the gate electrode 106 and the surface protective film 110 thereunder can be embedded in a trench formed in the nitride semiconductor layered structure 100. The semiconductor device of such a structure is generally referred to as a transistor of a trench type MIS type or MOS type.

[0091] In Figure 12 , a trench is formed in a portion of the second nitride semiconductor layer 102 corresponding to the formation region of the gate electrode 106, the first insulating film 111 is formed so as to cover the inner wall (side surface and bottom surface) of the trench, and the second insulating film 112 is formed in contact with the first insulating film 111. Further, the gate electrode 106 is formed on the first insulating film 111, and a portion thereof is embedded in the trench.

[0092] In Figure 12 , the gate electrode 106 is in contact with only the first insulating film 111 among the first and second insulating films 111 and 112, but can be in contact with both the first and second insulating films 111 and 112. Further, the first insulating film 111 and the trench in which the gate electrode 106 is embedded can either reach the surface or the inside of the first nitride semiconductor layer 101 through the second nitride semiconductor layer 102 as shown in Figure 12 , or can be a shallower trench which does not reach the second nitride semiconductor layer 102.

[0093] According to the semiconductor device of Embodiment 8, the gate leakage current caused by electron conduction can be greatly suppressed by the high conduction band discontinuity caused by the surface protective film 110 under the gate electrode 106. In addition, as the surface protective film 110, if an insulating gate material having a high insulating breakdown electric field strength (for example, SiO2, Al2O3, or the like) is selected, the gate voltage bias to the positive direction (also referred to as gate swing) can be enlarged, a high input power and a high output power can be obtained in a high-frequency transistor, and thus a high output of a high-frequency amplifier can be achieved.

[0094] In addition, in the case of adopting a trench type configuration as in Figure 12 , the 2DEG directly under the gate electrode 106 can be repelled, and thus a normally-off operation can be achieved. The normally-off operation is a necessary element in a power switching element in terms of fail-safe, and thus the semiconductor device of Embodiment 8 can be applied not only to a high-frequency amplifier but also to a power switching element.

[0095] <Embodiment 9>

[0096] Figure 13 , Figure 14 and Figure 15 are cross-sectional views schematically showing examples of the structure of the semiconductor device according to Embodiment 9. In Embodiment 9, the surface protective film 110 is provided in a stacked configuration with a fourth insulating film 114 (see FIG. 9B) that uniformly covers the upper surface of the surface protective film 110, or a fifth insulating film 115 (see FIG. 9C) that uniformly covers the lower surface of the surface protective film 110. In addition, as shown in Figure 13 , the surface protective film 110 can be provided with both the fourth insulating film 114 and the fifth insulating film 115. That is, the nitride semiconductor stacked structure 100 can be provided with at least one of the fourth insulating film 114 and the fifth insulating film 115. Figure 14 Figure 15

[0097] ​​In the surface protective film 110, the portion other than the fourth insulating film 114 and the fifth insulating film 115 can be the same as the portion shown in embodiments 1 to 9. That is, the portion of the surface protective film 110 other than the fourth insulating film 114 and the fifth insulating film 115 is composed of two or more insulating films with different carbon concentrations. These two insulating films are arranged in the in-plane direction (from the gate electrode 106 toward the source electrode 104 or the drain electrode 105), and the carbon concentration of these two insulating films is gradient in the in-plane direction, becoming lower as they approach the gate electrode 106. In embodiment 9, the portion of the surface protective film 110 other than the fourth insulating film 114 and the fifth insulating film 115 is similar to that in embodiment 1, composed of a first insulating film 111 that is in contact with the gate electrode 106 and has a lower carbon concentration, and a second insulating film 112 that is adjacent to it and has a higher carbon concentration.

[0098] The fourth insulating film 114, which uniformly covers the lower surface of the surface protective film 110, can be made of the same material or composition as the first insulating film 111 or the second insulating film 112, or it can be made of a completely different material. For example, the fourth insulating film 114 is preferably SiN, which has high affinity for nitride semiconductors and high surface end-capping capability. x AlN x Nitride materials can be used, but any material can be used as long as the following effects can be achieved.

[0099] according to Figure 13 In addition to having the same effects as in Embodiment 1, the semiconductor device with the structure of the fourth insulating film 114 (e.g., SiN) is provided on the lower surface of the surface protective film 110 (the portion that is bonded to the nitride semiconductor stack structure 100). x AlN x The following effects can be obtained: it can suppress interface defects that are inevitably generated at the heterogeneous bonding interface, and suppress oxidation and deterioration of the surface of the nitride semiconductor stacked structure 100.

[0100] The fifth insulating film 115, which uniformly covers the upper surface of the surface protective film 110, can be made of the same material or composition as the first insulating film 111 or the second insulating film 112, or it can be made of a completely different material. For example, the fifth insulating film 115 is preferably made of a material with high gas barrier properties and high adhesion and affinity to the first insulating film 111 or the second insulating film 112. For example, the material of the first insulating film 111 and the second insulating film 112 is AlO. x In this case, the material of the fifth insulating film 115 is preferably SiON, AlON, or SiN. x Materials can be used, but any material can be used as long as the following effect can be achieved.

[0101] According to Figure 14 the semiconductor device of Embodiment 1, in addition to the same effects as Embodiment 1, the gas barrier property of the semiconductor device can be made high by the fifth insulating film 115. Also, as in Embodiment 5, the function of mechanical or electrical protection can be additionally added.

[0102] In addition, as Figure 15 indicated, if both the fifth insulating film 115 which uniformly covers the lower surface and the fifth insulating film 115 which uniformly covers the upper surface are provided to the surface protective film 110, both the effects of the fourth insulating film 114 and the effects of the fifth insulating film 115 can be obtained.

[0103] <Embodiment 10>

[0104] Figure 16 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to Embodiment 10. As Figure 16 indicated, in the surface protective film 110 of Embodiment 10, the first insulating film 111 is formed not only at the position where the gate electrode 106 is in contact with but also at the position where the drain electrode 105 is adjacent to. In addition, the second insulating film 112 is formed so as to be adjacent to both the first insulating film 111 where the gate electrode 106 is in contact with and the first insulating film 111 where the drain electrode 105 is adjacent to. Thus, the carbon concentration in the surface protective film 110 has a gradient not only in the vicinity of the gate electrode 106 but also in the vicinity of the drain electrode 105.

[0105] Figure 16 is an example in which the surface protective film 110 is composed of two kinds of insulating films, the first insulating film 111 and the second insulating film 112. Although not shown, in the case where the surface protective film 110 is composed of three kinds of insulating films, the first insulating film 111, the second insulating film 112, and the third insulating film 113, for example, as Figure 3 indicated, the first insulating film 111 is formed at both the position where the gate electrode 106 is in contact with and the position where the drain electrode 105 is adjacent to. In addition, the second insulating film 112 is formed at both the position where the first insulating film 111 where the gate electrode 106 is in contact with is adjacent to and the position where the first insulating film 111 where the drain electrode 105 is adjacent to is adjacent to. Further, the third insulating film 113 is formed between the second insulating films 112 formed at these two positions.

[0106] According to the semiconductor device of Embodiment 10, in addition to the same effects as Embodiment 1, the following effects can be obtained: the current collapse generated on the drain electrode 105 side can be suppressed, and the high-frequency characteristics can be further improved.

[0107] The dynamic load line input to the high frequency transistor sometimes becomes a strong cutoff state, and a voltage of 50 V to 100 V is applied to the drain electrode, and a voltage of -5 V is applied to the gate electrode. At this time, a strong electric field is concentrated on the drain electrode side, and in the case where the element withstand voltage is low, destruction is sometimes caused depending on the situation. The strong electric field concentration on the drain electrode side sometimes induces charge trapping in the nitride semiconductor surface or the nitride semiconductor crystal, and current collapse occurs. In addition, a phenomenon of drain lag in which the transient response of the drain current when a pulse is supplied between the drain electrode and the source electrode is delayed sometimes occurs. The semiconductor device of Embodiment 10 can pay attention to such a problem, particularly, charge trapping to the surface side, and can suppress trapping to the interface level, the defect level, or the like caused by carbon.

[0108] In addition, Embodiments 1 to 10 are contents related to the structures of the semiconductor device, and the structures can be combined. For example, Figure 17 An example of a structure of a semiconductor device obtained by combining Embodiments 1, 2, 3, 5, 6, 7, 9, and 10 is shown. That is, in the semiconductor device of Figure 17 In the semiconductor device of Embodiment 11, the nitride semiconductor layer stack structure 100 is composed of the first nitride semiconductor layer 101, the second nitride semiconductor layer 102, and the cap layer 107. In addition, the surface protective film 110 includes three kinds of insulating films, i.e., the first insulating film 111, the second insulating film 112, and the third insulating film 113, which are arranged in the in-plane direction and have different carbon concentrations, respectively, and has a gradient of the carbon concentration in both the vicinity of the gate electrode 106 and the vicinity of the drain electrode 105. Further, the surface protective film 110 has the fourth insulating film 114 which uniformly covers the lower surface and the fifth insulating film 115 which uniformly covers the upper surface. The gate electrode 106 is in a T-shaped form in a cross-sectional view including the gate field plate 106a, and is covered with the surface protective film 110. In Figure 17 In the semiconductor device of Embodiment 11, the effects of Embodiments 1, 2, 3, 5, 6, 7, 9, and 10 can be obtained.

[0109] <Embodiment 11>

[0110] Figure 18 is a flowchart showing an example of a manufacturing method of the semiconductor device according to Embodiment 11. The flowchart corresponds to the manufacturing method of the semiconductor device of Embodiment 1, and by changing the process of a part of the flowchart as described below, the manufacturing of the semiconductor device of the other embodiments can also be dealt with. Figure 1

[0111] Hereinafter, the manufacturing method of the semiconductor device according to Figure 18 ​The manufacturing method of the semiconductor device according to Embodiment 11 will be described. Further, the order of the processes shown in the flowchart can be changed, or an additional process can be inserted between the processes, as long as the structure of the semiconductor device according to Embodiment 1 is not impaired.

[0112] In the semiconductor layer formation process of Step S101, the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102 are formed on the substrate 10 by an epitaxial crystal growth technique, thereby forming the nitride semiconductor layer stack structure 100. As the epitaxial crystal growth technique, MOCVD method, MBE method, and the like are representative. The substrate 10 can be Si, SiC, sapphire, GaN, diamond, or the like. In Step S101, if a cladding layer 107 composed of GaN is further formed on the second nitride semiconductor layer 102 by epitaxial growth, the nitride semiconductor layer stack structure 100 provided with the cladding layer 107 can be formed as in Embodiment 7 ( Figure 10 ).

[0113] In the inter-element separation process of Step S102, the element region 121 in which the HEMT is formed and the separation region 122 other than the element region 121 are separated. As a representative inter-element separation technique, there are, for example, an ion implantation technique in which the ordered crystal state of the nitride semiconductor layer is partially destroyed by applying Ar ions or the like to the separation region with a high acceleration voltage, a method in which the nitride semiconductor layer present in the separation region is partially removed by a reactive ion etching method or the like, thereby causing the 2DEG to disappear, and the like. In the case where such a technique is used, the inter-element separation process is performed in a state in which the element region 121 is protected with a photoresist or a hard mask. Therefore, the element region 121 and the separation region 122 are defined by the pattern of the photoresist or the hard mask described above.

[0114] In the source electrode and drain electrode formation process of Step S103, the source electrode 104 and the drain electrode 105 are formed on the second nitride semiconductor layer 102 of the element region 121. This process includes a dopant implantation process for forming an injection region 103 for obtaining an ohmic semiconductor-metal contact, and a metal electrode formation process for forming the source electrode 104 and the drain electrode 105. The formation region of the injection region 103 is defined by the pattern of the photoresist or the hard mask used as a mask in the dopant implantation process. In addition, the source electrode 104 and the drain electrode 105 are defined by the pattern of the photoresist or the hard mask used as a mask when the metal is patterned in the metal electrode formation process. These photoresists and hard masks are removed by a lift-off technique, an etching technique, or the like.

[0115] In the protective film formation step of step S104, a protective film composed of, for example, SiN x , etc. is formed so as to cover the exposed region of the second nitride semiconductor layer 102 (a region in which the active electrode 104 and the drain electrode 105 are not formed) from the viewpoint of surface protection of the semiconductor device.

[0116] In the heat treatment step of step S105, the second nitride semiconductor layer 102 and the source electrode 104 and the drain electrode 105 are electrically connected by performing heat treatment called ohmic sintering or ohmic alloying. By this step, ohmic semiconductor-metal contact is achieved between the second nitride semiconductor layer 102 and the source electrode 104 and the drain electrode 105. In ohmic sintering, an annealing system in which the temperature increase, the temperature maintenance, and the temperature decrease are controlled with high precision is required. In addition, the optimum temperature for obtaining ohmic properties strongly depends on the material of the source electrode 104 and the drain electrode 105, the layer thickness ratio, the composition of the second nitride semiconductor layer 102, and the like. Heat treatment at a temperature higher than necessary can possibly cause a decrease in the element separation function of the separation region 122 formed in step S102, cause damage to the nitride semiconductor crystal, and cause damage to the Schottky junction interface, and thus it is preferable to perform condition optimization in advance.

[0117] In the protective film removal step of step S106, the protective film formed in step S104 is removed. If the protective film is SiN x , this step can be performed by wet etching using hydrofluoric acid or the like or dry etching. However, this step cannot be a step that affects the second nitride semiconductor layer 102, the source electrode 104, and the drain electrode 105. In addition, step S106 can be omitted, and the protective film formed in step S104 can be used as the fourth insulating film 114 shown in Embodiment 9 Figure 13 and Figure 15 ).

[0118] In the first insulating film formation step of step S107, the first insulating film 111 having a relatively low carbon concentration is formed on the second nitride semiconductor layer 102. The first insulating film 111 is formed so as to cover at least a part of the formation region of the gate electrode 106 formed in the following step S109. This step is performed in a state in which a hard mask or a photoresist or the like is used to cover a region that is not covered by the first insulating film 111. After the first insulating film 111 is formed, the hard mask or the photoresist is removed. In step S107, if the first insulating film 111 is also formed at a position at which the drain electrode 105 is connected, the carbon concentration in the surface protective film 110 can have a gradient also in the vicinity of the drain electrode 105 as in Embodiment 10 Figure 16 .

[0119] In the second insulating film forming step of step S108, the second insulating film 112 having a higher carbon concentration than the first insulating film 111 is formed in a manner to be adjacent to the first insulating film 111. In a case where the second insulating film 112 is formed to be adjacent to the first insulating film 111 only in the in-plane direction, the second insulating film 112 is formed after a hard mask or a photoresist is formed in a manner to overlap the first insulating film 111. In a case where a part of the second insulating film 112 is also formed on the first insulating film 111, the second insulating film 112 is formed after a hard mask or a photoresist is formed in a manner to expose a part of the upper surface of the first insulating film 111. Further, by narrowing the formation region of the second insulating film 112 and repeatedly performing the same process as that of step S108 one or more times while changing the carbon concentration of the insulating film, a surface protective film 110 composed of three or more insulating films having different carbon concentrations can be formed as in Embodiment 2. Figure 3 ).

[0120] Here, a technique for forming an insulating film having a gradient of carbon concentration will be described. For example, in a case where an insulating film composed of AlO x is formed by an atomic layer deposition method, TMA and DMAH are used as organic metal precursors, respectively, so that an insulating film having a high carbon concentration and an insulating film having a low carbon concentration can be produced, respectively. The AlO x film formed using DMAH has a carbon concentration about 50% lower than the AlO x film formed using TMA. Therefore, the AlO x film formed using DMAH is set as the first insulating film 111, and the AlO x film formed using TMA is set as the second insulating film 112. Further, the oxidizing agent of the organic metal precursor is preferably ozone or water. The reason is that, when plasma oxygen is used, depending on the degree of reactivity thereof, the carbon concentration is likely to become substantially uniform regardless of which organic metal precursor is used.

[0121] Further, as described above, regarding the amount of carbon (carbon concentration) remaining in the AlO x film, if the film formation temperature of the AlO x film is made to be 200°C or higher, the carbon concentration in the AlO x film has a tendency to become lower than when the film formation temperature is made to be 200°C or lower. Therefore, the AlO x film formed by making the film formation temperature to be 200°C or higher can be set as the first insulating film 111, and the AlO x film formed by making the film formation temperature to be in the range of room temperature to 200°C can be set as the second insulating film 112.

[0122] Further, if the AlO xWhen the oxidizing agent used in the film formation of the film is O2 plasma, AlO is formed, and the AlO is present in the form of AlO x The tendency of the carbon concentration in the film to increase. Therefore, AlO formed using plasma oxygen as the oxidizing agent can also be used x formed using ozone as the oxidizing agent is provided as the first insulating film 111. x formed as the second insulating film.

[0123] In the surface protective film opening process of step S109, an opening reaching the second nitride semiconductor layer 102 is formed in a portion of the surface protective film 110 corresponding to the formation region of the gate electrode 106 between the source electrode 104 and the drain electrode 105. As an insulating film opening technique, there are techniques such as reactive ion etching, a solution method, electrochemical reaction etching, photoelectrochemical reaction etching, and the like. Further, if step S109 is omitted, or the opening is made to a depth that does not reach the second nitride semiconductor layer 102 and the gate electrode 106 is formed on the first insulating film 111 in the next step S110, the gate electrode structure can be made into an insulating gate type (MIS type or MOS type) as in Embodiment 8 Figure 11 ).

[0124] In the gate electrode formation process of step S110, the gate electrode 106 is formed in a manner of being embedded in the opening formed in step S109. Note that the contact of the metal of the gate electrode 106 and the second nitride semiconductor layer 102 becomes a Schottky property contact. The metal of the gate electrode 106 can be formed using a sputtering method, an evaporation method, an inkjet method, or the like. The metal of the gate electrode 106 is patterned using a photoresist or a hard mask. In addition, the remaining metal needs to be completely removed by an appropriate optimal method such as a lift-off method, an etching method, or the like. Here, if the gate electrode 106 is formed in a region wider than the opening formed in step S109, so that a portion of the gate electrode 106 also extends on the surface protective film 110, the semiconductor device of Embodiment 3 Figure 4 ) and Embodiment 6 Figure 8 and Figure 9 ) can be manufactured.

[0125] If a process of forming the source field plate 104a is added after step S110, the semiconductor device of Embodiment 4 Figure 5 and Figure 6 ) can be manufactured. In addition, after step S110, formation of an interlayer insulating film, formation of a via, formation of a wiring electrode, or the like can be performed as needed.

[0126] According to the method for manufacturing a semiconductor device according to Embodiment 11, the semiconductor device of Embodiment 1 can be easily manufactured.

[0127] <Embodiment 12>

[0128] Figure 19 is a flowchart showing an example of a manufacturing method of a semiconductor device according to Embodiment 12. The flowchart corresponds to the manufacturing method of the semiconductor device (1) according to Embodiment 5, but by changing a part of the flowchart as explained below, the manufacturing of the semiconductor device according to other embodiments can also be dealt with. Figure 7 ) of Embodiment 5, but by changing a part of the flowchart as explained below, the manufacturing of the semiconductor device according to other embodiments can also be dealt with.

[0129] The manufacturing method of the semiconductor device according to Embodiment 12 will be explained below according to Figure 19 . Furthermore, as long as the structure of the semiconductor device according to Embodiment 5 is not impaired, the order of the processes shown in the flowchart can be changed, or an additional process can be inserted between the processes.

[0130] In the semiconductor layer forming process of Step S201, the first nitride semiconductor layer 101 and the second nitride semiconductor layer 102 are formed on the substrate 10 by an epitaxial crystal growth technique, thereby forming the nitride semiconductor layer stack structure 100. As the epitaxial crystal growth technique, MOCVD method, MBE method, etc. are representative. The substrate 10 can be Si, SiC, sapphire, GaN, diamond, etc. In Step S201, if a cladding layer 107 composed of GaN is further formed on the second nitride semiconductor layer 102 by epitaxial growth, the nitride semiconductor layer stack structure 100 provided with the cladding layer 107 can be formed as in Embodiment 7 Figure 10 ).

[0131] In the inter-element separation process of Step S202, the element region 121 where the HEMT is formed and the separation region 122 other than the element region 121 are separated. As a representative inter-element separation technique, there are, for example, ion implantation technique in which the ordered crystal state of the nitride semiconductor layer is partially destroyed by applying Ar ions or the like to the separation region at a high acceleration voltage, a method in which the nitride semiconductor layer existing in the separation region is partially removed by a reactive ion etching method or the like so that the 2DEG disappears, etc. In the case where such a technique is used, the inter-element separation process is performed in a state where the element region 121 is protected by a photoresist or a hard mask. Therefore, the element region 121 and the separation region 122 are defined by the pattern of the photoresist or the hard mask described above.

[0132] In the source electrode and drain electrode forming step of step S203, the source electrode 104 and the drain electrode 105 are formed on the second nitride semiconductor layer 102 of the element region 121. This step includes a dopant implantation step for forming an injection region 103 for obtaining an ohmic semiconductor-metal contact, and a metal electrode forming step for forming the source electrode 104 and the drain electrode 105. The formation region of the injection region 103 is defined by a pattern of a photoresist or a hard mask used as a mask in the dopant implantation step. In addition, the source electrode 104 and the drain electrode 105 are defined by a pattern of a photoresist or a hard mask used as a mask when a metal is patterned in the metal electrode forming step. These photoresists or hard masks are removed by a lift-off technique, an etching technique, or the like.

[0133] In the protective film forming step of step S204, a protective film composed of, for example, SiN x , or the like is formed so as to cover the exposed region of the second nitride semiconductor layer 102 (a region on which the source electrode 104 and the drain electrode 105 are not formed) from the viewpoint of surface protection of the semiconductor device.

[0134] In the heat treatment step of step S205, the second nitride semiconductor layer 102 and the source electrode 104 and the drain electrode 105 are electrically connected by performing heat treatment called ohmic sintering or ohmic alloying. By this step, an ohmic semiconductor-metal contact is achieved between the second nitride semiconductor layer 102 and the source electrode 104 and the drain electrode 105. In ohmic sintering, an annealing system in which the temperature rising, the temperature holding, and the temperature falling are controlled with high precision is required. In addition, the optimum temperature for obtaining the ohmic property strongly depends on the material of the source electrode 104 and the drain electrode 105, the layer thickness ratio, the composition of the second nitride semiconductor layer 102, and the like. Heat treatment at a temperature higher than necessary can possibly cause a decrease in the element separation function of the separation region 122 formed in step S202, cause damage to the nitride semiconductor crystal, and cause damage to the Schottky junction interface, so it is preferable to perform condition optimization in advance.

[0135] In the protective film opening step of step S206, a portion of the protective film formed in step S204 corresponding to the formation region of the gate electrode 106 is formed to have an opening reaching the second nitride semiconductor layer 102. As a method of partially opening the protective film, there are techniques such as reactive ion etching, a solution method, electrochemical reaction etching, photoelectrochemical reaction etching, and the like. In addition, if step S206 is omitted, or the opening is made to have a depth not reaching the second nitride semiconductor layer 102 and the gate electrode 106 is formed on the protective film formed in step S204 in a later step S110, the gate structure can be made into an insulating gate type (MIS type or MOS type) as in Embodiment 8 Figure 11 .

[0136] In the gate electrode forming step of step S207, the gate electrode 106 is formed in a manner of being embedded into the opening formed in step S206. Note that the contact of the metal of the gate electrode 106 and the second nitride semiconductor layer 102 becomes a contact of Schottky property. The metal of the gate electrode 106 can be formed using a sputtering method, an evaporation method, an inkjet method, or the like. The metal of the gate electrode 106 is patterned using a photoresist or a hard mask. In addition, the remaining metal needs to be completely removed by an appropriate optimal method such as a selective lift-off method or an etching method. Here, if the gate electrode 106 is formed in a region wider than the opening formed in step S109, so that a part of the gate electrode 106 extends also over the protective film, a semiconductor device of Embodiment 3 Figure 4 ) and Embodiment 6 Figure 8 and Figure 9 ) can be manufactured.

[0137] Next, in the protective film removing step of step S208, the protective film formed in step S204 is removed in its entirety. In order to avoid damage to the second nitride semiconductor layer 102, it is preferable that this step be performed not by a dry etching method but by a wet etching method. However, since the protective film has undergone a high-temperature heat history of ohmic sintering, the etching rate is sometimes extremely slow. In that case, it is preferable that the protective film be removed at high speed without damage by combining both a dry etching and a wet etching. At this time, the surfaces of the source electrode 104, the drain electrode 105, and the gate electrode 106, and the second nitride semiconductor layer 102 cannot be removed.

[0138] Next, in the first insulating film forming step of step S209, the first insulating film 111 having a relatively low carbon concentration is formed over the second nitride semiconductor layer 102 in a manner of covering the gate electrode 106. This step is performed in a state where a region not covered with the first insulating film 111 is covered with a hard mask or a photoresist or the like. After the first insulating film 111 is formed, the hard mask or the photoresist is removed. That is, the formation region and the non-formation region of the first insulating film 111 are defined by a pattern of the photoresist or the hard mask. In the case where the first insulating film is formed in a manner of covering the entire gate electrode 106, surface coverage becomes important, so a deposition method with high directivity such as a sputtering method is not suitable. If it is an atomic layer deposition method, since it is a deposition technique with excellent step coverage, it is preferable. After the first insulating film 111 is formed, the hard mask or the photoresist is removed. In step S209, if the first insulating film 111 is formed also at a position where the drain electrode 105 is in contact, the carbon concentration in the surface protective film 110 can have a gradient also in the vicinity of the drain electrode 105 as in Embodiment 10 Figure 16 ).

[0139] In the second insulating film forming step of step S210, the second insulating film 112 having a higher carbon concentration than the first insulating film 111 is formed in a manner to be adjacent to the first insulating film 111. In a case where the second insulating film 112 is formed to be adjacent to the first insulating film 111 only in the in-plane direction, the second insulating film 112 is formed after a hard mask or a photoresist is formed in a manner to overlap the first insulating film 111. In a case where a part of the second insulating film 112 is also formed on the first insulating film 111, the second insulating film 112 is formed after a hard mask or a photoresist is formed in a manner to expose a part of the upper surface of the first insulating film 111. Further, by narrowing the formation region of the second insulating film 112 and repeatedly performing the same process as that of step S210 one or more times while changing the carbon concentration of the insulating film, a surface protective film 110 composed of three or more insulating films having different carbon concentrations can be formed as in Embodiment 2. Figure 3 ).

[0140] Here, a technique for forming an insulating film having a gradient of carbon concentration will be described. For example, in a case where an insulating film composed of AlO x is formed by an atomic layer deposition method, TMA and DMAH are used as organic metal precursors, respectively, so that an insulating film having a high carbon concentration and an insulating film having a low carbon concentration can be produced, respectively. The AlO x film formed using DMAH has a carbon concentration about 50% lower than the AlO x film formed using TMA. Therefore, the AlO x film formed using DMAH is set as the first insulating film 111, and the AlO x film formed using TMA is set as the second insulating film 112. Further, the oxidizing agent of the organic metal precursor is preferably ozone or water. The reason is that, when plasma oxygen is used, depending on the degree of reactivity thereof, the carbon concentration is likely to become substantially uniform regardless of which organic metal precursor is used.

[0141] Further, as described above, regarding the amount of carbon (carbon concentration) remaining in the AlO x film, if the film formation temperature of the AlO x film is 200°C or higher, the carbon concentration in the AlO x film tends to be lower than when the film formation temperature is 200°C or lower. Therefore, the AlO x film formed so that the film formation temperature is 200°C or higher can be set as the first insulating film 111, and the AlO x film formed so that the film formation temperature is in the range of room temperature to 200°C can be set as the second insulating film 112.

[0142] Further, if the AlO xWhen the oxidizing agent used in the film formation of the film is O2 plasma, AlO x tendency of the carbon concentration in the film to increase. Therefore, AlO x formed using ozone as the oxidizing agent is provided as the first insulating film 111. x formed using ozone as the oxidizing agent is provided as the second insulating film.

[0143] According to the method for manufacturing a semiconductor device according to Embodiment 12, the semiconductor device according to Embodiment 5 can be easily formed. Figure 7 the semiconductor device according to Embodiment 5.

[0144] In the above-described embodiments, the material, the material, the size, the shape, the relative positional relationship, or the conditions for implementation of each constituent element are sometimes described, but these are only one example in all aspects and are not limited to the examples described in this specification.

[0145] Therefore, an infinite number of modifications and equivalents that are not illustrated can be assumed within the scope of the technology disclosed in this specification. For example, cases in which at least one constituent element is modified, cases in which something is added or omitted, and cases in which at least one constituent element in at least one embodiment is extracted and combined with a constituent element of another embodiment are included.

[0146] In addition, as long as there is no contradiction, a constituent element described as being provided "one" in the above-described embodiments can be provided "one or more".

[0147] Furthermore, each constituent element in the above-described embodiments is a conceptual unit, and within the scope of the technology disclosed in this specification, cases in which one constituent element is composed of a plurality of structures, cases in which one constituent element corresponds to a part of a certain structure, and cases in which a plurality of constituent elements are provided to one structure are included.

[0148] In addition, in each constituent element in the above-described embodiments, as long as the same function is exerted, a structure having another structure or shape is included.

[0149] In addition, the explanations in this specification are referred to for all purposes related to the present technology and should not be considered prior art.

[0150] In addition, in the above-described embodiments, in cases in which a material name or the like is described without being specifically specified, as long as there is no contradiction, an alloy or the like including another additive in the material is included.

[0151] Furthermore, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

Claims

1. A semiconductor device comprising: a substrate; a nitride semiconductor stacked structure formed on the substrate; a source electrode and a drain electrode formed on the nitride semiconductor stacked structure; a gate electrode formed on the nitride semiconductor stacked structure between the source electrode and the drain electrode; and a surface protective film covering the nitride semiconductor stacked structure, the nitride semiconductor stacked structure including: a first nitride semiconductor layer formed on the substrate; and a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer having a different composition from the first nitride semiconductor layer, a two-dimensional electron gas being formed at a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer, the surface protective film including: a first insulating film containing carbon formed on the nitride semiconductor stacked structure so as to be in contact with the gate electrode; and a second insulating film formed on the nitride semiconductor stacked structure so as to be adjacent to the first insulating film in a planar direction, the second insulating film having a higher carbon concentration than the first insulating film, the carbon concentration in the surface protective film having a gradient toward the source electrode or the drain electrode with the gate electrode as a center.

2. The semiconductor device according to claim 1, wherein the surface protective film further includes a third insulating film formed on the nitride semiconductor stacked structure so as to be adjacent to the second insulating film, the third insulating film having a higher carbon concentration than the second insulating film.

3. The semiconductor device according to claim 1, wherein the surface protective film is composed of three or more insulating films having different carbon concentrations respectively, the three or more insulating films being arranged in the planar direction, the carbon concentration being lower as closer to the gate electrode with respect to the three or more insulating films.

4. The semiconductor device according to any one of claims 1 to 3, wherein a part of the gate electrode extends toward the drain electrode to constitute a gate field plate.

5. The semiconductor device according to any one of claims 1 to 3, wherein a part of the source electrode extends toward the drain electrode to constitute a source field plate.

6. The semiconductor device according to any one of claims 1 to 3, wherein the gate electrode has a T-shaped, Y-shaped or Γ-shaped shape in a cross-sectional view.

7. The semiconductor device according to any one of claims 1 to 3, wherein the surface protective film covers the gate electrode.

8. The semiconductor device according to any one of claims 1 to 3, wherein the surface protective film is interposed between the gate electrode and the nitride semiconductor stacked structure.

9. The semiconductor device according to any one of claims 1 to 3, wherein the nitride semiconductor stacked structure further includes a cap layer formed on the second nitride semiconductor layer and composed of a nitride semiconductor having a different composition from the second nitride semiconductor layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10. The semiconductor device according to any one of Claims 1 to 3, wherein the surface protective film further includes one or both of a fourth insulating film that uniformly covers an upper surface of the surface protective film and a fifth insulating film that uniformly covers a lower surface of the surface protective film.

11. The semiconductor device according to any one of Claims 1 to 3, wherein the first insulating film is further formed at a position adjacent to the drain electrode, the second insulating film is further formed at a position adjacent to the first insulating film adjacent to the drain electrode.

12. A manufacturing method of a semiconductor device, comprising: a step of forming a nitride semiconductor layer stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer different in composition from the first nitride semiconductor layer on a substrate; a step of forming a source electrode and a drain electrode on the nitride semiconductor layer stack structure; a step of forming a protective film covering the nitride semiconductor layer stack structure, the source electrode, and the drain electrode; a step of, after the protective film is formed, performing heat treatment for electrically connecting the source electrode and the drain electrode to the nitride semiconductor layer stack structure; a step of, after the heat treatment, removing the protective film; a step of, after the protective film is removed, forming a surface protective film including a first insulating film containing carbon and a second insulating film having a larger carbon concentration than the first insulating film and adjacent to the first insulating film in an in-plane direction on an upper surface of the nitride semiconductor layer stack structure; and a step of forming a gate electrode in contact with the first insulating film between the source electrode and the drain electrode, the carbon concentration in the surface protective film has a gradient toward the source electrode or the drain electrode centering on the gate electrode.

13. The method for manufacturing a semiconductor device according to claim 12, wherein further comprising: a step of, before the gate electrode is formed, forming an opening reaching the nitride semiconductor layer stack structure in a portion of the first insulating film between the source electrode and the drain electrode in the surface protective film, the gate electrode is formed to be embedded in the opening.

14. The manufacturing method of a semiconductor device according to Claim 12, wherein the gate electrode is formed on the first insulating film of the surface protective film.

15. A manufacturing method of a semiconductor device, comprising: a step of forming a nitride semiconductor layer stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer different in composition from the first nitride semiconductor layer on a substrate; a step of forming a source electrode and a drain electrode on the nitride semiconductor layer stack structure; a step of forming a protective film covering the nitride semiconductor layer stack structure, the source electrode, and the drain electrode; a step of, after the protective film is formed, performing heat treatment for electrically connecting the source electrode and the drain electrode to the nitride semiconductor layer stack structure; a step of, in a portion of the protective film between the source electrode and the drain electrode, forming an opening reaching the nitride semiconductor layer stack structure; a step of forming a gate electrode in the opening; a step of, after the gate electrode is formed, removing the protective film; and a step of forming a surface protective film including a first insulating film containing carbon and a second insulating film having a larger carbon concentration than the first insulating film and being adjacent to the first insulating film in a planar direction on an upper surface of the nitride semiconductor layer stack structure after the protective film is removed, the carbon concentration in the surface protective film has a gradient in a direction from the gate electrode toward the source electrode or the drain electrode.

16. The method according to claim 15, wherein in the step of forming the surface protective film, the first insulating film is formed so as to cover the gate electrode.

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